axis_crc: Inital value, Final XOR und Input/Output reflected aber dafür Timingfehler
This commit is contained in:
Matthias Biermann
+4
-4
@@ -2,10 +2,10 @@
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="axi_crc_dma_ip" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739118610"/>
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<Generation Name="SIMULATION" State="RESET" Timestamp="1739118610"/>
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<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739118610"/>
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<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739118610"/>
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<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739140816"/>
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<Generation Name="SIMULATION" State="RESET" Timestamp="1739140816"/>
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<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739140816"/>
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<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739140816"/>
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<FileCollection Name="SOURCES" Type="SOURCES"/>
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</CompositeFile>
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</Root>
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+5
-2
@@ -2,7 +2,7 @@
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--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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--Date : Sat Feb 8 22:19:13 2025
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--Date : Sun Feb 9 17:44:48 2025
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--Host : BiermannSurface running 64-bit major release (build 9200)
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--Command : generate_target axi_crc_dma_ip_wrapper.bd
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--Design : axi_crc_dma_ip_wrapper
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@@ -49,6 +49,7 @@ entity axi_crc_dma_ip_wrapper is
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M_AXI_wready : in STD_LOGIC;
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M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
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M_AXI_wvalid : out STD_LOGIC;
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RESETN : in STD_LOGIC;
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S_AXIL_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
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S_AXIL_arready : out STD_LOGIC;
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S_AXIL_arvalid : in STD_LOGIC;
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@@ -123,7 +124,8 @@ architecture STRUCTURE of axi_crc_dma_ip_wrapper is
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M_AXI_rlast : in STD_LOGIC;
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M_AXI_rvalid : in STD_LOGIC;
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M_AXI_rready : out STD_LOGIC;
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CLK : in STD_LOGIC
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CLK : in STD_LOGIC;
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RESETN : in STD_LOGIC
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);
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end component axi_crc_dma_ip;
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begin
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@@ -164,6 +166,7 @@ axi_crc_dma_ip_i: component axi_crc_dma_ip
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M_AXI_wready => M_AXI_wready,
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M_AXI_wstrb(3 downto 0) => M_AXI_wstrb(3 downto 0),
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M_AXI_wvalid => M_AXI_wvalid,
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RESETN => RESETN,
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S_AXIL_araddr(7 downto 0) => S_AXIL_araddr(7 downto 0),
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S_AXIL_arready => S_AXIL_arready,
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S_AXIL_arvalid => S_AXIL_arvalid,
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+32
@@ -493,6 +493,38 @@
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>finalXOR</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">31</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>inOutReflected</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">1</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>S_AXIS_TVALID</spirit:name>
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<spirit:wire>
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+68
-36
@@ -1551,6 +1551,38 @@
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>finalXOR</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">31</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>inOutReflected</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">1</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>FIFO_NUM_FREE</spirit:name>
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<spirit:wire>
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@@ -2596,22 +2628,22 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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@@ -2619,13 +2651,13 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2639,36 +2671,36 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+58
-4
@@ -579,7 +579,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -746,7 +746,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -926,7 +926,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1006,7 +1006,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1135,6 +1135,24 @@
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 16:44:50 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:145f8ab0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
@@ -1938,6 +1956,42 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+2134
File diff suppressed because it is too large
Load Diff
+41
@@ -0,0 +1,41 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:13:59 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_ip_axis_fifo_0_0 -prefix
|
||||
// axi_crc_dma_ip_axis_fifo_0_0_ axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_fifo,Vivado 2023.1" *)
|
||||
module axi_crc_dma_ip_axis_fifo_0_0(S_AXIS_ACLK, S_AXIS_ARESETN, S_AXIS_TVALID,
|
||||
S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, S_AXIS_TUSER, S_NUM_FREE, M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY, M_AXIS_TUSER,
|
||||
M_NUM_AVAIL)
|
||||
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_ARESETN,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,S_AXIS_TUSER[0:0],S_NUM_FREE[7:0],M_AXIS_ARESETN,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY,M_AXIS_TUSER[0:0],M_NUM_AVAIL[7:0]" */
|
||||
/* synthesis syn_force_seq_prim="S_AXIS_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="M_AXIS_ACLK" */;
|
||||
input S_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXIS_ARESETN;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
input [0:0]S_AXIS_TUSER;
|
||||
output [7:0]S_NUM_FREE;
|
||||
input M_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input M_AXIS_ARESETN;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
output [0:0]M_AXIS_TUSER;
|
||||
output [7:0]M_NUM_AVAIL;
|
||||
endmodule
|
||||
+58
-4
@@ -579,7 +579,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -746,7 +746,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -926,7 +926,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1006,7 +1006,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK_0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_ip_CLK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -1135,6 +1135,24 @@
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 16:44:50 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d0b2d433</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
@@ -1938,6 +1956,42 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_1_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_1_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_1_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_1_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_ip_axis_fifo_1_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
|
||||
+2134
File diff suppressed because it is too large
Load Diff
+41
@@ -0,0 +1,41 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:13:59 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_ip_axis_fifo_1_0 -prefix
|
||||
// axi_crc_dma_ip_axis_fifo_1_0_ axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_fifo,Vivado 2023.1" *)
|
||||
module axi_crc_dma_ip_axis_fifo_1_0(S_AXIS_ACLK, S_AXIS_ARESETN, S_AXIS_TVALID,
|
||||
S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, S_AXIS_TUSER, S_NUM_FREE, M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY, M_AXIS_TUSER,
|
||||
M_NUM_AVAIL)
|
||||
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_ARESETN,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,S_AXIS_TUSER[0:0],S_NUM_FREE[7:0],M_AXIS_ARESETN,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY,M_AXIS_TUSER[0:0],M_NUM_AVAIL[7:0]" */
|
||||
/* synthesis syn_force_seq_prim="S_AXIS_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="M_AXIS_ACLK" */;
|
||||
input S_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXIS_ARESETN;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
input [0:0]S_AXIS_TUSER;
|
||||
output [7:0]S_NUM_FREE;
|
||||
input M_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input M_AXIS_ARESETN;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
output [0:0]M_AXIS_TUSER;
|
||||
output [7:0]M_NUM_AVAIL;
|
||||
endmodule
|
||||
+50
-5
@@ -2,10 +2,55 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739118613"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1739118613"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739118613"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739118613"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1739186498"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739186499"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1739186498"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739186499"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axi_crc_dma_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axi_crc_dma_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axi_crc_dma_sim_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\axi_crc_dma_sim_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axi_crc_dma_sim_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\axi_crc_dma_sim_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axi_crc_dma_sim_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 9 12:21:29 2025
|
||||
--Date : Mon Feb 10 12:21:38 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
|
||||
--Design : axi_crc_dma_sim_1_wrapper
|
||||
|
||||
+5
-5
@@ -581,7 +581,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:dc1943c5</spirit:value>
|
||||
<spirit:value>9:69754ca2</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -597,11 +597,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 08 16:20:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Mon Feb 10 11:21:38 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:dc1943c5</spirit:value>
|
||||
<spirit:value>9:69754ca2</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -983,7 +983,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>REVISION_NO</spirit:name>
|
||||
<spirit:displayName>Revision No</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">20</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">21</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
@@ -1039,7 +1039,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>REVISION_NO</spirit:name>
|
||||
<spirit:displayName>Revision No</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">20</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">21</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
|
||||
+1
-1
@@ -149,7 +149,7 @@ BEGIN
|
||||
STIM_FILENAME => "../../axi_crc_dma_sim.mem",
|
||||
HAS_FINISHED_OUT => false,
|
||||
HAS_INTERRUPT_IN => true,
|
||||
REVISION_NO => 20
|
||||
REVISION_NO => 21
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt_in => interrupt_in,
|
||||
|
||||
+88
-12
@@ -436,6 +436,40 @@
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bba2692b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axi_crc_dma_sim_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Feb 10 11:21:38 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bba2692b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -444,7 +478,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -456,7 +490,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -472,7 +506,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -488,7 +522,39 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>finalXOR</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>inOutReflected</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -500,7 +566,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -516,7 +582,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -531,7 +597,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -546,7 +612,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -558,7 +624,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -574,7 +640,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -586,7 +652,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -598,7 +664,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -615,6 +681,16 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
|
||||
+6
@@ -59,6 +59,8 @@ ENTITY axi_crc_dma_sim_1_axis_crc_0_0 IS
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
@@ -79,6 +81,8 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_crc_0_0_arch OF axi_crc_dma_sim_1_axis_crc_0
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
@@ -112,6 +116,8 @@ BEGIN
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
|
||||
+179
-103
@@ -1479,6 +1479,40 @@
|
||||
</spirit:memoryMap>
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||
<spirit:modelName>axis_dma</spirit:modelName>
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<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:a1417149</spirit:value>
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||||
</spirit:parameter>
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||||
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||||
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|
||||
<spirit:view>
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||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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||||
<spirit:language>vhdl</spirit:language>
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||||
<spirit:modelName>axi_crc_dma_sim_1_axis_dma_0_0</spirit:modelName>
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||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Mon Feb 10 11:21:38 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:a1417149</spirit:value>
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||||
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|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -1487,7 +1521,7 @@
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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||||
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|
||||
</spirit:wire>
|
||||
@@ -1499,7 +1533,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
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||||
@@ -1511,7 +1545,7 @@
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1530,7 +1564,7 @@
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1546,7 +1580,39 @@
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
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||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>finalXOR</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
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||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>inOutReflected</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1562,7 +1628,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1578,7 +1644,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1594,7 +1660,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1609,7 +1675,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1624,7 +1690,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1640,7 +1706,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1655,7 +1721,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1670,7 +1736,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1686,7 +1752,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1701,7 +1767,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1713,7 +1779,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1732,7 +1798,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1748,7 +1814,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
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||||
<spirit:driver>
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||||
@@ -1763,7 +1829,7 @@
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
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||||
<spirit:driver>
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||||
@@ -1778,7 +1844,7 @@
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||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
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||||
@@ -1794,7 +1860,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1806,7 +1872,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1818,7 +1884,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1837,7 +1903,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1849,7 +1915,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1864,7 +1930,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1883,7 +1949,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1899,7 +1965,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
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||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1915,7 +1981,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1931,7 +1997,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1947,7 +2013,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1963,7 +2029,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1979,7 +2045,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1991,7 +2057,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2003,7 +2069,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2022,7 +2088,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2041,7 +2107,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2060,7 +2126,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic_vector</spirit:typeName>
|
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2075,7 +2141,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2090,7 +2156,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2105,7 +2171,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2124,7 +2190,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2140,7 +2206,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2156,7 +2222,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2172,7 +2238,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2188,7 +2254,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2204,7 +2270,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2220,7 +2286,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2232,7 +2298,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2247,7 +2313,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2266,7 +2332,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2282,7 +2348,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2294,7 +2360,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2313,7 +2379,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2325,7 +2391,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2337,7 +2403,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2356,7 +2422,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2375,7 +2441,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2390,7 +2456,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2406,7 +2472,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2421,7 +2487,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2436,7 +2502,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2448,7 +2514,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2464,7 +2530,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2476,7 +2542,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2488,7 +2554,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2544,6 +2610,16 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_dma:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
@@ -2594,24 +2670,24 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2619,13 +2695,13 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2639,36 +2715,36 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+6
@@ -60,6 +60,8 @@ ENTITY axi_crc_dma_sim_1_axis_dma_0_0 IS
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
@@ -142,6 +144,8 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
@@ -294,6 +298,8 @@ BEGIN
|
||||
INTERRUPT => INTERRUPT,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
FIFO_NUM_FREE => FIFO_NUM_FREE,
|
||||
FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
|
||||
+697
@@ -0,0 +1,697 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Mon Feb 10 12:21:38 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1.bd
|
||||
--Design : axi_crc_dma_sim_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axi_crc_dma_imp_1PQG7GB is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_arready : in STD_LOGIC;
|
||||
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_arvalid : out STD_LOGIC;
|
||||
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_awready : in STD_LOGIC;
|
||||
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_awvalid : out STD_LOGIC;
|
||||
M_AXI_bready : out STD_LOGIC;
|
||||
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_bvalid : in STD_LOGIC;
|
||||
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_rlast : in STD_LOGIC;
|
||||
M_AXI_rready : out STD_LOGIC;
|
||||
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_rvalid : in STD_LOGIC;
|
||||
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_wlast : out STD_LOGIC;
|
||||
M_AXI_wready : in STD_LOGIC;
|
||||
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_wvalid : out STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_arready : out STD_LOGIC;
|
||||
S_AXIL_arvalid : in STD_LOGIC;
|
||||
S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_awready : out STD_LOGIC;
|
||||
S_AXIL_awvalid : in STD_LOGIC;
|
||||
S_AXIL_bready : in STD_LOGIC;
|
||||
S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_bvalid : out STD_LOGIC;
|
||||
S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_rready : in STD_LOGIC;
|
||||
S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_rvalid : out STD_LOGIC;
|
||||
S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_wready : out STD_LOGIC;
|
||||
S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_wvalid : in STD_LOGIC
|
||||
);
|
||||
end axi_crc_dma_imp_1PQG7GB;
|
||||
|
||||
architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
component axi_crc_dma_sim_1_axis_fifo_0_0 is
|
||||
port (
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
M_AXIS_ACLK : in STD_LOGIC;
|
||||
M_AXIS_ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_fifo_0_0;
|
||||
component axi_crc_dma_sim_1_axis_fifo_1_0 is
|
||||
port (
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
M_AXIS_ACLK : in STD_LOGIC;
|
||||
M_AXIS_ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_fifo_1_0;
|
||||
component axi_crc_dma_sim_1_axis_crc_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_crc_0_0;
|
||||
component axi_crc_dma_sim_1_axis_dma_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
finalXOR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
inOutReflected : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
FIFO_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_dma_0_0;
|
||||
signal CLK_1 : STD_LOGIC;
|
||||
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_ARREADY : STD_LOGIC;
|
||||
signal Conn1_ARVALID : STD_LOGIC;
|
||||
signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_AWREADY : STD_LOGIC;
|
||||
signal Conn1_AWVALID : STD_LOGIC;
|
||||
signal Conn1_BREADY : STD_LOGIC;
|
||||
signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn1_BVALID : STD_LOGIC;
|
||||
signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_RREADY : STD_LOGIC;
|
||||
signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn1_RVALID : STD_LOGIC;
|
||||
signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_WREADY : STD_LOGIC;
|
||||
signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn1_WVALID : STD_LOGIC;
|
||||
signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_ARREADY : STD_LOGIC;
|
||||
signal Conn2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn2_ARVALID : STD_LOGIC;
|
||||
signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_AWREADY : STD_LOGIC;
|
||||
signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn2_AWVALID : STD_LOGIC;
|
||||
signal Conn2_BREADY : STD_LOGIC;
|
||||
signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_BVALID : STD_LOGIC;
|
||||
signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn2_RLAST : STD_LOGIC;
|
||||
signal Conn2_RREADY : STD_LOGIC;
|
||||
signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_RVALID : STD_LOGIC;
|
||||
signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_WLAST : STD_LOGIC;
|
||||
signal Conn2_WREADY : STD_LOGIC;
|
||||
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_WVALID : STD_LOGIC;
|
||||
signal RESETN_1 : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dma_0_INTERRUPT : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dma_0_finalXOR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_inOutReflected : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
begin
|
||||
CLK_1 <= CLK;
|
||||
Conn1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0);
|
||||
Conn1_ARVALID <= S_AXIL_arvalid;
|
||||
Conn1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0);
|
||||
Conn1_AWVALID <= S_AXIL_awvalid;
|
||||
Conn1_BREADY <= S_AXIL_bready;
|
||||
Conn1_RREADY <= S_AXIL_rready;
|
||||
Conn1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0);
|
||||
Conn1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0);
|
||||
Conn1_WVALID <= S_AXIL_wvalid;
|
||||
Conn2_ARREADY <= M_AXI_arready;
|
||||
Conn2_AWREADY <= M_AXI_awready;
|
||||
Conn2_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
|
||||
Conn2_BVALID <= M_AXI_bvalid;
|
||||
Conn2_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
|
||||
Conn2_RID(0) <= M_AXI_rid(0);
|
||||
Conn2_RLAST <= M_AXI_rlast;
|
||||
Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
|
||||
Conn2_RVALID <= M_AXI_rvalid;
|
||||
Conn2_WREADY <= M_AXI_wready;
|
||||
INTERRUPT <= axis_dma_0_INTERRUPT;
|
||||
M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0);
|
||||
M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0);
|
||||
M_AXI_arid(0) <= Conn2_ARID(0);
|
||||
M_AXI_arlen(3 downto 0) <= Conn2_ARLEN(3 downto 0);
|
||||
M_AXI_arsize(2 downto 0) <= Conn2_ARSIZE(2 downto 0);
|
||||
M_AXI_arvalid <= Conn2_ARVALID;
|
||||
M_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0);
|
||||
M_AXI_awburst(1 downto 0) <= Conn2_AWBURST(1 downto 0);
|
||||
M_AXI_awlen(3 downto 0) <= Conn2_AWLEN(3 downto 0);
|
||||
M_AXI_awsize(2 downto 0) <= Conn2_AWSIZE(2 downto 0);
|
||||
M_AXI_awvalid <= Conn2_AWVALID;
|
||||
M_AXI_bready <= Conn2_BREADY;
|
||||
M_AXI_rready <= Conn2_RREADY;
|
||||
M_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0);
|
||||
M_AXI_wlast <= Conn2_WLAST;
|
||||
M_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0);
|
||||
M_AXI_wvalid <= Conn2_WVALID;
|
||||
RESETN_1 <= RESETN;
|
||||
S_AXIL_arready <= Conn1_ARREADY;
|
||||
S_AXIL_awready <= Conn1_AWREADY;
|
||||
S_AXIL_bresp(1 downto 0) <= Conn1_BRESP(1 downto 0);
|
||||
S_AXIL_bvalid <= Conn1_BVALID;
|
||||
S_AXIL_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0);
|
||||
S_AXIL_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0);
|
||||
S_AXIL_rvalid <= Conn1_RVALID;
|
||||
S_AXIL_wready <= Conn1_WREADY;
|
||||
axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => CLK_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
RESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
|
||||
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
|
||||
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
|
||||
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
|
||||
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
|
||||
);
|
||||
axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
|
||||
port map (
|
||||
CLK => CLK_1,
|
||||
FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
|
||||
INTERRUPT => axis_dma_0_INTERRUPT,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
|
||||
M_AXI_ARADDR(31 downto 0) => Conn2_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => Conn2_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_ARID(0) => Conn2_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => Conn2_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_ARREADY => Conn2_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => Conn2_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => Conn2_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => Conn2_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => Conn2_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_AWID(0) => NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED(0),
|
||||
M_AXI_AWLEN(3 downto 0) => Conn2_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_AWREADY => Conn2_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => Conn2_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => Conn2_AWVALID,
|
||||
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
|
||||
M_AXI_BREADY => Conn2_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => Conn2_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => Conn2_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => Conn2_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => Conn2_RID(0),
|
||||
M_AXI_RLAST => Conn2_RLAST,
|
||||
M_AXI_RREADY => Conn2_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => Conn2_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => Conn2_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => Conn2_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => NLW_axis_dma_0_M_AXI_WID_UNCONNECTED(31 downto 0),
|
||||
M_AXI_WLAST => Conn2_WLAST,
|
||||
M_AXI_WREADY => Conn2_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => Conn2_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => Conn2_WVALID,
|
||||
RESETN => RESETN_1,
|
||||
S_AXIL_ARADDR(7 downto 0) => Conn1_ARADDR(7 downto 0),
|
||||
S_AXIL_ARREADY => Conn1_ARREADY,
|
||||
S_AXIL_ARVALID => Conn1_ARVALID,
|
||||
S_AXIL_AWADDR(7 downto 0) => Conn1_AWADDR(7 downto 0),
|
||||
S_AXIL_AWREADY => Conn1_AWREADY,
|
||||
S_AXIL_AWVALID => Conn1_AWVALID,
|
||||
S_AXIL_BREADY => Conn1_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => Conn1_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => Conn1_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => Conn1_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => Conn1_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => Conn1_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => Conn1_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => Conn1_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => Conn1_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => Conn1_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => Conn1_WVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
|
||||
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
|
||||
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
|
||||
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
|
||||
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
|
||||
);
|
||||
axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0
|
||||
port map (
|
||||
M_AXIS_ACLK => CLK_1,
|
||||
M_AXIS_ARESETN => RESETN_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0),
|
||||
M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
|
||||
M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0),
|
||||
S_AXIS_ACLK => CLK_1,
|
||||
S_AXIS_ARESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
|
||||
S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0)
|
||||
);
|
||||
axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0
|
||||
port map (
|
||||
M_AXIS_ACLK => CLK_1,
|
||||
M_AXIS_ARESETN => RESETN_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0),
|
||||
M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
|
||||
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
S_AXIS_ACLK => CLK_1,
|
||||
S_AXIS_ARESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axi_crc_dma_sim_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=7,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=6,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1.hwdef";
|
||||
end axi_crc_dma_sim_1;
|
||||
|
||||
architecture STRUCTURE of axi_crc_dma_sim_1 is
|
||||
component axi_crc_dma_sim_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
interrupt_in : in STD_LOGIC;
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axil_master_with_rom_0_0;
|
||||
component axi_crc_dma_sim_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_sim_1_clk_rst_generator_0_0;
|
||||
component axi_crc_dma_sim_1_axi3_slave_verif_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_RLAST : out STD_LOGIC;
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WLAST : in STD_LOGIC;
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axi3_slave_verif_0_0;
|
||||
signal axi_crc_dma_INTERRUPT : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal axi_crc_dma_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_BREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_BVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal axi_crc_dma_M_AXI_RLAST : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_RREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_RVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_WLAST : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_WREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_WVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
begin
|
||||
axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXI_ARADDR(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
|
||||
S_AXI_ARBURST(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
|
||||
S_AXI_ARID(0) => axi_crc_dma_M_AXI_ARID(0),
|
||||
S_AXI_ARLEN(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
|
||||
S_AXI_ARREADY => axi_crc_dma_M_AXI_ARREADY,
|
||||
S_AXI_ARSIZE(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
|
||||
S_AXI_ARVALID => axi_crc_dma_M_AXI_ARVALID,
|
||||
S_AXI_AWADDR(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
|
||||
S_AXI_AWBURST(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
|
||||
S_AXI_AWLEN(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
|
||||
S_AXI_AWREADY => axi_crc_dma_M_AXI_AWREADY,
|
||||
S_AXI_AWSIZE(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
|
||||
S_AXI_AWVALID => axi_crc_dma_M_AXI_AWVALID,
|
||||
S_AXI_BREADY => axi_crc_dma_M_AXI_BREADY,
|
||||
S_AXI_BRESP(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
|
||||
S_AXI_BVALID => axi_crc_dma_M_AXI_BVALID,
|
||||
S_AXI_RDATA(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
|
||||
S_AXI_RID(0) => axi_crc_dma_M_AXI_RID(0),
|
||||
S_AXI_RLAST => axi_crc_dma_M_AXI_RLAST,
|
||||
S_AXI_RREADY => axi_crc_dma_M_AXI_RREADY,
|
||||
S_AXI_RRESP(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
|
||||
S_AXI_RVALID => axi_crc_dma_M_AXI_RVALID,
|
||||
S_AXI_WDATA(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
|
||||
S_AXI_WLAST => axi_crc_dma_M_AXI_WLAST,
|
||||
S_AXI_WREADY => axi_crc_dma_M_AXI_WREADY,
|
||||
S_AXI_WSTRB(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
|
||||
S_AXI_WVALID => axi_crc_dma_M_AXI_WVALID
|
||||
);
|
||||
axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
INTERRUPT => axi_crc_dma_INTERRUPT,
|
||||
M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0),
|
||||
M_AXI_arlen(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_arready => axi_crc_dma_M_AXI_ARREADY,
|
||||
M_AXI_arsize(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_arvalid => axi_crc_dma_M_AXI_ARVALID,
|
||||
M_AXI_awaddr(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_awburst(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_awlen(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_awready => axi_crc_dma_M_AXI_AWREADY,
|
||||
M_AXI_awsize(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_awvalid => axi_crc_dma_M_AXI_AWVALID,
|
||||
M_AXI_bready => axi_crc_dma_M_AXI_BREADY,
|
||||
M_AXI_bresp(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_bvalid => axi_crc_dma_M_AXI_BVALID,
|
||||
M_AXI_rdata(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_rid(0) => axi_crc_dma_M_AXI_RID(0),
|
||||
M_AXI_rlast => axi_crc_dma_M_AXI_RLAST,
|
||||
M_AXI_rready => axi_crc_dma_M_AXI_RREADY,
|
||||
M_AXI_rresp(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_rvalid => axi_crc_dma_M_AXI_RVALID,
|
||||
M_AXI_wdata(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_wlast => axi_crc_dma_M_AXI_WLAST,
|
||||
M_AXI_wready => axi_crc_dma_M_AXI_WREADY,
|
||||
M_AXI_wstrb(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_wvalid => axi_crc_dma_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
S_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
S_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID
|
||||
);
|
||||
axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => axi_crc_dma_INTERRUPT
|
||||
);
|
||||
clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
+697
@@ -0,0 +1,697 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Mon Feb 10 12:21:38 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1.bd
|
||||
--Design : axi_crc_dma_sim_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axi_crc_dma_imp_1PQG7GB is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_arready : in STD_LOGIC;
|
||||
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_arvalid : out STD_LOGIC;
|
||||
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_awready : in STD_LOGIC;
|
||||
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_awvalid : out STD_LOGIC;
|
||||
M_AXI_bready : out STD_LOGIC;
|
||||
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_bvalid : in STD_LOGIC;
|
||||
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_rlast : in STD_LOGIC;
|
||||
M_AXI_rready : out STD_LOGIC;
|
||||
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_rvalid : in STD_LOGIC;
|
||||
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_wlast : out STD_LOGIC;
|
||||
M_AXI_wready : in STD_LOGIC;
|
||||
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_wvalid : out STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_arready : out STD_LOGIC;
|
||||
S_AXIL_arvalid : in STD_LOGIC;
|
||||
S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_awready : out STD_LOGIC;
|
||||
S_AXIL_awvalid : in STD_LOGIC;
|
||||
S_AXIL_bready : in STD_LOGIC;
|
||||
S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_bvalid : out STD_LOGIC;
|
||||
S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_rready : in STD_LOGIC;
|
||||
S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_rvalid : out STD_LOGIC;
|
||||
S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_wready : out STD_LOGIC;
|
||||
S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_wvalid : in STD_LOGIC
|
||||
);
|
||||
end axi_crc_dma_imp_1PQG7GB;
|
||||
|
||||
architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
component axi_crc_dma_sim_1_axis_fifo_0_0 is
|
||||
port (
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
M_AXIS_ACLK : in STD_LOGIC;
|
||||
M_AXIS_ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_fifo_0_0;
|
||||
component axi_crc_dma_sim_1_axis_fifo_1_0 is
|
||||
port (
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
M_AXIS_ACLK : in STD_LOGIC;
|
||||
M_AXIS_ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_fifo_1_0;
|
||||
component axi_crc_dma_sim_1_axis_crc_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_crc_0_0;
|
||||
component axi_crc_dma_sim_1_axis_dma_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
finalXOR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
inOutReflected : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
FIFO_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axis_dma_0_0;
|
||||
signal CLK_1 : STD_LOGIC;
|
||||
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_ARREADY : STD_LOGIC;
|
||||
signal Conn1_ARVALID : STD_LOGIC;
|
||||
signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_AWREADY : STD_LOGIC;
|
||||
signal Conn1_AWVALID : STD_LOGIC;
|
||||
signal Conn1_BREADY : STD_LOGIC;
|
||||
signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn1_BVALID : STD_LOGIC;
|
||||
signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_RREADY : STD_LOGIC;
|
||||
signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn1_RVALID : STD_LOGIC;
|
||||
signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_WREADY : STD_LOGIC;
|
||||
signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn1_WVALID : STD_LOGIC;
|
||||
signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_ARREADY : STD_LOGIC;
|
||||
signal Conn2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn2_ARVALID : STD_LOGIC;
|
||||
signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_AWREADY : STD_LOGIC;
|
||||
signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn2_AWVALID : STD_LOGIC;
|
||||
signal Conn2_BREADY : STD_LOGIC;
|
||||
signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_BVALID : STD_LOGIC;
|
||||
signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal Conn2_RLAST : STD_LOGIC;
|
||||
signal Conn2_RREADY : STD_LOGIC;
|
||||
signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn2_RVALID : STD_LOGIC;
|
||||
signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_WLAST : STD_LOGIC;
|
||||
signal Conn2_WREADY : STD_LOGIC;
|
||||
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_WVALID : STD_LOGIC;
|
||||
signal RESETN_1 : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dma_0_INTERRUPT : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dma_0_finalXOR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_inOutReflected : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
begin
|
||||
CLK_1 <= CLK;
|
||||
Conn1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0);
|
||||
Conn1_ARVALID <= S_AXIL_arvalid;
|
||||
Conn1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0);
|
||||
Conn1_AWVALID <= S_AXIL_awvalid;
|
||||
Conn1_BREADY <= S_AXIL_bready;
|
||||
Conn1_RREADY <= S_AXIL_rready;
|
||||
Conn1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0);
|
||||
Conn1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0);
|
||||
Conn1_WVALID <= S_AXIL_wvalid;
|
||||
Conn2_ARREADY <= M_AXI_arready;
|
||||
Conn2_AWREADY <= M_AXI_awready;
|
||||
Conn2_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
|
||||
Conn2_BVALID <= M_AXI_bvalid;
|
||||
Conn2_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
|
||||
Conn2_RID(0) <= M_AXI_rid(0);
|
||||
Conn2_RLAST <= M_AXI_rlast;
|
||||
Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
|
||||
Conn2_RVALID <= M_AXI_rvalid;
|
||||
Conn2_WREADY <= M_AXI_wready;
|
||||
INTERRUPT <= axis_dma_0_INTERRUPT;
|
||||
M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0);
|
||||
M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0);
|
||||
M_AXI_arid(0) <= Conn2_ARID(0);
|
||||
M_AXI_arlen(3 downto 0) <= Conn2_ARLEN(3 downto 0);
|
||||
M_AXI_arsize(2 downto 0) <= Conn2_ARSIZE(2 downto 0);
|
||||
M_AXI_arvalid <= Conn2_ARVALID;
|
||||
M_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0);
|
||||
M_AXI_awburst(1 downto 0) <= Conn2_AWBURST(1 downto 0);
|
||||
M_AXI_awlen(3 downto 0) <= Conn2_AWLEN(3 downto 0);
|
||||
M_AXI_awsize(2 downto 0) <= Conn2_AWSIZE(2 downto 0);
|
||||
M_AXI_awvalid <= Conn2_AWVALID;
|
||||
M_AXI_bready <= Conn2_BREADY;
|
||||
M_AXI_rready <= Conn2_RREADY;
|
||||
M_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0);
|
||||
M_AXI_wlast <= Conn2_WLAST;
|
||||
M_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0);
|
||||
M_AXI_wvalid <= Conn2_WVALID;
|
||||
RESETN_1 <= RESETN;
|
||||
S_AXIL_arready <= Conn1_ARREADY;
|
||||
S_AXIL_awready <= Conn1_AWREADY;
|
||||
S_AXIL_bresp(1 downto 0) <= Conn1_BRESP(1 downto 0);
|
||||
S_AXIL_bvalid <= Conn1_BVALID;
|
||||
S_AXIL_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0);
|
||||
S_AXIL_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0);
|
||||
S_AXIL_rvalid <= Conn1_RVALID;
|
||||
S_AXIL_wready <= Conn1_WREADY;
|
||||
axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => CLK_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
RESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
|
||||
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
|
||||
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
|
||||
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
|
||||
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
|
||||
);
|
||||
axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
|
||||
port map (
|
||||
CLK => CLK_1,
|
||||
FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
|
||||
INTERRUPT => axis_dma_0_INTERRUPT,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
|
||||
M_AXI_ARADDR(31 downto 0) => Conn2_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => Conn2_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_ARID(0) => Conn2_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => Conn2_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_ARREADY => Conn2_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => Conn2_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => Conn2_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => Conn2_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => Conn2_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_AWID(0) => NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED(0),
|
||||
M_AXI_AWLEN(3 downto 0) => Conn2_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_AWREADY => Conn2_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => Conn2_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => Conn2_AWVALID,
|
||||
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
|
||||
M_AXI_BREADY => Conn2_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => Conn2_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => Conn2_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => Conn2_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => Conn2_RID(0),
|
||||
M_AXI_RLAST => Conn2_RLAST,
|
||||
M_AXI_RREADY => Conn2_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => Conn2_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => Conn2_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => Conn2_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => NLW_axis_dma_0_M_AXI_WID_UNCONNECTED(31 downto 0),
|
||||
M_AXI_WLAST => Conn2_WLAST,
|
||||
M_AXI_WREADY => Conn2_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => Conn2_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => Conn2_WVALID,
|
||||
RESETN => RESETN_1,
|
||||
S_AXIL_ARADDR(7 downto 0) => Conn1_ARADDR(7 downto 0),
|
||||
S_AXIL_ARREADY => Conn1_ARREADY,
|
||||
S_AXIL_ARVALID => Conn1_ARVALID,
|
||||
S_AXIL_AWADDR(7 downto 0) => Conn1_AWADDR(7 downto 0),
|
||||
S_AXIL_AWREADY => Conn1_AWREADY,
|
||||
S_AXIL_AWVALID => Conn1_AWVALID,
|
||||
S_AXIL_BREADY => Conn1_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => Conn1_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => Conn1_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => Conn1_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => Conn1_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => Conn1_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => Conn1_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => Conn1_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => Conn1_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => Conn1_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => Conn1_WVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
|
||||
finalXOR(31 downto 0) => axis_dma_0_finalXOR(31 downto 0),
|
||||
inOutReflected(1 downto 0) => axis_dma_0_inOutReflected(1 downto 0),
|
||||
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
|
||||
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
|
||||
);
|
||||
axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0
|
||||
port map (
|
||||
M_AXIS_ACLK => CLK_1,
|
||||
M_AXIS_ARESETN => RESETN_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0),
|
||||
M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
|
||||
M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0),
|
||||
S_AXIS_ACLK => CLK_1,
|
||||
S_AXIS_ARESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
|
||||
S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0)
|
||||
);
|
||||
axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0
|
||||
port map (
|
||||
M_AXIS_ACLK => CLK_1,
|
||||
M_AXIS_ARESETN => RESETN_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0),
|
||||
M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
|
||||
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
S_AXIS_ACLK => CLK_1,
|
||||
S_AXIS_ARESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axi_crc_dma_sim_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=7,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=6,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1.hwdef";
|
||||
end axi_crc_dma_sim_1;
|
||||
|
||||
architecture STRUCTURE of axi_crc_dma_sim_1 is
|
||||
component axi_crc_dma_sim_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
interrupt_in : in STD_LOGIC;
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axil_master_with_rom_0_0;
|
||||
component axi_crc_dma_sim_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_sim_1_clk_rst_generator_0_0;
|
||||
component axi_crc_dma_sim_1_axi3_slave_verif_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_RLAST : out STD_LOGIC;
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WLAST : in STD_LOGIC;
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axi3_slave_verif_0_0;
|
||||
signal axi_crc_dma_INTERRUPT : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal axi_crc_dma_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_BREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_BVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal axi_crc_dma_M_AXI_RLAST : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_RREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_RVALID : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_WLAST : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_WREADY : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_WVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
begin
|
||||
axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXI_ARADDR(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
|
||||
S_AXI_ARBURST(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
|
||||
S_AXI_ARID(0) => axi_crc_dma_M_AXI_ARID(0),
|
||||
S_AXI_ARLEN(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
|
||||
S_AXI_ARREADY => axi_crc_dma_M_AXI_ARREADY,
|
||||
S_AXI_ARSIZE(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
|
||||
S_AXI_ARVALID => axi_crc_dma_M_AXI_ARVALID,
|
||||
S_AXI_AWADDR(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
|
||||
S_AXI_AWBURST(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
|
||||
S_AXI_AWLEN(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
|
||||
S_AXI_AWREADY => axi_crc_dma_M_AXI_AWREADY,
|
||||
S_AXI_AWSIZE(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
|
||||
S_AXI_AWVALID => axi_crc_dma_M_AXI_AWVALID,
|
||||
S_AXI_BREADY => axi_crc_dma_M_AXI_BREADY,
|
||||
S_AXI_BRESP(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
|
||||
S_AXI_BVALID => axi_crc_dma_M_AXI_BVALID,
|
||||
S_AXI_RDATA(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
|
||||
S_AXI_RID(0) => axi_crc_dma_M_AXI_RID(0),
|
||||
S_AXI_RLAST => axi_crc_dma_M_AXI_RLAST,
|
||||
S_AXI_RREADY => axi_crc_dma_M_AXI_RREADY,
|
||||
S_AXI_RRESP(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
|
||||
S_AXI_RVALID => axi_crc_dma_M_AXI_RVALID,
|
||||
S_AXI_WDATA(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
|
||||
S_AXI_WLAST => axi_crc_dma_M_AXI_WLAST,
|
||||
S_AXI_WREADY => axi_crc_dma_M_AXI_WREADY,
|
||||
S_AXI_WSTRB(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
|
||||
S_AXI_WVALID => axi_crc_dma_M_AXI_WVALID
|
||||
);
|
||||
axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
INTERRUPT => axi_crc_dma_INTERRUPT,
|
||||
M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0),
|
||||
M_AXI_arlen(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_arready => axi_crc_dma_M_AXI_ARREADY,
|
||||
M_AXI_arsize(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_arvalid => axi_crc_dma_M_AXI_ARVALID,
|
||||
M_AXI_awaddr(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_awburst(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_awlen(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_awready => axi_crc_dma_M_AXI_AWREADY,
|
||||
M_AXI_awsize(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_awvalid => axi_crc_dma_M_AXI_AWVALID,
|
||||
M_AXI_bready => axi_crc_dma_M_AXI_BREADY,
|
||||
M_AXI_bresp(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_bvalid => axi_crc_dma_M_AXI_BVALID,
|
||||
M_AXI_rdata(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_rid(0) => axi_crc_dma_M_AXI_RID(0),
|
||||
M_AXI_rlast => axi_crc_dma_M_AXI_RLAST,
|
||||
M_AXI_rready => axi_crc_dma_M_AXI_RREADY,
|
||||
M_AXI_rresp(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_rvalid => axi_crc_dma_M_AXI_RVALID,
|
||||
M_AXI_wdata(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_wlast => axi_crc_dma_M_AXI_WLAST,
|
||||
M_AXI_wready => axi_crc_dma_M_AXI_WREADY,
|
||||
M_AXI_wstrb(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_wvalid => axi_crc_dma_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
S_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
S_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID
|
||||
);
|
||||
axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => axi_crc_dma_INTERRUPT
|
||||
);
|
||||
clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
+50
-5
@@ -2,10 +2,55 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axi_crc_dma_syn_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739118616"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1739118616"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739118616"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739118616"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739140848"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739140848"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739140848"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739140848"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axi_crc_dma_syn_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axi_crc_dma_syn_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axi_crc_dma_syn_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\axi_crc_dma_syn_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axi_crc_dma_syn_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\axi_crc_dma_syn_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axi_crc_dma_syn_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
|
||||
|
||||
################################################################################
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 9 12:30:19 2025
|
||||
--Date : Sun Feb 9 23:40:42 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_syn_1_wrapper.bd
|
||||
--Design : axi_crc_dma_syn_1_wrapper
|
||||
|
||||
+133
-134
@@ -1500,7 +1500,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:39 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:48 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1518,7 +1518,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1538,7 +1538,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1566,7 +1566,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1605,7 +1605,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1625,7 +1625,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1663,7 +1663,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1683,7 +1683,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:36 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:47 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1701,7 +1701,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1714,7 +1714,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1731,7 +1731,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1758,7 +1758,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1785,7 +1785,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1812,7 +1812,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1839,7 +1839,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1866,7 +1866,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1893,7 +1893,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1920,7 +1920,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1947,7 +1947,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1974,7 +1974,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2001,7 +2001,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2024,7 +2024,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2047,7 +2047,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2071,7 +2071,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2098,7 +2098,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2125,7 +2125,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2148,7 +2148,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2175,7 +2175,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2198,7 +2198,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2221,7 +2221,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2245,7 +2245,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2269,7 +2269,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2293,7 +2293,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2313,7 +2313,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2333,7 +2333,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2360,7 +2360,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2387,7 +2387,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2414,7 +2414,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2441,7 +2441,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2468,7 +2468,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2495,7 +2495,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2522,7 +2522,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2549,7 +2549,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2576,7 +2576,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2603,7 +2603,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2630,7 +2630,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2653,7 +2653,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2676,7 +2676,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2700,7 +2700,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2724,7 +2724,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2748,7 +2748,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2768,7 +2768,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2792,7 +2792,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2812,7 +2812,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2832,7 +2832,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2859,7 +2859,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2883,7 +2883,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2907,7 +2907,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2931,7 +2931,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2955,7 +2955,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2979,7 +2979,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3003,7 +3003,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3027,7 +3027,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3051,7 +3051,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3075,7 +3075,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3099,7 +3099,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3119,7 +3119,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3139,7 +3139,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3166,7 +3166,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3190,7 +3190,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3214,7 +3214,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3234,7 +3234,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3258,7 +3258,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3278,7 +3278,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3298,7 +3298,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3325,7 +3325,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3352,7 +3352,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3379,7 +3379,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3402,7 +3402,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3425,7 +3425,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3449,7 +3449,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3473,7 +3473,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3497,7 +3497,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3521,7 +3521,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3545,7 +3545,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3569,7 +3569,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3593,7 +3593,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3617,7 +3617,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3641,7 +3641,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3665,7 +3665,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3689,7 +3689,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3709,7 +3709,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3729,7 +3729,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3756,7 +3756,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3783,7 +3783,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3810,7 +3810,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3833,7 +3833,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3860,7 +3860,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3883,7 +3883,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3906,7 +3906,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -4552,68 +4552,67 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+216
-21
@@ -137,7 +137,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -296,7 +296,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -407,7 +407,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -436,6 +436,101 @@
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:15667cfd</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:67c4611f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 22:33:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:67c4611f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
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||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:67c4611f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axi_crc_dma_syn_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 22:30:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:15667cfd</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axi_crc_dma_syn_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 22:30:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:67c4611f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -444,7 +539,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -456,7 +552,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -472,7 +569,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -488,7 +586,42 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>finalXOR</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>inOutReflected</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -500,7 +633,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -516,7 +650,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -531,7 +666,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -546,7 +682,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -558,7 +695,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -574,7 +712,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -586,7 +725,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -598,7 +738,8 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -615,6 +756,60 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.vhdl</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
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||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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||||
</spirit:file>
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||||
</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
@@ -631,12 +826,12 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -648,8 +843,8 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+8013
File diff suppressed because it is too large
Load Diff
+37
@@ -0,0 +1,37 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Feb 9 23:33:42 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_axis_crc_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_crc,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_axis_crc_0_0(CLK, RESETN, initial_value, polynomial, finalXOR,
|
||||
inOutReflected, S_AXIS_TVALID, S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID,
|
||||
M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="RESETN,initial_value[31:0],polynomial[31:0],finalXOR[31:0],inOutReflected[1:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY" */
|
||||
/* synthesis syn_force_seq_prim="CLK" */;
|
||||
input CLK /* synthesis syn_isclock = 1 */;
|
||||
input RESETN;
|
||||
input [31:0]initial_value;
|
||||
input [31:0]polynomial;
|
||||
input [31:0]finalXOR;
|
||||
input [1:0]inOutReflected;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
endmodule
|
||||
+130
@@ -0,0 +1,130 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_crc;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_crc
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0_arch;
|
||||
+138
@@ -0,0 +1,138 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_crc;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_crc_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_crc
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0_arch;
|
||||
+79
-45
@@ -1488,7 +1488,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e96bcc06</spirit:value>
|
||||
<spirit:value>9:338a2746</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1500,7 +1500,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:da7079bd</spirit:value>
|
||||
<spirit:value>9:2d5f1ca5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1514,11 +1514,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:33:28 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:42:00 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:da7079bd</spirit:value>
|
||||
<spirit:value>9:2d5f1ca5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1529,7 +1529,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:da7079bd</spirit:value>
|
||||
<spirit:value>9:2d5f1ca5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1545,11 +1545,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:20 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e96bcc06</spirit:value>
|
||||
<spirit:value>9:338a2746</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1565,11 +1565,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:20 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:da7079bd</spirit:value>
|
||||
<spirit:value>9:2d5f1ca5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1651,6 +1651,40 @@
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>finalXOR</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>inOutReflected</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>FIFO_NUM_FREE</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -2811,22 +2845,22 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2834,13 +2868,13 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2854,36 +2888,36 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+1938
-1174
File diff suppressed because it is too large
Load Diff
+15
-12
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Feb 9 12:33:27 2025
|
||||
// Date : Sun Feb 9 23:41:59 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v
|
||||
@@ -16,23 +16,26 @@
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_dma,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_axis_dma_0_0(CLK, RESETN, INTERRUPT, initial_value,
|
||||
polynomial, FIFO_NUM_FREE, FIFO_NUM_AVAIL, S_AXIL_AWADDR, S_AXIL_AWVALID, S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB, S_AXIL_BVALID, S_AXIL_BREADY,
|
||||
S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY, S_AXIL_RDATA, S_AXIL_RVALID,
|
||||
S_AXIL_RREADY, S_AXIL_RRESP, M_AXI_ARREADY, M_AXI_ARVALID, M_AXI_ARADDR, M_AXI_ARID,
|
||||
M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT, M_AXI_ARCACHE, M_AXI_RREADY,
|
||||
M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST, M_AXI_AWREADY, M_AXI_AWVALID,
|
||||
M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID, M_AXI_AWBURST, M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA, M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID,
|
||||
M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP, S_AXIS_TVALID, S_AXIS_TDATA,
|
||||
S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="RESETN,INTERRUPT,initial_value[31:0],polynomial[31:0],FIFO_NUM_FREE[7:0],FIFO_NUM_AVAIL[7:0],S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY" */
|
||||
polynomial, finalXOR, inOutReflected, FIFO_NUM_FREE, FIFO_NUM_AVAIL, S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP, M_AXI_ARREADY, M_AXI_ARVALID,
|
||||
M_AXI_ARADDR, M_AXI_ARID, M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE, M_AXI_RREADY, M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST,
|
||||
M_AXI_AWREADY, M_AXI_AWVALID, M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID,
|
||||
M_AXI_AWBURST, M_AXI_AWPROT, M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA,
|
||||
M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID, M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP,
|
||||
S_AXIS_TVALID, S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA,
|
||||
M_AXIS_TLAST, M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="RESETN,INTERRUPT,initial_value[31:0],polynomial[31:0],finalXOR[31:0],inOutReflected[1:0],FIFO_NUM_FREE[7:0],FIFO_NUM_AVAIL[7:0],S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY" */
|
||||
/* synthesis syn_force_seq_prim="CLK" */;
|
||||
input CLK /* synthesis syn_isclock = 1 */;
|
||||
input RESETN;
|
||||
output INTERRUPT;
|
||||
output [31:0]initial_value;
|
||||
output [31:0]polynomial;
|
||||
output [31:0]finalXOR;
|
||||
output [1:0]inOutReflected;
|
||||
input [7:0]FIFO_NUM_FREE;
|
||||
input [7:0]FIFO_NUM_AVAIL;
|
||||
input [7:0]S_AXIL_AWADDR;
|
||||
|
||||
+6
@@ -60,6 +60,8 @@ ENTITY axi_crc_dma_syn_1_axis_dma_0_0 IS
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
@@ -142,6 +144,8 @@ ARCHITECTURE axi_crc_dma_syn_1_axis_dma_0_0_arch OF axi_crc_dma_syn_1_axis_dma_0
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
@@ -294,6 +298,8 @@ BEGIN
|
||||
INTERRUPT => INTERRUPT,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
FIFO_NUM_FREE => FIFO_NUM_FREE,
|
||||
FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
|
||||
+6
@@ -60,6 +60,8 @@ ENTITY axi_crc_dma_syn_1_axis_dma_0_0 IS
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
@@ -142,6 +144,8 @@ ARCHITECTURE axi_crc_dma_syn_1_axis_dma_0_0_arch OF axi_crc_dma_syn_1_axis_dma_0
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
finalXOR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
inOutReflected : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
@@ -302,6 +306,8 @@ BEGIN
|
||||
INTERRUPT => INTERRUPT,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
FIFO_NUM_FREE => FIFO_NUM_FREE,
|
||||
FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
|
||||
+297
-13
@@ -36309,7 +36309,7 @@
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP1_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP1)) = 1) ">true</xilinx:isEnabled>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP1_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP1)) = 1) ">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
@@ -36333,7 +36333,7 @@
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP2_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2)) = 1) ">true</xilinx:isEnabled>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP2_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2)) = 1) ">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
@@ -36357,7 +36357,7 @@
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP3_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP3)) = 1) ">true</xilinx:isEnabled>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP3_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP3)) = 1) ">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
@@ -37741,6 +37741,13 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_ENET0_RESET_IO</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6104"><Select></spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET0_RESET_IO">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_ENET1_PERIPHERAL_ENABLE</spirit:name>
|
||||
@@ -38532,6 +38539,13 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_I2C0_RESET_IO</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6904"><Select></spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C0_RESET_IO">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PCW_I2C1_PERIPHERAL_ENABLE</spirit:name>
|
||||
@@ -40693,16 +40707,16 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_BRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_CACHE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_LOCK" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_PROT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_QOS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_RRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.ID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.MAX_BURST_LENGTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
@@ -40710,7 +40724,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.PROTOCOL" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
@@ -40724,6 +40738,8 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_HP0_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_APU_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
@@ -40732,6 +40748,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
@@ -40744,14 +40761,28 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_UART_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_USB0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_USB1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_APU_CLK_RATIO_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_APU_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ARMPLL_CTRL_FBDIV" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_CAN0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_GRP_CLK_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN1_GRP_CLK_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
@@ -40760,6 +40791,10 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CLK1_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CLK2_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CLK3_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CORE0_FIQ_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CORE0_IRQ_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CORE1_FIQ_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CORE1_IRQ_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CPU_CPU_6X4X_MAX_RANGE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CPU_CPU_PLL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_CPU_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
@@ -40780,18 +40815,26 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DDR_PORT1_HPR_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DDR_PORT2_HPR_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DDR_PORT3_HPR_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DDR_RAM_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DDR_RAM_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DM_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DQS_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_DQ_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_ENET0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET0_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET1_GRP_MDIO_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
@@ -40803,37 +40846,82 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_ENET_RESET_SELECT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_4K_TIMER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CAN0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CAN1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLK0_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLK1_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLK2_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLK3_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG0_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG1_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG2_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG3_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_DDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_CAN0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_CAN1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_ENET0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_ENET1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_GPIO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_I2C0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_I2C1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_PJTAG" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_SDIO0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_SDIO1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_SPI0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_SPI1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_SRAM_INT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_TRACE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_TTC0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_TTC1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_UART0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_UART1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_WDT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_ENET0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_ENET1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_GPIO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_I2C0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_I2C1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_MODEM_UART0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_MODEM_UART1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_PJTAG" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_PTP_ENET0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_PTP_ENET1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_QSPI" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_RST0_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_RST1_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_RST2_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_RST3_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_SDIO0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_SDIO1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_SMC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_SPI0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_SPI1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_TRACE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_TTC0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_TTC1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_UART0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_UART1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_USB0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_USB1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_EN_WDT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_DIVISOR1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK_CLK0_BUF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK_CLK1_BUF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK_CLK2_BUF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FCLK_CLK3_BUF" xilinx:valueSource="user"/>
|
||||
@@ -40845,20 +40933,38 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FPGA_FCLK1_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FPGA_FCLK2_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_FPGA_FCLK3_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GP0_EN_MODIFIABLE_TXN" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GP0_NUM_READ_THREADS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GP0_NUM_WRITE_THREADS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GP1_EN_MODIFIABLE_TXN" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GP1_NUM_READ_THREADS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GP1_NUM_WRITE_THREADS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_MIO_GPIO_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_MIO_GPIO_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C0_GRP_INT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C0_I2C0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C0_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C1_GRP_INT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C1_I2C1_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C1_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C_RESET_POLARITY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_I2C_RESET_SELECT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_IMPORT_BOARD_PRESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_INCLUDE_ACP_TRANS_CHECK" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_INCLUDE_TRACE_BUFFER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_IOPLL_CTRL_FBDIV" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_IO_IO_PLL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_IRQ_F2P_INTR" xilinx:valueSource="user"/>
|
||||
@@ -41079,12 +41185,42 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_MIO_9_IOTYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_MIO_9_PULLUP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_MIO_9_SLEW" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_MIO_PRIMITIVE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_MIO_TREE_PERIPHERALS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_MIO_TREE_SIGNALS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_FREQMHZ" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_THREAD_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_THREAD_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_AR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_CLR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_RC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_REA" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_RR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_WC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_WP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_GRP_D8_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_CEOE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_PC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_RC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_TR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_WC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_WP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS0_WE_TIME" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_CEOE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_PC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_RC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_TR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_WC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_WP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_CS1_WE_TIME" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_A25_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS0_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS1_ENABLE" xilinx:valueSource="user"/>
|
||||
@@ -41092,8 +41228,49 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_CEOE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_PC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_RC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_TR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_WE_TIME" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_CEOE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_PC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_RC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_TR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_WE_TIME" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_OVERRIDE_BASIC_CLOCK" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_CAN0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_CAN1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_CTI_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC2_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC3_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC4_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC5_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC6_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC7_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_DMAC_ABORT_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_ENET0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_ENET1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_GPIO_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_I2C0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_I2C1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_QSPI_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_SDIO0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_SDIO1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_SMC_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_SPI0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_SPI1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_UART0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_UART1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_USB0_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_P2F_USB1_INTR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY2" xilinx:valueSource="user"/>
|
||||
@@ -41102,13 +41279,16 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PACKAGE_NAME" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PERIPHERAL_BOARD_PRESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PJTAG_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PLL_BYPASSMODE_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PRESET_BANK0_VOLTAGE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PRESET_BANK1_VOLTAGE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PS7_SI_REV" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_IO1_ENABLE" xilinx:valueSource="user"/>
|
||||
@@ -41128,55 +41308,123 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD0_SD0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_VALID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SINGLE_QSPI_DATA_MODE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T2" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T3" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T4" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T5" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T6" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_VALID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_SPI0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_SPI1_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_VALID" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_ARUSER_VAL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_AWUSER_VAL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_FREQMHZ" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_FREQMHZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_ID_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_BUFFER_CLOCK_DELAY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_BUFFER_FIFO_SIZE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_GRP_16BIT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_GRP_2BIT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_GRP_32BIT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_GRP_4BIT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_GRP_8BIT_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_INTERNAL_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TRACE_PIPELINE_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC0_TTC0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TTC_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_BAUD_RATE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_UART0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_BAUD_RATE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_UART1_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
@@ -41256,20 +41504,56 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RCD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_GENERATE_SUMMARY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_USB0_IO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_BASEADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_HIGHADDR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_POLARITY" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_SELECT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_AXI_FABRIC_IDLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_AXI_NONSECURE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_CORESIGHT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_CROSS_TRIGGER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_CR_FABRIC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DDR_BYPASS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DEBUG" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DEFAULT_ACP_USER_VAL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DMA0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DMA1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DMA2" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_DMA3" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_EXPANDED_IOP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_HIGH_OCM" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_M_AXI_GP0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_M_AXI_GP1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_PROC_EVENT_BUS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_ACP" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_GP0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_GP1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP1" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP2" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP3" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_TRACE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USE_TRACE_DATA_EDGE_DETECTOR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_VALUE_SILVERSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_CLKSRC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
|
||||
+5
-13
@@ -1147,7 +1147,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:21 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1165,7 +1165,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:23:16 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:29:50 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1201,7 +1201,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:31:04 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:57 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1220,7 +1220,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:21 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1239,10 +1239,6 @@
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcb74394</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
@@ -1263,10 +1259,6 @@
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcb74394</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
@@ -1281,7 +1273,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:21 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+77072
-77072
File diff suppressed because it is too large
Load Diff
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sat Feb 8 17:01:45 2025
|
||||
// Date : Sun Feb 9 18:06:45 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_system_ila_0_0 -prefix
|
||||
// axi_crc_dma_syn_1_system_ila_0_0_ axi_crc_dma_syn_1_system_ila_0_0_stub.v
|
||||
|
||||
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_2505" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739100635"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739100635"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739100635"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739100635"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739140847"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739140847"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739140847"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739140847"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_2505.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+4
-4
@@ -1046,7 +1046,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:22 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:43 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1065,7 +1065,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:23 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:44 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1096,7 +1096,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:23 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:43 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1116,7 +1116,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:22 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:43 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:29 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:29 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:29 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:29 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:33 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:33 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:34 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:34 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:34 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:34 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -1276,7 +1276,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1296,7 +1296,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1319,7 +1319,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1339,7 +1339,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:32 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:32 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:32 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:32 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:32 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:32 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:33 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:33 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:33 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 09 11:30:33 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 09 22:40:46 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+1
-1
@@ -70,7 +70,7 @@ entity bd_2505 is
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
|
||||
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_2505 : entity is "axi_crc_dma_syn_1_system_ila_0_0.hwdef";
|
||||
end bd_2505;
|
||||
|
||||
+1
-1
@@ -70,7 +70,7 @@ entity bd_2505 is
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
|
||||
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_2505 : entity is "axi_crc_dma_syn_1_system_ila_0_0.hwdef";
|
||||
end bd_2505;
|
||||
|
||||
+2945
File diff suppressed because it is too large
Load Diff
+2945
File diff suppressed because it is too large
Load Diff
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axis_crc_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739118620"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1739118620"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739118620"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739118620"/>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739140074"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1739140074"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739140074"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739140074"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+32
@@ -493,6 +493,38 @@
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>finalXOR</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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<spirit:name>inOutReflected</spirit:name>
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<spirit:wire>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>S_AXIS_TVALID</spirit:name>
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<spirit:wire>
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@@ -145,7 +145,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:value>d4eba47a</spirit:value>
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<spirit:value>22ad4826</spirit:value>
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@@ -158,7 +158,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>d4eba47a</spirit:value>
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<spirit:value>22ad4826</spirit:value>
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@@ -232,6 +232,40 @@
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<spirit:port>
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<spirit:name>finalXOR</spirit:name>
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<spirit:wire>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>inOutReflected</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">1</spirit:left>
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<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>S_AXIS_TVALID</spirit:name>
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<spirit:wire>
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@@ -395,7 +429,7 @@
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<xilinx:designToolContext>IPI</xilinx:designToolContext>
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</xilinx:designToolContexts>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2025-02-09T16:30:18Z</xilinx:coreCreationDateTime>
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<xilinx:coreCreationDateTime>2025-02-09T22:28:00Z</xilinx:coreCreationDateTime>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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@@ -617,7 +617,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>49dac030</spirit:value>
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<spirit:value>f933c5bf</spirit:value>
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</spirit:parameter>
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@@ -630,7 +630,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>49dac030</spirit:value>
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<spirit:value>f933c5bf</spirit:value>
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</spirit:parameter>
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</spirit:view>
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@@ -720,6 +720,40 @@
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>finalXOR</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">31</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:port>
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<spirit:port>
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<spirit:name>inOutReflected</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long">1</spirit:left>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:port>
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<spirit:port>
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<spirit:name>FIFO_NUM_FREE</spirit:name>
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<spirit:wire>
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@@ -1837,7 +1871,7 @@
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<xilinx:designToolContext>IPI</xilinx:designToolContext>
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</xilinx:designToolContexts>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2025-02-09T11:26:22Z</xilinx:coreCreationDateTime>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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+196
-176
@@ -1,7 +1,7 @@
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{
|
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"design": {
|
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"design_info": {
|
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"boundary_crc": "0xCDBBA3AC8BB03EA5",
|
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"boundary_crc": "0xBC3680FA37F622D3",
|
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"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip",
|
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"name": "axi_crc_dma_ip",
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@@ -12,8 +12,8 @@
|
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"design_tree": {
|
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"axis_fifo_0": "",
|
||||
"axis_fifo_1": "",
|
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"axis_dma_0": "",
|
||||
"axis_crc_0": ""
|
||||
"axis_crc_0": "",
|
||||
"axis_dma_0": ""
|
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},
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"interface_ports": {
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"S_AXIL": {
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@@ -34,7 +34,7 @@
|
||||
"value": "0"
|
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},
|
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"CLK_DOMAIN": {
|
||||
"value": "axi_crc_dma_ip_CLK_0",
|
||||
"value": "axi_crc_dma_ip_CLK",
|
||||
"value_src": "default"
|
||||
},
|
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"DATA_WIDTH": {
|
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@@ -231,7 +231,7 @@
|
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"value_src": "const_prop"
|
||||
},
|
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"CLK_DOMAIN": {
|
||||
"value": "axi_crc_dma_ip_CLK_0",
|
||||
"value": "axi_crc_dma_ip_CLK",
|
||||
"value_src": "default"
|
||||
},
|
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"DATA_WIDTH": {
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@@ -550,6 +550,183 @@
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}
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}
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},
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"axis_crc_0": {
|
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"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
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"xci_name": "axi_crc_dma_ip_axis_crc_0_0",
|
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"xci_path": "ip\\axi_crc_dma_ip_axis_crc_0_0\\axi_crc_dma_ip_axis_crc_0_0.xci",
|
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"inst_hier_path": "axis_crc_0",
|
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"reference_info": {
|
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"ref_type": "hdl",
|
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"ref_name": "axis_crc",
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"boundary_crc": "0x0"
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},
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"interface_ports": {
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"M_AXIS": {
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"mode": "Master",
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"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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"value": "4",
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},
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"value_src": "constant"
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},
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"value_src": "constant"
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},
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},
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},
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},
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},
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"value_src": "constant"
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}
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"physical_name": "M_AXIS_TLAST",
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"physical_name": "M_AXIS_TVALID",
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"physical_name": "M_AXIS_TREADY",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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},
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"value_src": "constant"
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},
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"value_src": "constant"
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},
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"value_src": "constant"
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},
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},
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}
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},
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"left": "31",
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"right": "0"
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},
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"physical_name": "S_AXIS_TLAST",
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},
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"physical_name": "S_AXIS_TVALID",
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"direction": "I"
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},
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"TREADY": {
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"physical_name": "S_AXIS_TREADY",
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"direction": "O"
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}
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}
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}
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},
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"ports": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "M_AXIS:S_AXIS",
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"value_src": "constant"
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},
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"ASSOCIATED_RESET": {
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"value": "RESETN",
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"value_src": "constant"
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}
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}
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},
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"RESETN": {
|
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"type": "rst",
|
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"direction": "I",
|
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"parameters": {
|
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"POLARITY": {
|
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"value": "ACTIVE_LOW",
|
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"value_src": "constant"
|
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}
|
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}
|
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},
|
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"initial_value": {
|
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"direction": "I",
|
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"left": "31",
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"right": "0"
|
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},
|
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"polynomial": {
|
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"direction": "I",
|
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"left": "31",
|
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"right": "0"
|
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},
|
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"finalXOR": {
|
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"direction": "I",
|
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"left": "31",
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"right": "0"
|
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},
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"inOutReflected": {
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"direction": "I",
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"left": "1",
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"right": "0"
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}
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}
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},
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"axis_dma_0": {
|
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"vlnv": "xilinx.com:module_ref:axis_dma:1.0",
|
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"xci_name": "axi_crc_dma_ip_axis_dma_0_0",
|
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@@ -1196,6 +1373,16 @@
|
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"left": "31",
|
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"right": "0"
|
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},
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"finalXOR": {
|
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"direction": "O",
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"left": "31",
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"right": "0"
|
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},
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"inOutReflected": {
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"direction": "O",
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"left": "1",
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"right": "0"
|
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},
|
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"FIFO_NUM_FREE": {
|
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"direction": "I",
|
||||
"left": "7",
|
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@@ -1215,173 +1402,6 @@
|
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}
|
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}
|
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}
|
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},
|
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"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axi_crc_dma_ip_axis_crc_0_0",
|
||||
"xci_path": "ip\\axi_crc_dma_ip_axis_crc_0_0\\axi_crc_dma_ip_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
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"TDATA_NUM_BYTES": {
|
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"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
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"TDEST_WIDTH": {
|
||||
"value": "0",
|
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"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
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"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
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"HAS_TKEEP": {
|
||||
"value": "0",
|
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"value_src": "constant"
|
||||
},
|
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"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
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}
|
||||
},
|
||||
"port_maps": {
|
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"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
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"left": "31",
|
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"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
@@ -1430,8 +1450,8 @@
|
||||
"axis_fifo_1/M_AXIS_ACLK",
|
||||
"axis_fifo_0/S_AXIS_ACLK",
|
||||
"axis_fifo_0/M_AXIS_ACLK",
|
||||
"axis_dma_0/CLK",
|
||||
"axis_crc_0/CLK"
|
||||
"axis_crc_0/CLK",
|
||||
"axis_dma_0/CLK"
|
||||
]
|
||||
},
|
||||
"RESETN_0_1": {
|
||||
@@ -1441,8 +1461,8 @@
|
||||
"axis_fifo_0/M_AXIS_ARESETN",
|
||||
"axis_fifo_1/M_AXIS_ARESETN",
|
||||
"axis_fifo_1/S_AXIS_ARESETN",
|
||||
"axis_dma_0/RESETN",
|
||||
"axis_crc_0/RESETN"
|
||||
"axis_crc_0/RESETN",
|
||||
"axis_dma_0/RESETN"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_initial_value": {
|
||||
|
||||
+2
@@ -40,6 +40,8 @@
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
|
||||
+38
-36
@@ -55,6 +55,8 @@
|
||||
"INTERRUPT": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"initial_value": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"FIFO_NUM_FREE": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"FIFO_NUM_AVAIL": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
@@ -177,25 +179,25 @@
|
||||
"address_space_ref": "M_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -251,26 +253,26 @@
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+4
-4
@@ -81,7 +81,7 @@
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -108,7 +108,7 @@
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -154,7 +154,7 @@
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -172,7 +172,7 @@
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
|
||||
+4
-4
@@ -81,7 +81,7 @@
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -108,7 +108,7 @@
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -154,7 +154,7 @@
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -172,7 +172,7 @@
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK_0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_ip_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
|
||||
+14
-14
@@ -6,27 +6,27 @@
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port S_AXIL -pg 1 -lvl 0 -x -10 -y 290 -defaultsOSRD
|
||||
preplace port M_AXI -pg 1 -lvl 5 -x 1390 -y 300 -defaultsOSRD
|
||||
preplace port M_AXI -pg 1 -lvl 5 -x 1440 -y 300 -defaultsOSRD
|
||||
preplace port port-id_CLK -pg 1 -lvl 0 -x -10 -y 90 -defaultsOSRD
|
||||
preplace port port-id_RESETN -pg 1 -lvl 0 -x -10 -y 120 -defaultsOSRD
|
||||
preplace inst axis_fifo_0 -pg 1 -lvl 1 -x 180 -y 110 -defaultsOSRD
|
||||
preplace inst axis_fifo_1 -pg 1 -lvl 3 -x 820 -y 170 -defaultsOSRD
|
||||
preplace inst axis_dma_0 -pg 1 -lvl 4 -x 1170 -y 320 -defaultsOSRD
|
||||
preplace inst axis_fifo_1 -pg 1 -lvl 3 -x 850 -y 170 -defaultsOSRD
|
||||
preplace inst axis_crc_0 -pg 1 -lvl 2 -x 510 -y 130 -defaultsOSRD
|
||||
preplace netloc CLK_0_1 1 0 4 10 10 350 10 660 70 1000J
|
||||
preplace netloc RESETN_0_1 1 0 4 20 210 350 240 670 280 970J
|
||||
preplace netloc axis_dma_0_initial_value 1 1 4 360 20 NJ 20 NJ 20 1350
|
||||
preplace netloc axis_dma_0_polynomial 1 1 4 370 30 NJ 30 NJ 30 1360
|
||||
preplace inst axis_dma_0 -pg 1 -lvl 4 -x 1210 -y 320 -defaultsOSRD
|
||||
preplace netloc CLK_0_1 1 0 4 10 10 360 10 680 40 1030J
|
||||
preplace netloc RESETN_0_1 1 0 4 20 210 340 280 700 280 1000J
|
||||
preplace netloc axis_dma_0_initial_value 1 1 4 350 270 670J 50 NJ 50 1410
|
||||
preplace netloc axis_dma_0_polynomial 1 1 4 360 260 690J 70 NJ 70 1390
|
||||
preplace netloc axis_fifo_0_S_NUM_FREE 1 1 3 330 350 NJ 350 NJ
|
||||
preplace netloc axis_fifo_1_M_NUM_AVAIL 1 3 1 980 190n
|
||||
preplace netloc axis_fifo_1_M_NUM_AVAIL 1 3 1 1010 190n
|
||||
preplace netloc S_AXIL_0_1 1 0 4 NJ 290 NJ 290 NJ 290 NJ
|
||||
preplace netloc axis_crc_0_M_AXIS 1 2 1 N 130
|
||||
preplace netloc axis_dma_0_M_AXI 1 4 1 N 300
|
||||
preplace netloc axis_dma_0_M_AXIS 1 0 5 30 230 NJ 230 650J 60 NJ 60 1340
|
||||
preplace netloc axis_fifo_0_M_AXIS 1 1 1 N 90
|
||||
preplace netloc axis_fifo_1_M_AXIS 1 3 1 990 150n
|
||||
levelinfo -pg 1 -10 180 510 820 1170 1390
|
||||
pagesize -pg 1 -db -bbox -sgen -110 0 1480 430
|
||||
preplace netloc axis_dma_0_M_AXI 1 4 1 1420 280n
|
||||
preplace netloc axis_dma_0_M_AXIS 1 0 5 30 250 NJ 250 660J 60 NJ 60 1400
|
||||
preplace netloc axis_fifo_0_M_AXIS 1 1 1 330 70n
|
||||
preplace netloc axis_fifo_1_M_AXIS 1 3 1 1020 150n
|
||||
levelinfo -pg 1 -10 180 510 850 1210 1440
|
||||
pagesize -pg 1 -db -bbox -sgen -110 0 1530 440
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
+212
-175
@@ -7,14 +7,15 @@
|
||||
"name": "axi_crc_dma_sim_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1"
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axi_crc_dma": {
|
||||
"axis_fifo_0": "",
|
||||
"axis_fifo_1": "",
|
||||
"axis_dma_0": "",
|
||||
"axis_crc_0": ""
|
||||
"axis_crc_0": "",
|
||||
"axis_dma_0": ""
|
||||
},
|
||||
"axil_master_with_rom_0": "",
|
||||
"clk_rst_generator_0": "",
|
||||
@@ -71,6 +72,183 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axi_crc_dma_sim_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\axi_crc_dma_sim_1_axis_crc_0_0\\axi_crc_dma_sim_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axi_crc_dma/axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"finalXOR": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"inOutReflected": {
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_dma_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_dma:1.0",
|
||||
"xci_name": "axi_crc_dma_sim_1_axis_dma_0_0",
|
||||
@@ -704,6 +882,10 @@
|
||||
"SENSITIVITY": {
|
||||
"value": "LEVEL_HIGH",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PortWidth": {
|
||||
"value": "1",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
@@ -717,6 +899,16 @@
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"finalXOR": {
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"inOutReflected": {
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"FIFO_NUM_FREE": {
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
@@ -736,173 +928,6 @@
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axi_crc_dma_sim_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\axi_crc_dma_sim_1_axis_crc_0_0\\axi_crc_dma_sim_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axi_crc_dma/axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
@@ -951,8 +976,8 @@
|
||||
"axis_fifo_0/S_AXIS_ACLK",
|
||||
"axis_fifo_1/S_AXIS_ACLK",
|
||||
"axis_fifo_1/M_AXIS_ACLK",
|
||||
"axis_dma_0/CLK",
|
||||
"axis_crc_0/CLK"
|
||||
"axis_crc_0/CLK",
|
||||
"axis_dma_0/CLK"
|
||||
]
|
||||
},
|
||||
"RESETN_1": {
|
||||
@@ -962,8 +987,8 @@
|
||||
"axis_fifo_1/S_AXIS_ARESETN",
|
||||
"axis_fifo_1/M_AXIS_ARESETN",
|
||||
"axis_fifo_0/S_AXIS_ARESETN",
|
||||
"axis_dma_0/RESETN",
|
||||
"axis_crc_0/RESETN"
|
||||
"axis_crc_0/RESETN",
|
||||
"axis_dma_0/RESETN"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_INTERRUPT": {
|
||||
@@ -972,6 +997,18 @@
|
||||
"INTERRUPT"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_finalXOR": {
|
||||
"ports": [
|
||||
"axis_dma_0/finalXOR",
|
||||
"axis_crc_0/finalXOR"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_inOutReflected": {
|
||||
"ports": [
|
||||
"axis_dma_0/inOutReflected",
|
||||
"axis_crc_0/inOutReflected"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_initial_value": {
|
||||
"ports": [
|
||||
"axis_dma_0/initial_value",
|
||||
@@ -1005,7 +1042,7 @@
|
||||
"inst_hier_path": "axil_master_with_rom_0",
|
||||
"parameters": {
|
||||
"REVISION_NO": {
|
||||
"value": "20"
|
||||
"value": "21"
|
||||
},
|
||||
"STIM_FILENAME": {
|
||||
"value": "../../axi_crc_dma_sim.mem"
|
||||
|
||||
+2
-2
@@ -12,13 +12,13 @@
|
||||
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
"REVISION_NO": [ { "value": "21", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
"REVISION_NO": [ { "value": "21", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
|
||||
+2
@@ -40,6 +40,8 @@
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
|
||||
+40
-38
@@ -2,7 +2,7 @@
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axi_crc_dma_sim_1_axis_dma_0_0",
|
||||
"cell_name": "axi_crc_dma/axis_dma_0",
|
||||
"cell_name": "axis_dma_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_dma:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0",
|
||||
@@ -55,6 +55,8 @@
|
||||
"INTERRUPT": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"initial_value": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"FIFO_NUM_FREE": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"FIFO_NUM_AVAIL": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
@@ -177,25 +179,25 @@
|
||||
"address_space_ref": "M_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -251,26 +253,26 @@
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -339,7 +341,7 @@
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "INTERRUPT" } ]
|
||||
|
||||
+12
-12
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.56016",
|
||||
"Default View_TopLeft":"-10,-137",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"-98,-239",
|
||||
"Display-PortTypeOthers":"true",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_ExpandedHierarchyInLayout":"",
|
||||
@@ -19,17 +19,17 @@ pagesize -pg 1 -db -bbox -sgen 0 0 1990 480
|
||||
"Interfaces View_TopLeft":"-199,-369",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 660 -y 110 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 360 -y 100 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 90 -y 100 -defaultsOSRD
|
||||
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 897 -y 120 -defaultsOSRD
|
||||
preplace netloc axi_crc_dma_INTERRUPT 1 1 3 240 20 NJ 20 770
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 240 180 540 180 780J
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 230 190 550 190 790J
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 650 -y 110 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 360 -y 90 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 100 -defaultsOSRD
|
||||
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 887 -y 120 -defaultsOSRD
|
||||
preplace netloc axi_crc_dma_INTERRUPT 1 1 3 240 180 NJ 180 760
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 220 170 540 30 770J
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 230 10 530 20 780J
|
||||
preplace netloc axi_crc_dma_M_AXI 1 3 1 N 100
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 480 90n
|
||||
levelinfo -pg 1 -20 90 360 660 897 1000
|
||||
pagesize -pg 1 -db -bbox -sgen -20 -140 2290 540
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 N 90
|
||||
levelinfo -pg 1 0 110 360 650 887 980
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 2360 660
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
+231
-174
@@ -7,14 +7,15 @@
|
||||
"name": "axi_crc_dma_syn_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1"
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axi_crc_dma": {
|
||||
"axis_fifo_1": "",
|
||||
"axis_fifo_0": "",
|
||||
"axis_dma_0": "",
|
||||
"axis_crc_0": ""
|
||||
"axis_crc_0": "",
|
||||
"axis_dma_0": ""
|
||||
},
|
||||
"PS": {
|
||||
"processing_system7_0": "",
|
||||
@@ -252,6 +253,207 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axi_crc_dma_syn_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\axi_crc_dma_syn_1_axis_crc_0_0\\axi_crc_dma_syn_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axi_crc_dma/axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "user_prop"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "user_prop"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "user_prop"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"finalXOR": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"inOutReflected": {
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_dma_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_dma:1.0",
|
||||
"xci_name": "axi_crc_dma_syn_1_axis_dma_0_0",
|
||||
@@ -950,6 +1152,16 @@
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"finalXOR": {
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"inOutReflected": {
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"FIFO_NUM_FREE": {
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
@@ -969,173 +1181,6 @@
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axi_crc_dma_syn_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\axi_crc_dma_syn_1_axis_crc_0_0\\axi_crc_dma_syn_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axi_crc_dma/axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
@@ -1201,6 +1246,18 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_dma_0_finalXOR": {
|
||||
"ports": [
|
||||
"axis_dma_0/finalXOR",
|
||||
"axis_crc_0/finalXOR"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_inOutReflected": {
|
||||
"ports": [
|
||||
"axis_dma_0/inOutReflected",
|
||||
"axis_crc_0/inOutReflected"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_initial_value": {
|
||||
"ports": [
|
||||
"axis_dma_0/initial_value",
|
||||
@@ -1232,8 +1289,8 @@
|
||||
"axis_fifo_0/S_AXIS_ACLK",
|
||||
"axis_fifo_1/M_AXIS_ACLK",
|
||||
"axis_fifo_1/S_AXIS_ACLK",
|
||||
"axis_dma_0/CLK",
|
||||
"axis_crc_0/CLK"
|
||||
"axis_crc_0/CLK",
|
||||
"axis_dma_0/CLK"
|
||||
]
|
||||
},
|
||||
"rst_ps7_0_100M_peripheral_aresetn": {
|
||||
@@ -1243,8 +1300,8 @@
|
||||
"axis_fifo_0/S_AXIS_ARESETN",
|
||||
"axis_fifo_1/M_AXIS_ARESETN",
|
||||
"axis_fifo_1/S_AXIS_ARESETN",
|
||||
"axis_dma_0/RESETN",
|
||||
"axis_crc_0/RESETN"
|
||||
"axis_crc_0/RESETN",
|
||||
"axis_dma_0/RESETN"
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
|
||||
+34
-34
@@ -132,26 +132,26 @@
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -210,26 +210,26 @@
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -289,7 +289,7 @@
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
|
||||
+8
-6
@@ -40,6 +40,8 @@
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
@@ -63,9 +65,9 @@
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -89,9 +91,9 @@
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
@@ -121,10 +123,10 @@
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
|
||||
+39
-37
@@ -2,7 +2,7 @@
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axi_crc_dma_syn_1_axis_dma_0_0",
|
||||
"cell_name": "axi_crc_dma/axis_dma_0",
|
||||
"cell_name": "axis_dma_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_dma:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0",
|
||||
@@ -55,6 +55,8 @@
|
||||
"INTERRUPT": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"initial_value": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"FIFO_NUM_FREE": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"FIFO_NUM_AVAIL": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
@@ -177,25 +179,25 @@
|
||||
"address_space_ref": "M_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -251,26 +253,26 @@
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+282
-282
@@ -8,43 +8,43 @@
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_DDR_RAM_HIGHADDR": [ { "value": "0x3FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_ENET1_HIGHADDR": [ { "value": "0xE000CFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SDIO0_BASEADDR": [ { "value": "0xE0100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SDIO0_HIGHADDR": [ { "value": "0xE0100FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SDIO1_BASEADDR": [ { "value": "0xE0101000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SDIO1_HIGHADDR": [ { "value": "0xE0101FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB0_BASEADDR": [ { "value": "0xE0102000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_USB0_HIGHADDR": [ { "value": "0xE0102fff", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_USB1_BASEADDR": [ { "value": "0xE0103000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB1_HIGHADDR": [ { "value": "0xE0103fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_ENET1_HIGHADDR": [ { "value": "0xE000CFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SDIO0_BASEADDR": [ { "value": "0xE0100000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SDIO0_HIGHADDR": [ { "value": "0xE0100FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SDIO1_BASEADDR": [ { "value": "0xE0101000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SDIO1_HIGHADDR": [ { "value": "0xE0101FFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB0_BASEADDR": [ { "value": "0xE0102000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_USB0_HIGHADDR": [ { "value": "0xE0102fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_USB1_BASEADDR": [ { "value": "0xE0103000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB1_HIGHADDR": [ { "value": "0xE0103fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "value_src": "user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK_CLK1_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK_CLK2_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK_CLK3_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -119,22 +119,22 @@
|
||||
"PCW_QSPI_PERIPHERAL_FREQMHZ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_SMC_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB0_PERIPHERAL_FREQMHZ": [ { "value": "60", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SDIO_PERIPHERAL_FREQMHZ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_UART_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_FREQMHZ": [ { "value": "166.666666", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "-1", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "-1", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "-1", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "-1", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -148,17 +148,17 @@
|
||||
"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "125.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_USB0_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_USB0_PERIPHERAL_FREQMHZ": [ { "value": "60", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": [ { "value": "50.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": [ { "value": "100.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_I2C_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_I2C_PERIPHERAL_FREQMHZ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "100.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -201,60 +201,60 @@
|
||||
"PCW_DCI_PERIPHERAL_DIVISOR0": [ { "value": "15", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DCI_PERIPHERAL_DIVISOR1": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_PCAP_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ARMPLL_CTRL_FBDIV": [ { "value": "40", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IOPLL_CTRL_FBDIV": [ { "value": "30", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DDRPLL_CTRL_FBDIV": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CPU_CPU_PLL_FREQMHZ": [ { "value": "1333.333", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IO_IO_PLL_FREQMHZ": [ { "value": "1000.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DDR_DDR_PLL_FREQMHZ": [ { "value": "1066.667", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SMC_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_SMC_PERIPHERAL_VALID": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_SDIO_PERIPHERAL_VALID": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_VALID": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_VALID": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_UART_PERIPHERAL_VALID": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CAN0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CAN1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_PTP_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_PTP_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_GPIO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CAN1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_ENET0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_ENET1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_PTP_ENET0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_PTP_ENET1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_GPIO": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_I2C0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_I2C1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CD_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_PJTAG": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SDIO0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CD_SDIO0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_WP_SDIO0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CD_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_WP_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CD_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_WP_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SPI0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SPI1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_UART0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_MODEM_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_MODEM_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_UART1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_MODEM_UART0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_MODEM_UART1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_TTC0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_TTC1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_WDT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_TTC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_WDT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_TRACE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_AXI_NONSECURE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_M_AXI_GP0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_M_AXI_GP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_GP0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_GP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_ACP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_M_AXI_GP1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_GP0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_GP1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_ACP": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP2": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP3": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "100", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -264,16 +264,16 @@
|
||||
"PCW_S_AXI_HP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP2_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_DMA0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DMA1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DMA2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DMA3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_TRACE_PIPELINE_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_INCLUDE_TRACE_BUFFER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_BUFFER_FIFO_SIZE": [ { "value": "128", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_TRACE_DATA_EDGE_DETECTOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_BUFFER_CLOCK_DELAY": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_DMA0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DMA1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DMA2": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DMA3": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_TRACE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_TRACE_PIPELINE_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_INCLUDE_TRACE_BUFFER": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_BUFFER_FIFO_SIZE": [ { "value": "128", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_TRACE_DATA_EDGE_DETECTOR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_BUFFER_CLOCK_DELAY": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_CROSS_TRIGGER": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FTM_CTI_IN0": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FTM_CTI_IN1": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -283,129 +283,129 @@
|
||||
"PCW_FTM_CTI_OUT1": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FTM_CTI_OUT2": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FTM_CTI_OUT3": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_DEBUG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_CR_FABRIC": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_AXI_FABRIC_IDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DDR_BYPASS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DEBUG": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_CR_FABRIC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_AXI_FABRIC_IDLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DDR_BYPASS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_FABRIC_INTERRUPT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_PROC_EVENT_BUS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_EXPANDED_IOP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_HIGH_OCM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_PS_SLCR_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_EXPANDED_PS_SLCR_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_CORESIGHT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SRAM_INT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GPIO_EMIO_GPIO_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_GP0_NUM_WRITE_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP0_NUM_READ_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_NUM_WRITE_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_NUM_READ_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_UART0_BAUD_RATE": [ { "value": "115200", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_PROC_EVENT_BUS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_EXPANDED_IOP": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_HIGH_OCM": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_PS_SLCR_REGISTERS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_EXPANDED_PS_SLCR_REGISTERS": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USE_CORESIGHT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SRAM_INT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GPIO_EMIO_GPIO_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_GP0_NUM_WRITE_THREADS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP0_NUM_READ_THREADS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_NUM_WRITE_THREADS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_NUM_READ_THREADS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_UART0_BAUD_RATE": [ { "value": "115200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_UART1_BAUD_RATE": [ { "value": "115200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_4K_TIMER": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP0_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP1_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_ACP_ID_WIDTH": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_INCLUDE_ACP_TRANS_CHECK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DEFAULT_ACP_USER_VAL": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_ACP_ARUSER_VAL": [ { "value": "31", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_ACP_AWUSER_VAL": [ { "value": "31", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP0_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ID_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_THREAD_ID_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_ID_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_ENABLE_STATIC_REMAP": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_SUPPORT_NARROW_BURST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_THREAD_ID_WIDTH": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP0_ID_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP1_ID_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_ACP_ID_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_INCLUDE_ACP_TRANS_CHECK": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DEFAULT_ACP_USER_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_ACP_ARUSER_VAL": [ { "value": "31", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_ACP_AWUSER_VAL": [ { "value": "31", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP0_ID_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP0_DATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP1_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP1_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP2_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP2_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP1_ID_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP1_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP2_ID_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP2_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_ID_WIDTH": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_NUM_F2P_INTR_INPUTS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_DDR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SMC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_DDR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SMC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_QSPI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CAN0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CAN1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CAN1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_ENET0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_ENET1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_GPIO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_I2C0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_I2C1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_PJTAG": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SDIO0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SPI0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SPI1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_UART0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_UART1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_MODEM_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_MODEM_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_MODEM_UART0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_MODEM_UART1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_TTC0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_TTC1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_WDT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_TTC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_WDT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_TRACE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_USB0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_USB1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_DQ_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_DQS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_DM_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_MIO_PRIMITIVE": [ { "value": "54", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLK0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_USB1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_DQ_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_DQS_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_DM_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_MIO_PRIMITIVE": [ { "value": "54", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLK0_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLK1_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLK2_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLK3_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG0_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_DMAC_ABORT_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC2_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC3_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC4_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC5_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC6_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC7_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_SMC_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_QSPI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CTI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_GPIO_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_USB0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_ENET0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_SDIO0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_I2C0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_SPI0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_UART0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CAN0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_USB1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_ENET1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_SDIO1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_I2C1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_SPI1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_UART1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CAN1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_EN_RST0_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST1_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST2_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_RST3_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG0_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG1_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG2_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_CLKTRIG3_PORT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_DMAC_ABORT_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC2_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC3_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC4_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC5_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC6_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC7_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_SMC_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_QSPI_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CTI_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_GPIO_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_USB0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_ENET0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_SDIO0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_I2C0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_SPI0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_UART0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CAN0_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_USB1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_ENET1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_SDIO1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_I2C1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_SPI1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_UART1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CAN1_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IRQ_F2P_INTR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_IRQ_F2P_MODE": [ { "value": "DIRECT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CORE0_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE0_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE1_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE1_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_VALUE_SILVERSION": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP0_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_IMPORT_BOARD_PRESET": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PERIPHERAL_BOARD_PRESET": [ { "value": "part0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CORE0_FIQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE0_IRQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE1_FIQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE1_IRQ_INTR": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_VALUE_SILVERSION": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP0_EN_MODIFIABLE_TXN": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_EN_MODIFIABLE_TXN": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_IMPORT_BOARD_PRESET": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PERIPHERAL_BOARD_PRESET": [ { "value": "part0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PRESET_BANK0_VOLTAGE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PRESET_BANK1_VOLTAGE": [ { "value": "LVCMOS 1.8V", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_UIPARAM_DDR_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -479,7 +479,7 @@
|
||||
"PCW_ENET_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_ENET1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET1_ENET1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_ENET1_GRP_MDIO_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -494,13 +494,13 @@
|
||||
"PCW_SD0_GRP_WP_IO": [ { "value": "EMIO", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SD0_GRP_POW_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SD0_GRP_POW_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SD1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SD1_SD1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_CD_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_CD_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_CD_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_WP_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_WP_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_WP_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_POW_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_POW_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SD1_GRP_POW_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_UART0_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_UART0_UART0_IO": [ { "value": "MIO 10 .. 11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -530,28 +530,28 @@
|
||||
"PCW_CAN0_CAN0_IO": [ { "value": "<Select>", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_GRP_CLK_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_GRP_CLK_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN1_CAN1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_GRP_CLK_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_GRP_CLK_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN1_GRP_CLK_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TRACE_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TRACE_TRACE_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_2BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_2BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_2BIT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_4BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_4BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_4BIT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_8BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_8BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_8BIT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_16BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_16BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_16BIT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_32BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_32BIT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_GRP_32BIT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TRACE_INTERNAL_WIDTH": [ { "value": "2", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TRACE_INTERNAL_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_WDT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_TTC0_IO": [ { "value": "EMIO", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_TTC1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_PJTAG_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PJTAG_PJTAG_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -561,7 +561,7 @@
|
||||
"PCW_USB_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_USB0_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_USB0_RESET_IO": [ { "value": "MIO 46", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_USB1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_USB1_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_USB1_USB1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_USB1_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -570,7 +570,7 @@
|
||||
"PCW_I2C0_GRP_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C0_GRP_INT_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C0_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C0_RESET_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C1_I2C1_IO": [ { "value": "MIO 12 .. 13", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C1_GRP_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -582,7 +582,7 @@
|
||||
"PCW_GPIO_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_GPIO_MIO_GPIO_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_GPIO_MIO_GPIO_IO": [ { "value": "MIO", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_GPIO_EMIO_GPIO_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_GPIO_EMIO_GPIO_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_GPIO_EMIO_GPIO_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_APU_CLK_RATIO_ENABLE": [ { "value": "6:2:1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "1000 Mbps", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -593,29 +593,29 @@
|
||||
"PCW_QSPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SDIO_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_UART_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK0_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK1_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK2_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK3_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK0_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK1_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK2_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FCLK3_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET0_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET1_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN0_PERIPHERAL_CLKSRC": [ { "value": "External", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN1_PERIPHERAL_CLKSRC": [ { "value": "External", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN0_PERIPHERAL_CLKSRC": [ { "value": "External", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CAN1_PERIPHERAL_CLKSRC": [ { "value": "External", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TPIU_PERIPHERAL_CLKSRC": [ { "value": "External", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK1_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK1_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_CLKSRC": [ { "value": "CPU_1X", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_DCI_PERIPHERAL_CLKSRC": [ { "value": "DDR PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PCAP_PERIPHERAL_CLKSRC": [ { "value": "IO PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_USB_RESET_POLARITY": [ { "value": "Active Low", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ENET_RESET_POLARITY": [ { "value": "Active Low", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C_RESET_POLARITY": [ { "value": "Active Low", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_I2C_RESET_POLARITY": [ { "value": "Active Low", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_MIO_0_PULLUP": [ { "value": "enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_MIO_0_IOTYPE": [ { "value": "LVCMOS 3.3V", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_MIO_0_DIRECTION": [ { "value": "inout", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -833,57 +833,57 @@
|
||||
"PCW_MIO_53_DIRECTION": [ { "value": "inout", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_MIO_53_SLEW": [ { "value": "slow", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"preset": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_UIPARAM_GENERATE_SUMMARY": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_UIPARAM_GENERATE_SUMMARY": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_MIO_TREE_PERIPHERALS": [ { "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#UART 0#UART 0#I2C 1#I2C 1#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_MIO_TREE_SIGNALS": [ { "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#rx#tx#scl#sda#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PS7_SI_REV": [ { "value": "PRODUCTION", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PS7_SI_REV": [ { "value": "PRODUCTION", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FPGA_FCLK0_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FPGA_FCLK1_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FPGA_FCLK2_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_FPGA_FCLK3_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_TR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_PC": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_WP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_CEOE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_WC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_RC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_WE_TIME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_TR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_PC": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_WP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_CEOE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_WC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_RC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_WE_TIME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_TR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_PC": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_WP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_CEOE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_WC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_RC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_WE_TIME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_TR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_PC": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_WP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_CEOE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_WC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_RC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_WE_TIME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_RR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_AR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_CLR": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_WP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_REA": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_WC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_RC": [ { "value": "11", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T0": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T1": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T2": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T3": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T4": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T5": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T6": [ { "value": "NA", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PACKAGE_NAME": [ { "value": "clg400", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_TR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_PC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_WP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_CEOE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_WC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_T_RC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS0_WE_TIME": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_TR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_PC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_WP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_CEOE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_WC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_T_RC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_SRAM_CS1_WE_TIME": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_TR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_PC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_WP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_CEOE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_WC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_T_RC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS0_WE_TIME": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_TR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_PC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_WP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_CEOE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_WC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_T_RC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NOR_CS1_WE_TIME": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_RR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_AR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_CLR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_WP": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_REA": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_WC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_NAND_CYCLES_T_RC": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T0": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T1": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T2": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T3": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T4": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T5": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SMC_CYCLE_T6": [ { "value": "NA", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PACKAGE_NAME": [ { "value": "clg400", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_PLL_BYPASSMODE_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
@@ -1266,23 +1266,23 @@
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "6", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "6", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+35
-17
@@ -1,24 +1,42 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.93601",
|
||||
"Default View_TopLeft":"30,1",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"Default View_ScaleFactor":"1.57143",
|
||||
"Default View_TopLeft":"689,339",
|
||||
"ExpandedHierarchyInLayout":"/PS",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 3 -x 720 -y 250 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 3 -x 720 -y 280 -defaultsOSRD
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 1 -x 190 -y 150 -defaultsOSRD
|
||||
preplace inst PS -pg 1 -lvl 2 -x 530 -y 300 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 2 -x 530 -y 110 -defaultsOSRD
|
||||
preplace netloc axi_crc_dma_INTERRUPT1 1 1 1 380 140n
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 60 70 360 400 670
|
||||
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 3 40 50 390 410 660
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 3 50 60 400 390 680
|
||||
preplace netloc axis_dma_0_M_AXI 1 1 1 370 80n
|
||||
preplace netloc processing_system7_0_DDR 1 2 1 680J 250n
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 2 1 NJ 280
|
||||
levelinfo -pg 1 0 190 530 720
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 830 420
|
||||
preplace port DDR -pg 1 -lvl 3 -x 1830 -y 350 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 3 -x 1830 -y 380 -defaultsOSRD
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 1 -x 190 -y 230 -defaultsOSRD
|
||||
preplace inst PS -pg 1 -lvl 2 -x 570 -y 402 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 2 -x 570 -y 210 -defaultsOSRD
|
||||
preplace inst PS|processing_system7_0 -pg 1 -lvl 2 -x 1050 -y 532 -defaultsOSRD
|
||||
preplace inst PS|rst_ps7_0_100M -pg 1 -lvl 2 -x 1050 -y 832 -defaultsOSRD
|
||||
preplace inst PS|xlconstant_0 -pg 1 -lvl 2 -x 1050 -y 972 -defaultsOSRD
|
||||
preplace inst PS|axi_mem_intercon -pg 1 -lvl 1 -x 670 -y 512 -defaultsOSRD
|
||||
preplace inst PS|axi_interconnect_0 -pg 1 -lvl 3 -x 1440 -y 562 -defaultsOSRD
|
||||
preplace netloc axi_crc_dma_INTERRUPT1 1 1 1 370 240n
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 130 360 90 1790
|
||||
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 3 40 150 350 1054 1780
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 3 30 140 370 100 1780
|
||||
preplace netloc axis_dma_0_M_AXI 1 1 1 340 180n
|
||||
preplace netloc processing_system7_0_DDR 1 2 1 1800 350n
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 2 1 1810 380n
|
||||
preplace netloc PS|IRQ_F2P_1 1 0 2 NJ 652 830
|
||||
preplace netloc PS|processing_system7_0_FCLK_CLK0 1 0 4 500 642 820 722 1290 682 NJ
|
||||
preplace netloc PS|processing_system7_0_FCLK_RESET0_N 1 1 2 830 732 1270
|
||||
preplace netloc PS|rst_ps7_0_100M_peripheral_aresetn 1 0 4 510 632 810J 342 1300 702 NJ
|
||||
preplace netloc PS|xlconstant_0_dout 1 2 1 1280 462n
|
||||
preplace netloc PS|axi_interconnect_0_M00_AXI 1 3 1 N 562
|
||||
preplace netloc PS|axi_mem_intercon_M00_AXI 1 1 1 N 512
|
||||
preplace netloc PS|axis_dma_0_M_AXI 1 0 1 N 452
|
||||
preplace netloc PS|processing_system7_0_DDR 1 2 2 N 402 NJ
|
||||
preplace netloc PS|processing_system7_0_FIXED_IO 1 2 2 N 422 NJ
|
||||
preplace netloc PS|processing_system7_0_M_AXI_GP0 1 2 1 N 502
|
||||
levelinfo -pg 1 0 190 570 1830
|
||||
levelinfo -hier PS * 670 1050 1440 *
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1940 1070
|
||||
pagesize -hier PS -db -bbox -sgen 470 332 1630 1032
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
@@ -247,6 +247,16 @@
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"finalXOR": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"inOutReflected": {
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+2
@@ -40,6 +40,8 @@
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"finalXOR": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"inOutReflected": [ { "direction": "in", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
|
||||
@@ -1,25 +1,25 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"161,74",
|
||||
"Default View_TopLeft":"165,74",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 120 -y 280 -defaultsOSRD
|
||||
preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 920 -y 340 -defaultsOSRD
|
||||
preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 930 -y 340 -defaultsOSRD
|
||||
preplace inst axis_master_simmodel_0 -pg 1 -lvl 2 -x 350 -y 300 -defaultsOSRD
|
||||
preplace inst xlconstant_1 -pg 1 -lvl 2 -x 350 -y 80 -defaultsOSRD
|
||||
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 350 -y 180 -defaultsOSRD
|
||||
preplace inst axis_crc_0 -pg 1 -lvl 3 -x 640 -y 320 -defaultsOSRD
|
||||
preplace netloc AXIS_ARESETN_1 1 1 3 240 380 500 420 790J
|
||||
preplace netloc axis_master_simmodel_0_FINISHED 1 0 3 10 370 NJ 370 450
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 250 390 480 430 780J
|
||||
preplace inst axis_crc_0 -pg 1 -lvl 3 -x 650 -y 320 -defaultsOSRD
|
||||
preplace netloc AXIS_ARESETN_1 1 1 3 240 370 470 190 810J
|
||||
preplace netloc axis_master_simmodel_0_FINISHED 1 0 3 10 390 NJ 390 450
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 250 380 500 200 800J
|
||||
preplace netloc xlconstant_0_dout 1 2 1 460J 180n
|
||||
preplace netloc xlconstant_1_dout 1 2 1 490J 80n
|
||||
preplace netloc axis_master_simmodel_0_M_AXIS 1 2 1 450 280n
|
||||
preplace netloc axis_master_simmodel_0_M_AXIS 1 2 1 480 260n
|
||||
preplace netloc crc_M_AXIS 1 3 1 N 320
|
||||
levelinfo -pg 1 -10 120 350 640 920 1040
|
||||
pagesize -pg 1 -db -bbox -sgen -10 0 1040 440
|
||||
levelinfo -pg 1 -10 120 350 650 930 1050
|
||||
pagesize -pg 1 -db -bbox -sgen -10 0 1050 440
|
||||
"
|
||||
}
|
||||
0
|
||||
|
||||
@@ -61,20 +61,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="224"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="276"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="91"/>
|
||||
<Option Name="WTModelSimExportSim" Val="91"/>
|
||||
<Option Name="WTQuestaExportSim" Val="91"/>
|
||||
<Option Name="WTXSimExportSim" Val="92"/>
|
||||
<Option Name="WTModelSimExportSim" Val="92"/>
|
||||
<Option Name="WTQuestaExportSim" Val="92"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="91"/>
|
||||
<Option Name="WTRivieraExportSim" Val="91"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="91"/>
|
||||
<Option Name="WTVcsExportSim" Val="92"/>
|
||||
<Option Name="WTRivieraExportSim" Val="92"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="92"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -109,18 +109,36 @@
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_syn_1.bd" FileRelPathName="ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_syn_1_axis_dma_0_0"/>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_syn_1.bd" FileRelPathName="ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_syn_1_axis_crc_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_syn_1.bd" FileRelPathName="ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_syn_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_syn_1.bd" FileRelPathName="ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_syn_1_axis_dma_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/axi_crc_dma_ip/hdl/axi_crc_dma_ip_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
@@ -128,12 +146,12 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_axis_slave_simmodel_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_axis_slave_simmodel_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_axis_master_simmodel_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -165,14 +183,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_crc_dma_syn_1_wrapper"/>
|
||||
@@ -323,6 +333,12 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_crc_dma_syn_1_axis_crc_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crc_dma_syn_1_axis_crc_0_0" RelGenDir="$PGENDIR/axi_crc_dma_syn_1_axis_crc_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_crc_dma_syn_1_axis_crc_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_crc_dma_syn_1_axis_dma_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crc_dma_syn_1_axis_dma_0_0" RelGenDir="$PGENDIR/axi_crc_dma_syn_1_axis_dma_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_crc_dma_syn_1_axis_dma_0_0"/>
|
||||
@@ -399,9 +415,23 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_axis_crc_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_crc_dma_syn_1_axis_crc_0_0" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_axis_crc_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crc_dma_syn_1_axis_crc_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_crc_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_crc_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_axis_dma_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_crc_dma_syn_1_axis_dma_0_0" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_axis_dma_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crc_dma_syn_1_axis_dma_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_dma_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_dma_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -497,9 +527,30 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_axis_crc_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_axis_crc_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crc_dma_syn_1_axis_crc_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_crc_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_crc_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_axis_dma_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_axis_dma_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crc_dma_syn_1_axis_dma_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_dma_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axis_dma_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
@@ -6,6 +6,14 @@
|
||||
0000000000000000000000000000111100001111
|
||||
0000000000000000000000000001010000000001
|
||||
0000000000000000000000000000100100001111
|
||||
0000000000000000000000000001100000000001
|
||||
1111010010101100111110110001001100001111
|
||||
0000000000000000000000000001110000000001
|
||||
1111111111111111111111111111111100001111
|
||||
0000000000000000000000000010000000000001
|
||||
1111111111111111111111111111111100001111
|
||||
0000000000000000000000000010010000000001
|
||||
0000000000000000000000000000001100001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000000000000000000000000001100001111
|
||||
0000000000000000000000000000000000000110
|
||||
|
||||
@@ -11,12 +11,12 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="3,408.303 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="3,914.894 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="3,715.816 ns"></Cursor1Time>
|
||||
<ZoomStartTime time="1,566.900 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,822.094 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="2,080.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="244"></NameColumnWidth>
|
||||
<NameColumnWidth column_width="236"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="116"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="11" />
|
||||
@@ -76,6 +76,14 @@
|
||||
<obj_property name="ElementShortName">initial_value_reg[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">initial_value_reg[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/U0/finalXOR" type="array">
|
||||
<obj_property name="ElementShortName">finalXOR[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">finalXOR[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/U0/inOutReflected" type="array">
|
||||
<obj_property name="ElementShortName">inOutReflected[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">inOutReflected[1:0]</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXI" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXI</obj_property>
|
||||
@@ -170,10 +178,6 @@
|
||||
<obj_property name="ElementShortName">state</obj_property>
|
||||
<obj_property name="ObjectShortName">state</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/U0/run_reg_del" type="logic">
|
||||
<obj_property name="ElementShortName">run_reg_del</obj_property>
|
||||
<obj_property name="ObjectShortName">run_reg_del</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/U0/run_reg_set" type="logic">
|
||||
<obj_property name="ElementShortName">run_reg_set</obj_property>
|
||||
<obj_property name="ObjectShortName">run_reg_set</obj_property>
|
||||
|
||||
@@ -11,15 +11,15 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="608.945 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="123.245 ns"></Cursor1Time>
|
||||
<ZoomStartTime time="166.667 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,166.667 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="349.025 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="640"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="488"></ValueColumnWidth>
|
||||
<ValueColumnWidth column_width="480"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="12" />
|
||||
<WVObjectSize size="14" />
|
||||
<wvobject fp_name="/axis_crc_tb/CLK" type="logic">
|
||||
<obj_property name="ElementShortName">CLK</obj_property>
|
||||
<obj_property name="ObjectShortName">CLK</obj_property>
|
||||
@@ -36,6 +36,15 @@
|
||||
<obj_property name="ElementShortName">polynomial[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">polynomial[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/uut/finalXOR" type="array">
|
||||
<obj_property name="ElementShortName">finalXOR[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">finalXOR[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/uut/inOutReflected" type="array">
|
||||
<obj_property name="ElementShortName">inOutReflected[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">inOutReflected[1:0]</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="group1287" type="group">
|
||||
<obj_property name="label">S_AXIS</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
@@ -91,8 +100,8 @@
|
||||
<obj_property name="ObjectShortName">CLK_PERIOD</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/test_data" type="array">
|
||||
<obj_property name="ElementShortName">test_data[0:3][31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_data[0:3][31:0]</obj_property>
|
||||
<obj_property name="ElementShortName">test_data[0:2][31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_data[0:2][31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/polynomials" type="array">
|
||||
<obj_property name="ElementShortName">polynomials[0:2][31:0]</obj_property>
|
||||
|
||||
+61
-41
@@ -10,6 +10,8 @@ entity axis_crc is
|
||||
-- for crc calculation
|
||||
initial_value : in std_logic_vector(31 downto 0);
|
||||
polynomial : in std_logic_vector(31 downto 0);
|
||||
finalXOR : in std_logic_vector(31 downto 0);
|
||||
inOutReflected : in std_logic_vector( 1 downto 0);
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
@@ -27,19 +29,30 @@ end entity;
|
||||
|
||||
architecture rtl of axis_crc is
|
||||
|
||||
type state_t is (IDLE, SECOND_HALF, PROVIDE_DATA, CHECKSUM);
|
||||
signal state : state_t := IDLE;
|
||||
function reflect(input : std_logic_vector) return std_logic_vector is
|
||||
variable result : std_logic_vector(input'range);
|
||||
begin
|
||||
for i in input'range loop
|
||||
result(i) := input(input'low + input'length - 1 - i);
|
||||
end loop;
|
||||
return result;
|
||||
end function;
|
||||
|
||||
signal crc_sig : std_logic_vector(31 downto 0);
|
||||
|
||||
type state_t is (IDLE, FIRST_HALF, SECOND_HALF, PROVIDE_DATA, CHECKSUM);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
begin
|
||||
process
|
||||
-- fuer CRC-Berechnung
|
||||
variable CRC : std_logic_vector(31 downto 0);
|
||||
variable MSB : std_logic;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable CRC : std_logic_vector(31 downto 0);
|
||||
variable MSB : std_logic;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable lowerByte : std_logic_vector(7 downto 0);
|
||||
variable upperByte : std_logic_vector(7 downto 0);
|
||||
variable firstWord : boolean := false; -- is True if first word of current packet receiving
|
||||
variable last : std_logic;
|
||||
|
||||
variable last : std_logic;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
@@ -48,7 +61,8 @@ begin
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TLAST <= '0';
|
||||
crc_sig <= initial_value;
|
||||
CRC := (others=>'0');
|
||||
firstWord := true;
|
||||
|
||||
else
|
||||
case state is
|
||||
@@ -56,17 +70,30 @@ begin
|
||||
if S_AXIS_TVALID = '1' then
|
||||
data := S_AXIS_TDATA;
|
||||
last := S_AXIS_TLAST;
|
||||
S_AXIS_TREADY <= '0';
|
||||
|
||||
CRC := crc_sig;
|
||||
-- load initial value
|
||||
if firstWord = true then
|
||||
CRC := initial_value;
|
||||
firstWord := false;
|
||||
end if;
|
||||
|
||||
-- Board speichert Daten mit LITTLE ENDIAN
|
||||
-- -> Die Daten aus dem Speicher sollen aufsteigend
|
||||
-- in die CRC-Summe reingerechnet werden
|
||||
-- Daher: Erst untere 16 Bit in die CRC Summe reinrechnen
|
||||
|
||||
-- Erstes byte reinrechnen
|
||||
CRC := CRC xor (data(7 downto 0) & (23 downto 0 =>'0'));
|
||||
for i in 0 to 7 loop
|
||||
upperByte := data(7 downto 0);
|
||||
lowerByte := data(15 downto 8);
|
||||
|
||||
-- Reflect Input
|
||||
if inOutReflected(0) = '1' then
|
||||
upperByte := reflect(upperByte);
|
||||
lowerByte := reflect(lowerByte);
|
||||
end if;
|
||||
|
||||
-- Erstes und zweites byte reinrechnen
|
||||
CRC := CRC xor (upperByte & lowerByte & (15 downto 0 =>'0'));
|
||||
for i in 0 to 15 loop
|
||||
if CRC(31) = '1' then
|
||||
CRC := (CRC(30 downto 0) & '0') xor polynomial;
|
||||
else
|
||||
@@ -74,25 +101,24 @@ begin
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
-- Zweites byte reinrechnen
|
||||
CRC := CRC xor (data(15 downto 8) & (23 downto 0 =>'0'));
|
||||
for i in 0 to 7 loop
|
||||
if CRC(31) = '1' then
|
||||
CRC := (CRC(30 downto 0) & '0') xor polynomial;
|
||||
else
|
||||
CRC := CRC(30 downto 0) & '0';
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
S_AXIS_TREADY <= '0';
|
||||
state <= SECOND_HALF;
|
||||
end if;
|
||||
|
||||
when SECOND_HALF =>
|
||||
|
||||
-- Dann obere 16 Bit in die CRC Summe reinrechnen
|
||||
upperByte := data(23 downto 16);
|
||||
lowerByte := data(31 downto 24);
|
||||
|
||||
-- Reflect Input
|
||||
if inOutReflected(0) = '1' then
|
||||
upperByte := reflect(upperByte);
|
||||
lowerByte := reflect(lowerByte);
|
||||
end if;
|
||||
|
||||
-- Drittes byte reinrechnen
|
||||
CRC := CRC xor (data(23 downto 16) & (23 downto 0 =>'0'));
|
||||
for i in 0 to 7 loop
|
||||
CRC := CRC xor (upperByte & lowerByte & (15 downto 0 =>'0'));
|
||||
for i in 0 to 15 loop
|
||||
if CRC(31) = '1' then
|
||||
CRC := (CRC(30 downto 0) & '0') xor polynomial;
|
||||
else
|
||||
@@ -100,18 +126,6 @@ begin
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
-- Viertes byte reinrechnen
|
||||
CRC := CRC xor (data(31 downto 24) & (23 downto 0 =>'0'));
|
||||
for i in 0 to 7 loop
|
||||
if CRC(31) = '1' then
|
||||
CRC := (CRC(30 downto 0) & '0') xor polynomial;
|
||||
else
|
||||
CRC := CRC(30 downto 0) & '0';
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
crc_sig <= CRC;
|
||||
|
||||
-- Daten an M_AXIS ausgeben
|
||||
M_AXIS_TVALID <= '1';
|
||||
M_AXIS_TDATA <= data;
|
||||
@@ -122,7 +136,14 @@ begin
|
||||
if M_AXIS_TREADY = '1' then
|
||||
if last = '1' then
|
||||
M_AXIS_TLAST <= '1';
|
||||
M_AXIS_TDATA <= crc_sig;
|
||||
|
||||
-- Reflect Output
|
||||
if inOutReflected(1) = '1' then
|
||||
CRC := reflect(CRC);
|
||||
end if;
|
||||
|
||||
CRC := CRC xor finalXOR;
|
||||
M_AXIS_TDATA <= CRC;
|
||||
state <= CHECKSUM;
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
@@ -136,8 +157,7 @@ begin
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TLAST <= '0';
|
||||
|
||||
crc_sig <= initial_value;
|
||||
|
||||
firstWord := true;
|
||||
state <= IDLE;
|
||||
end if;
|
||||
|
||||
|
||||
@@ -11,8 +11,10 @@ architecture testbench of axis_crc_tb is
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESETN : std_logic := '0';
|
||||
|
||||
signal initial_value : std_logic_vector(31 downto 0) := x"00000000";
|
||||
signal polynomial : std_logic_vector(31 downto 0) := x"04C11DB7"; -- Standard CRC-32 Poly
|
||||
signal initial_value : std_logic_vector(31 downto 0) := x"FFFFFFFF";
|
||||
signal polynomial : std_logic_vector(31 downto 0) := x"F4ACFB13"; -- Standard CRC-32 Poly
|
||||
signal finalXOR : std_logic_vector(31 downto 0) := x"FFFFFFFF";
|
||||
signal inOutReflected : std_logic_vector( 1 downto 0) := "11";
|
||||
|
||||
-- AXIS Input Signals (Stimulus)
|
||||
signal S_AXIS_TVALID : std_logic := '0';
|
||||
@@ -42,9 +44,9 @@ architecture testbench of axis_crc_tb is
|
||||
);
|
||||
|
||||
constant polynomials : word_array := (
|
||||
x"04C11DB7",
|
||||
x"814141AB",
|
||||
x"1EDC6F41",
|
||||
x"A833982B"
|
||||
x"F4ACFB13"
|
||||
);
|
||||
|
||||
constant initialValues : word_array := (
|
||||
@@ -52,6 +54,10 @@ architecture testbench of axis_crc_tb is
|
||||
x"FFFFFFFF"
|
||||
);
|
||||
|
||||
type inOutReflected_t is array (natural range<>) of std_logic_vector(1 downto 0);
|
||||
-- constant inOutReflecteds : inOutReflected_t := ();
|
||||
|
||||
|
||||
|
||||
signal received_crc : std_logic_vector(31 downto 0);
|
||||
|
||||
@@ -66,6 +72,8 @@ begin
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
finalXOR => finalXOR,
|
||||
inOutReflected => inOutReflected,
|
||||
|
||||
-- AXI Streaming Target (Input)
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
@@ -103,7 +111,7 @@ begin
|
||||
|
||||
-- Send Data over S_AXIS
|
||||
for poly in polynomials'range loop
|
||||
polynomial <= polynomials(poly);
|
||||
-- polynomial <= polynomials(poly);
|
||||
|
||||
for b in test_data'range loop
|
||||
S_AXIS_TDATA <= test_data(b);
|
||||
|
||||
+23
-17
@@ -20,6 +20,8 @@ entity axis_dma is
|
||||
-- for crc calulaction
|
||||
initial_value : out std_logic_vector(31 downto 0);
|
||||
polynomial : out std_logic_vector(31 downto 0);
|
||||
finalXOR : out std_logic_vector(31 downto 0);
|
||||
inOutReflected : out std_logic_vector( 1 downto 0);
|
||||
|
||||
-- FIFOs
|
||||
FIFO_NUM_FREE : in std_logic_vector(7 downto 0);
|
||||
@@ -106,6 +108,8 @@ architecture rtl of axis_dma is
|
||||
signal packet_number_reg : std_logic_vector(15 downto 0);
|
||||
signal polynomial_reg : std_logic_vector(31 downto 0);
|
||||
signal initial_value_reg : std_logic_vector(31 downto 0);
|
||||
signal finalXOR_reg : std_logic_vector(31 downto 0);
|
||||
signal inOut_reflected_reg : std_logic_vector( 1 downto 0);
|
||||
|
||||
-- Helper Signals
|
||||
signal run_reg_set : std_logic;
|
||||
@@ -134,19 +138,6 @@ begin
|
||||
interrupt_sig <= '1' when read_state=FINISHED and write_state=FINISHED and interrupt_enable_reg='1' else '0';
|
||||
INTERRUPT <= interrupt_sig;
|
||||
|
||||
-- Flip-Flop for run_reg
|
||||
-- process
|
||||
-- begin
|
||||
-- wait until rising_edge(clk);
|
||||
|
||||
-- if RESETN = '0' or interrupt_sig = '1' then
|
||||
-- run_reg <= '0';
|
||||
-- elsif run_reg_set = '1' then
|
||||
-- run_reg <= '1';
|
||||
-- elsif run_reg_clear = '1' then
|
||||
-- run_reg <= '0';
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
-------------------------------------------
|
||||
-- S_AXIL Schnittstelle
|
||||
@@ -156,10 +147,11 @@ begin
|
||||
S_AXIL_ARREADY <= '1'; -- IP is always ready
|
||||
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
|
||||
-- Fuer axis_crc-Komponente
|
||||
polynomial <= polynomial_reg;
|
||||
initial_value <= initial_value_reg;
|
||||
|
||||
-- AXIL Register nach aussen fuehren
|
||||
polynomial <= polynomial_reg;
|
||||
initial_value <= initial_value_reg;
|
||||
inOutReflected <= inOut_reflected_reg;
|
||||
|
||||
process
|
||||
begin
|
||||
@@ -178,6 +170,8 @@ begin
|
||||
packet_size_reg <= (others => '0');
|
||||
polynomial_reg <= polynomial_default;
|
||||
initial_value_reg <= initial_value_default;
|
||||
finalXOR_reg <= (others=>'0');
|
||||
inOut_reflected_reg <= (others=>'0');
|
||||
else
|
||||
-- FLip Flop-Register fuer sauberes Setzen und Loeschen des Run-Signals
|
||||
if interrupt_sig = '1' then
|
||||
@@ -212,6 +206,10 @@ begin
|
||||
S_AXIL_RDATA <= polynomial_reg;
|
||||
elsif S_AXIL_ARADDR(7 downto 0) = x"1C" then
|
||||
S_AXIL_RDATA <= initial_value_reg;
|
||||
elsif S_AXIL_ARADDR(7 downto 0) = x"20" then
|
||||
S_AXIL_RDATA <= finalXOR_reg;
|
||||
elsif S_AXIL_ARADDR(7 downto 0) = x"24" then
|
||||
S_AXIL_RDATA(1 downto 0) <= inOut_reflected_reg;
|
||||
end if;
|
||||
S_AXIL_RVALID <= '1';
|
||||
end if;
|
||||
@@ -260,6 +258,14 @@ begin
|
||||
if S_AXIL_WSTRB = "1111" then
|
||||
initial_value_reg <= S_AXIL_WDATA;
|
||||
end if;
|
||||
elsif S_AXIL_AWADDR = x"20" then
|
||||
if S_AXIL_WSTRB = "1111" then
|
||||
finalXOR_reg <= S_AXIL_WDATA;
|
||||
end if;
|
||||
elsif S_AXIL_AWADDR = x"24" then
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
inOut_reflected_reg <= S_AXIL_WDATA(1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
+90
-59
@@ -11,14 +11,30 @@ uint8_t calcCRC8(uint8_t* data, size_t size);
|
||||
// Berechnen einer 16 Bit CRC-Pruefsumme
|
||||
uint16_t calcCRC16(uint8_t* inBytes, size_t size);
|
||||
|
||||
// Berechnen einer 32 Bit CRC-Pruefsumme
|
||||
uint32_t calcCRC32(uint8_t* inBytes, size_t size, uint32_t polynomial, uint32_t initialValue);
|
||||
// Berechnen einer 32 Bit CRC-Pruefsumme mit allen Parametern
|
||||
uint32_t calcCRC32(
|
||||
uint8_t* inBytes,
|
||||
size_t size,
|
||||
uint32_t polynomial,
|
||||
uint32_t initialValue,
|
||||
uint32_t finalXOR,
|
||||
uint8_t inputReflected,
|
||||
uint8_t outputReflected
|
||||
);
|
||||
|
||||
// Check einer 32 Bit CRC-Pruefsumme
|
||||
int checkCrc32(uint8_t* data, size_t size, uint32_t crc, uint32_t polynomial);
|
||||
int checkCrc32(
|
||||
uint8_t* data,
|
||||
size_t size,
|
||||
uint32_t crc,
|
||||
uint32_t polynomial,
|
||||
uint32_t initialValue,
|
||||
uint32_t finalXOR,
|
||||
uint8_t inputReflected,
|
||||
uint8_t outputReflected
|
||||
);
|
||||
|
||||
// Berechnung der Pruefsummen fuer Testbenches
|
||||
void calc_crc_tb();
|
||||
// Berechnung der Pruefsummen fuer Testbench
|
||||
void calc_axis_crc_tb();
|
||||
|
||||
|
||||
@@ -26,7 +42,7 @@ int main()
|
||||
{
|
||||
// Testweise Pruefsumme berechnen und ausgeben
|
||||
char msg[] = "Hello World!";
|
||||
uint32_t crc = calcCRC32((uint8_t*) msg, strlen(msg), 0x814141AB, 0);
|
||||
uint32_t crc = calcCRC32((uint8_t*) msg, strlen(msg), 0x4C11DB7, 0xFFFFFFFF, 0xFFFFFFFF, 1, 1);
|
||||
printf("CRC32 of '%s': 0x%08x\n\n", msg, crc);
|
||||
|
||||
uint8_t crc8 = calcCRC8((uint8_t*) msg, strlen(msg));
|
||||
@@ -35,59 +51,24 @@ int main()
|
||||
uint16_t crc16 = calcCRC16((uint8_t*) msg, strlen(msg));
|
||||
printf("CRC16 of '%s': 0x%04x\n\n", msg, crc16);
|
||||
|
||||
int crcValid = checkCrc32((uint8_t*) msg, strlen(msg), crc, 0x4C11DB7);
|
||||
|
||||
// test mit crccalc.com
|
||||
uint8_t daten[4] = {0x12, 0x34, 0x56, 0x78};
|
||||
crc = calcCRC32(daten, 4, 0x04C11DB7, 0);
|
||||
crc = calcCRC32(daten, 4, 0x04C11DB7, 0xFFFFFFFF, 0xFFFFFFFF, 0, 0);
|
||||
printf("0x%08x\n\n", crc);
|
||||
|
||||
// calc_crc_tb();
|
||||
// calc_axis_crc_tb();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Berechnung der Pruefsummen fuer crc_tb
|
||||
void calc_crc_tb()
|
||||
{
|
||||
// CRC-Pruefsummen fuer Testbench crc_tb berechnen
|
||||
uint8_t testcases[11][11] = {
|
||||
{8, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88}, // CRC_tb
|
||||
{8, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF, 0x11}, // CRC_tb
|
||||
{8, 0x12, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xDE}, // CRC_tb
|
||||
};
|
||||
|
||||
uint32_t testPolynomials[3] = {
|
||||
0x4C11DB7,
|
||||
0x1EDC6F41,
|
||||
0xA833982B,
|
||||
};
|
||||
|
||||
uint32_t initalValues[2] = {
|
||||
0x0,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
for (int testcase = 0; testcase < 3; testcase++) {
|
||||
for (int polynomial = 0; polynomial < 3; polynomial++) {
|
||||
for (int intialValue = 0; intialValue < 2; intialValue++) {
|
||||
uint32_t checksum;
|
||||
checksum = calcCRC32(testcases[testcase]+1, testcases[testcase][0], testPolynomials[polynomial], initalValues[intialValue]);
|
||||
printf("Testfall %d, polynom %d, iV %d: x\"%08x\"\n", testcase, polynomial, intialValue, checksum);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void calc_axis_crc_tb()
|
||||
{
|
||||
uint32_t test_data[4] = {0x11223344, 0x55667788, 0xAABBCCDD, 0xEEFF5307};
|
||||
char test_data[] = "Hello World!";
|
||||
|
||||
uint32_t testPolynomials[3] = {
|
||||
0x4C11DB7,
|
||||
0x1EDC6F41,
|
||||
0xA833982B,
|
||||
0x814141AB,
|
||||
};
|
||||
|
||||
uint32_t initalValues[2] = {
|
||||
@@ -98,7 +79,7 @@ void calc_axis_crc_tb()
|
||||
for (int polynomial = 0; polynomial < 3; polynomial++) {
|
||||
for (int intialValue = 0; intialValue < 2; intialValue++) {
|
||||
uint32_t checksum;
|
||||
checksum = calcCRC32((uint8_t*) test_data, 16, testPolynomials[polynomial], initalValues[intialValue]);
|
||||
checksum = calcCRC32((uint8_t*) test_data, 16, testPolynomials[polynomial], initalValues[intialValue], 0x0, 0, 0);
|
||||
printf("Polynom %d, iV %d: x\"%08x\"\n", polynomial, intialValue, checksum);
|
||||
}
|
||||
}
|
||||
@@ -117,7 +98,8 @@ uint8_t calcCRC8(uint8_t* inBytes, size_t size)
|
||||
crc = (uint8_t) ((crc << 1) ^ polynomial);
|
||||
}
|
||||
else {
|
||||
crc <<= 1;
|
||||
crc = (uint8_t)(crc << 1);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -136,7 +118,8 @@ uint16_t calcCRC16(uint8_t* inBytes, size_t size)
|
||||
if ((crc & 0x8000) != 0) {
|
||||
crc = (uint16_t) (crc << 1) ^ polynomial;
|
||||
} else {
|
||||
crc <<= 1;
|
||||
crc = (uint16_t)(crc << 1);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -144,12 +127,33 @@ uint16_t calcCRC16(uint8_t* inBytes, size_t size)
|
||||
return crc;
|
||||
}
|
||||
|
||||
uint32_t calcCRC32(uint8_t* inBytes, size_t size, uint32_t polynomial, uint32_t initialValue)
|
||||
{
|
||||
uint32_t crc = 0;
|
||||
uint32_t calcCRC32(
|
||||
uint8_t* inBytes,
|
||||
size_t size,
|
||||
uint32_t polynomial,
|
||||
uint32_t initialValue,
|
||||
uint32_t finalXOR,
|
||||
uint8_t inputReflected,
|
||||
uint8_t outputReflected
|
||||
) {
|
||||
uint32_t crc = initialValue;
|
||||
uint8_t byte;
|
||||
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
crc ^= (uint32_t) (inBytes[i] << 24);
|
||||
byte = inBytes[i];
|
||||
|
||||
if (inputReflected != 0) {
|
||||
uint8_t reflected = 0;
|
||||
|
||||
for (int b = 0; b < 8; b++) {
|
||||
if ((byte & (1<<b)) != 0) {
|
||||
reflected |= (uint8_t) (1<<(7-b));
|
||||
}
|
||||
}
|
||||
byte = reflected;
|
||||
}
|
||||
|
||||
crc ^= (uint32_t) (byte << 24);
|
||||
|
||||
for (int bit = 0; bit < 8; bit++) {
|
||||
if ((crc & (uint32_t)(1<<31)) != 0) {
|
||||
@@ -160,20 +164,47 @@ uint32_t calcCRC32(uint8_t* inBytes, size_t size, uint32_t polynomial, uint32_t
|
||||
}
|
||||
}
|
||||
|
||||
return crc;
|
||||
if (outputReflected != 0) {
|
||||
uint32_t reflected = 0;
|
||||
|
||||
for (int i = 0; i < 32; i++) {
|
||||
if ((crc & (uint32_t) (1<<i)) != 0) {
|
||||
reflected |= (uint32_t) (1<<(31-i));
|
||||
}
|
||||
}
|
||||
crc = reflected;
|
||||
}
|
||||
|
||||
return crc ^ finalXOR;
|
||||
}
|
||||
|
||||
int checkCrc32(uint8_t* data, size_t size, uint32_t crc, uint32_t polynomial)
|
||||
{
|
||||
int checkCrc32(
|
||||
uint8_t* data,
|
||||
size_t size,
|
||||
uint32_t crc,
|
||||
uint32_t polynomial,
|
||||
uint32_t initialValue,
|
||||
uint32_t finalXOR,
|
||||
uint8_t inputReflected,
|
||||
uint8_t outputReflected
|
||||
) {
|
||||
// Daten und CRC zusammenhaengend in den HEAP Speicher kopieren
|
||||
uint8_t *dataCrc = malloc(size + 4);
|
||||
memcpy_s(dataCrc, size+4, data, size);
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
dataCrc[size+i] = (crc >> (24 - 8 * i)) & 0xFF; // Extract the MSB first
|
||||
}
|
||||
memcpy_s((dataCrc+size), 4, &crc, 4);
|
||||
// for (uint32_t i = 0; i < 4; i++) {
|
||||
// dataCrc[size+i] = (crc >> (24 - 8 * i)) & 0xFF; // Extract the MSB first
|
||||
// }
|
||||
|
||||
// CRC von Daten mit CRC-Pruefsumme berechnen
|
||||
// Bei validen Daten bzw. Pruefsumme kommt Null heraus
|
||||
if (calcCRC32(dataCrc, size+4, polynomial, 0x0) == 0) return 1;
|
||||
else return 0;
|
||||
uint32_t ret = calcCRC32(dataCrc, size+4, polynomial, initialValue, finalXOR, inputReflected, outputReflected);
|
||||
if (ret == 0) {
|
||||
ret = 1;
|
||||
} else {
|
||||
ret = 0;
|
||||
};
|
||||
|
||||
free(dataCrc);
|
||||
return ret;
|
||||
}
|
||||
+39
-5
@@ -1,6 +1,8 @@
|
||||
#pragma once
|
||||
#ifndef AXI_CRC_DMA_H_
|
||||
#define AXI_CRC_DMA_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
// -------------------------------------------------------------------------------------------------
|
||||
// Control Register:
|
||||
@@ -29,9 +31,18 @@
|
||||
// Polynomial Register:
|
||||
// 31..0 : Polynomial
|
||||
// -------------------------------------------------------------------------------------------------
|
||||
// Intial Value Register:
|
||||
// Initial Value Register:
|
||||
// 31..0 : Initial Value
|
||||
// -------------------------------------------------------------------------------------------------
|
||||
// Final XOR Register:
|
||||
// 31..0 : Final XOR Value
|
||||
// -------------------------------------------------------------------------------------------------
|
||||
// InOutReflected Register:
|
||||
// 0 : Input Reflected
|
||||
// 1 : Output Reflected
|
||||
// 31..2 : Reserved
|
||||
// -------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
@@ -39,8 +50,31 @@ typedef struct
|
||||
volatile uint32_t InterruptStatus; // [0] INT Status
|
||||
volatile uint32_t ReadAddress; // [31:0] Read Address of Data
|
||||
volatile uint32_t WriteAddress; // [31:0] Write Address of Data
|
||||
volatile uint32_t PacketSize; // [15:0] Size of Packets in 32 Bit words
|
||||
volatile uint32_t NumberPackets; // [15:0] Number of Packets
|
||||
volatile uint32_t PacketSize; // [15:0] Size of Packets Minus 1 in 32 Bit words
|
||||
volatile uint32_t NumberPackets; // [15:0] Number of Packets Minus 1
|
||||
volatile uint32_t Polynomial; // [31:0] Polynomial for CRC Calculation
|
||||
volatile uint32_t InitialValue; // [31:0] Intial Value of CRC Calculation
|
||||
volatile uint32_t InitialValue; // [31:0] Initial Value of CRC Calculation
|
||||
volatile uint32_t FinalXOR; // [31:0] Final XOR Value
|
||||
volatile uint32_t InOutReflected; // [0] Input Reflected, [1] Output Reflected
|
||||
} CRC_Typedef;
|
||||
|
||||
typedef CRC_Typedef *PCRC_Typedef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Polynomial;
|
||||
uint32_t InitalValue;
|
||||
uint32_t FinalXOR;
|
||||
bool InputReflected;
|
||||
bool OutputReflected;
|
||||
} CrcParameterSet;
|
||||
|
||||
const CrcParameterSet CRC32_AIXM = {
|
||||
.Polynomial = 0x814141ab,
|
||||
.InitalValue = 0x0,
|
||||
.FinalXOR = 0x0,
|
||||
.InputReflected = false,
|
||||
.OutputReflected = false
|
||||
};
|
||||
|
||||
#endif /* AXI_CRC_DMA_H_ */
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
@@ -12,21 +13,29 @@ typedef struct
|
||||
volatile uint32_t InitialValue; // [31:0] Intial Value of CRC Calculation
|
||||
} CRC_Typedef;
|
||||
|
||||
static char msg[] = "Hello World!";
|
||||
|
||||
int main()
|
||||
{
|
||||
CRC_Typedef* CRC = (CRC_Typedef*) 0x43c00000;
|
||||
|
||||
printf("Hello\n");
|
||||
|
||||
uint8_t dest[13];
|
||||
|
||||
// Schreib- und Leseadresse setzen
|
||||
CRC->ReadAddress = 0x20000000;
|
||||
CRC->WriteAddress = 0x30000000;
|
||||
CRC->ReadAddress = (uint32_t) msg;
|
||||
CRC->WriteAddress = (uint32_t) dest;
|
||||
|
||||
// Packetgroesse und -anzahl setzen
|
||||
CRC->PacketSize = 16;
|
||||
CRC->NumberPackets = 5;
|
||||
CRC->PacketSize = 2;
|
||||
CRC->NumberPackets = 0;
|
||||
|
||||
// Generatorpolynom und Initialwert setzen
|
||||
CRC->Polynomial = 0x04C11DB7;
|
||||
CRC->InitialValue = 00000000;
|
||||
CRC->Polynomial = 0x814141AB;
|
||||
CRC->InitialValue = 0xFFFFFFFF;
|
||||
|
||||
//
|
||||
|
||||
// Interrupt aktivieren
|
||||
CRC->Control |= (1<<1);
|
||||
@@ -35,15 +44,15 @@ int main()
|
||||
CRC->Control |= (1<<0);
|
||||
|
||||
while (1) {
|
||||
// Status abfragen
|
||||
if ((CRC->Control & (1<<0)) == 0) {
|
||||
// Status abfragen
|
||||
if ((CRC->Control & (1<<0)) == 0) {
|
||||
|
||||
// Interrupt zuruecksetzen
|
||||
CRC->InterruptStatus = 1;
|
||||
// Interrupt zuruecksetzen
|
||||
CRC->InterruptStatus = 0;
|
||||
|
||||
// Erneut starten
|
||||
CRC->Control |= (1<<0);
|
||||
}
|
||||
// Erneut starten
|
||||
CRC->Control |= (1<<0);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -6,6 +6,14 @@
|
||||
0000000000000000000000000000111100001111
|
||||
0000000000000000000000000001010000000001
|
||||
0000000000000000000000000000100100001111
|
||||
0000000000000000000000000001100000000001
|
||||
1111010010101100111110110001001100001111
|
||||
0000000000000000000000000001110000000001
|
||||
1111111111111111111111111111111100001111
|
||||
0000000000000000000000000010000000000001
|
||||
1111111111111111111111111111111100001111
|
||||
0000000000000000000000000010010000000001
|
||||
0000000000000000000000000000001100001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000000000000000000000000001100001111
|
||||
0000000000000000000000000000000000000110
|
||||
|
||||
@@ -1,8 +1,12 @@
|
||||
wal 0x08 0x20000000
|
||||
wal 0x0C 0x30000000
|
||||
wal 0x10 15
|
||||
wal 0x14 9
|
||||
wal 0 0x00000003
|
||||
wal 0x08 0x20000000 # Read Address
|
||||
wal 0x0C 0x30000000 # Write Address
|
||||
wal 0x10 15 # Packet Size
|
||||
wal 0x14 9 # Packet Number
|
||||
wal 0x18 0xF4ACFB13 # Polynomial
|
||||
wal 0x1c 0xFFFFFFFF # Inital Value
|
||||
wal 0x20 0xFFFFFFFF # FinalXOR
|
||||
wal 0x24 0x3 # InOutReflected
|
||||
wal 0 0x00000003 # Start IP with Interrupt Enabled
|
||||
wfi
|
||||
wal 0x04 0x1
|
||||
wal 0 0x00000003
|
||||
Reference in New Issue
Block a user