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axis_crc Timing + TB verbessert

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This commit is contained in:
Matthias Biermann
2025-02-11 20:22:55 +01:00
parent 7725db8f3b
commit ba7b4d18fa
144 changed files with 145324 additions and 145718 deletions
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/axi_crc_dma_ip.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_ip" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739224593"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1739224593"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739224593"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739224593"/>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739299489"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1739299489"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739299489"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739299489"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xml
+36 -36
View File
@@ -2628,22 +2628,22 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
@@ -2651,13 +2651,13 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -2671,36 +2671,36 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1739226271"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739226272"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1739226271"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739226272"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1739301287"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739301288"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1739301287"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739301288"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\axi_crc_dma_sim_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Mon Feb 10 23:24:31 2025
--Date : Tue Feb 11 20:14:47 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
--Design : axi_crc_dma_sim_1_wrapper
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml
+1 -1
View File
@@ -461,7 +461,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 11:21:38 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 19:14:47 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml
+36 -36
View File
@@ -2672,22 +2672,22 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
@@ -2695,13 +2695,13 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -2715,36 +2715,36 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd
+19 -19
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Mon Feb 10 23:24:31 2025
--Date : Tue Feb 11 20:14:47 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1.bd
--Design : axi_crc_dma_sim_1
@@ -105,24 +105,6 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_sim_1_axis_fifo_1_0;
component axi_crc_dma_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_crc_0_0;
component axi_crc_dma_sim_1_axis_dma_0_0 is
port (
CLK : in STD_LOGIC;
@@ -195,6 +177,24 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_dma_0_0;
component axi_crc_dma_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_crc_0_0;
signal CLK_1 : STD_LOGIC;
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_ARREADY : STD_LOGIC;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd
+19 -19
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Mon Feb 10 23:24:31 2025
--Date : Tue Feb 11 20:14:47 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1.bd
--Design : axi_crc_dma_sim_1
@@ -105,24 +105,6 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_sim_1_axis_fifo_1_0;
component axi_crc_dma_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_crc_0_0;
component axi_crc_dma_sim_1_axis_dma_0_0 is
port (
CLK : in STD_LOGIC;
@@ -195,6 +177,24 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_dma_0_0;
component axi_crc_dma_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
finalXOR : in STD_LOGIC_VECTOR ( 31 downto 0 );
inOutReflected : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_crc_0_0;
signal CLK_1 : STD_LOGIC;
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_ARREADY : STD_LOGIC;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/axi_crc_dma_syn_1.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_syn_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739281398"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739281398"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739281398"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739281398"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739299570"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739299570"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739299570"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739299570"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\axi_crc_dma_syn_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/hdl/axi_crc_dma_syn_1_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Feb 11 14:43:08 2025
--Date : Tue Feb 11 19:46:02 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_syn_1_wrapper.bd
--Design : axi_crc_dma_syn_1_wrapper
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0.xml
+22 -22
View File
@@ -394,7 +394,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -601,7 +601,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1044,7 +1044,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1251,7 +1251,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1326,7 +1326,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>aclk frequency</spirit:displayName>
<spirit:description>aclk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -1348,7 +1348,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1500,11 +1500,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:18 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e2ea4d7</spirit:value>
<spirit:value>9:0c8b6373</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1518,11 +1518,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e2ea4d7</spirit:value>
<spirit:value>9:0c8b6373</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1538,11 +1538,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9c99685e</spirit:value>
<spirit:value>9:eafa79f8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1566,11 +1566,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9c99685e</spirit:value>
<spirit:value>9:eafa79f8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1605,11 +1605,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:37bf8ee8</spirit:value>
<spirit:value>9:c1780b5b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1625,11 +1625,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:37bf8ee8</spirit:value>
<spirit:value>9:c1780b5b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1663,11 +1663,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e2ea4d7</spirit:value>
<spirit:value>9:0c8b6373</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1683,11 +1683,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6e2ea4d7</spirit:value>
<spirit:value>9:0c8b6373</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0_ooc.xdc
+1 -1
View File
@@ -52,6 +52,6 @@
# #########################################################
create_clock -period 15 -name aclk [get_ports aclk]
create_clock -period 10 -name aclk [get_ports aclk]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0_sim_netlist.v
+4 -4
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Feb 10 22:18:56 2025
// Date : Tue Feb 11 19:41:25 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top axi_crc_dma_syn_1_auto_pc_0 -prefix
// axi_crc_dma_syn_1_auto_pc_0_ axi_crc_dma_syn_1_auto_pc_0_sim_netlist.v
@@ -75,7 +75,7 @@ module axi_crc_dma_syn_1_auto_pc_0
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
@@ -114,7 +114,7 @@ module axi_crc_dma_syn_1_auto_pc_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
@@ -133,7 +133,7 @@ module axi_crc_dma_syn_1_auto_pc_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/axi_crc_dma_syn_1_auto_pc_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Feb 10 22:18:56 2025
// Date : Tue Feb 11 19:41:25 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_auto_pc_0 -prefix
// axi_crc_dma_syn_1_auto_pc_0_ axi_crc_dma_syn_1_auto_pc_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/sim/axi_crc_dma_syn_1_auto_pc_0.v
+5 -5
View File
@@ -115,7 +115,7 @@ module axi_crc_dma_syn_1_auto_pc_0 (
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
@@ -195,8 +195,8 @@ output wire [1 : 0] s_axi_rresp;
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_TH\
READS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREA\
DS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@@ -235,8 +235,8 @@ input wire [31 : 0] m_axi_rdata;
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_\
THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
EADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_pc_0/synth/axi_crc_dma_syn_1_auto_pc_0.v
+5 -5
View File
@@ -117,7 +117,7 @@ module axi_crc_dma_syn_1_auto_pc_0 (
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
@@ -197,8 +197,8 @@ output wire [1 : 0] s_axi_rresp;
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_TH\
READS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREA\
DS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@@ -237,8 +237,8 @@ input wire [31 : 0] m_axi_rdata;
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_\
THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
EADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0.xml
+24 -24
View File
@@ -346,7 +346,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -553,7 +553,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -916,7 +916,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1123,7 +1123,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1198,7 +1198,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>s_axi_aclk frequency</spirit:displayName>
<spirit:description>s_axi_aclk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -1220,7 +1220,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1511,11 +1511,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:18 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5dbe2805</spirit:value>
<spirit:value>9:4d2a9fb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1530,11 +1530,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5dbe2805</spirit:value>
<spirit:value>9:4d2a9fb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1548,11 +1548,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5dbe2805</spirit:value>
<spirit:value>9:4d2a9fb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1568,11 +1568,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ec781f57</spirit:value>
<spirit:value>9:587926c3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1596,11 +1596,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ec781f57</spirit:value>
<spirit:value>9:587926c3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1644,11 +1644,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e6488476</spirit:value>
<spirit:value>9:ca436a2f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1664,11 +1664,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e6488476</spirit:value>
<spirit:value>9:ca436a2f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1708,11 +1708,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5dbe2805</spirit:value>
<spirit:value>9:4d2a9fb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1728,11 +1728,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5dbe2805</spirit:value>
<spirit:value>9:4d2a9fb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0_ooc.xdc
+1 -1
View File
@@ -52,6 +52,6 @@
# #########################################################
create_clock -period 15 -name s_axi_aclk [get_ports s_axi_aclk]
create_clock -period 10 -name s_axi_aclk [get_ports s_axi_aclk]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0_sim_netlist.v
+4 -4
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 12:07:29 2025
// Date : Tue Feb 11 19:41:24 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top axi_crc_dma_syn_1_auto_us_0 -prefix
// axi_crc_dma_syn_1_auto_us_0_ axi_crc_dma_syn_1_auto_us_0_sim_netlist.v
@@ -88,7 +88,7 @@ module axi_crc_dma_syn_1_auto_us_0
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [0:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
@@ -126,7 +126,7 @@ module axi_crc_dma_syn_1_auto_us_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [3:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
@@ -159,7 +159,7 @@ module axi_crc_dma_syn_1_auto_us_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/axi_crc_dma_syn_1_auto_us_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 12:07:29 2025
// Date : Tue Feb 11 19:41:24 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_auto_us_0 -prefix
// axi_crc_dma_syn_1_auto_us_0_ axi_crc_dma_syn_1_auto_us_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/sim/axi_crc_dma_syn_1_auto_us_0.v
+5 -5
View File
@@ -128,7 +128,7 @@ module axi_crc_dma_syn_1_auto_us_0 (
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
@@ -206,8 +206,8 @@ output wire [1 : 0] s_axi_rresp;
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@@ -274,8 +274,8 @@ input wire [1 : 0] m_axi_rresp;
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_0/synth/axi_crc_dma_syn_1_auto_us_0.v
+5 -5
View File
@@ -130,7 +130,7 @@ module axi_crc_dma_syn_1_auto_us_0 (
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
@@ -208,8 +208,8 @@ output wire [1 : 0] s_axi_rresp;
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@@ -276,8 +276,8 @@ input wire [1 : 0] m_axi_rresp;
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1.xml
+24 -24
View File
@@ -346,7 +346,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -553,7 +553,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -916,7 +916,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1123,7 +1123,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -1198,7 +1198,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>s_axi_aclk frequency</spirit:displayName>
<spirit:description>s_axi_aclk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SI_CLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -1220,7 +1220,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SI_CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1511,11 +1511,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:18 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:10 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9ead6447</spirit:value>
<spirit:value>9:8e39d3f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1530,11 +1530,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9ead6447</spirit:value>
<spirit:value>9:8e39d3f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1548,11 +1548,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9ead6447</spirit:value>
<spirit:value>9:8e39d3f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1568,11 +1568,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e0ace2c2</spirit:value>
<spirit:value>9:54addb56</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1596,11 +1596,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e0ace2c2</spirit:value>
<spirit:value>9:54addb56</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1644,11 +1644,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ea9c79e3</spirit:value>
<spirit:value>9:c69797ba</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1664,11 +1664,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ea9c79e3</spirit:value>
<spirit:value>9:c69797ba</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1708,11 +1708,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:16 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9ead6447</spirit:value>
<spirit:value>9:8e39d3f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1728,11 +1728,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:17 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:09 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9ead6447</spirit:value>
<spirit:value>9:8e39d3f1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1_ooc.xdc
+1 -1
View File
@@ -52,6 +52,6 @@
# #########################################################
create_clock -period 15 -name s_axi_aclk [get_ports s_axi_aclk]
create_clock -period 10 -name s_axi_aclk [get_ports s_axi_aclk]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1_sim_netlist.v
+4 -4
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 12:07:29 2025
// Date : Tue Feb 11 19:41:24 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top axi_crc_dma_syn_1_auto_us_1 -prefix
// axi_crc_dma_syn_1_auto_us_1_ axi_crc_dma_syn_1_auto_us_0_sim_netlist.v
@@ -88,7 +88,7 @@ module axi_crc_dma_syn_1_auto_us_1
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [0:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
@@ -126,7 +126,7 @@ module axi_crc_dma_syn_1_auto_us_1
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [3:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
@@ -159,7 +159,7 @@ module axi_crc_dma_syn_1_auto_us_1
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/axi_crc_dma_syn_1_auto_us_1_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 12:07:29 2025
// Date : Tue Feb 11 19:41:24 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_auto_us_1 -prefix
// axi_crc_dma_syn_1_auto_us_1_ axi_crc_dma_syn_1_auto_us_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/sim/axi_crc_dma_syn_1_auto_us_1.v
+5 -5
View File
@@ -128,7 +128,7 @@ module axi_crc_dma_syn_1_auto_us_1 (
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
@@ -206,8 +206,8 @@ output wire [1 : 0] s_axi_rresp;
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@@ -274,8 +274,8 @@ input wire [1 : 0] m_axi_rresp;
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_auto_us_1/synth/axi_crc_dma_syn_1_auto_us_1.v
+5 -5
View File
@@ -130,7 +130,7 @@ module axi_crc_dma_syn_1_auto_us_1 (
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
@@ -208,8 +208,8 @@ output wire [1 : 0] s_axi_rresp;
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
@@ -276,8 +276,8 @@ input wire [1 : 0] m_axi_rresp;
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREAD\
S 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_2d_mmvs_0_0/axi_crc_dma_syn_1_axi_2d_mmvs_0_0.xml
+13 -13
View File
@@ -307,7 +307,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -514,7 +514,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -741,7 +741,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -948,7 +948,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1131,7 +1131,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1149,7 +1149,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1305,7 +1305,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1323,7 +1323,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1991,7 +1991,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2018,7 +2018,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2115,7 +2115,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:32:54 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:39:26 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -4158,7 +4158,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -4169,7 +4169,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_2d_mmvs_0_0/axi_crc_dma_syn_1_axi_2d_mmvs_0_0_sim_netlist.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 14:32:53 2025
// Date : Tue Feb 11 19:39:25 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_2d_mmvs_0_0/axi_crc_dma_syn_1_axi_2d_mmvs_0_0_sim_netlist.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_2d_mmvs_0_0/axi_crc_dma_syn_1_axi_2d_mmvs_0_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 14:32:53 2025
// Date : Tue Feb 11 19:39:25 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_2d_mmvs_0_0/axi_crc_dma_syn_1_axi_2d_mmvs_0_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0.xml
+9 -9
View File
@@ -119,7 +119,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -137,7 +137,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -278,7 +278,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -296,7 +296,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -380,7 +380,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -407,7 +407,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -471,7 +471,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Feb 09 22:33:42 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:47:38 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -502,7 +502,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Feb 09 22:30:20 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:03 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -522,7 +522,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Feb 09 22:30:20 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:03 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v
+6101 -6571
View File
File diff suppressed because it is too large Load Diff
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
+2 -2
View File
@@ -2,10 +2,10 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Feb 9 23:33:42 2025
// Date : Tue Feb 11 19:47:38 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/axi_crc_dma_syn_1_axis_crc_0_0_stub.v
// Design : axi_crc_dma_syn_1_axis_crc_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd
+3 -3
View File
@@ -95,19 +95,19 @@ ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0
END COMPONENT axis_crc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_crc
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_crc_0_0/synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd
+3 -3
View File
@@ -103,19 +103,19 @@ ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0
ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 1e+08, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_crc
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0.xml
+47 -47
View File
@@ -119,7 +119,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -137,7 +137,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -278,7 +278,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -296,7 +296,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -625,7 +625,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -832,7 +832,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1052,7 +1052,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1259,7 +1259,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1370,7 +1370,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1397,7 +1397,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1514,7 +1514,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:59:44 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:38:52 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2845,22 +2845,22 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
@@ -2868,13 +2868,13 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -2888,36 +2888,36 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Feb 10 22:59:44 2025
// Date : Tue Feb 11 19:38:52 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_sim_netlist.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Feb 10 22:59:44 2025
// Date : Tue Feb 11 19:38:52 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_dma_0_0/axi_crc_dma_syn_1_axis_dma_0_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_0_0/axi_crc_dma_syn_1_axis_fifo_0_0.xml
+21 -21
View File
@@ -561,7 +561,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -579,7 +579,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -728,7 +728,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -746,7 +746,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -899,7 +899,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -926,7 +926,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -979,7 +979,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1006,7 +1006,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1145,7 +1145,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 13:29:20 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:39:37 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1965,6 +1965,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -1979,18 +1991,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_0_0/axi_crc_dma_syn_1_axis_fifo_0_0_sim_netlist.v
+4 -4
View File
@@ -2,18 +2,18 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Fri Feb 7 16:13:59 2025
// Date : Tue Feb 11 19:38:36 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top axi_crc_dma_syn_1_axis_fifo_0_0 -prefix
// axi_crc_dma_syn_1_axis_fifo_0_0_ axi_crc_dma_syn_1_axis_fifo_0_0_sim_netlist.v
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
// axi_crc_dma_syn_1_axis_fifo_0_0_ axi_crc_dma_syn_1_axis_fifo_1_0_sim_netlist.v
// Design : axi_crc_dma_syn_1_axis_fifo_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_axis_fifo_0_0,axis_fifo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axis_fifo,Vivado 2023.1" *)
(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_axis_fifo_1_0,axis_fifo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axis_fifo,Vivado 2023.1" *)
(* NotValidForBitStream *)
module axi_crc_dma_syn_1_axis_fifo_0_0
(S_AXIS_ACLK,
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_0_0/axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
+3 -3
View File
@@ -2,11 +2,11 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Fri Feb 7 16:13:59 2025
// Date : Tue Feb 11 19:38:36 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_axis_fifo_0_0 -prefix
// axi_crc_dma_syn_1_axis_fifo_0_0_ axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
// axi_crc_dma_syn_1_axis_fifo_0_0_ axi_crc_dma_syn_1_axis_fifo_1_0_stub.v
// Design : axi_crc_dma_syn_1_axis_fifo_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_1_0/axi_crc_dma_syn_1_axis_fifo_1_0.xml
+21 -21
View File
@@ -561,7 +561,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -579,7 +579,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -728,7 +728,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -746,7 +746,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -899,7 +899,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -926,7 +926,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -979,7 +979,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1006,7 +1006,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1145,7 +1145,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 08 13:29:20 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:38:38 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -1965,6 +1965,18 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_1_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_1_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_1_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -1979,18 +1991,6 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_1_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>axi_crc_dma_syn_1_axis_fifo_1_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_1_0/axi_crc_dma_syn_1_axis_fifo_1_0_sim_netlist.v
+8 -5
View File
@@ -2,18 +2,18 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Fri Feb 7 16:13:59 2025
// Date : Tue Feb 11 19:38:38 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top axi_crc_dma_syn_1_axis_fifo_1_0 -prefix
// axi_crc_dma_syn_1_axis_fifo_1_0_ axi_crc_dma_syn_1_axis_fifo_0_0_sim_netlist.v
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_1_0/axi_crc_dma_syn_1_axis_fifo_1_0_sim_netlist.v
// Design : axi_crc_dma_syn_1_axis_fifo_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_axis_fifo_0_0,axis_fifo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axis_fifo,Vivado 2023.1" *)
(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_axis_fifo_1_0,axis_fifo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axis_fifo,Vivado 2023.1" *)
(* NotValidForBitStream *)
module axi_crc_dma_syn_1_axis_fifo_1_0
(S_AXIS_ACLK,
@@ -83,6 +83,7 @@ module axi_crc_dma_syn_1_axis_fifo_1_0
.S_NUM_FREE(S_NUM_FREE));
endmodule
(* ORIG_REF_NAME = "axis_fifo" *)
module axi_crc_dma_syn_1_axis_fifo_1_0_axis_fifo
(M_AXIS_TDATA,
DOPADOP,
@@ -145,6 +146,7 @@ module axi_crc_dma_syn_1_axis_fifo_1_0_axis_fifo
.S_NUM_FREE(S_NUM_FREE));
endmodule
(* ORIG_REF_NAME = "bmem_dp" *)
module axi_crc_dma_syn_1_axis_fifo_1_0_bmem_dp
(M_AXIS_TDATA,
DOPADOP,
@@ -497,6 +499,7 @@ module axi_crc_dma_syn_1_axis_fifo_1_0_bmem_dp
.O(E));
endmodule
(* ORIG_REF_NAME = "generic_fifo" *)
module axi_crc_dma_syn_1_axis_fifo_1_0_generic_fifo
(M_AXIS_TDATA,
DOPADOP,
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_1_0/axi_crc_dma_syn_1_axis_fifo_1_0_stub.v
+4 -4
View File
@@ -2,11 +2,11 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Fri Feb 7 16:13:59 2025
// Date : Tue Feb 11 19:38:38 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_axis_fifo_1_0 -prefix
// axi_crc_dma_syn_1_axis_fifo_1_0_ axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axis_fifo_1_0/axi_crc_dma_syn_1_axis_fifo_1_0_stub.v
// Design : axi_crc_dma_syn_1_axis_fifo_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xml
+33 -33
View File
@@ -4076,7 +4076,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -4256,7 +4256,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -5275,7 +5275,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -5464,7 +5464,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -9107,7 +9107,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">100000000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -9199,7 +9199,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK1.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">125000000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK1.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">1.25e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -9291,7 +9291,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK2.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">200000000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK2.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">2e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -9383,7 +9383,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK3.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">66666672</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FCLK_CLK3.FREQ_HZ" spirit:dependency="(spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)))" spirit:minimum="100000" spirit:maximum="333000000">6.66667e+07</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -10968,7 +10968,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -10995,7 +10995,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -11152,7 +11152,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP_ACLK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP_ACLK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -11179,7 +11179,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP_ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACP_ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -15203,7 +15203,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:691774a9</spirit:value>
<spirit:value>9:2ec54347</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -15218,11 +15218,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:33 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:56 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4d392fa0</spirit:value>
<spirit:value>9:cec8ac07</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -15241,11 +15241,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:34 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:56 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:691774a9</spirit:value>
<spirit:value>9:2ec54347</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -15260,11 +15260,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:37 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:58 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4d392fa0</spirit:value>
<spirit:value>9:cec8ac07</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -15283,11 +15283,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:32 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:54 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:06e1c9c4</spirit:value>
<spirit:value>9:f4c3f48a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -15301,11 +15301,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:07:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:38:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:06e1c9c4</spirit:value>
<spirit:value>9:f4c3f48a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -15316,7 +15316,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:06e1c9c4</spirit:value>
<spirit:value>9:f4c3f48a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -15332,11 +15332,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:33 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:56 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e0c97780</spirit:value>
<spirit:value>9:3f15fe76</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -15356,11 +15356,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:34 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:56 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e0c97780</spirit:value>
<spirit:value>9:3f15fe76</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -15380,11 +15380,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 11:05:32 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:54 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:06e1c9c4</spirit:value>
<spirit:value>9:f4c3f48a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -35677,7 +35677,7 @@
<spirit:parameter>
<spirit:name>PCW_M_AXI_GP0_FREQMHZ</spirit:name>
<spirit:displayName>PCW M AXI GP0 FREQMHZ</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_FREQMHZ" spirit:order="45601">66</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_FREQMHZ" spirit:order="45601">100.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -35725,7 +35725,7 @@
<spirit:parameter>
<spirit:name>PCW_S_AXI_ACP_FREQMHZ</spirit:name>
<spirit:displayName>PCW S AXI ACP FREQMHZ</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ" spirit:order="46001">66</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ" spirit:order="46001">100.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -36285,7 +36285,7 @@
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP0_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0)) = 1) ">false</xilinx:isEnabled>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP0_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0)) = 1) ">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0_sim_netlist.v
+11 -11
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 12:07:14 2025
// Date : Tue Feb 11 19:38:42 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0_sim_netlist.v
@@ -164,7 +164,7 @@ module axi_crc_dma_syn_1_processing_system7_0_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
@@ -175,7 +175,7 @@ module axi_crc_dma_syn_1_processing_system7_0_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARREADY" *) output S_AXI_ACP_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWREADY" *) output S_AXI_ACP_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BVALID" *) output S_AXI_ACP_BVALID;
@@ -187,7 +187,7 @@ module axi_crc_dma_syn_1_processing_system7_0_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BID" *) output [2:0]S_AXI_ACP_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RID" *) output [2:0]S_AXI_ACP_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RDATA" *) output [63:0]S_AXI_ACP_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_ACP_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP_ACLK, ASSOCIATED_BUSIF S_AXI_ACP, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) input S_AXI_ACP_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_ACP_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP_ACLK, ASSOCIATED_BUSIF S_AXI_ACP, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input S_AXI_ACP_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARVALID" *) input S_AXI_ACP_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWVALID" *) input S_AXI_ACP_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP BREADY" *) input S_AXI_ACP_BREADY;
@@ -216,12 +216,12 @@ module axi_crc_dma_syn_1_processing_system7_0_0
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARUSER" *) input [4:0]S_AXI_ACP_ARUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP AWUSER" *) input [4:0]S_AXI_ACP_AWUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WDATA" *) input [63:0]S_AXI_ACP_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [7:0]S_AXI_ACP_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [7:0]S_AXI_ACP_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) output FCLK_CLK1;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *) output FCLK_CLK2;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) output FCLK_CLK3;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 1.25e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *) output FCLK_CLK1;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 2e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *) output FCLK_CLK2;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 6.66667e+07, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) output FCLK_CLK3;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
@@ -708,7 +708,7 @@ module axi_crc_dma_syn_1_processing_system7_0_0
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "axi_crc_dma_syn_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={66} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={66} usageRate={0.5} />/>" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={100.0} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100.0} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
axi_crc_dma_syn_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
@@ -1417,7 +1417,7 @@ endmodule
(* C_USE_S_AXI_ACP = "1" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "axi_crc_dma_syn_1_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={66} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={66} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={100.0} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100.0} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module axi_crc_dma_syn_1_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 12:07:14 2025
// Date : Tue Feb 11 19:38:42 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
+3 -3
View File
@@ -149,10 +149,10 @@
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={66} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={66} usageRate={0.5} />/>" *)
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={100.0} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100.0} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.050, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.044, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.035, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.100, PCW_UIPARAM_DDR_BOARD_DELAY0=0.221, PCW_UIPARAM_DDR_BOARD_DELAY1=0.222, PCW_UIPARAM_DDR_BOARD_DELAY2=0.217, PCW_UIPARAM_DDR_BOARD_DELAY3=0.244, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=27.9, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=29.4, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=27.9, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=29.4, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=18.8, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=18.8, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=18.8, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=18.8, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=105.056, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=66.904, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=89.1715, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=113.63, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=98.503, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=68.5855, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=90.295, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=103.977, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=80.4535, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=125, PCW_FPGA2_PERIPHERAL_FREQMHZ=200, PCW_FPGA3_PERIPHERAL_FREQMHZ=65, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=1, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=66\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=66, PCW_S_AXI_HP0_FREQMHZ=66, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=125, PCW_FPGA2_PERIPHERAL_FREQMHZ=200, PCW_FPGA3_PERIPHERAL_FREQMHZ=65, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=1, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100.0\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=100.0, PCW_S_AXI_HP0_FREQMHZ=66, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=32, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\
, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 10 .. 11, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0\
, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 14 .. 15, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=MIO 12 .. 13, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/synth/axi_crc_dma_syn_1_processing_system7_0_0.v
+10 -10
View File
@@ -239,7 +239,7 @@ output wire [3 : 0] M_AXI_GP0_AWLEN;
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
@@ -262,8 +262,8 @@ input wire [11 : 0] M_AXI_GP0_RID;
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_REA\
D_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
HREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARREADY" *)
@@ -288,7 +288,7 @@ output wire [2 : 0] S_AXI_ACP_BID;
output wire [2 : 0] S_AXI_ACP_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP RDATA" *)
output wire [63 : 0] S_AXI_ACP_RDATA;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP_ACLK, ASSOCIATED_BUSIF S_AXI_ACP, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP_ACLK, ASSOCIATED_BUSIF S_AXI_ACP, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_ACP_ACLK CLK" *)
input wire S_AXI_ACP_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP ARVALID" *)
@@ -347,23 +347,23 @@ input wire [4 : 0] S_AXI_ACP_ARUSER;
input wire [4 : 0] S_AXI_ACP_AWUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WDATA" *)
input wire [63 : 0] S_AXI_ACP_WDATA;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_ACP, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 3, ADDR_WIDTH 32, AWUSER_WIDTH 5, ARUSER_WIDTH 5, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH\
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_ACP WSTRB" *)
input wire [7 : 0] S_AXI_ACP_WSTRB;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [0 : 0] IRQ_F2P;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 1.25e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK1, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *)
output wire FCLK_CLK1;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 200000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 2e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK2, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *)
output wire FCLK_CLK2;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 6.66667e+07, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *)
output wire FCLK_CLK3;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/axi_crc_dma_syn_1_rst_ps7_0_100M_0.xml
+15 -15
View File
@@ -30,7 +30,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -52,7 +52,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -398,11 +398,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:18:43 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:40:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d7e00b03</spirit:value>
<spirit:value>9:52fc2f24</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -416,11 +416,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:17:22 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d7e00b03</spirit:value>
<spirit:value>9:52fc2f24</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -434,11 +434,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:17:22 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d7e00b03</spirit:value>
<spirit:value>9:52fc2f24</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -461,7 +461,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2065e500</spirit:value>
<spirit:value>9:3f28786b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -477,11 +477,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:17:22 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2065e500</spirit:value>
<spirit:value>9:3f28786b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -500,11 +500,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:17:22 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d7e00b03</spirit:value>
<spirit:value>9:52fc2f24</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -520,11 +520,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Feb 10 21:17:22 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:59 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d7e00b03</spirit:value>
<spirit:value>9:52fc2f24</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/axi_crc_dma_syn_1_rst_ps7_0_100M_0_ooc.xdc
+1 -1
View File
@@ -52,6 +52,6 @@
# #########################################################
create_clock -period 15 -name slowest_sync_clk [get_ports slowest_sync_clk]
create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/axi_crc_dma_syn_1_rst_ps7_0_100M_0_sim_netlist.v
+2 -2
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Feb 10 22:18:43 2025
// Date : Tue Feb 11 19:40:08 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/axi_crc_dma_syn_1_rst_ps7_0_100M_0_sim_netlist.v
@@ -26,7 +26,7 @@ module axi_crc_dma_syn_1_rst_ps7_0_100M_0
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/axi_crc_dma_syn_1_rst_ps7_0_100M_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Mon Feb 10 22:18:43 2025
// Date : Tue Feb 11 19:40:08 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-abschlussprojekt2/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/axi_crc_dma_syn_1_rst_ps7_0_100M_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/sim/axi_crc_dma_syn_1_rst_ps7_0_100M_0.vhd
+1 -1
View File
@@ -117,7 +117,7 @@ ARCHITECTURE axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch OF axi_crc_dma_syn_1_rst_ps
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_rst_ps7_0_100M_0/synth/axi_crc_dma_syn_1_rst_ps7_0_100M_0.vhd
+1 -1
View File
@@ -123,7 +123,7 @@ ARCHITECTURE axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch OF axi_crc_dma_syn_1_rst_ps
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0.xml
+15 -23
View File
@@ -23,7 +23,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -50,7 +50,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -311,7 +311,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -518,7 +518,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -904,7 +904,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1111,7 +1111,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1465,7 +1465,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1672,7 +1672,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1906,7 +1906,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2113,7 +2113,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2181,7 +2181,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:09 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:03 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2199,7 +2199,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:25:35 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:35:33 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2235,7 +2235,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:39 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:24 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2254,7 +2254,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:09 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:03 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2273,10 +2273,6 @@
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:82b36c6a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>rtl</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
@@ -2297,10 +2293,6 @@
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:82b36c6a</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>rtl</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
@@ -2315,7 +2307,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:09 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:03 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0_ooc.xdc
+1 -1
View File
@@ -52,6 +52,6 @@
# #########################################################
create_clock -period 15 -name clk [get_ports clk]
create_clock -period 10 -name clk [get_ports clk]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0_sim_netlist.v
+137247 -137231
View File
File diff suppressed because it is too large Load Diff
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0_stub.v
+1 -1
View File
@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Feb 11 14:38:40 2025
// Date : Tue Feb 11 19:43:27 2025
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_system_ila_0_0 -prefix
// axi_crc_dma_syn_1_system_ila_0_0_ axi_crc_dma_syn_1_system_ila_0_0_stub.v
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/bd_2505.bd
+12 -12
View File
@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0x8F8EEED5F26BDFF6",
"boundary_crc": "0x8F8EEED5C4BCD9CC",
"design_src": "SBD",
"device": "xc7z020clg400-1",
"name": "bd_2505",
@@ -60,7 +60,7 @@
"value_src": "default"
},
"CLK_DOMAIN": {
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3",
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
},
"DATA_WIDTH": {
@@ -68,7 +68,7 @@
"value_src": "default"
},
"FREQ_HZ": {
"value": "66666672",
"value": "1e+08",
"value_src": "default"
},
"HAS_BRESP": {
@@ -191,7 +191,7 @@
"value_src": "default"
},
"CLK_DOMAIN": {
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3",
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
},
"DATA_WIDTH": {
@@ -199,7 +199,7 @@
"value_src": "default"
},
"FREQ_HZ": {
"value": "66666672",
"value": "1e+08",
"value_src": "default"
},
"HAS_BRESP": {
@@ -322,7 +322,7 @@
"value_src": "default"
},
"CLK_DOMAIN": {
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3",
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
},
"DATA_WIDTH": {
@@ -330,7 +330,7 @@
"value_src": "default"
},
"FREQ_HZ": {
"value": "66666672",
"value": "1e+08",
"value_src": "default"
},
"HAS_BRESP": {
@@ -453,7 +453,7 @@
"value_src": "default"
},
"CLK_DOMAIN": {
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3",
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
},
"DATA_WIDTH": {
@@ -461,7 +461,7 @@
"value_src": "default"
},
"FREQ_HZ": {
"value": "66666672",
"value": "1e+08",
"value_src": "default"
},
"HAS_BRESP": {
@@ -575,11 +575,11 @@
"value": "resetn"
},
"CLK_DOMAIN": {
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3",
"value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0",
"value_src": "default_prop"
},
"FREQ_HZ": {
"value": "66666672",
"value": "1e+08",
"value_src": "default_prop"
},
"FREQ_TOLERANCE_HZ": {
@@ -649,7 +649,7 @@
"value": "0"
},
"C_ILA_CLK_FREQ": {
"value": "66666672"
"value": "100000000"
},
"C_INPUT_PIPE_STAGES": {
"value": "0"
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/bd_2505.bxml
+4 -10
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="bd_2505" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739281394"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739281394"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739281394"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739281394"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739299568"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739299568"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739299568"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739299568"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\bd_2505.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
@@ -19,12 +19,6 @@
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\bd_2505.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="bd_2505_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/bd_2505_ooc.xdc
+1 -1
View File
@@ -6,6 +6,6 @@
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name clk -period 15 [get_ports clk]
create_clock -name clk -period 10 [get_ports clk]
################################################################################
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_0/bd_2505_ila_lib_0.xci
+3 -3
View File
@@ -2068,7 +2068,7 @@
"C_EN_DDR_ILA": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"C_DDR_CLK_GEN": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"C_CLK_FREQ": [ { "value": "200", "resolve_type": "user", "format": "float", "usage": "all" } ],
"C_ILA_CLK_FREQ": [ { "value": "66666672", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_ILA_CLK_FREQ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_CLK_PERIOD": [ { "value": "5", "resolve_type": "user", "format": "float", "usage": "all" } ],
"C_CLKFBOUT_MULT_F": [ { "value": "10", "resolve_type": "user", "format": "float", "usage": "all" } ],
"C_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -6385,10 +6385,10 @@
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_0_AXIS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_0/bd_2505_ila_lib_0.xml
+12 -12
View File
@@ -91,7 +91,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>clk frequency</spirit:displayName>
<spirit:description>clk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -113,7 +113,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1046,11 +1046,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:10 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:94e93606</spirit:value>
<spirit:value>9:58f34699</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1065,11 +1065,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:10 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:94e93606</spirit:value>
<spirit:value>9:58f34699</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1080,7 +1080,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:94e93606</spirit:value>
<spirit:value>9:58f34699</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1096,11 +1096,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:10 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:45ed6dd3</spirit:value>
<spirit:value>9:14bb298f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1116,11 +1116,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:10 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:04 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:94e93606</spirit:value>
<spirit:value>9:58f34699</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -69581,7 +69581,7 @@
<spirit:parameter>
<spirit:name>C_ILA_CLK_FREQ</spirit:name>
<spirit:displayName>Clk Freq</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ILA_CLK_FREQ" spirit:order="206123">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ILA_CLK_FREQ" spirit:order="206123">100000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_CLK_PERIOD</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_0/synth/bd_2505_ila_lib_0.vhd
+2 -2
View File
@@ -4311,7 +4311,7 @@ ATTRIBUTE X_CORE_INFO OF bd_2505_ila_lib_0_arch : ARCHITECTURE IS "ila,Vivado 20
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_2505_ila_lib_0_arch : ARCHITECTURE IS "bd_2505_ila_lib_0,ila_v6_2_13_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bd_2505_ila_lib_0_arch : ARCHITECTURE IS "bd_2505_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=105,C_DATA_DEPTH=4096,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=66666672,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE2_WIDTH=2,C_PROBE3_WIDTH=2,C_PROBE4_WIDTH=8,C_PROBE5_WIDTH=3,C_PROBE6_WIDTH=2,C_PROBE7_WIDTH=8,C_PROBE8_WIDTH=3,C_PROBE9_WIDTH=2,C_PROBE10_WIDTH=2,C_PROBE11_WIDTH=2,C_PROBE12_WIDTH=32,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=32,C_PROBE15_WIDTH=4,C_PROBE16_WIDTH=2,C_PROBE17_WIDTH=2,C_PROBE18_WIDTH=2,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=2,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=160,C_PROBE23_WIDTH=2,C_PROBE24_WIDTH=32,C_PROBE25_WIDTH=2,C_PROBE26_WIDTH=4,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=4,C_PROBE29_WIDTH=3,C_PROBE30_WIDTH=3,C_PROBE31_WIDTH=2,C_PROBE32_WIDTH=32,C_PROBE33_WIDTH=2,C_PROBE34_WIDTH=4,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=4,C_PROBE37_WIDTH=3,C_PROBE38_WIDTH=3,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=2,C_PROBE42_WIDTH=2,C_PROBE43_WIDTH=32,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=2,C_PROBE46_WIDTH=32,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=4,C_PROBE49_WIDTH=2,C_PROBE50_WIDTH=3,C_PROBE51_WIDTH=2,C_PROBE52_WIDTH=2,C_PROBE53_WIDTH=3,"&
ATTRIBUTE CORE_GENERATION_INFO OF bd_2505_ila_lib_0_arch : ARCHITECTURE IS "bd_2505_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=105,C_DATA_DEPTH=4096,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE2_WIDTH=2,C_PROBE3_WIDTH=2,C_PROBE4_WIDTH=8,C_PROBE5_WIDTH=3,C_PROBE6_WIDTH=2,C_PROBE7_WIDTH=8,C_PROBE8_WIDTH=3,C_PROBE9_WIDTH=2,C_PROBE10_WIDTH=2,C_PROBE11_WIDTH=2,C_PROBE12_WIDTH=32,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=32,C_PROBE15_WIDTH=4,C_PROBE16_WIDTH=2,C_PROBE17_WIDTH=2,C_PROBE18_WIDTH=2,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=2,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=160,C_PROBE23_WIDTH=2,C_PROBE24_WIDTH=32,C_PROBE25_WIDTH=2,C_PROBE26_WIDTH=4,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=4,C_PROBE29_WIDTH=3,C_PROBE30_WIDTH=3,C_PROBE31_WIDTH=2,C_PROBE32_WIDTH=32,C_PROBE33_WIDTH=2,C_PROBE34_WIDTH=4,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=4,C_PROBE37_WIDTH=3,C_PROBE38_WIDTH=3,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=2,C_PROBE42_WIDTH=2,C_PROBE43_WIDTH=32,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=2,C_PROBE46_WIDTH=32,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=4,C_PROBE49_WIDTH=2,C_PROBE50_WIDTH=3,C_PROBE51_WIDTH=2,C_PROBE52_WIDTH=2,C_PROBE53_WIDTH=3,"&
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=160,C_PROBE56_WIDTH=2,C_PROBE57_WIDTH=32,C_PROBE58_WIDTH=2,C_PROBE59_WIDTH=4,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=4,C_PROBE62_WIDTH=3,C_PROBE63_WIDTH=3,C_PROBE64_WIDTH=2,C_PROBE65_WIDTH=32,C_PROBE66_WIDTH=2,C_PROBE67_WIDTH=4,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=4,C_PROBE70_WIDTH=3,C_PROBE71_WIDTH=3,C_PROBE72_WIDTH=2,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=2,C_PROBE75_WIDTH=2,C_PROBE76_WIDTH=32,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=2,C_PROBE79_WIDTH=32,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=4,C_PROBE82_WIDTH=2,C_PROBE83_WIDTH=3,C_PROBE84_WIDTH=2,C_PROBE85_WIDTH=2,C_PROBE86_WIDTH=3,C_PROBE87_WIDTH=2,C_PROBE88_WIDTH=16,C_PROBE89_WIDTH=3,C_PROBE90_WIDTH=2,C_PROBE91_WIDTH=16,C_PROBE92_WIDTH=3,C_PROBE93_WIDTH=2,C_PROBE94_WIDTH=2,C_PROBE95_WIDTH=2,C_PROBE96_WIDTH=32,C_PROBE97_WIDTH=2,C_PROBE98_WIDTH=32,C_PROBE99_WIDTH=4,C_PROBE100_WIDTH=2,C_PROBE101_WIDTH=2,C_PROBE102_WIDTH=2,C_PROBE103_WIDTH=2,C_PROBE104_WIDTH=2,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
@@ -4379,7 +4379,7 @@ C_EN_STRG_QUAL => 0,
C_INPUT_PIPE_STAGES => 0,
C_EN_TIME_TAG => 0,
C_TIME_TAG_WIDTH => 32,
C_ILA_CLK_FREQ => 66666672,
C_ILA_CLK_FREQ => 100000000,
C_PROBE0_WIDTH => 1,
C_PROBE1_WIDTH => 1,
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_1/bd_2505_g_inst_0.xci
+18 -18
View File
@@ -2961,10 +2961,10 @@
"parameters": {
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"ASSOCIATED_BUSIF": [ { "value": "m_slot_0_axi:m_slot_1_axi:m_slot_2_axi:m_slot_3_axi:m_slot_4_axi:m_slot_5_axi:m_slot_6_axi:m_slot_7_axi:m_slot_8_axi:m_slot_9_axi:m_slot_10_axi:m_slot_11_axi:m_slot_12_axi:m_slot_13_axi:m_slot_14_axi:m_slot_15_axi:m_slot_0_axis:m_slot_1_axis:m_slot_2_axis:m_slot_3_axis:m_slot_4_axis:m_slot_5_axis:m_slot_6_axis:m_slot_7_axis:m_slot_8_axis:m_slot_9_axis:m_slot_10_axis:m_slot_11_axis:m_slot_12_axis:m_slot_13_axis:m_slot_14_axis:m_slot_15_axis:slot_0_axi:slot_1_axi:slot_2_axi:slot_3_axi:slot_4_axi:slot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:slot_12_axi:slot_13_axi:slot_14_axi:slot_15_axi:slot_0_axis:slot_1_axis:slot_2_axis:slot_3_axis:slot_4_axis:slot_5_axis:slot_6_axis:slot_7_axis:slot_8_axis:slot_9_axis:slot_10_axis:slot_11_axis:slot_12_axis:slot_13_axis:slot_14_axis:slot_15_axis:mux_0_axis:mux_1_axis:mux_2_axis:mux_3_axis:mux_0_axi:mux_1_axi:mux_2_axi:mux_3_axi", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "66666672", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "1e+08", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
@@ -2991,7 +2991,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3014,7 +3014,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3050,7 +3050,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3073,7 +3073,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3124,7 +3124,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3147,7 +3147,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3198,7 +3198,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3221,7 +3221,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3257,7 +3257,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3280,7 +3280,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3316,7 +3316,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3339,7 +3339,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3390,7 +3390,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3413,7 +3413,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3464,7 +3464,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -3487,7 +3487,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_1/bd_2505_g_inst_0.xml
+27 -27
View File
@@ -34,7 +34,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>aclk frequency</spirit:displayName>
<spirit:description>aclk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -56,7 +56,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -502,7 +502,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -709,7 +709,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_0_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1364,7 +1364,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1571,7 +1571,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_1_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2226,7 +2226,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2433,7 +2433,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_2_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -3088,7 +3088,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -3295,7 +3295,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SLOT_3_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -17742,7 +17742,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_0_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_0_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -17949,7 +17949,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_0_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_0_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -18604,7 +18604,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_1_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_1_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -18811,7 +18811,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_1_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_1_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -19466,7 +19466,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_2_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_2_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -19673,7 +19673,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_2_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_2_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -20328,7 +20328,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_3_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_3_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -20535,7 +20535,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_3_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_SLOT_3_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -31156,7 +31156,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a451c5e4</spirit:value>
<spirit:value>9:6b45d273</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -31172,11 +31172,11 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c2054979</spirit:value>
<spirit:value>9:70e8dddc</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -31192,11 +31192,11 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c2054979</spirit:value>
<spirit:value>9:70e8dddc</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -31212,11 +31212,11 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a451c5e4</spirit:value>
<spirit:value>9:6b45d273</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -31232,11 +31232,11 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a451c5e4</spirit:value>
<spirit:value>9:6b45d273</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_2505_g_inst_0.v
+18 -18
View File
@@ -287,8 +287,8 @@ module bd_2505_g_inst_0 (
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET aresetn, ASSOCIATED_BUSIF m_slot_0_axi:m_slot_1_axi:m_slot_2_axi:m_slot_3_axi:m_slot_4_axi:m_slot_5_axi:m_slot_6_axi:m_slot_7_axi:m_slot_8_axi:m_slot_9_axi:m_slot_10_axi:m_slot_11_axi:m_slot_12_axi:m_slot_13_axi:m_slot_14_axi:m_slot_15_axi:m_slot_0_axis:m_slot_1_axis:m_slot_2_axis:m_slot_3_axis:m_slot_4_axis:m_slot_5_axis:m_slot_6_axis:m_slot_7_axis:m_slot_8_axis:m_slot_9_axis:m_slot_10_axis:m_slot_11_axis:m_slot_12_axis:m_slot_13_axis:m_slot_14_a\
xis:m_slot_15_axis:slot_0_axi:slot_1_axi:slot_2_axi:slot_3_axi:slot_4_axi:slot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:slot_12_axi:slot_13_axi:slot_14_axi:slot_15_axi:slot_0_axis:slot_1_axis:slot_2_axis:slot_3_axis:slot_4_axis:slot_5_axis:slot_6_axis:slot_7_axis:slot_8_axis:slot_9_axis:slot_10_axis:slot_11_axis:slot_12_axis:slot_13_axis:slot_14_axis:slot_15_axis:mux_0_axis:mux_1_axis:mux_2_axis:mux_3_axis:mux_0_axi:mux_1_axi:mux_2_axi:mux_3_axi, FREQ_HZ 66666672\
, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
xis:m_slot_15_axis:slot_0_axi:slot_1_axi:slot_2_axi:slot_3_axi:slot_4_axi:slot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:slot_12_axi:slot_13_axi:slot_14_axi:slot_15_axi:slot_0_axis:slot_1_axis:slot_2_axis:slot_3_axis:slot_4_axis:slot_5_axis:slot_6_axis:slot_7_axis:slot_8_axis:slot_9_axis:slot_10_axis:slot_11_axis:slot_12_axis:slot_13_axis:slot_14_axis:slot_15_axis:mux_0_axis:mux_1_axis:mux_2_axis:mux_3_axis:mux_0_axi:mux_1_axi:mux_2_axi:mux_3_axi, FREQ_HZ 1e+08, F\
REQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
@@ -346,8 +346,8 @@ input wire [31 : 0] slot_0_axi_rdata;
input wire [1 : 0] slot_0_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RVALID" *)
input wire slot_0_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RREADY" *)
input wire slot_0_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWID" *)
@@ -518,8 +518,8 @@ input wire [31 : 0] slot_3_axi_rdata;
input wire [1 : 0] slot_3_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_3_axi RVALID" *)
input wire slot_3_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_\
READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_3_axi RREADY" *)
input wire slot_3_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi AWADDR" *)
@@ -558,8 +558,8 @@ output wire [31 : 0] m_slot_0_axi_rdata;
output wire [1 : 0] m_slot_0_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RVALID" *)
output wire m_slot_0_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM\
_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_RE\
AD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RREADY" *)
output wire m_slot_0_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWID" *)
@@ -730,24 +730,24 @@ output wire [31 : 0] m_slot_3_axi_rdata;
output wire [1 : 0] m_slot_3_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_3_axi RVALID" *)
output wire m_slot_3_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NU\
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_3_axi RREADY" *)
output wire m_slot_3_axi_rready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
HREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WID" *)
input wire [0 : 0] slot_1_axi_wid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
HREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_2_axi WID" *)
input wire [0 : 0] slot_2_axi_wid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WID" *)
output wire [0 : 0] m_slot_1_axi_wid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_2_axi WID" *)
output wire [0 : 0] m_slot_2_axi_wid;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_1/synth/bd_2505_g_inst_0.v
+18 -18
View File
@@ -347,8 +347,8 @@ module bd_2505_g_inst_0 (
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_clock, ASSOCIATED_RESET aresetn, ASSOCIATED_BUSIF m_slot_0_axi:m_slot_1_axi:m_slot_2_axi:m_slot_3_axi:m_slot_4_axi:m_slot_5_axi:m_slot_6_axi:m_slot_7_axi:m_slot_8_axi:m_slot_9_axi:m_slot_10_axi:m_slot_11_axi:m_slot_12_axi:m_slot_13_axi:m_slot_14_axi:m_slot_15_axi:m_slot_0_axis:m_slot_1_axis:m_slot_2_axis:m_slot_3_axis:m_slot_4_axis:m_slot_5_axis:m_slot_6_axis:m_slot_7_axis:m_slot_8_axis:m_slot_9_axis:m_slot_10_axis:m_slot_11_axis:m_slot_12_axis:m_slot_13_axis:m_slot_14_a\
xis:m_slot_15_axis:slot_0_axi:slot_1_axi:slot_2_axi:slot_3_axi:slot_4_axi:slot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:slot_12_axi:slot_13_axi:slot_14_axi:slot_15_axi:slot_0_axis:slot_1_axis:slot_2_axis:slot_3_axis:slot_4_axis:slot_5_axis:slot_6_axis:slot_7_axis:slot_8_axis:slot_9_axis:slot_10_axis:slot_11_axis:slot_12_axis:slot_13_axis:slot_14_axis:slot_15_axis:mux_0_axis:mux_1_axis:mux_2_axis:mux_3_axis:mux_0_axi:mux_1_axi:mux_2_axi:mux_3_axi, FREQ_HZ 66666672\
, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
xis:m_slot_15_axis:slot_0_axi:slot_1_axi:slot_2_axi:slot_3_axi:slot_4_axi:slot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:slot_12_axi:slot_13_axi:slot_14_axi:slot_15_axi:slot_0_axis:slot_1_axis:slot_2_axis:slot_3_axis:slot_4_axis:slot_5_axis:slot_6_axis:slot_7_axis:slot_8_axis:slot_9_axis:slot_10_axis:slot_11_axis:slot_12_axis:slot_13_axis:slot_14_axis:slot_15_axis:mux_0_axis:mux_1_axis:mux_2_axis:mux_3_axis:mux_0_axi:mux_1_axi:mux_2_axi:mux_3_axi, FREQ_HZ 1e+08, F\
REQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
@@ -406,8 +406,8 @@ input wire [31 : 0] slot_0_axi_rdata;
input wire [1 : 0] slot_0_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RVALID" *)
input wire slot_0_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_0_axi RREADY" *)
input wire slot_0_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi AWID" *)
@@ -578,8 +578,8 @@ input wire [31 : 0] slot_3_axi_rdata;
input wire [1 : 0] slot_3_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_3_axi RVALID" *)
input wire slot_3_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_\
READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_3_axi RREADY" *)
input wire slot_3_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi AWADDR" *)
@@ -618,8 +618,8 @@ output wire [31 : 0] m_slot_0_axi_rdata;
output wire [1 : 0] m_slot_0_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RVALID" *)
output wire m_slot_0_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM\
_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_0_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_RE\
AD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_0_axi RREADY" *)
output wire m_slot_0_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi AWID" *)
@@ -790,24 +790,24 @@ output wire [31 : 0] m_slot_3_axi_rdata;
output wire [1 : 0] m_slot_3_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_3_axi RVALID" *)
output wire m_slot_3_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NU\
M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_3_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_3_axi RREADY" *)
output wire m_slot_3_axi_rready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
HREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_1_axi WID" *)
input wire [0 : 0] slot_1_axi_wid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_REA\
D_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
HREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slot_2_axi WID" *)
input wire [0 : 0] slot_2_axi_wid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_1_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_1_axi WID" *)
output wire [0 : 0] m_slot_1_axi_wid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_R\
EAD_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_slot_2_axi, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_slot_2_axi WID" *)
output wire [0 : 0] m_slot_2_axi_wid;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_10/bd_2505_slot_1_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_11/bd_2505_slot_1_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_12/bd_2505_slot_1_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_13/bd_2505_slot_1_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_14/bd_2505_slot_2_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_15/bd_2505_slot_2_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_16/bd_2505_slot_2_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_17/bd_2505_slot_2_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_18/bd_2505_slot_2_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_19/bd_2505_slot_3_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_2/bd_2505_slot_0_apc_0.xci
+4 -4
View File
@@ -133,7 +133,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -156,7 +156,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -192,10 +192,10 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:PC_AXI", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_2/bd_2505_slot_0_apc_0.xml
+13 -13
View File
@@ -394,7 +394,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -601,7 +601,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1038,7 +1038,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>aclk frequency</spirit:displayName>
<spirit:description>aclk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -1060,7 +1060,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1257,7 +1257,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9bdb5174</spirit:value>
<spirit:value>9:6534d6f0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1276,11 +1276,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5977df94</spirit:value>
<spirit:value>9:ea4d47c4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1296,11 +1296,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5977df94</spirit:value>
<spirit:value>9:ea4d47c4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1319,11 +1319,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9bdb5174</spirit:value>
<spirit:value>9:6534d6f0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1339,11 +1339,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9bdb5174</spirit:value>
<spirit:value>9:6534d6f0</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_2/sim/bd_2505_slot_0_apc_0.sv
+3 -3
View File
@@ -81,7 +81,7 @@ module bd_2505_slot_0_apc_0 (
output wire [159 : 0] pc_status;
output wire pc_asserted;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
@@ -123,8 +123,8 @@ input wire [31 : 0] pc_axi_rdata;
input wire [1 : 0] pc_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RVALID" *)
input wire pc_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_\
THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RREADY" *)
input wire pc_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_2/synth/bd_2505_slot_0_apc_0.sv
+3 -3
View File
@@ -83,7 +83,7 @@ module bd_2505_slot_0_apc_0 (
output wire [159 : 0] pc_status;
output wire pc_asserted;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
@@ -125,8 +125,8 @@ input wire [31 : 0] pc_axi_rdata;
input wire [1 : 0] pc_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RVALID" *)
input wire pc_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 66666672, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_\
THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 1e+08, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
EADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RREADY" *)
input wire pc_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_20/bd_2505_slot_3_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_21/bd_2505_slot_3_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_22/bd_2505_slot_3_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_23/bd_2505_slot_3_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:14 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:08 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_3/bd_2505_slot_1_apc_0.xci
+4 -4
View File
@@ -152,7 +152,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -175,7 +175,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -230,10 +230,10 @@
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:PC_AXI", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
"FREQ_HZ": [ { "value": "66666672", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_HZ": [ { "value": "1e+08", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_3/bd_2505_slot_1_apc_0.xml
+13 -13
View File
@@ -394,7 +394,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.FREQ_HZ">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.FREQ_HZ">1e+08</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -601,7 +601,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.PC_AXI.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1038,7 +1038,7 @@
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>aclk frequency</spirit:displayName>
<spirit:description>aclk frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">66666672</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" spirit:minimum="1" spirit:maximum="1000000000" spirit:rangeType="long">1e+08</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
@@ -1060,7 +1060,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -1257,7 +1257,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f5d26808</spirit:value>
<spirit:value>9:f9de4659</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1276,11 +1276,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:18e76d98</spirit:value>
<spirit:value>9:7ac88fb2</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1296,11 +1296,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:18e76d98</spirit:value>
<spirit:value>9:7ac88fb2</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1319,11 +1319,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f5d26808</spirit:value>
<spirit:value>9:f9de4659</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1339,11 +1339,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:12 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f5d26808</spirit:value>
<spirit:value>9:f9de4659</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_3/sim/bd_2505_slot_1_apc_0.sv
+3 -3
View File
@@ -100,7 +100,7 @@ module bd_2505_slot_1_apc_0 (
output wire [159 : 0] pc_status;
output wire pc_asserted;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
@@ -180,8 +180,8 @@ input wire [31 : 0] pc_axi_rdata;
input wire [1 : 0] pc_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RVALID" *)
input wire pc_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_TH\
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREA\
DS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RREADY" *)
input wire pc_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_3/synth/bd_2505_slot_1_apc_0.sv
+3 -3
View File
@@ -102,7 +102,7 @@ module bd_2505_slot_1_apc_0 (
output wire [159 : 0] pc_status;
output wire pc_asserted;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXI:PC_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
@@ -182,8 +182,8 @@ input wire [31 : 0] pc_axi_rdata;
input wire [1 : 0] pc_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RVALID" *)
input wire pc_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 66666672, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, NUM_READ_TH\
READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME PC_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 1e+08, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREA\
DS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 PC_AXI RREADY" *)
input wire pc_axi_rready;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_4/bd_2505_slot_0_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_5/bd_2505_slot_0_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_6/bd_2505_slot_0_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_7/bd_2505_slot_0_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_8/bd_2505_slot_0_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/ip/ip_9/bd_2505_slot_1_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Feb 11 13:43:13 UTC 2025</spirit:value>
<spirit:value>Tue Feb 11 18:46:07 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/sim/bd_2505.vhd
+6 -6
View File
@@ -128,7 +128,7 @@ entity bd_2505 is
resetn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=24,numReposBlks=24,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=24,numReposBlks=24,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of bd_2505 : entity is "axi_crc_dma_syn_1_system_ila_0_0.hwdef";
end bd_2505;
@@ -1003,11 +1003,11 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_3_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI WVALID";
attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXI:SLOT_2_AXI:SLOT_3_AXI, ASSOCIATED_RESET resetn, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXI:SLOT_2_AXI:SLOT_3_AXI, ASSOCIATED_RESET resetn, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of SLOT_0_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 8, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 8, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
@@ -1017,7 +1017,7 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_0_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
attribute X_INTERFACE_INFO of SLOT_0_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
attribute X_INTERFACE_INFO of SLOT_1_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_1_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_1_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_1_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_1_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_1_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARBURST";
attribute X_INTERFACE_INFO of SLOT_1_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARCACHE";
attribute X_INTERFACE_INFO of SLOT_1_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARID";
@@ -1044,7 +1044,7 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_1_AXI_wid : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI WID";
attribute X_INTERFACE_INFO of SLOT_1_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI WSTRB";
attribute X_INTERFACE_INFO of SLOT_2_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_2_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_2_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_2_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_2_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_2_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARBURST";
attribute X_INTERFACE_INFO of SLOT_2_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARCACHE";
attribute X_INTERFACE_INFO of SLOT_2_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARID";
@@ -1067,7 +1067,7 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_2_AXI_wid : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WID";
attribute X_INTERFACE_INFO of SLOT_2_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WSTRB";
attribute X_INTERFACE_INFO of SLOT_3_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_3_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_3_AXI, ADDR_WIDTH 16, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_3_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_3_AXI, ADDR_WIDTH 16, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_3_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI ARPROT";
attribute X_INTERFACE_INFO of SLOT_3_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI AWADDR";
attribute X_INTERFACE_INFO of SLOT_3_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI AWPROT";
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/bd_0/synth/bd_2505.vhd
+6 -6
View File
@@ -128,7 +128,7 @@ entity bd_2505 is
resetn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=24,numReposBlks=24,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
attribute CORE_GENERATION_INFO of bd_2505 : entity is "bd_2505,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_2505,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=24,numReposBlks=24,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of bd_2505 : entity is "axi_crc_dma_syn_1_system_ila_0_0.hwdef";
end bd_2505;
@@ -1003,11 +1003,11 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_3_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI WVALID";
attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXI:SLOT_2_AXI:SLOT_3_AXI, ASSOCIATED_RESET resetn, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, FREQ_HZ 66666672, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXI:SLOT_2_AXI:SLOT_3_AXI, ASSOCIATED_RESET resetn, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of SLOT_0_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 8, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 8, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
@@ -1017,7 +1017,7 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_0_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
attribute X_INTERFACE_INFO of SLOT_0_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
attribute X_INTERFACE_INFO of SLOT_1_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_1_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_1_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_1_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_1_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_1_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARBURST";
attribute X_INTERFACE_INFO of SLOT_1_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARCACHE";
attribute X_INTERFACE_INFO of SLOT_1_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI ARID";
@@ -1044,7 +1044,7 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_1_AXI_wid : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI WID";
attribute X_INTERFACE_INFO of SLOT_1_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_1_AXI WSTRB";
attribute X_INTERFACE_INFO of SLOT_2_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_2_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_2_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_2_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_2_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 1, INSERT_VIP 0, MAX_BURST_LENGTH 16, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI3, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_2_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARBURST";
attribute X_INTERFACE_INFO of SLOT_2_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARCACHE";
attribute X_INTERFACE_INFO of SLOT_2_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI ARID";
@@ -1067,7 +1067,7 @@ architecture STRUCTURE of bd_2505 is
attribute X_INTERFACE_INFO of SLOT_2_AXI_wid : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WID";
attribute X_INTERFACE_INFO of SLOT_2_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_2_AXI WSTRB";
attribute X_INTERFACE_INFO of SLOT_3_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of SLOT_3_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_3_AXI, ADDR_WIDTH 16, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK3, DATA_WIDTH 32, FREQ_HZ 66666672, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_PARAMETER of SLOT_3_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_3_AXI, ADDR_WIDTH 16, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, DATA_WIDTH 32, FREQ_HZ 1e+08, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of SLOT_3_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI ARPROT";
attribute X_INTERFACE_INFO of SLOT_3_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI AWADDR";
attribute X_INTERFACE_INFO of SLOT_3_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_3_AXI AWPROT";

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