ram + axi_master angefanen
This commit is contained in:
Matthias Biermann
@@ -1,3 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c4755494d6f6465:2
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6d6f64655f636f756e7465727c4755494d6f6465:3
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eof:
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@@ -112,6 +112,13 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../crc_axi_ram.vhd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="axi_crc"/>
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@@ -174,20 +181,16 @@
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<Runs Version="1" Minor="20">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
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<Step Id="synth_design"/>
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@@ -0,0 +1,154 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity crc_axi_master is
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generic (
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DWIDTH : positive := 32;
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IDWIDTH : positive := 1;
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MAX_BURSTLEN : positive := 16;
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BRAM_AWIDTH : positive := 4
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- Control signals
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start : in std_logic;
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write : in std_logic;
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addr_axi : in std_logic_vector(DWIDTH-1 downto 0);
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size : in std_logic_vector(15 downto 0);
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ip_idle : out std_logic;
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-- Interface to BRAM
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waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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wdata : out std_logic_vector(DWIDTH-1 downto 0);
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we : out std_logic;
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raddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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rdata : in std_logic_vector(DWIDTH-1 downto 0);
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re : out std_logic;
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-- AXI Master Interface (Memory)
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M_AXI_ARREADY : in std_logic;
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M_AXI_ARVALID : out std_logic;
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M_AXI_ARADDR : out std_logic_vector(31 downto 0);
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M_AXI_ARID : out std_logic_vector(IDWIDTH-1 downto 0);
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M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
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M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
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M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
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M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
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M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
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M_AXI_RREADY : out std_logic;
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M_AXI_RVALID : in std_logic;
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M_AXI_RDATA : in std_logic_vector(DWIDTH-1 downto 0);
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M_AXI_RRESP : in std_logic_vector( 1 downto 0);
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M_AXI_RID : in std_logic_vector(IDWIDTH-1 downto 0);
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M_AXI_RLAST : in std_logic;
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M_AXI_AWREADY : in std_logic := '0';
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M_AXI_AWVALID : out std_logic;
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M_AXI_AWADDR : out std_logic_vector(31 downto 0);
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M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
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M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
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M_AXI_AWID : out std_logic_vector(IDWIDTH-1 downto 0);
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M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
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M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
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M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
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M_AXI_WREADY : in std_logic := '0';
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M_AXI_WVALID : out std_logic;
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M_AXI_WDATA : out std_logic_vector(DWIDTH-1 downto 0);
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M_AXI_WSTRB : out std_logic_vector(DWIDTH/8-1 downto 0);
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M_AXI_WLAST : out std_logic;
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M_AXI_WID : out std_logic_vector(DWIDTH-1 downto 0);
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M_AXI_BREADY : out std_logic;
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M_AXI_BVALID : in std_logic := '0';
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M_AXI_BID : in std_logic_vector( DWIDTH-1 downto 0);
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M_AXI_BRESP : in std_logic_vector( 1 downto 0)
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);
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end entity;
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architecture rtl of crc_axi_master is
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-- for read requests
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type read_fsm_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT);
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signal state_read : read_fsm_state_t := IDLE;
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-- for write requests
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type write_fsm_state_t is (IDLE, REQ, R_WAIT_REQ_ACCEPT);
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signal state_write : write_fsm_state_t := IDLE;
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signal Wait_for_End_of_Burst : std_logic;
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signal fsm_active : std_logic := '0';
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begin
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--------------------------------
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-- AXI Read Request Engine
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--------------------------------
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-- static outputs
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M_AXI_ARSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
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M_AXI_ARBURST <= "01";
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M_AXI_ARPROT <= "000";
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M_AXI_ARCACHE <= "1111";
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M_AXI_ARID <= (others=>'0');
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M_AXI_RREADY <= '1';
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process
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begin
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wait until rising_edge(CLK);
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if RESETN = '1' then
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M_AXI_ARVALID <= '0';
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M_AXI_ARADDR <= (others=>'0');
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M_AXI_ARLEN <= (others=>'0');
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state_read <= IDLE;
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else
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case state_read is
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when IDLE =>
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ip_idle <= '1';
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if fsm_active = '0' and start = '1' and write = '0' then
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end if;
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when others => null;
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end case;
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end if;
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end process;
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--------------------------------
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-- AXI Write Request Engine
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--------------------------------
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-- static outputs
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||||
M_AXI_AWSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
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M_AXI_AWBURST <= "01";
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M_AXI_AWPROT <= "000";
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M_AXI_AWCACHE <= "1111";
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M_AXI_BREADY <= '1';
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M_AXI_WSTRB <= (others=>'1');
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M_AXI_AWID <= (others=>'0');
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M_AXI_WID <= (others=>'0');
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process
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begin
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wait until rising_edge(CLK);
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if RESETN = '1' then
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M_AXI_WVALID <= '0';
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M_AXI_AWVALID <= '0';
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M_AXI_AWADDR <= (others=>'0');
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M_AXI_AWLEN <= (others=>'0');
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M_AXI_WLAST <= '0';
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state_write <= IDLE;
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else
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case state_write is
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when IDLE =>
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ip_idle <= '1';
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if fsm_active = '0' and start = '1' and write = '1' then
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end if;
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when others => null;
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end case;
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end if;
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end process;
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||||
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end architecture;
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||||
@@ -0,0 +1,89 @@
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# Created by https://www.toptal.com/developers/gitignore/api/vivado
|
||||
# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
|
||||
|
||||
### Vivado ###
|
||||
#########################################################################################################
|
||||
## This is an example .gitignore file for Vivado, please treat it as an example as
|
||||
## it might not be complete. In addition, XAPP 1165 should be followed.
|
||||
#########
|
||||
#Exclude all
|
||||
*
|
||||
!*/
|
||||
!.gitignore
|
||||
###########################################################################
|
||||
## VIVADO
|
||||
#Source files:
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||||
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
|
||||
!*.vhd
|
||||
!*.v
|
||||
!*.sv
|
||||
!*.bd
|
||||
!*.edif
|
||||
#IP files
|
||||
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
|
||||
#.xci + .dcp: implementation possible but not re-synthesis
|
||||
#*.xci(www.spiritconsortium.org)
|
||||
!*.xci
|
||||
#.xcix: Core container file
|
||||
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
|
||||
!*.xcix
|
||||
#*.dcp(checkpoint files)
|
||||
!*.dcp
|
||||
!*.vds
|
||||
!*.pb
|
||||
#All bd comments and layout coordinates are stored within .ui
|
||||
!*.ui
|
||||
!*.ooc
|
||||
#System Generator
|
||||
!*.mdl
|
||||
!*.slx
|
||||
!*.bxml
|
||||
#Simulation logic analyzer
|
||||
!*.wcfg
|
||||
!*.coe
|
||||
#MIG
|
||||
!*.prj
|
||||
!*.mem
|
||||
#Project files
|
||||
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
|
||||
#Do NOT ignore *.xpr files
|
||||
!*.xpr
|
||||
#Include *.xml files for 2013.4 or earlier version
|
||||
!*.xml
|
||||
#Constraint files
|
||||
#Do NOT ignore *.xdc files
|
||||
!*.xdc
|
||||
#TCL - files
|
||||
!*.tcl
|
||||
#Journal - files
|
||||
!*.jou
|
||||
#Reports
|
||||
!*.rpt
|
||||
!*.txt
|
||||
!*.vdi
|
||||
#C-files
|
||||
!*.c
|
||||
!*.h
|
||||
!*.elf
|
||||
!*.bmm
|
||||
!*.xmp
|
||||
|
||||
# End of https://www.toptal.com/developers/gitignore/api/vivado
|
||||
|
||||
# Vidado project directories which are not needed
|
||||
.Xil/
|
||||
*.cache/
|
||||
*.hw/
|
||||
*.ip_user_files/
|
||||
*.runs/
|
||||
*.sim/
|
||||
# design checkpoint file
|
||||
*.dcp
|
||||
|
||||
# ignore Vivado log files
|
||||
*.log
|
||||
*.jou
|
||||
vivado_pid*.str
|
||||
|
||||
# DO NOT ignore images as bitmap files
|
||||
!*.bmp
|
||||
@@ -0,0 +1,8 @@
|
||||
0000000000000000000000000000000000000001
|
||||
0000000100000000000000000000111100001111
|
||||
0000000000000000000000000000010000000001
|
||||
0001000000000000000000000000000000001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000100000000000000001000111100001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000000000000000
|
||||
+56
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="crc_axi_master_sim" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738100221"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738100221"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738100221"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738100221"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\crc_axi_master_sim.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_sim.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_sim_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\crc_axi_master_sim.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_sim.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\crc_axi_master_sim.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_sim.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 22:37:01 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim_wrapper.bd
|
||||
--Design : crc_axi_master_sim_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim_wrapper is
|
||||
end crc_axi_master_sim_wrapper;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim_wrapper is
|
||||
component crc_axi_master_sim is
|
||||
end component crc_axi_master_sim;
|
||||
begin
|
||||
crc_axi_master_sim_i: component crc_axi_master_sim
|
||||
;
|
||||
end STRUCTURE;
|
||||
+4467
File diff suppressed because it is too large
Load Diff
+425
@@ -0,0 +1,425 @@
|
||||
#ifndef IP_CRC_AXI_MASTER_SIM_AXI_VIP_0_0_H_
|
||||
#define IP_CRC_AXI_MASTER_SIM_AXI_VIP_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "crc_axi_master_sim_axi_vip_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport crc_axi_master_sim_axi_vip_0_0 : public crc_axi_master_sim_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_sim_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport crc_axi_master_sim_axi_vip_0_0 : public crc_axi_master_sim_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_sim_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport crc_axi_master_sim_axi_vip_0_0 : public crc_axi_master_sim_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_sim_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport crc_axi_master_sim_axi_vip_0_0 : public crc_axi_master_sim_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_sim_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport crc_axi_master_sim_axi_vip_0_0 : public crc_axi_master_sim_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_sim_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_CRC_AXI_MASTER_SIM_AXI_VIP_0_0_H_
|
||||
+291
@@ -0,0 +1,291 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_vip:1.1
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module crc_axi_master_sim_axi_vip_0_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [0 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [0 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS\
|
||||
_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
axi_vip_v1_1_14_top #(
|
||||
.C_AXI_PROTOCOL(1),
|
||||
.C_AXI_INTERFACE_MODE(2),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WID_WIDTH(1),
|
||||
.C_AXI_RID_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(0),
|
||||
.C_AXI_ARUSER_WIDTH(0),
|
||||
.C_AXI_WUSER_WIDTH(0),
|
||||
.C_AXI_RUSER_WIDTH(0),
|
||||
.C_AXI_BUSER_WIDTH(0),
|
||||
.C_AXI_SUPPORTS_NARROW(1),
|
||||
.C_AXI_HAS_BURST(1),
|
||||
.C_AXI_HAS_LOCK(0),
|
||||
.C_AXI_HAS_CACHE(1),
|
||||
.C_AXI_HAS_REGION(0),
|
||||
.C_AXI_HAS_PROT(1),
|
||||
.C_AXI_HAS_QOS(0),
|
||||
.C_AXI_HAS_WSTRB(1),
|
||||
.C_AXI_HAS_BRESP(1),
|
||||
.C_AXI_HAS_RRESP(1),
|
||||
.C_AXI_HAS_ARESETN(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'B1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(2'B0),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(2'B0),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'B0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'B0),
|
||||
.m_axi_bid(1'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'B0),
|
||||
.m_axi_bready(),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'B0),
|
||||
.m_axi_rid(1'B0),
|
||||
.m_axi_rdata(32'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'B0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'B0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+93
@@ -0,0 +1,93 @@
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
//NOTE: This file has been automatically generated by Vivado.
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ps/1ps
|
||||
package crc_axi_master_sim_axi_vip_0_0_pkg;
|
||||
import axi_vip_pkg::*;
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// These parameters are named after the component for use in your verification
|
||||
// environment.
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_PROTOCOL = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_READ_WRITE_MODE = "READ_WRITE";
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_INTERFACE_MODE = 2;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_ADDR_WIDTH = 32;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_DATA_WIDTH = 32;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_ID_WIDTH = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_AWUSER_WIDTH = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_ARUSER_WIDTH = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_RUSER_WIDTH = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_WUSER_WIDTH = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_BUSER_WIDTH = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_SUPPORTS_NARROW = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_BURST = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_LOCK = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_CACHE = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_REGION = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_QOS = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_PROT = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_WSTRB = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_BRESP = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_RRESP = 1;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_ACLKEN = 0;
|
||||
parameter crc_axi_master_sim_axi_vip_0_0_VIP_HAS_ARESETN = 1;
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
typedef axi_slv_agent #(crc_axi_master_sim_axi_vip_0_0_VIP_PROTOCOL,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ADDR_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_AWUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_WUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_BUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ARUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_RUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_SUPPORTS_NARROW,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_BURST,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_LOCK,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_CACHE,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_REGION,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_PROT,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_QOS,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_WSTRB,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_BRESP,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_RRESP,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_ARESETN) crc_axi_master_sim_axi_vip_0_0_slv_t;
|
||||
|
||||
typedef axi_slv_mem_agent #(crc_axi_master_sim_axi_vip_0_0_VIP_PROTOCOL,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ADDR_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_AWUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_WUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_BUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_ARUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_RUSER_WIDTH,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_SUPPORTS_NARROW,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_BURST,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_LOCK,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_CACHE,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_REGION,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_PROT,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_QOS,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_WSTRB,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_BRESP,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_RRESP,
|
||||
crc_axi_master_sim_axi_vip_0_0_VIP_HAS_ARESETN) crc_axi_master_sim_axi_vip_0_0_slv_mem_t;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// How to start the verification component
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// crc_axi_master_sim_axi_vip_0_0_slv_t crc_axi_master_sim_axi_vip_0_0_slv;
|
||||
// initial begin : START_crc_axi_master_sim_axi_vip_0_0_SLAVE
|
||||
// crc_axi_master_sim_axi_vip_0_0_slv = new("crc_axi_master_sim_axi_vip_0_0_slv", `crc_axi_master_sim_axi_vip_0_0_PATH_TO_INTERFACE);
|
||||
// crc_axi_master_sim_axi_vip_0_0_slv.start_slave();
|
||||
// end
|
||||
|
||||
endpackage : crc_axi_master_sim_axi_vip_0_0_pkg
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
#ifndef IP_CRC_AXI_MASTER_SIM_AXI_VIP_0_0_SC_H_
|
||||
#define IP_CRC_AXI_MASTER_SIM_AXI_VIP_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_vip;
|
||||
|
||||
class DllExport crc_axi_master_sim_axi_vip_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~crc_axi_master_sim_axi_vip_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_vip* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
crc_axi_master_sim_axi_vip_0_0_sc(const crc_axi_master_sim_axi_vip_0_0_sc&);
|
||||
const crc_axi_master_sim_axi_vip_0_0_sc& operator=(const crc_axi_master_sim_axi_vip_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_CRC_AXI_MASTER_SIM_AXI_VIP_0_0_SC_H_
|
||||
+151
@@ -0,0 +1,151 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: crc_axi_master_sim_axi_vip_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module crc_axi_master_sim_axi_vip_0_0 (
|
||||
input bit_as_bool aclk,
|
||||
input bit_as_bool aresetn,
|
||||
input bit [0 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [0 : 0] s_axi_wid,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [0 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [0 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [0 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module crc_axi_master_sim_axi_vip_0_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awcache,s_axi_awprot,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arcache,s_axi_arprot,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit aclk;
|
||||
input bit aresetn;
|
||||
input bit [0 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [0 : 0] s_axi_wid;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [0 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <xtlm.h>
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
#include <utils/xtlm_aximm_passthru_module.h>
|
||||
#include <systemc>
|
||||
#include "sim_ipc_aximm_master.h"
|
||||
#include "sim_ipc_aximm_slave.h"
|
||||
|
||||
class axi_vip: public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
axi_vip(sc_core::sc_module_name module_name,
|
||||
xsc::common_cpp::properties model_param_props);
|
||||
virtual ~axi_vip();
|
||||
SC_HAS_PROCESS (axi_vip);
|
||||
xtlm::xtlm_aximm_target_socket *S_TARGET_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket *S_TARGET_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_wr_socket;
|
||||
std::vector<xtlm::xtlm_aximm_target_stub*> stubTargetSkt;
|
||||
std::vector<xtlm::xtlm_aximm_initiator_stub*> stubInitSkt;
|
||||
sc_core::sc_in<bool> aclk;
|
||||
sc_core::sc_in<bool> aresetn;
|
||||
private:
|
||||
xtlm::xtlm_aximm_passthru_module *P1;
|
||||
xtlm::xtlm_aximm_passthru_module *P2;
|
||||
sim_ipc_aximm_master* m_ipc_master;
|
||||
sim_ipc_aximm_slave* m_ipc_slave;
|
||||
|
||||
};
|
||||
|
||||
+82
@@ -0,0 +1,82 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "ipc2aximm_socket.h"
|
||||
#include <systemc>
|
||||
|
||||
class sim_ipc_aximm_master : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
SC_HAS_PROCESS(sim_ipc_aximm_master);
|
||||
|
||||
sim_ipc_aximm_master(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties &ppts);
|
||||
|
||||
~sim_ipc_aximm_master();
|
||||
|
||||
sc_core::sc_in<bool> m_aximm_aresetn;
|
||||
sc_core::sc_in<bool> m_aximm_aclk;
|
||||
|
||||
//Read & Write Sockets
|
||||
xtlm::xtlm_aximm_initiator_socket* rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* wr_socket;
|
||||
|
||||
xtlm::xtlm_aximm_initiator_rd_socket_util rd_util;
|
||||
xtlm::xtlm_aximm_initiator_wr_socket_util wr_util;
|
||||
private:
|
||||
//! SystemC Method to Read incoming data from ipc...
|
||||
void ipc2aximm_receive();
|
||||
void send_response();
|
||||
std::string get_ipi_name(std::string s);
|
||||
|
||||
xsc::ipc2aximm_socket* m_ipc2aximm_socket;
|
||||
xsc::common_cpp::report_handler m_logger;
|
||||
};
|
||||
+82
@@ -0,0 +1,82 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "aximm2ipc_socket.h"
|
||||
|
||||
class sim_ipc_aximm_slave : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
SC_HAS_PROCESS(sim_ipc_aximm_slave);
|
||||
sim_ipc_aximm_slave(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties& ppts);
|
||||
~sim_ipc_aximm_slave();
|
||||
|
||||
sc_core::sc_in<bool> s_aximm_aclk;
|
||||
sc_core::sc_in<bool> s_aximm_aresetn;
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* wr_socket;
|
||||
|
||||
xtlm::xtlm_aximm_target_rd_socket_util rd_util;
|
||||
xtlm::xtlm_aximm_target_wr_socket_util wr_util;
|
||||
|
||||
private:
|
||||
//! SystemC method to send the AXIMM data to external process
|
||||
void aximm2ipc_send();
|
||||
|
||||
//! SystemC Method to handle AXIMM Response
|
||||
void aximm_resp_handler();
|
||||
|
||||
std::string get_ipi_name(std::string s);
|
||||
|
||||
xsc::aximm2ipc_socket* m_aximm2ipc_socket;
|
||||
xsc::common_cpp::report_handler m_logger;
|
||||
};
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>crc_axi_master_sim_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Jan 28 21:08:28 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:098d4af8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Jan 28 21:08:28 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:098d4af8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_sim_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">crc_axi_master_sim_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_sim_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_sim_clk_rst_generator_0_0_arch OF crc_axi_master_sim_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_sim_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 10000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END crc_axi_master_sim_clk_rst_generator_0_0_arch;
|
||||
+1554
File diff suppressed because it is too large
Load Diff
+267
@@ -0,0 +1,267 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_master:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_sim_crc_axi_master_0_2 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
start : IN STD_LOGIC;
|
||||
write : IN STD_LOGIC;
|
||||
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
ip_idle : OUT STD_LOGIC;
|
||||
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : OUT STD_LOGIC;
|
||||
raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END crc_axi_master_sim_crc_axi_master_0_2;
|
||||
|
||||
ARCHITECTURE crc_axi_master_sim_crc_axi_master_0_2_arch OF crc_axi_master_sim_crc_axi_master_0_2 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_sim_crc_axi_master_0_2_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
BRAM_AWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
start : IN STD_LOGIC;
|
||||
write : IN STD_LOGIC;
|
||||
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
ip_idle : OUT STD_LOGIC;
|
||||
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : OUT STD_LOGIC;
|
||||
raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT crc_axi_master;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS" &
|
||||
"_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
BEGIN
|
||||
U0 : crc_axi_master
|
||||
GENERIC MAP (
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
BRAM_AWIDTH => 4
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
start => start,
|
||||
write => write,
|
||||
addr_axi => addr_axi,
|
||||
size => size,
|
||||
ip_idle => ip_idle,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
raddr => raddr,
|
||||
rdata => rdata,
|
||||
re => re,
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END crc_axi_master_sim_crc_axi_master_0_2_arch;
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>crc_axi_master_sim_crc_axi_master_sim_c_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master_sim_control</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c50bf4c4</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_crc_axi_master_sim_c_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Jan 28 21:08:28 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c50bf4c4</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>start</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>write</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>addr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>size</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>axi_idle</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_sim_crc_axi_master_sim_c_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master_sim_control:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">crc_axi_master_sim_crc_axi_master_sim_c_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>crc_axi_master_sim_control_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_master_sim_control:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_sim_crc_axi_master_sim_c_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
start : OUT STD_LOGIC;
|
||||
write : OUT STD_LOGIC;
|
||||
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
axi_idle : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_sim_crc_axi_master_sim_c_0_0_arch OF crc_axi_master_sim_crc_axi_master_sim_c_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_sim_crc_axi_master_sim_c_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master_sim_control IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
start : OUT STD_LOGIC;
|
||||
write : OUT STD_LOGIC;
|
||||
addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
axi_idle : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT crc_axi_master_sim_control;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST";
|
||||
BEGIN
|
||||
U0 : crc_axi_master_sim_control
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => resetn,
|
||||
start => start,
|
||||
write => write,
|
||||
addr => addr,
|
||||
size => size,
|
||||
axi_idle => axi_idle
|
||||
);
|
||||
END crc_axi_master_sim_crc_axi_master_sim_c_0_0_arch;
|
||||
+295
@@ -0,0 +1,295 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>crc_axi_master_sim_crc_axi_ram_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_ram</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a61066fb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_crc_axi_ram_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Jan 28 21:08:28 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a61066fb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>waddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AW')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>wdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>we</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>raddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AW')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>re</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>AW</spirit:name>
|
||||
<spirit:displayName>Aw</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AW" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_sim_crc_axi_ram_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_ram:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>AW</spirit:name>
|
||||
<spirit:displayName>Aw</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AW" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">crc_axi_master_sim_crc_axi_ram_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>crc_axi_ram_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_ram:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_sim_crc_axi_ram_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
raddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : IN STD_LOGIC
|
||||
);
|
||||
END crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_sim_crc_axi_ram_0_0_arch OF crc_axi_master_sim_crc_axi_ram_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_sim_crc_axi_ram_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_ram IS
|
||||
GENERIC (
|
||||
AW : INTEGER;
|
||||
DATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
waddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : IN STD_LOGIC;
|
||||
raddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT crc_axi_ram;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
BEGIN
|
||||
U0 : crc_axi_ram
|
||||
GENERIC MAP (
|
||||
AW => 4,
|
||||
DATA_WIDTH => 32
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
raddr => raddr,
|
||||
rdata => rdata,
|
||||
re => re
|
||||
);
|
||||
END crc_axi_master_sim_crc_axi_ram_0_0_arch;
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- clk_rst_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_rst_generator is
|
||||
generic
|
||||
(
|
||||
CLOCK_PERIOD : integer := 10000;
|
||||
HAS_CLK_INPUT : boolean := true;
|
||||
HAS_RESET_INPUT : boolean := true;
|
||||
HAS_STOP_INPUT : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
clk_in : in std_logic := '1';
|
||||
rst_in : in std_logic := '0';
|
||||
|
||||
clk : out std_logic;
|
||||
rst_n : out std_logic;
|
||||
|
||||
stop_simulation : in std_logic := '0'
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of clk_rst_generator is
|
||||
|
||||
signal clk_sim : std_logic := '1';
|
||||
signal clk_in_sig : std_logic := '1';
|
||||
signal clk_sig : std_logic := '1';
|
||||
signal rst_sig : std_logic := '0';
|
||||
signal rst_in_sync : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk <= clk_sig;
|
||||
rst_n <= not rst_sig;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
clk_sig <= clk_in_sig and clk_sim;
|
||||
-- Dies ist kein gated Clock!
|
||||
-- Fuer die Synthese ist clk_sim konstant '1'
|
||||
-- somit wird die UND-Verknuepfung 'wegoptimiert'
|
||||
-- und was übrig bleibt, ist ein 'Draht'
|
||||
|
||||
-- synthesis translate_off
|
||||
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
-- synthesis translate_on
|
||||
|
||||
process (clk_in) begin
|
||||
clk_in_sig <= clk_in;
|
||||
-- synthesis translate_off
|
||||
clk_in_sig <= '1';
|
||||
-- synthesis translate_on
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- RESET GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
process
|
||||
variable rescnt : unsigned (6 downto 0) := (others=>'1');
|
||||
begin
|
||||
wait until rising_edge(clk_sig);
|
||||
|
||||
rst_in_sync <= rst_in;
|
||||
if rst_in_sync = '1' then
|
||||
rescnt := (others=>'1');
|
||||
end if;
|
||||
|
||||
if rescnt = 0 then
|
||||
rst_sig <= '0';
|
||||
else
|
||||
rescnt := rescnt - 1;
|
||||
rst_sig <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- STOP SIMULATION INPUT (simulation only)
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- synthesis translate_off
|
||||
process (stop_simulation) begin
|
||||
if stop_simulation = '1' then
|
||||
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
|
||||
end if;
|
||||
end process;
|
||||
-- synthesis translate_on
|
||||
|
||||
end rtl;
|
||||
+670
@@ -0,0 +1,670 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axis to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axi2vector #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
|
||||
// payloads
|
||||
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
|
||||
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
|
||||
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
|
||||
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
|
||||
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
|
||||
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
|
||||
|
||||
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
|
||||
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
|
||||
|
||||
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
|
||||
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
|
||||
|
||||
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
|
||||
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
|
||||
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
|
||||
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
|
||||
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
|
||||
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
|
||||
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
|
||||
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
|
||||
|
||||
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
end
|
||||
|
||||
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
|
||||
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
|
||||
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
|
||||
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
|
||||
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
|
||||
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
|
||||
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
|
||||
|
||||
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
|
||||
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
|
||||
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
|
||||
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
|
||||
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
|
||||
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
|
||||
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign s_axi_buser = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign s_axi_bid = 'b0;
|
||||
assign s_axi_buser = 'b0;
|
||||
|
||||
assign s_axi_rlast = 1'b1;
|
||||
assign s_axi_rid = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: SRL based FIFO for AXIS/AXI Channels.
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter C_FAMILY = "virtex7",
|
||||
parameter integer C_PAYLOAD_WIDTH = 1,
|
||||
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
input wire aclk, // Clock
|
||||
input wire aresetn, // Reset
|
||||
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
|
||||
input wire s_valid, // Input data valid
|
||||
output reg s_ready, // Input data ready
|
||||
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
|
||||
output reg m_valid, // Output data valid
|
||||
input wire m_ready // Output data ready
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
|
||||
wire [4-1:0] fifo_addr;
|
||||
wire push;
|
||||
wire pop ;
|
||||
reg areset_r1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
always @(posedge aclk) begin
|
||||
areset_r1 <= ~aresetn;
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
|
||||
end
|
||||
else begin
|
||||
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
|
||||
~push & pop ? fifo_index - 1'b1 :
|
||||
fifo_index;
|
||||
end
|
||||
end
|
||||
|
||||
assign push = s_valid & s_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
s_ready <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
s_ready <= areset_r1 ? 1'b1 :
|
||||
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
|
||||
~push & pop ? 1'b1 :
|
||||
s_ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign pop = m_valid & m_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
m_valid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
|
||||
push & ~pop ? 1'b1 :
|
||||
m_valid;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
|
||||
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
|
||||
end
|
||||
else begin : gen_fifo_addr
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
|
||||
SRL16E
|
||||
u_srl_fifo(
|
||||
.Q ( m_payload[i] ) ,
|
||||
.A0 ( fifo_addr[0] ) ,
|
||||
.A1 ( fifo_addr[1] ) ,
|
||||
.A2 ( fifo_addr[2] ) ,
|
||||
.A3 ( fifo_addr[3] ) ,
|
||||
.CE ( push ) ,
|
||||
.CLK ( aclk ) ,
|
||||
.D ( s_payload[i] )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axi to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_vector2axi #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
|
||||
// payloads
|
||||
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
|
||||
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
|
||||
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
|
||||
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
|
||||
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
|
||||
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
|
||||
|
||||
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
|
||||
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
|
||||
|
||||
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
|
||||
|
||||
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
|
||||
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
|
||||
|
||||
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
|
||||
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
|
||||
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
|
||||
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
|
||||
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
|
||||
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
|
||||
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
|
||||
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
|
||||
|
||||
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
assign m_axi_wid = 1'b0;
|
||||
end
|
||||
|
||||
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
|
||||
|
||||
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
|
||||
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
|
||||
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
|
||||
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
|
||||
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
|
||||
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
|
||||
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
|
||||
|
||||
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
|
||||
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
|
||||
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
|
||||
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
|
||||
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
|
||||
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
|
||||
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_awburst = 'b0;
|
||||
assign m_axi_awcache = 'b0;
|
||||
assign m_axi_awlen = 'b0;
|
||||
assign m_axi_awlock = 'b0;
|
||||
assign m_axi_awid = 'b0;
|
||||
assign m_axi_awqos = 'b0;
|
||||
|
||||
assign m_axi_wlast = 1'b1;
|
||||
assign m_axi_wid = 'b0;
|
||||
|
||||
|
||||
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_arburst = 'b0;
|
||||
assign m_axi_arcache = 'b0;
|
||||
assign m_axi_arlen = 'b0;
|
||||
assign m_axi_arlock = 'b0;
|
||||
assign m_axi_arid = 'b0;
|
||||
assign m_axi_arqos = 'b0;
|
||||
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
+633
@@ -0,0 +1,633 @@
|
||||
// (c) Copyright 2016 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// AXI VIP wrapper
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// axi_vip
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_vip_v1_1_14_top #
|
||||
(
|
||||
parameter C_AXI_PROTOCOL = 0,
|
||||
parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_WDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_RDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_WID_WIDTH = 0,
|
||||
parameter integer C_AXI_RID_WIDTH = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_SUPPORTS_NARROW = 1,
|
||||
parameter integer C_AXI_HAS_BURST = 1,
|
||||
parameter integer C_AXI_HAS_LOCK = 1,
|
||||
parameter integer C_AXI_HAS_CACHE = 1,
|
||||
parameter integer C_AXI_HAS_REGION = 1,
|
||||
parameter integer C_AXI_HAS_PROT = 1,
|
||||
parameter integer C_AXI_HAS_QOS = 1,
|
||||
parameter integer C_AXI_HAS_WSTRB = 1,
|
||||
parameter integer C_AXI_HAS_BRESP = 1,
|
||||
parameter integer C_AXI_HAS_RRESP = 1,
|
||||
parameter integer C_AXI_HAS_ARESETN = 1
|
||||
)
|
||||
(
|
||||
//NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
|
||||
//Please refer xgui tcl and coreinfo.yml
|
||||
|
||||
// System Signals
|
||||
input wire aclk,
|
||||
input wire aclken,
|
||||
input wire aresetn,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
input wire s_axi_awvalid,
|
||||
output wire s_axi_awready,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
input wire s_axi_wvalid,
|
||||
output wire s_axi_wready,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
output wire s_axi_bvalid,
|
||||
input wire s_axi_bready,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
input wire s_axi_arvalid,
|
||||
output wire s_axi_arready,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
output wire s_axi_rvalid,
|
||||
input wire s_axi_rready,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
);
|
||||
|
||||
/**********************************************************************************************
|
||||
* NOTE:
|
||||
* C_AXI_INTERFACE_MODE =0 -- MASTER MODE,
|
||||
* C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE
|
||||
* C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
|
||||
* Please refer xgui tcl and coreinfo.yml
|
||||
* User can change PASS_THROUGH VIP to run time master mode or run time slave mode during
|
||||
* the simulation
|
||||
*********************************************************************************************/
|
||||
|
||||
/**********************************************************************************************
|
||||
* Master_mode means that either the dut is statically being configured to be in master mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in master mode
|
||||
* in run time.
|
||||
|
||||
* Slave mode means that either the dut is statically being configured to be in slave mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in slave mode
|
||||
* in run time.
|
||||
|
||||
* Pass-through mode means that either the dut is statically being configured to be in
|
||||
* pass-through mode or it statically being configured to be pass-through mode and switched
|
||||
* to be in master/slave mode and then switch back to be in pass-through mode in run time
|
||||
*********************************************************************************************/
|
||||
|
||||
logic runtime_master =0;
|
||||
logic runtime_slave =0;
|
||||
|
||||
wire run_slave_mode;
|
||||
wire run_master_mode;
|
||||
wire run_passth_mode;
|
||||
wire compile_master_mode;
|
||||
wire compile_slave_mode;
|
||||
wire master_mode;
|
||||
wire slave_mode;
|
||||
|
||||
assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
|
||||
assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
|
||||
assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
|
||||
|
||||
assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;
|
||||
assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
|
||||
|
||||
assign master_mode = compile_master_mode || run_master_mode;
|
||||
assign slave_mode = compile_slave_mode || run_slave_mode;
|
||||
|
||||
// Slave Interface Write Address Ports Internal
|
||||
assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
|
||||
assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
|
||||
assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}};
|
||||
assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}};
|
||||
assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}};
|
||||
assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}};
|
||||
assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}};
|
||||
assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
|
||||
assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz};
|
||||
assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
|
||||
assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
|
||||
assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz};
|
||||
assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
|
||||
assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz};
|
||||
assign s_axi_wready = slave_mode? IF.WREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}};
|
||||
assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
|
||||
assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}};
|
||||
assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}};
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
|
||||
assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
|
||||
assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}};
|
||||
assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}};
|
||||
assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}};
|
||||
assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ;
|
||||
assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}};
|
||||
assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
|
||||
assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz};
|
||||
assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0};
|
||||
|
||||
//Slave Interface Read Data Ports
|
||||
assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
|
||||
assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}};
|
||||
assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}};
|
||||
assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
|
||||
assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}};
|
||||
assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}};
|
||||
|
||||
// Master Interface Write Address Port
|
||||
assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}};
|
||||
assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}};
|
||||
assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}};
|
||||
assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}};
|
||||
assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
|
||||
assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}};
|
||||
assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
|
||||
assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0};
|
||||
assign IF.AWREADY = master_mode? m_axi_awready :{1'bz};
|
||||
|
||||
// Master Interface Write Data Ports Internal
|
||||
assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
|
||||
assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
|
||||
assign m_axi_wlast = master_mode? IF.WLAST : {1'b0};
|
||||
assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
|
||||
assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0};
|
||||
assign IF.WREADY = master_mode? m_axi_wready : {1'bz};
|
||||
|
||||
// Master Interface Write Response Ports Internal
|
||||
assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}};
|
||||
assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
|
||||
assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz;
|
||||
assign m_axi_bready = master_mode? IF.BREADY : 1'b0;
|
||||
|
||||
// Master Interface Read Address Port Internal
|
||||
assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}};
|
||||
assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}};
|
||||
assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}};
|
||||
assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}};
|
||||
assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
|
||||
assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}};
|
||||
assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
|
||||
assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0};
|
||||
assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}};
|
||||
|
||||
// Master Interface Read Data Ports Internal
|
||||
assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
|
||||
assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}};
|
||||
assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}};
|
||||
assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
|
||||
assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}};
|
||||
assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}};
|
||||
|
||||
axi_vip_if #(
|
||||
.C_AXI_PROTOCOL(C_AXI_PROTOCOL),
|
||||
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
|
||||
.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
|
||||
.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
|
||||
.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
|
||||
.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ),
|
||||
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ),
|
||||
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
|
||||
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
|
||||
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
|
||||
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
|
||||
.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
|
||||
.C_AXI_HAS_BURST(C_AXI_HAS_BURST),
|
||||
.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
|
||||
.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
|
||||
.C_AXI_HAS_REGION(C_AXI_HAS_REGION),
|
||||
.C_AXI_HAS_PROT(C_AXI_HAS_PROT),
|
||||
.C_AXI_HAS_QOS(C_AXI_HAS_QOS),
|
||||
.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
|
||||
.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
|
||||
.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
|
||||
.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
|
||||
) IF (
|
||||
.ACLK(aclk),
|
||||
.ARESET_N(aresetn),
|
||||
.ACLKEN(aclken)
|
||||
);
|
||||
|
||||
|
||||
//synthesis translate_off
|
||||
initial begin
|
||||
$display("XilinxAXIVIP: Found at Path: %m");
|
||||
end
|
||||
|
||||
//set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode
|
||||
generate
|
||||
initial begin
|
||||
if(C_AXI_INTERFACE_MODE ==0) begin
|
||||
IF.set_intf_master;
|
||||
end else if(C_AXI_INTERFACE_MODE ==2) begin
|
||||
IF.set_intf_slave;
|
||||
end else if(C_AXI_INTERFACE_MODE ==1) begin
|
||||
$display("This AXI VIP is in passthrough mode");
|
||||
end else begin
|
||||
$fatal(0,"This AXI VIP's mode is out of range");
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/*
|
||||
Function: set_passthrough_mode
|
||||
Sets AXI VIP passthrough into run time passthrough mode
|
||||
*/
|
||||
function void set_passthrough_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_monitor();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction: set_passthrough_mode
|
||||
|
||||
/*
|
||||
Function: set_master_mode
|
||||
Sets AXI VIP passthrough into run time master mode
|
||||
*/
|
||||
function void set_master_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 1;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_master();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
|
||||
end
|
||||
endfunction : set_master_mode
|
||||
|
||||
/*
|
||||
Function: set_slave_mode
|
||||
Sets AXI VIP passthrough into run time slave mode
|
||||
*/
|
||||
function void set_slave_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 1;
|
||||
IF.set_intf_slave();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction : set_slave_mode
|
||||
|
||||
/*
|
||||
Function: set_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 1
|
||||
*/
|
||||
function void set_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 1;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: clr_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 0
|
||||
*/
|
||||
function void clr_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 0;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_aw_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_aw_wait_cycles = new_num;
|
||||
endfunction : set_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_ar_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_ar_wait_cycles = new_num;
|
||||
endfunction : set_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_r_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_r_wait_cycles = new_num;
|
||||
endfunction : set_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_b_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_b_wait_cycles = new_num;
|
||||
endfunction : set_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_w_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_w_wait_cycles = new_num;
|
||||
endfunction : set_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlast_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
|
||||
endfunction : set_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_rtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlcmd_wait_cycles = new_num;
|
||||
endfunction : set_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_aw_wait_cycles();
|
||||
return(IF.PC.max_aw_wait_cycles);
|
||||
endfunction : get_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_ar_wait_cycles();
|
||||
return(IF.PC.max_ar_wait_cycles);
|
||||
endfunction : get_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_r_wait_cycles();
|
||||
return(IF.PC.max_r_wait_cycles);
|
||||
endfunction : get_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_b_wait_cycles();
|
||||
return(IF.PC.max_b_wait_cycles);
|
||||
endfunction : get_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_w_wait_cycles();
|
||||
return(IF.PC.max_w_wait_cycles);
|
||||
endfunction :get_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlast_wait_cycles();
|
||||
return(IF.PC.max_wlast_to_awvalid_wait_cycles);
|
||||
endfunction :get_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_rtransfers_wait_cycles();
|
||||
return(IF.PC.max_rtransfers_wait_cycles);
|
||||
endfunction :get_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wtransfers_wait_cycles();
|
||||
return(IF.PC.max_wtransfers_wait_cycles);
|
||||
endfunction :get_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlcmd_wait_cycles();
|
||||
return(IF.PC.max_wlcmd_wait_cycles);
|
||||
endfunction :get_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
|
||||
*/
|
||||
function void set_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 1;
|
||||
endfunction : set_fatal_to_warnings
|
||||
|
||||
/*
|
||||
Function: clr_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
|
||||
*/
|
||||
function void clr_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 0;
|
||||
endfunction : clr_fatal_to_warnings
|
||||
//synthesis translate_on
|
||||
|
||||
endmodule // axi_vip_v1_1_14_top
|
||||
|
||||
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 22:37:01 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim.bd
|
||||
--Design : crc_axi_master_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
|
||||
end crc_axi_master_sim;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim is
|
||||
component crc_axi_master_sim_axi_vip_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_axi_vip_0_0;
|
||||
component crc_axi_master_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
component crc_axi_master_sim_crc_axi_ram_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : in STD_LOGIC;
|
||||
raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
start : out STD_LOGIC;
|
||||
write : out STD_LOGIC;
|
||||
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
axi_idle : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_0_2 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
start : in STD_LOGIC;
|
||||
write : in STD_LOGIC;
|
||||
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
ip_idle : out STD_LOGIC;
|
||||
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : out STD_LOGIC;
|
||||
raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_0_2;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_idle : STD_LOGIC;
|
||||
signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_re : STD_LOGIC;
|
||||
signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_we : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
|
||||
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
begin
|
||||
axi_vip_0: component crc_axi_master_sim_axi_vip_0_0
|
||||
port map (
|
||||
aclk => clk_rst_generator_0_clk,
|
||||
aresetn => clk_rst_generator_0_rst_n,
|
||||
s_axi_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
s_axi_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
s_axi_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
|
||||
s_axi_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
s_axi_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
s_axi_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
|
||||
s_axi_arready => crc_axi_master_0_M_AXI_ARREADY,
|
||||
s_axi_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
s_axi_arvalid => crc_axi_master_0_M_AXI_ARVALID,
|
||||
s_axi_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
s_axi_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
s_axi_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
|
||||
s_axi_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
|
||||
s_axi_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
s_axi_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
|
||||
s_axi_awready => crc_axi_master_0_M_AXI_AWREADY,
|
||||
s_axi_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
s_axi_awvalid => crc_axi_master_0_M_AXI_AWVALID,
|
||||
s_axi_bid(0) => crc_axi_master_0_M_AXI_BID(0),
|
||||
s_axi_bready => crc_axi_master_0_M_AXI_BREADY,
|
||||
s_axi_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
s_axi_bvalid => crc_axi_master_0_M_AXI_BVALID,
|
||||
s_axi_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
s_axi_rid(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
s_axi_rlast => crc_axi_master_0_M_AXI_RLAST,
|
||||
s_axi_rready => crc_axi_master_0_M_AXI_RREADY,
|
||||
s_axi_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
s_axi_rvalid => crc_axi_master_0_M_AXI_RVALID,
|
||||
s_axi_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
s_axi_wid(0) => crc_axi_master_0_M_AXI_WID(0),
|
||||
s_axi_wlast => crc_axi_master_0_M_AXI_WLAST,
|
||||
s_axi_wready => crc_axi_master_0_M_AXI_WREADY,
|
||||
s_axi_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
s_axi_wvalid => crc_axi_master_0_M_AXI_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
|
||||
M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
|
||||
M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
|
||||
M_AXI_AWID(0) => crc_axi_master_0_M_AXI_AWID(0),
|
||||
M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
|
||||
M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(31 downto 1) => B"0000000000000000000000000000000",
|
||||
M_AXI_BID(0) => crc_axi_master_0_M_AXI_BID(0),
|
||||
M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
|
||||
M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
ip_idle => crc_axi_master_0_idle,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
|
||||
port map (
|
||||
addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
axi_idle => crc_axi_master_0_idle,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n,
|
||||
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we
|
||||
);
|
||||
end STRUCTURE;
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 22:37:01 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim.bd
|
||||
--Design : crc_axi_master_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
|
||||
end crc_axi_master_sim;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim is
|
||||
component crc_axi_master_sim_axi_vip_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_axi_vip_0_0;
|
||||
component crc_axi_master_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
component crc_axi_master_sim_crc_axi_ram_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : in STD_LOGIC;
|
||||
raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
start : out STD_LOGIC;
|
||||
write : out STD_LOGIC;
|
||||
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
axi_idle : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_0_2 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
start : in STD_LOGIC;
|
||||
write : in STD_LOGIC;
|
||||
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
ip_idle : out STD_LOGIC;
|
||||
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : out STD_LOGIC;
|
||||
raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_0_2;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WID : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_idle : STD_LOGIC;
|
||||
signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_re : STD_LOGIC;
|
||||
signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_we : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
|
||||
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
begin
|
||||
axi_vip_0: component crc_axi_master_sim_axi_vip_0_0
|
||||
port map (
|
||||
aclk => clk_rst_generator_0_clk,
|
||||
aresetn => clk_rst_generator_0_rst_n,
|
||||
s_axi_araddr(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
s_axi_arburst(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
s_axi_arcache(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
|
||||
s_axi_arid(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
s_axi_arlen(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
s_axi_arprot(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
|
||||
s_axi_arready => crc_axi_master_0_M_AXI_ARREADY,
|
||||
s_axi_arsize(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
s_axi_arvalid => crc_axi_master_0_M_AXI_ARVALID,
|
||||
s_axi_awaddr(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
s_axi_awburst(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
s_axi_awcache(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
|
||||
s_axi_awid(0) => crc_axi_master_0_M_AXI_AWID(0),
|
||||
s_axi_awlen(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
s_axi_awprot(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
|
||||
s_axi_awready => crc_axi_master_0_M_AXI_AWREADY,
|
||||
s_axi_awsize(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
s_axi_awvalid => crc_axi_master_0_M_AXI_AWVALID,
|
||||
s_axi_bid(0) => crc_axi_master_0_M_AXI_BID(0),
|
||||
s_axi_bready => crc_axi_master_0_M_AXI_BREADY,
|
||||
s_axi_bresp(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
s_axi_bvalid => crc_axi_master_0_M_AXI_BVALID,
|
||||
s_axi_rdata(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
s_axi_rid(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
s_axi_rlast => crc_axi_master_0_M_AXI_RLAST,
|
||||
s_axi_rready => crc_axi_master_0_M_AXI_RREADY,
|
||||
s_axi_rresp(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
s_axi_rvalid => crc_axi_master_0_M_AXI_RVALID,
|
||||
s_axi_wdata(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
s_axi_wid(0) => crc_axi_master_0_M_AXI_WID(0),
|
||||
s_axi_wlast => crc_axi_master_0_M_AXI_WLAST,
|
||||
s_axi_wready => crc_axi_master_0_M_AXI_WREADY,
|
||||
s_axi_wstrb(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
s_axi_wvalid => crc_axi_master_0_M_AXI_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => crc_axi_master_0_M_AXI_ARCACHE(3 downto 0),
|
||||
M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => crc_axi_master_0_M_AXI_ARPROT(2 downto 0),
|
||||
M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => crc_axi_master_0_M_AXI_AWCACHE(3 downto 0),
|
||||
M_AXI_AWID(0) => crc_axi_master_0_M_AXI_AWID(0),
|
||||
M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => crc_axi_master_0_M_AXI_AWPROT(2 downto 0),
|
||||
M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(31 downto 1) => B"0000000000000000000000000000000",
|
||||
M_AXI_BID(0) => crc_axi_master_0_M_AXI_BID(0),
|
||||
M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => crc_axi_master_0_M_AXI_WID(31 downto 0),
|
||||
M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
ip_idle => crc_axi_master_0_idle,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
|
||||
port map (
|
||||
addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
axi_idle => crc_axi_master_0_idle,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n,
|
||||
size(15 downto 0) => crc_axi_master_sim_c_0_size(15 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738085583"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738085583"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738085583"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738085583"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 18:33:02 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1_wrapper.bd
|
||||
--Design : design_1_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_wrapper is
|
||||
end design_1_wrapper;
|
||||
|
||||
architecture STRUCTURE of design_1_wrapper is
|
||||
component design_1 is
|
||||
end component design_1;
|
||||
begin
|
||||
design_1_i: component design_1
|
||||
;
|
||||
end STRUCTURE;
|
||||
+2342
File diff suppressed because it is too large
Load Diff
+315
@@ -0,0 +1,315 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axi_read_generator:1.0
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axi_read_generator_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
TRIGGER : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_read_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_read_generator_0_0_arch OF design_1_axi_read_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_read_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_read_generator IS
|
||||
GENERIC (
|
||||
DATA_WIDTH : INTEGER;
|
||||
ID_WIDTH : INTEGER;
|
||||
DEFAULT_MEMADDR : INTEGER;
|
||||
DEFAULT_BURSTLEN : INTEGER;
|
||||
DEFAULT_REQ_PAUSE : INTEGER;
|
||||
DEFAULT_RUN : BOOLEAN;
|
||||
DEFAULT_PIPELINING : BOOLEAN;
|
||||
DEFAULT_ARCACHE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
TRIGGER : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_read_generator;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS" &
|
||||
"_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_" &
|
||||
"BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axi_read_generator
|
||||
GENERIC MAP (
|
||||
DATA_WIDTH => 32,
|
||||
ID_WIDTH => 4,
|
||||
DEFAULT_MEMADDR => 268435456,
|
||||
DEFAULT_BURSTLEN => 16,
|
||||
DEFAULT_REQ_PAUSE => 1000,
|
||||
DEFAULT_RUN => true,
|
||||
DEFAULT_PIPELINING => false,
|
||||
DEFAULT_ARCACHE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
TRIGGER => TRIGGER,
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP
|
||||
);
|
||||
END design_1_axi_read_generator_0_0_arch;
|
||||
+4467
File diff suppressed because it is too large
Load Diff
+425
@@ -0,0 +1,425 @@
|
||||
#ifndef IP_DESIGN_1_AXI_VIP_0_0_H_
|
||||
#define IP_DESIGN_1_AXI_VIP_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "design_1_axi_vip_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport design_1_axi_vip_0_0 : public design_1_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport design_1_axi_vip_0_0 : public design_1_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport design_1_axi_vip_0_0 : public design_1_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_axi_vip_0_0 : public design_1_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_axi_vip_0_0 : public design_1_axi_vip_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_axi_vip_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_axi_vip_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_DESIGN_1_AXI_VIP_0_0_H_
|
||||
+291
@@ -0,0 +1,291 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_vip:1.1
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_axi_vip_0_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLOCK, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLOCK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RESET, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RESET RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [3 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [3 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [3 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [3 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [3 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS\
|
||||
_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
|
||||
axi_vip_v1_1_14_top #(
|
||||
.C_AXI_PROTOCOL(1),
|
||||
.C_AXI_INTERFACE_MODE(2),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WID_WIDTH(4),
|
||||
.C_AXI_RID_WIDTH(4),
|
||||
.C_AXI_AWUSER_WIDTH(0),
|
||||
.C_AXI_ARUSER_WIDTH(0),
|
||||
.C_AXI_WUSER_WIDTH(0),
|
||||
.C_AXI_RUSER_WIDTH(0),
|
||||
.C_AXI_BUSER_WIDTH(0),
|
||||
.C_AXI_SUPPORTS_NARROW(1),
|
||||
.C_AXI_HAS_BURST(1),
|
||||
.C_AXI_HAS_LOCK(0),
|
||||
.C_AXI_HAS_CACHE(1),
|
||||
.C_AXI_HAS_REGION(0),
|
||||
.C_AXI_HAS_PROT(1),
|
||||
.C_AXI_HAS_QOS(0),
|
||||
.C_AXI_HAS_WSTRB(1),
|
||||
.C_AXI_HAS_BRESP(1),
|
||||
.C_AXI_HAS_RRESP(1),
|
||||
.C_AXI_HAS_ARESETN(1)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aclken(1'B1),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(2'B0),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(2'B0),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'B0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'B0),
|
||||
.m_axi_bid(4'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'B0),
|
||||
.m_axi_bready(),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'B0),
|
||||
.m_axi_rid(4'B0),
|
||||
.m_axi_rdata(32'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'B0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'B0),
|
||||
.m_axi_rready()
|
||||
);
|
||||
endmodule
|
||||
+93
@@ -0,0 +1,93 @@
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
//NOTE: This file has been automatically generated by Vivado.
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ps/1ps
|
||||
package design_1_axi_vip_0_0_pkg;
|
||||
import axi_vip_pkg::*;
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// These parameters are named after the component for use in your verification
|
||||
// environment.
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
parameter design_1_axi_vip_0_0_VIP_PROTOCOL = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_READ_WRITE_MODE = "READ_WRITE";
|
||||
parameter design_1_axi_vip_0_0_VIP_INTERFACE_MODE = 2;
|
||||
parameter design_1_axi_vip_0_0_VIP_ADDR_WIDTH = 32;
|
||||
parameter design_1_axi_vip_0_0_VIP_DATA_WIDTH = 32;
|
||||
parameter design_1_axi_vip_0_0_VIP_ID_WIDTH = 4;
|
||||
parameter design_1_axi_vip_0_0_VIP_AWUSER_WIDTH = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_ARUSER_WIDTH = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_RUSER_WIDTH = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_WUSER_WIDTH = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_BUSER_WIDTH = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_SUPPORTS_NARROW = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_BURST = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_LOCK = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_CACHE = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_REGION = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_QOS = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_PROT = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_WSTRB = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_BRESP = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_RRESP = 1;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_ACLKEN = 0;
|
||||
parameter design_1_axi_vip_0_0_VIP_HAS_ARESETN = 1;
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
typedef axi_slv_agent #(design_1_axi_vip_0_0_VIP_PROTOCOL,
|
||||
design_1_axi_vip_0_0_VIP_ADDR_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_AWUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_WUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_BUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_ARUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_RUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_SUPPORTS_NARROW,
|
||||
design_1_axi_vip_0_0_VIP_HAS_BURST,
|
||||
design_1_axi_vip_0_0_VIP_HAS_LOCK,
|
||||
design_1_axi_vip_0_0_VIP_HAS_CACHE,
|
||||
design_1_axi_vip_0_0_VIP_HAS_REGION,
|
||||
design_1_axi_vip_0_0_VIP_HAS_PROT,
|
||||
design_1_axi_vip_0_0_VIP_HAS_QOS,
|
||||
design_1_axi_vip_0_0_VIP_HAS_WSTRB,
|
||||
design_1_axi_vip_0_0_VIP_HAS_BRESP,
|
||||
design_1_axi_vip_0_0_VIP_HAS_RRESP,
|
||||
design_1_axi_vip_0_0_VIP_HAS_ARESETN) design_1_axi_vip_0_0_slv_t;
|
||||
|
||||
typedef axi_slv_mem_agent #(design_1_axi_vip_0_0_VIP_PROTOCOL,
|
||||
design_1_axi_vip_0_0_VIP_ADDR_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_DATA_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_ID_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_AWUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_WUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_BUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_ARUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_RUSER_WIDTH,
|
||||
design_1_axi_vip_0_0_VIP_SUPPORTS_NARROW,
|
||||
design_1_axi_vip_0_0_VIP_HAS_BURST,
|
||||
design_1_axi_vip_0_0_VIP_HAS_LOCK,
|
||||
design_1_axi_vip_0_0_VIP_HAS_CACHE,
|
||||
design_1_axi_vip_0_0_VIP_HAS_REGION,
|
||||
design_1_axi_vip_0_0_VIP_HAS_PROT,
|
||||
design_1_axi_vip_0_0_VIP_HAS_QOS,
|
||||
design_1_axi_vip_0_0_VIP_HAS_WSTRB,
|
||||
design_1_axi_vip_0_0_VIP_HAS_BRESP,
|
||||
design_1_axi_vip_0_0_VIP_HAS_RRESP,
|
||||
design_1_axi_vip_0_0_VIP_HAS_ARESETN) design_1_axi_vip_0_0_slv_mem_t;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// How to start the verification component
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// design_1_axi_vip_0_0_slv_t design_1_axi_vip_0_0_slv;
|
||||
// initial begin : START_design_1_axi_vip_0_0_SLAVE
|
||||
// design_1_axi_vip_0_0_slv = new("design_1_axi_vip_0_0_slv", `design_1_axi_vip_0_0_PATH_TO_INTERFACE);
|
||||
// design_1_axi_vip_0_0_slv.start_slave();
|
||||
// end
|
||||
|
||||
endpackage : design_1_axi_vip_0_0_pkg
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
#ifndef IP_DESIGN_1_AXI_VIP_0_0_SC_H_
|
||||
#define IP_DESIGN_1_AXI_VIP_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_vip;
|
||||
|
||||
class DllExport design_1_axi_vip_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_axi_vip_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_axi_vip_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* S_TARGET_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_TARGET_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_vip* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
design_1_axi_vip_0_0_sc(const design_1_axi_vip_0_0_sc&);
|
||||
const design_1_axi_vip_0_0_sc& operator=(const design_1_axi_vip_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_DESIGN_1_AXI_VIP_0_0_SC_H_
|
||||
+151
@@ -0,0 +1,151 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: design_1_axi_vip_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_axi_vip_0_0 (
|
||||
input bit_as_bool aclk,
|
||||
input bit_as_bool aresetn,
|
||||
input bit [3 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [3 : 0] s_axi_wid,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [3 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [3 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [3 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_axi_vip_0_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awcache,s_axi_awprot,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arcache,s_axi_arprot,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit aclk;
|
||||
input bit aresetn;
|
||||
input bit [3 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [3 : 0] s_axi_wid;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [3 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [3 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [3 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <xtlm.h>
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
#include <utils/xtlm_aximm_passthru_module.h>
|
||||
#include <systemc>
|
||||
#include "sim_ipc_aximm_master.h"
|
||||
#include "sim_ipc_aximm_slave.h"
|
||||
|
||||
class axi_vip: public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
axi_vip(sc_core::sc_module_name module_name,
|
||||
xsc::common_cpp::properties model_param_props);
|
||||
virtual ~axi_vip();
|
||||
SC_HAS_PROCESS (axi_vip);
|
||||
xtlm::xtlm_aximm_target_socket *S_TARGET_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket *S_TARGET_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket *M_INITIATOR_wr_socket;
|
||||
std::vector<xtlm::xtlm_aximm_target_stub*> stubTargetSkt;
|
||||
std::vector<xtlm::xtlm_aximm_initiator_stub*> stubInitSkt;
|
||||
sc_core::sc_in<bool> aclk;
|
||||
sc_core::sc_in<bool> aresetn;
|
||||
private:
|
||||
xtlm::xtlm_aximm_passthru_module *P1;
|
||||
xtlm::xtlm_aximm_passthru_module *P2;
|
||||
sim_ipc_aximm_master* m_ipc_master;
|
||||
sim_ipc_aximm_slave* m_ipc_slave;
|
||||
|
||||
};
|
||||
|
||||
+82
@@ -0,0 +1,82 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "ipc2aximm_socket.h"
|
||||
#include <systemc>
|
||||
|
||||
class sim_ipc_aximm_master : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
SC_HAS_PROCESS(sim_ipc_aximm_master);
|
||||
|
||||
sim_ipc_aximm_master(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties &ppts);
|
||||
|
||||
~sim_ipc_aximm_master();
|
||||
|
||||
sc_core::sc_in<bool> m_aximm_aresetn;
|
||||
sc_core::sc_in<bool> m_aximm_aclk;
|
||||
|
||||
//Read & Write Sockets
|
||||
xtlm::xtlm_aximm_initiator_socket* rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* wr_socket;
|
||||
|
||||
xtlm::xtlm_aximm_initiator_rd_socket_util rd_util;
|
||||
xtlm::xtlm_aximm_initiator_wr_socket_util wr_util;
|
||||
private:
|
||||
//! SystemC Method to Read incoming data from ipc...
|
||||
void ipc2aximm_receive();
|
||||
void send_response();
|
||||
std::string get_ipi_name(std::string s);
|
||||
|
||||
xsc::ipc2aximm_socket* m_ipc2aximm_socket;
|
||||
xsc::common_cpp::report_handler m_logger;
|
||||
};
|
||||
+82
@@ -0,0 +1,82 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "aximm2ipc_socket.h"
|
||||
|
||||
class sim_ipc_aximm_slave : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
SC_HAS_PROCESS(sim_ipc_aximm_slave);
|
||||
sim_ipc_aximm_slave(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties& ppts);
|
||||
~sim_ipc_aximm_slave();
|
||||
|
||||
sc_core::sc_in<bool> s_aximm_aclk;
|
||||
sc_core::sc_in<bool> s_aximm_aresetn;
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* wr_socket;
|
||||
|
||||
xtlm::xtlm_aximm_target_rd_socket_util rd_util;
|
||||
xtlm::xtlm_aximm_target_wr_socket_util wr_util;
|
||||
|
||||
private:
|
||||
//! SystemC method to send the AXIMM data to external process
|
||||
void aximm2ipc_send();
|
||||
|
||||
//! SystemC Method to handle AXIMM Response
|
||||
void aximm_resp_handler();
|
||||
|
||||
std::string get_ipi_name(std::string s);
|
||||
|
||||
xsc::aximm2ipc_socket* m_aximm2ipc_socket;
|
||||
xsc::common_cpp::report_handler m_logger;
|
||||
};
|
||||
+1105
File diff suppressed because it is too large
Load Diff
+177
@@ -0,0 +1,177 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:axil_master_with_rom:1.0
|
||||
-- IP Revision: 19
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axil_master_with_rom_0_0 IS
|
||||
PORT (
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axil_master_with_rom IS
|
||||
GENERIC (
|
||||
STIM_FILENAME : STRING;
|
||||
HAS_FINISHED_OUT : BOOLEAN;
|
||||
HAS_INTERRUPT_IN : BOOLEAN;
|
||||
REVISION_NO : INTEGER
|
||||
);
|
||||
PORT (
|
||||
interrupt_in : IN STD_LOGIC;
|
||||
finished_o : OUT STD_LOGIC;
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axil_master_with_rom;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
|
||||
"SERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axil_master_with_rom
|
||||
GENERIC MAP (
|
||||
STIM_FILENAME => "../../axi_verification_tb_test.mem",
|
||||
HAS_FINISHED_OUT => false,
|
||||
HAS_INTERRUPT_IN => false,
|
||||
REVISION_NO => 4
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt_in => '0',
|
||||
M_AXIL_ACLK => M_AXIL_ACLK,
|
||||
M_AXIL_ARESETN => M_AXIL_ARESETN,
|
||||
M_AXIL_ARREADY => M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => M_AXIL_ARVALID,
|
||||
M_AXIL_ARADDR => M_AXIL_ARADDR,
|
||||
M_AXIL_ARPROT => M_AXIL_ARPROT,
|
||||
M_AXIL_RREADY => M_AXIL_RREADY,
|
||||
M_AXIL_RVALID => M_AXIL_RVALID,
|
||||
M_AXIL_RDATA => M_AXIL_RDATA,
|
||||
M_AXIL_RRESP => M_AXIL_RRESP,
|
||||
M_AXIL_AWREADY => M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => M_AXIL_AWVALID,
|
||||
M_AXIL_AWADDR => M_AXIL_AWADDR,
|
||||
M_AXIL_AWPROT => M_AXIL_AWPROT,
|
||||
M_AXIL_WREADY => M_AXIL_WREADY,
|
||||
M_AXIL_WVALID => M_AXIL_WVALID,
|
||||
M_AXIL_WDATA => M_AXIL_WDATA,
|
||||
M_AXIL_WSTRB => M_AXIL_WSTRB,
|
||||
M_AXIL_BREADY => M_AXIL_BREADY,
|
||||
M_AXIL_BVALID => M_AXIL_BVALID,
|
||||
M_AXIL_BRESP => M_AXIL_BRESP
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0_arch;
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Jan 28 14:56:09 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d1e3a60d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Jan 28 15:18:51 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d1e3a60d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLOCK_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_CLK_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_RESET_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_STOP_INPUT" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 8000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0_arch;
|
||||
+285
@@ -0,0 +1,285 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axil_master_with_rom.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
-- AXIL-Master
|
||||
--
|
||||
-- Transactions des Masters werden durch ein ladbares ROM definiert
|
||||
-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet
|
||||
-- Das ROM besitzt eine Wortbreite von 40 bit
|
||||
-- Für einen Befehl werden 1 bis 2 Worte verwendet
|
||||
-- Nur 'wal' verwendet 2 40 - Bit - Worte
|
||||
--
|
||||
-- Die Codierung ist nachfolgend dargestellt :
|
||||
-- command wal : <39 : 8> Adresse <3 : 0> Befehl(wal = 1)
|
||||
-- <39 : 8> Daten <3 : 0> Befehl WStrobe
|
||||
-- command ral : <39 : 8> Adresse <3 : 0> Befehl(ral = 2)
|
||||
-- command wfi : Befehl(wfi = 6)
|
||||
-- command ral : <15 : 8> Wartezyklen <3 : 0> Befehl(slp = 7)
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axil_master_with_rom is
|
||||
generic
|
||||
(
|
||||
HAS_INTERRUPT_IN : boolean := true;
|
||||
HAS_FINISHED_OUT : boolean := false;
|
||||
REVISION_NO : integer := 1;
|
||||
STIM_FILENAME : string := "../../stimuli.mem"
|
||||
);
|
||||
port
|
||||
(
|
||||
interrupt_in : in std_logic:='0';
|
||||
finished_o : out std_logic;
|
||||
|
||||
M_AXIL_ACLK : in std_logic;
|
||||
M_AXIL_ARESETN : in std_logic;
|
||||
|
||||
M_AXIL_ARREADY : in std_logic;
|
||||
M_AXIL_ARVALID : out std_logic;
|
||||
M_AXIL_ARADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_ARPROT : out std_logic_vector(2 downto 0);
|
||||
M_AXIL_RREADY : out std_logic;
|
||||
M_AXIL_RVALID : in std_logic;
|
||||
M_AXIL_RDATA : in std_logic_vector(31 downto 0);
|
||||
M_AXIL_RRESP : in std_logic_vector(1 downto 0);
|
||||
M_AXIL_AWREADY : in std_logic;
|
||||
M_AXIL_AWVALID : out std_logic;
|
||||
M_AXIL_AWADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_AWPROT : out std_logic_vector(2 downto 0);
|
||||
M_AXIL_WREADY : in std_logic;
|
||||
M_AXIL_WVALID : out std_logic;
|
||||
M_AXIL_WDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_WSTRB : out std_logic_vector(3 downto 0);
|
||||
M_AXIL_BREADY : out std_logic;
|
||||
M_AXIL_BVALID : in std_logic;
|
||||
M_AXIL_BRESP : in std_logic_vector(1 downto 0)
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axil_master_with_rom is
|
||||
|
||||
|
||||
type TSTATE is (INIT,INIT_WAIT,
|
||||
GET_COMMAND,
|
||||
WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP,
|
||||
RD_ADDR,RD_DATA,
|
||||
WAIT_FOR_INT,
|
||||
SLEEP,SLEEP_WAIT,
|
||||
FINISHED
|
||||
);
|
||||
|
||||
signal state : TSTATE := INIT;
|
||||
|
||||
constant ADDR_WIDTH_CMD_ROM : integer := 12;
|
||||
|
||||
signal mdata : std_logic_vector(39 downto 0);
|
||||
signal maddr : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
cmdrom : entity work.axilm_rom
|
||||
generic map (
|
||||
FILENAME => STIM_FILENAME,
|
||||
DW => 40,
|
||||
AW => ADDR_WIDTH_CMD_ROM
|
||||
)
|
||||
port map (
|
||||
clk => M_AXIL_ACLK,
|
||||
a => maddr,
|
||||
q => mdata
|
||||
);
|
||||
|
||||
|
||||
process
|
||||
variable cnt8 : unsigned( 7 downto 0);
|
||||
variable cnt32 : unsigned(31 downto 0);
|
||||
variable addr_accepted : boolean;
|
||||
variable data_accepted : boolean;
|
||||
|
||||
begin
|
||||
wait until rising_edge(M_AXIL_ACLK);
|
||||
|
||||
if M_AXIL_ARESETN = '0' then
|
||||
state <= INIT;
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others=>'X');
|
||||
M_AXIL_ARPROT <= (others=>'0');
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_AWADDR <= (others=>'X');
|
||||
M_AXIL_AWPROT <= (others=>'0');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_BREADY <= '0';
|
||||
finished_o <= '0';
|
||||
else
|
||||
case state is
|
||||
|
||||
----
|
||||
-- Init
|
||||
----
|
||||
when INIT =>
|
||||
finished_o <= '0';
|
||||
cnt8 := x"10";
|
||||
maddr <= (others=>'0');
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others=>'X');
|
||||
M_AXIL_ARPROT <= (others=>'0');
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_AWADDR <= (others=>'X');
|
||||
M_AXIL_AWPROT <= (others=>'0');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_BREADY <= '0';
|
||||
state <= INIT_WAIT;
|
||||
|
||||
when INIT_WAIT =>
|
||||
cnt8 := cnt8 - 1;
|
||||
if cnt8 = 0 then
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when GET_COMMAND =>
|
||||
case (mdata(3 downto 0)) is
|
||||
when x"0" => state <= FINISHED;
|
||||
when x"1" => state <= WR_ADDR;
|
||||
when x"2" => state <= RD_ADDR;
|
||||
when x"6" => state <= WAIT_FOR_INT;
|
||||
when x"7" => state <= SLEEP;
|
||||
when others => maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
end case;
|
||||
|
||||
|
||||
----
|
||||
-- Write
|
||||
----
|
||||
when WR_ADDR =>
|
||||
M_AXIL_AWVALID <= '1';
|
||||
M_AXIL_AWADDR <= mdata(39 downto 8);
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others => 'X');
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
addr_accepted := false;
|
||||
data_accepted := false;
|
||||
state <= WR_ADDR_WAIT1;
|
||||
when WR_ADDR_WAIT1 =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
state <= WR_ADDR_WAIT2;
|
||||
when WR_ADDR_WAIT2 =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
state <= WR_DATA;
|
||||
when WR_DATA =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
M_AXIL_WSTRB <= mdata( 3 downto 0);
|
||||
M_AXIL_WDATA <= mdata(39 downto 8);
|
||||
M_AXIL_WVALID <= '1';
|
||||
state <= WR_DATA_WAIT;
|
||||
when WR_DATA_WAIT =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
if (M_AXIL_WREADY = '1') then
|
||||
M_AXIL_WVALID <= '0';
|
||||
data_accepted := true;
|
||||
end if;
|
||||
|
||||
if (addr_accepted and data_accepted) then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_BREADY <= '1';
|
||||
state <= WR_RESP;
|
||||
end if;
|
||||
when WR_RESP =>
|
||||
if M_AXIL_BVALID = '1' then
|
||||
M_AXIL_BREADY <= '0';
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
|
||||
----
|
||||
-- Read
|
||||
----
|
||||
when RD_ADDR =>
|
||||
M_AXIL_ARVALID <= '1';
|
||||
M_AXIL_ARADDR <= mdata(39 downto 8);
|
||||
M_AXIL_AWVALID <= 'X';
|
||||
M_AXIL_AWADDR <= (others => 'X');
|
||||
M_AXIL_RREADY <= '1';
|
||||
addr_accepted := false;
|
||||
state <= RD_DATA;
|
||||
when RD_DATA =>
|
||||
if (M_AXIL_ARREADY = '1') then
|
||||
M_AXIL_ARVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
if (M_AXIL_RVALID = '1') then
|
||||
M_AXIL_RREADY <= '0';
|
||||
data_accepted := true;
|
||||
end if;
|
||||
if (addr_accepted and data_accepted) then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_ARADDR <= (others => 'X');
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when WAIT_FOR_INT =>
|
||||
if (interrupt_in = '1') then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when SLEEP =>
|
||||
cnt32 := unsigned(mdata(39 downto 8));
|
||||
-- synthesis translate_off
|
||||
cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern
|
||||
-- synthesis translate_on
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
state <= SLEEP_WAIT;
|
||||
|
||||
when SLEEP_WAIT =>
|
||||
if (cnt32 /= 0) then
|
||||
cnt32 := cnt32 - 1;
|
||||
else
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when FINISHED =>
|
||||
finished_o <= '1';
|
||||
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end;
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axilm_rom.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
entity axilm_rom is
|
||||
|
||||
generic (
|
||||
FILENAME : string;
|
||||
DW : integer; -- Data Width
|
||||
AW : integer -- Address Width
|
||||
);
|
||||
port (
|
||||
clk : in std_logic; -- Clock
|
||||
a : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
q : out std_logic_vector(DW-1 downto 0) -- Data out port
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axilm_rom is
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
|
||||
|
||||
impure function InitMemFromFile(MemFileName : in string) return tmem is
|
||||
FILE MemFile : text is in MemFileName;
|
||||
variable MemFileLine : line;
|
||||
variable mem : tmem;
|
||||
begin
|
||||
for i in tmem'range loop
|
||||
readline(MemFile, MemFileLine);
|
||||
read(MemFileLine, mem(i));
|
||||
end loop;
|
||||
return mem;
|
||||
end function;
|
||||
|
||||
constant mem : tmem := InitMemFromFile(
|
||||
-- synthesis translate_off
|
||||
"../../" &
|
||||
-- synthesis translate_on
|
||||
FILENAME);
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
q <= mem(to_integer(unsigned(a)));
|
||||
end process;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- clk_rst_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_rst_generator is
|
||||
generic
|
||||
(
|
||||
CLOCK_PERIOD : integer := 10000;
|
||||
HAS_CLK_INPUT : boolean := true;
|
||||
HAS_RESET_INPUT : boolean := true;
|
||||
HAS_STOP_INPUT : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
clk_in : in std_logic := '1';
|
||||
rst_in : in std_logic := '0';
|
||||
|
||||
clk : out std_logic;
|
||||
rst_n : out std_logic;
|
||||
|
||||
stop_simulation : in std_logic := '0'
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of clk_rst_generator is
|
||||
|
||||
signal clk_sim : std_logic := '1';
|
||||
signal clk_in_sig : std_logic := '1';
|
||||
signal clk_sig : std_logic := '1';
|
||||
signal rst_sig : std_logic := '0';
|
||||
signal rst_in_sync : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk <= clk_sig;
|
||||
rst_n <= not rst_sig;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
clk_sig <= clk_in_sig and clk_sim;
|
||||
-- Dies ist kein gated Clock!
|
||||
-- Fuer die Synthese ist clk_sim konstant '1'
|
||||
-- somit wird die UND-Verknuepfung 'wegoptimiert'
|
||||
-- und was übrig bleibt, ist ein 'Draht'
|
||||
|
||||
-- synthesis translate_off
|
||||
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
-- synthesis translate_on
|
||||
|
||||
process (clk_in) begin
|
||||
clk_in_sig <= clk_in;
|
||||
-- synthesis translate_off
|
||||
clk_in_sig <= '1';
|
||||
-- synthesis translate_on
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- RESET GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
process
|
||||
variable rescnt : unsigned (6 downto 0) := (others=>'1');
|
||||
begin
|
||||
wait until rising_edge(clk_sig);
|
||||
|
||||
rst_in_sync <= rst_in;
|
||||
if rst_in_sync = '1' then
|
||||
rescnt := (others=>'1');
|
||||
end if;
|
||||
|
||||
if rescnt = 0 then
|
||||
rst_sig <= '0';
|
||||
else
|
||||
rescnt := rescnt - 1;
|
||||
rst_sig <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- STOP SIMULATION INPUT (simulation only)
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- synthesis translate_off
|
||||
process (stop_simulation) begin
|
||||
if stop_simulation = '1' then
|
||||
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
|
||||
end if;
|
||||
end process;
|
||||
-- synthesis translate_on
|
||||
|
||||
end rtl;
|
||||
+303
@@ -0,0 +1,303 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axi_read_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axi_read_generator is
|
||||
generic
|
||||
(
|
||||
DATA_WIDTH : integer := 32; -- Datenwortbreite
|
||||
ID_WIDTH : integer := 4; -- AXI ID Wortbreite
|
||||
DEFAULT_MEMADDR : integer := 16#10000000#; -- Speicheradresse (an die 4k Grenze denken!)
|
||||
DEFAULT_BURSTLEN : integer := 16; -- Burstlänge
|
||||
DEFAULT_REQ_PAUSE : integer := 1000; -- Waitcycles zwischen Requests
|
||||
DEFAULT_RUN : boolean := false; -- FSM aktiv oder nicht?
|
||||
DEFAULT_PIPELINING : boolean := false; -- Request Pipelining nutzen (oder halt nicht)
|
||||
DEFAULT_ARCACHE : integer := 0 -- ARCACHE-Setting
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic := '1';
|
||||
|
||||
TRIGGER : out std_logic;
|
||||
|
||||
-- AXI Master Interface (Memory)
|
||||
M_AXI_ARREADY : in std_logic := '1';
|
||||
M_AXI_ARVALID : out std_logic;
|
||||
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXI_ARID : out std_logic_vector(ID_WIDTH-1 downto 0);
|
||||
M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
|
||||
M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_RREADY : out std_logic;
|
||||
M_AXI_RVALID : in std_logic;
|
||||
M_AXI_RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
M_AXI_RRESP : in std_logic_vector( 1 downto 0);
|
||||
M_AXI_RID : in std_logic_vector(ID_WIDTH-1 downto 0);
|
||||
M_AXI_RLAST : in std_logic;
|
||||
|
||||
M_AXI_AWREADY : in std_logic := '0';
|
||||
M_AXI_AWVALID : out std_logic;
|
||||
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_AWID : out std_logic_vector(ID_WIDTH-1 downto 0);
|
||||
M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
|
||||
M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_WREADY : in std_logic := '0';
|
||||
M_AXI_WVALID : out std_logic;
|
||||
M_AXI_WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
M_AXI_WSTRB : out std_logic_vector(DATA_WIDTH/8-1 downto 0);
|
||||
M_AXI_WLAST : out std_logic;
|
||||
M_AXI_WID : out std_logic_vector(ID_WIDTH-1 downto 0);
|
||||
M_AXI_BREADY : out std_logic;
|
||||
M_AXI_BVALID : in std_logic := '0';
|
||||
M_AXI_BID : in std_logic_vector( ID_WIDTH-1 downto 0);
|
||||
M_AXI_BRESP : in std_logic_vector( 1 downto 0);
|
||||
|
||||
-- AXIL Slave
|
||||
S_AXIL_AWADDR : in std_logic_vector(14 downto 0) := (others=>'0');
|
||||
S_AXIL_AWVALID : in std_logic := '0';
|
||||
S_AXIL_AWREADY : out std_logic;
|
||||
S_AXIL_WDATA : in std_logic_vector(31 downto 0) := (others=>'0');
|
||||
S_AXIL_WVALID : in std_logic := '0';
|
||||
S_AXIL_WREADY : out std_logic;
|
||||
S_AXIL_WSTRB : in std_logic_vector( 3 downto 0) := (others=>'0');
|
||||
S_AXIL_BVALID : out std_logic;
|
||||
S_AXIL_BREADY : in std_logic := '1';
|
||||
S_AXIL_BRESP : out std_logic_vector( 1 downto 0);
|
||||
S_AXIL_ARADDR : in std_logic_vector(14 downto 0) := (others=>'0');
|
||||
S_AXIL_ARVALID : in std_logic := '0';
|
||||
S_AXIL_ARREADY : out std_logic;
|
||||
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
|
||||
S_AXIL_RVALID : out std_logic;
|
||||
S_AXIL_RREADY : in std_logic := '1';
|
||||
S_AXIL_RRESP : out std_logic_vector( 1 downto 0)
|
||||
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axi_read_generator is
|
||||
|
||||
function Bool_2_StdLogic(b: boolean) return std_logic is
|
||||
begin
|
||||
if b then
|
||||
return('1');
|
||||
else
|
||||
return('0');
|
||||
end if;
|
||||
end function;
|
||||
|
||||
constant reg_control_default : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(DEFAULT_REQ_PAUSE,16)) & -- Byte 3/2
|
||||
"0000" & std_logic_vector(to_unsigned(DEFAULT_ARCACHE,4)) & -- Byte 1
|
||||
Bool_2_StdLogic(DEFAULT_RUN) & Bool_2_StdLogic(DEFAULT_PIPELINING) & "0" & std_logic_vector(to_unsigned(DEFAULT_BURSTLEN,5)); -- Byte 0;
|
||||
|
||||
type T_FSM_STATE is (STARTUP,IDLE,WAIT_REQ_ACCEPT,REQ_PAUSE,WAIT_REQ_FINISHED);
|
||||
signal state : T_FSM_STATE := IDLE;
|
||||
|
||||
signal reg_memaddr : std_logic_vector (31 downto 0) := std_logic_vector(to_unsigned(DEFAULT_MEMADDR,32));
|
||||
signal reg_control : std_logic_vector (31 downto 0) := reg_control_default;
|
||||
|
||||
begin
|
||||
--------------------------------
|
||||
-- whole bunch of static outputs
|
||||
--------------------------------
|
||||
M_AXI_RREADY <= '1';
|
||||
M_AXI_AWVALID <= '0';
|
||||
M_AXI_AWADDR <= (others=>'0');
|
||||
M_AXI_AWLEN <= (others=>'0');
|
||||
M_AXI_AWSIZE <= (others=>'0');
|
||||
M_AXI_AWID <= (others=>'0');
|
||||
M_AXI_AWBURST <= (others=>'0');
|
||||
M_AXI_AWPROT <= (others=>'0');
|
||||
M_AXI_AWCACHE <= (others=>'0');
|
||||
M_AXI_WVALID <= '0';
|
||||
M_AXI_WDATA <= (others=>'0');
|
||||
M_AXI_WSTRB <= (others=>'0');
|
||||
M_AXI_WLAST <= '0';
|
||||
M_AXI_WID <= (others=>'0');
|
||||
M_AXI_BREADY <= '1';
|
||||
|
||||
--------------------------------
|
||||
-- AXI Read Request Engine
|
||||
--------------------------------
|
||||
process
|
||||
variable burstlen_coded : std_logic_vector (4 downto 0);
|
||||
variable arcache : std_logic_vector (3 downto 0);
|
||||
variable req_pipelining : std_logic;
|
||||
|
||||
variable cnt : unsigned (15 downto 0);
|
||||
variable id : unsigned (ID_WIDTH-1 downto 0);
|
||||
variable last_requested_id : std_logic_vector (ID_WIDTH-1 downto 0);
|
||||
variable pause_cycles : unsigned (15 downto 0);
|
||||
variable req_pipe_en : std_logic;
|
||||
variable run : std_logic;
|
||||
variable burst_finished : boolean;
|
||||
|
||||
variable start_delay_cnt : unsigned(27 downto 0);
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
pause_cycles := unsigned(reg_control(31 downto 16));
|
||||
arcache := reg_control(11 downto 8);
|
||||
run := reg_control(7);
|
||||
req_pipe_en := reg_control(6);
|
||||
burstlen_coded := std_logic_vector(unsigned(reg_control(4 downto 0))-1);
|
||||
|
||||
|
||||
if RESETN = '0' then
|
||||
M_AXI_ARVALID <= '0';
|
||||
TRIGGER <= '0';
|
||||
start_delay_cnt := to_unsigned(150000000,28);
|
||||
if run = '1' then -- no transaction during initialization (i.e. when booting from SD card)
|
||||
state <= STARTUP;
|
||||
else
|
||||
state <= IDLE;
|
||||
end if;
|
||||
else
|
||||
case state is
|
||||
when STARTUP =>
|
||||
if start_delay_cnt = 0 then
|
||||
state <= IDLE;
|
||||
end if;
|
||||
start_delay_cnt := start_delay_cnt - 1;
|
||||
|
||||
when IDLE =>
|
||||
M_AXI_ARADDR <= reg_memaddr;
|
||||
M_AXI_ARID <= std_logic_vector(id);
|
||||
M_AXI_ARLEN <= burstlen_coded(3 downto 0);
|
||||
M_AXI_ARBURST <= "01";
|
||||
M_AXI_ARPROT <= "000";
|
||||
M_AXI_ARCACHE <= arcache;
|
||||
case DATA_WIDTH/8 is
|
||||
when 1 => M_AXI_ARSIZE <= "000";
|
||||
when 2 => M_AXI_ARSIZE <= "001";
|
||||
when 4 => M_AXI_ARSIZE <= "010";
|
||||
when 8 => M_AXI_ARSIZE <= "011";
|
||||
when 16 => M_AXI_ARSIZE <= "100";
|
||||
when 32 => M_AXI_ARSIZE <= "101";
|
||||
when 64 => M_AXI_ARSIZE <= "110";
|
||||
when 128 => M_AXI_ARSIZE <= "111";
|
||||
when others => M_AXI_ARSIZE <= "011";
|
||||
end case;
|
||||
|
||||
if run = '1' then
|
||||
TRIGGER <= reg_control(5);
|
||||
burst_finished := false;
|
||||
last_requested_id := std_logic_vector(id);
|
||||
id := id + 1;
|
||||
M_AXI_ARVALID <= '1';
|
||||
state <= WAIT_REQ_ACCEPT;
|
||||
end if;
|
||||
|
||||
when WAIT_REQ_ACCEPT =>
|
||||
TRIGGER <= '0';
|
||||
if M_AXI_ARREADY = '1' then
|
||||
M_AXI_ARVALID <= '0';
|
||||
if pause_cycles /= 0 then
|
||||
cnt := pause_cycles;
|
||||
state <= REQ_PAUSE;
|
||||
elsif req_pipe_en = '0' then
|
||||
state <= WAIT_REQ_FINISHED;
|
||||
else
|
||||
state <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when REQ_PAUSE =>
|
||||
if M_AXI_RLAST = '1' and M_AXI_RID = last_requested_id then
|
||||
burst_finished := true;
|
||||
end if;
|
||||
|
||||
if cnt /= 0 then
|
||||
cnt := cnt - 1;
|
||||
else
|
||||
if req_pipe_en = '0' then
|
||||
state <= WAIT_REQ_FINISHED;
|
||||
else
|
||||
state <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when WAIT_REQ_FINISHED =>
|
||||
if burst_finished or (M_AXI_RLAST = '1' and M_AXI_RID = last_requested_id) then
|
||||
state <= IDLE;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
--------------------------------
|
||||
-- AXIL Interface
|
||||
--------------------------------
|
||||
S_AXIL_BRESP <= (others=>'0'); -- No write errors
|
||||
S_AXIL_RRESP <= (others=>'0'); -- No read errors
|
||||
S_AXIL_ARREADY <= '1'; -- IP is always ready
|
||||
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
|
||||
process
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
if RESETN = '0' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
S_AXIL_RVALID <= '0';
|
||||
|
||||
reg_control <= reg_control_default;
|
||||
reg_memaddr <= std_logic_vector(to_unsigned(DEFAULT_MEMADDR,32));
|
||||
|
||||
else
|
||||
if S_AXIL_RREADY = '1' then
|
||||
S_AXIL_RVALID <= '0';
|
||||
end if;
|
||||
|
||||
if S_AXIL_ARVALID = '1' then
|
||||
S_AXIL_RDATA <= (others=>'0');
|
||||
if S_AXIL_ARADDR(2) = '0' then
|
||||
S_AXIL_RDATA <= reg_control;
|
||||
else
|
||||
S_AXIL_RDATA <= reg_memaddr;
|
||||
end if;
|
||||
S_AXIL_RVALID <= '1';
|
||||
end if;
|
||||
|
||||
if S_AXIL_BREADY = '1' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
end if;
|
||||
|
||||
if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
|
||||
S_AXIL_BVALID <= '1';
|
||||
for i in 0 to 31 loop
|
||||
if S_AXIL_WSTRB(i/8) = '1' then
|
||||
if S_AXIL_AWADDR(2) = '0' then
|
||||
reg_control(i) <= S_AXIL_WDATA(i);
|
||||
else
|
||||
reg_memaddr(i) <= S_AXIL_WDATA(i);
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
+670
@@ -0,0 +1,670 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axis to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axi2vector #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
|
||||
// payloads
|
||||
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
|
||||
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
|
||||
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
|
||||
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
|
||||
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
|
||||
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
|
||||
|
||||
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
|
||||
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
|
||||
|
||||
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
|
||||
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
|
||||
|
||||
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
|
||||
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
|
||||
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
|
||||
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
|
||||
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
|
||||
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
|
||||
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
|
||||
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
|
||||
|
||||
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
end
|
||||
|
||||
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
|
||||
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
|
||||
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
|
||||
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
|
||||
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
|
||||
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
|
||||
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
|
||||
|
||||
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
|
||||
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
|
||||
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
|
||||
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
|
||||
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
|
||||
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
|
||||
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign s_axi_buser = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign s_axi_bid = 'b0;
|
||||
assign s_axi_buser = 'b0;
|
||||
|
||||
assign s_axi_rlast = 1'b1;
|
||||
assign s_axi_rid = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: SRL based FIFO for AXIS/AXI Channels.
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter C_FAMILY = "virtex7",
|
||||
parameter integer C_PAYLOAD_WIDTH = 1,
|
||||
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
input wire aclk, // Clock
|
||||
input wire aresetn, // Reset
|
||||
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
|
||||
input wire s_valid, // Input data valid
|
||||
output reg s_ready, // Input data ready
|
||||
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
|
||||
output reg m_valid, // Output data valid
|
||||
input wire m_ready // Output data ready
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
|
||||
wire [4-1:0] fifo_addr;
|
||||
wire push;
|
||||
wire pop ;
|
||||
reg areset_r1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
always @(posedge aclk) begin
|
||||
areset_r1 <= ~aresetn;
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
|
||||
end
|
||||
else begin
|
||||
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
|
||||
~push & pop ? fifo_index - 1'b1 :
|
||||
fifo_index;
|
||||
end
|
||||
end
|
||||
|
||||
assign push = s_valid & s_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
s_ready <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
s_ready <= areset_r1 ? 1'b1 :
|
||||
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
|
||||
~push & pop ? 1'b1 :
|
||||
s_ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign pop = m_valid & m_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
m_valid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
|
||||
push & ~pop ? 1'b1 :
|
||||
m_valid;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
|
||||
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
|
||||
end
|
||||
else begin : gen_fifo_addr
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
|
||||
SRL16E
|
||||
u_srl_fifo(
|
||||
.Q ( m_payload[i] ) ,
|
||||
.A0 ( fifo_addr[0] ) ,
|
||||
.A1 ( fifo_addr[1] ) ,
|
||||
.A2 ( fifo_addr[2] ) ,
|
||||
.A3 ( fifo_addr[3] ) ,
|
||||
.CE ( push ) ,
|
||||
.CLK ( aclk ) ,
|
||||
.D ( s_payload[i] )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axi to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_vector2axi #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
|
||||
// payloads
|
||||
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
|
||||
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
|
||||
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
|
||||
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
|
||||
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
|
||||
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
|
||||
|
||||
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
|
||||
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
|
||||
|
||||
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
|
||||
|
||||
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
|
||||
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
|
||||
|
||||
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
|
||||
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
|
||||
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
|
||||
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
|
||||
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
|
||||
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
|
||||
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
|
||||
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
|
||||
|
||||
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
assign m_axi_wid = 1'b0;
|
||||
end
|
||||
|
||||
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
|
||||
|
||||
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
|
||||
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
|
||||
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
|
||||
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
|
||||
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
|
||||
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
|
||||
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
|
||||
|
||||
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
|
||||
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
|
||||
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
|
||||
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
|
||||
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
|
||||
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
|
||||
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_awburst = 'b0;
|
||||
assign m_axi_awcache = 'b0;
|
||||
assign m_axi_awlen = 'b0;
|
||||
assign m_axi_awlock = 'b0;
|
||||
assign m_axi_awid = 'b0;
|
||||
assign m_axi_awqos = 'b0;
|
||||
|
||||
assign m_axi_wlast = 1'b1;
|
||||
assign m_axi_wid = 'b0;
|
||||
|
||||
|
||||
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_arburst = 'b0;
|
||||
assign m_axi_arcache = 'b0;
|
||||
assign m_axi_arlen = 'b0;
|
||||
assign m_axi_arlock = 'b0;
|
||||
assign m_axi_arid = 'b0;
|
||||
assign m_axi_arqos = 'b0;
|
||||
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
+633
@@ -0,0 +1,633 @@
|
||||
// (c) Copyright 2016 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// AXI VIP wrapper
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// axi_vip
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_vip_v1_1_14_top #
|
||||
(
|
||||
parameter C_AXI_PROTOCOL = 0,
|
||||
parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_WDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_RDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_WID_WIDTH = 0,
|
||||
parameter integer C_AXI_RID_WIDTH = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_SUPPORTS_NARROW = 1,
|
||||
parameter integer C_AXI_HAS_BURST = 1,
|
||||
parameter integer C_AXI_HAS_LOCK = 1,
|
||||
parameter integer C_AXI_HAS_CACHE = 1,
|
||||
parameter integer C_AXI_HAS_REGION = 1,
|
||||
parameter integer C_AXI_HAS_PROT = 1,
|
||||
parameter integer C_AXI_HAS_QOS = 1,
|
||||
parameter integer C_AXI_HAS_WSTRB = 1,
|
||||
parameter integer C_AXI_HAS_BRESP = 1,
|
||||
parameter integer C_AXI_HAS_RRESP = 1,
|
||||
parameter integer C_AXI_HAS_ARESETN = 1
|
||||
)
|
||||
(
|
||||
//NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
|
||||
//Please refer xgui tcl and coreinfo.yml
|
||||
|
||||
// System Signals
|
||||
input wire aclk,
|
||||
input wire aclken,
|
||||
input wire aresetn,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
input wire s_axi_awvalid,
|
||||
output wire s_axi_awready,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
input wire s_axi_wvalid,
|
||||
output wire s_axi_wready,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
output wire s_axi_bvalid,
|
||||
input wire s_axi_bready,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
input wire s_axi_arvalid,
|
||||
output wire s_axi_arready,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
output wire s_axi_rvalid,
|
||||
input wire s_axi_rready,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
);
|
||||
|
||||
/**********************************************************************************************
|
||||
* NOTE:
|
||||
* C_AXI_INTERFACE_MODE =0 -- MASTER MODE,
|
||||
* C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE
|
||||
* C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
|
||||
* Please refer xgui tcl and coreinfo.yml
|
||||
* User can change PASS_THROUGH VIP to run time master mode or run time slave mode during
|
||||
* the simulation
|
||||
*********************************************************************************************/
|
||||
|
||||
/**********************************************************************************************
|
||||
* Master_mode means that either the dut is statically being configured to be in master mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in master mode
|
||||
* in run time.
|
||||
|
||||
* Slave mode means that either the dut is statically being configured to be in slave mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in slave mode
|
||||
* in run time.
|
||||
|
||||
* Pass-through mode means that either the dut is statically being configured to be in
|
||||
* pass-through mode or it statically being configured to be pass-through mode and switched
|
||||
* to be in master/slave mode and then switch back to be in pass-through mode in run time
|
||||
*********************************************************************************************/
|
||||
|
||||
logic runtime_master =0;
|
||||
logic runtime_slave =0;
|
||||
|
||||
wire run_slave_mode;
|
||||
wire run_master_mode;
|
||||
wire run_passth_mode;
|
||||
wire compile_master_mode;
|
||||
wire compile_slave_mode;
|
||||
wire master_mode;
|
||||
wire slave_mode;
|
||||
|
||||
assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
|
||||
assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
|
||||
assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
|
||||
|
||||
assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;
|
||||
assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
|
||||
|
||||
assign master_mode = compile_master_mode || run_master_mode;
|
||||
assign slave_mode = compile_slave_mode || run_slave_mode;
|
||||
|
||||
// Slave Interface Write Address Ports Internal
|
||||
assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
|
||||
assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
|
||||
assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}};
|
||||
assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}};
|
||||
assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}};
|
||||
assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}};
|
||||
assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}};
|
||||
assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
|
||||
assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz};
|
||||
assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
|
||||
assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
|
||||
assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz};
|
||||
assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
|
||||
assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz};
|
||||
assign s_axi_wready = slave_mode? IF.WREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}};
|
||||
assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
|
||||
assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}};
|
||||
assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}};
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
|
||||
assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
|
||||
assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}};
|
||||
assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}};
|
||||
assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}};
|
||||
assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ;
|
||||
assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}};
|
||||
assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
|
||||
assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz};
|
||||
assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0};
|
||||
|
||||
//Slave Interface Read Data Ports
|
||||
assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
|
||||
assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}};
|
||||
assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}};
|
||||
assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
|
||||
assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}};
|
||||
assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}};
|
||||
|
||||
// Master Interface Write Address Port
|
||||
assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}};
|
||||
assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}};
|
||||
assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}};
|
||||
assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}};
|
||||
assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
|
||||
assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}};
|
||||
assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
|
||||
assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0};
|
||||
assign IF.AWREADY = master_mode? m_axi_awready :{1'bz};
|
||||
|
||||
// Master Interface Write Data Ports Internal
|
||||
assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
|
||||
assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
|
||||
assign m_axi_wlast = master_mode? IF.WLAST : {1'b0};
|
||||
assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
|
||||
assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0};
|
||||
assign IF.WREADY = master_mode? m_axi_wready : {1'bz};
|
||||
|
||||
// Master Interface Write Response Ports Internal
|
||||
assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}};
|
||||
assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
|
||||
assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz;
|
||||
assign m_axi_bready = master_mode? IF.BREADY : 1'b0;
|
||||
|
||||
// Master Interface Read Address Port Internal
|
||||
assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}};
|
||||
assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}};
|
||||
assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}};
|
||||
assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}};
|
||||
assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
|
||||
assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}};
|
||||
assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
|
||||
assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0};
|
||||
assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}};
|
||||
|
||||
// Master Interface Read Data Ports Internal
|
||||
assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
|
||||
assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}};
|
||||
assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}};
|
||||
assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
|
||||
assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}};
|
||||
assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}};
|
||||
|
||||
axi_vip_if #(
|
||||
.C_AXI_PROTOCOL(C_AXI_PROTOCOL),
|
||||
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
|
||||
.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
|
||||
.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
|
||||
.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
|
||||
.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ),
|
||||
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ),
|
||||
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
|
||||
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
|
||||
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
|
||||
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
|
||||
.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
|
||||
.C_AXI_HAS_BURST(C_AXI_HAS_BURST),
|
||||
.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
|
||||
.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
|
||||
.C_AXI_HAS_REGION(C_AXI_HAS_REGION),
|
||||
.C_AXI_HAS_PROT(C_AXI_HAS_PROT),
|
||||
.C_AXI_HAS_QOS(C_AXI_HAS_QOS),
|
||||
.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
|
||||
.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
|
||||
.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
|
||||
.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
|
||||
) IF (
|
||||
.ACLK(aclk),
|
||||
.ARESET_N(aresetn),
|
||||
.ACLKEN(aclken)
|
||||
);
|
||||
|
||||
|
||||
//synthesis translate_off
|
||||
initial begin
|
||||
$display("XilinxAXIVIP: Found at Path: %m");
|
||||
end
|
||||
|
||||
//set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode
|
||||
generate
|
||||
initial begin
|
||||
if(C_AXI_INTERFACE_MODE ==0) begin
|
||||
IF.set_intf_master;
|
||||
end else if(C_AXI_INTERFACE_MODE ==2) begin
|
||||
IF.set_intf_slave;
|
||||
end else if(C_AXI_INTERFACE_MODE ==1) begin
|
||||
$display("This AXI VIP is in passthrough mode");
|
||||
end else begin
|
||||
$fatal(0,"This AXI VIP's mode is out of range");
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/*
|
||||
Function: set_passthrough_mode
|
||||
Sets AXI VIP passthrough into run time passthrough mode
|
||||
*/
|
||||
function void set_passthrough_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_monitor();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction: set_passthrough_mode
|
||||
|
||||
/*
|
||||
Function: set_master_mode
|
||||
Sets AXI VIP passthrough into run time master mode
|
||||
*/
|
||||
function void set_master_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 1;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_master();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
|
||||
end
|
||||
endfunction : set_master_mode
|
||||
|
||||
/*
|
||||
Function: set_slave_mode
|
||||
Sets AXI VIP passthrough into run time slave mode
|
||||
*/
|
||||
function void set_slave_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 1;
|
||||
IF.set_intf_slave();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction : set_slave_mode
|
||||
|
||||
/*
|
||||
Function: set_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 1
|
||||
*/
|
||||
function void set_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 1;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: clr_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 0
|
||||
*/
|
||||
function void clr_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 0;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_aw_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_aw_wait_cycles = new_num;
|
||||
endfunction : set_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_ar_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_ar_wait_cycles = new_num;
|
||||
endfunction : set_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_r_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_r_wait_cycles = new_num;
|
||||
endfunction : set_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_b_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_b_wait_cycles = new_num;
|
||||
endfunction : set_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_w_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_w_wait_cycles = new_num;
|
||||
endfunction : set_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlast_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
|
||||
endfunction : set_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_rtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlcmd_wait_cycles = new_num;
|
||||
endfunction : set_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_aw_wait_cycles();
|
||||
return(IF.PC.max_aw_wait_cycles);
|
||||
endfunction : get_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_ar_wait_cycles();
|
||||
return(IF.PC.max_ar_wait_cycles);
|
||||
endfunction : get_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_r_wait_cycles();
|
||||
return(IF.PC.max_r_wait_cycles);
|
||||
endfunction : get_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_b_wait_cycles();
|
||||
return(IF.PC.max_b_wait_cycles);
|
||||
endfunction : get_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_w_wait_cycles();
|
||||
return(IF.PC.max_w_wait_cycles);
|
||||
endfunction :get_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlast_wait_cycles();
|
||||
return(IF.PC.max_wlast_to_awvalid_wait_cycles);
|
||||
endfunction :get_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_rtransfers_wait_cycles();
|
||||
return(IF.PC.max_rtransfers_wait_cycles);
|
||||
endfunction :get_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wtransfers_wait_cycles();
|
||||
return(IF.PC.max_wtransfers_wait_cycles);
|
||||
endfunction :get_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlcmd_wait_cycles();
|
||||
return(IF.PC.max_wlcmd_wait_cycles);
|
||||
endfunction :get_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
|
||||
*/
|
||||
function void set_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 1;
|
||||
endfunction : set_fatal_to_warnings
|
||||
|
||||
/*
|
||||
Function: clr_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
|
||||
*/
|
||||
function void clr_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 0;
|
||||
endfunction : clr_fatal_to_warnings
|
||||
//synthesis translate_on
|
||||
|
||||
endmodule // axi_vip_v1_1_14_top
|
||||
|
||||
|
||||
@@ -0,0 +1,340 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 18:33:02 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=4,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
|
||||
end design_1;
|
||||
|
||||
architecture STRUCTURE of design_1 is
|
||||
component design_1_axi_vip_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axi_vip_0_0;
|
||||
component design_1_axi_read_generator_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
TRIGGER : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axi_read_generator_0_0;
|
||||
component design_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component design_1_clk_rst_generator_0_0;
|
||||
component design_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axil_master_with_rom_0_0;
|
||||
signal axi_read_generator_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_WID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axi_read_generator_0_TRIGGER_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
begin
|
||||
axi_read_generator_0: component design_1_axi_read_generator_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => axi_read_generator_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => axi_read_generator_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => axi_read_generator_0_M_AXI_ARCACHE(3 downto 0),
|
||||
M_AXI_ARID(3 downto 0) => axi_read_generator_0_M_AXI_ARID(3 downto 0),
|
||||
M_AXI_ARLEN(3 downto 0) => axi_read_generator_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => axi_read_generator_0_M_AXI_ARPROT(2 downto 0),
|
||||
M_AXI_ARREADY => axi_read_generator_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => axi_read_generator_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => axi_read_generator_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => axi_read_generator_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => axi_read_generator_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => axi_read_generator_0_M_AXI_AWCACHE(3 downto 0),
|
||||
M_AXI_AWID(3 downto 0) => axi_read_generator_0_M_AXI_AWID(3 downto 0),
|
||||
M_AXI_AWLEN(3 downto 0) => axi_read_generator_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => axi_read_generator_0_M_AXI_AWPROT(2 downto 0),
|
||||
M_AXI_AWREADY => axi_read_generator_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => axi_read_generator_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => axi_read_generator_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(3 downto 0) => axi_read_generator_0_M_AXI_BID(3 downto 0),
|
||||
M_AXI_BREADY => axi_read_generator_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => axi_read_generator_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => axi_read_generator_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => axi_read_generator_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(3 downto 0) => axi_read_generator_0_M_AXI_RID(3 downto 0),
|
||||
M_AXI_RLAST => axi_read_generator_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => axi_read_generator_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => axi_read_generator_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => axi_read_generator_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => axi_read_generator_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(3 downto 0) => axi_read_generator_0_M_AXI_WID(3 downto 0),
|
||||
M_AXI_WLAST => axi_read_generator_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => axi_read_generator_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => axi_read_generator_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => axi_read_generator_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXIL_ARADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(14 downto 0),
|
||||
S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_AWADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(14 downto 0),
|
||||
S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
TRIGGER => NLW_axi_read_generator_0_TRIGGER_UNCONNECTED
|
||||
);
|
||||
axi_vip_0: component design_1_axi_vip_0_0
|
||||
port map (
|
||||
aclk => clk_rst_generator_0_clk,
|
||||
aresetn => clk_rst_generator_0_rst_n,
|
||||
s_axi_araddr(31 downto 0) => axi_read_generator_0_M_AXI_ARADDR(31 downto 0),
|
||||
s_axi_arburst(1 downto 0) => axi_read_generator_0_M_AXI_ARBURST(1 downto 0),
|
||||
s_axi_arcache(3 downto 0) => axi_read_generator_0_M_AXI_ARCACHE(3 downto 0),
|
||||
s_axi_arid(3 downto 0) => axi_read_generator_0_M_AXI_ARID(3 downto 0),
|
||||
s_axi_arlen(3 downto 0) => axi_read_generator_0_M_AXI_ARLEN(3 downto 0),
|
||||
s_axi_arprot(2 downto 0) => axi_read_generator_0_M_AXI_ARPROT(2 downto 0),
|
||||
s_axi_arready => axi_read_generator_0_M_AXI_ARREADY,
|
||||
s_axi_arsize(2 downto 0) => axi_read_generator_0_M_AXI_ARSIZE(2 downto 0),
|
||||
s_axi_arvalid => axi_read_generator_0_M_AXI_ARVALID,
|
||||
s_axi_awaddr(31 downto 0) => axi_read_generator_0_M_AXI_AWADDR(31 downto 0),
|
||||
s_axi_awburst(1 downto 0) => axi_read_generator_0_M_AXI_AWBURST(1 downto 0),
|
||||
s_axi_awcache(3 downto 0) => axi_read_generator_0_M_AXI_AWCACHE(3 downto 0),
|
||||
s_axi_awid(3 downto 0) => axi_read_generator_0_M_AXI_AWID(3 downto 0),
|
||||
s_axi_awlen(3 downto 0) => axi_read_generator_0_M_AXI_AWLEN(3 downto 0),
|
||||
s_axi_awprot(2 downto 0) => axi_read_generator_0_M_AXI_AWPROT(2 downto 0),
|
||||
s_axi_awready => axi_read_generator_0_M_AXI_AWREADY,
|
||||
s_axi_awsize(2 downto 0) => axi_read_generator_0_M_AXI_AWSIZE(2 downto 0),
|
||||
s_axi_awvalid => axi_read_generator_0_M_AXI_AWVALID,
|
||||
s_axi_bid(3 downto 0) => axi_read_generator_0_M_AXI_BID(3 downto 0),
|
||||
s_axi_bready => axi_read_generator_0_M_AXI_BREADY,
|
||||
s_axi_bresp(1 downto 0) => axi_read_generator_0_M_AXI_BRESP(1 downto 0),
|
||||
s_axi_bvalid => axi_read_generator_0_M_AXI_BVALID,
|
||||
s_axi_rdata(31 downto 0) => axi_read_generator_0_M_AXI_RDATA(31 downto 0),
|
||||
s_axi_rid(3 downto 0) => axi_read_generator_0_M_AXI_RID(3 downto 0),
|
||||
s_axi_rlast => axi_read_generator_0_M_AXI_RLAST,
|
||||
s_axi_rready => axi_read_generator_0_M_AXI_RREADY,
|
||||
s_axi_rresp(1 downto 0) => axi_read_generator_0_M_AXI_RRESP(1 downto 0),
|
||||
s_axi_rvalid => axi_read_generator_0_M_AXI_RVALID,
|
||||
s_axi_wdata(31 downto 0) => axi_read_generator_0_M_AXI_WDATA(31 downto 0),
|
||||
s_axi_wid(3 downto 0) => axi_read_generator_0_M_AXI_WID(3 downto 0),
|
||||
s_axi_wlast => axi_read_generator_0_M_AXI_WLAST,
|
||||
s_axi_wready => axi_read_generator_0_M_AXI_WREADY,
|
||||
s_axi_wstrb(3 downto 0) => axi_read_generator_0_M_AXI_WSTRB(3 downto 0),
|
||||
s_axi_wvalid => axi_read_generator_0_M_AXI_WVALID
|
||||
);
|
||||
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component design_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,340 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 18:33:02 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=4,numReposBlks=4,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
|
||||
end design_1;
|
||||
|
||||
architecture STRUCTURE of design_1 is
|
||||
component design_1_axi_vip_0_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axi_vip_0_0;
|
||||
component design_1_axi_read_generator_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
TRIGGER : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axi_read_generator_0_0;
|
||||
component design_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component design_1_clk_rst_generator_0_0;
|
||||
component design_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axil_master_with_rom_0_0;
|
||||
signal axi_read_generator_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_WID : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal axi_read_generator_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axi_read_generator_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axi_read_generator_0_TRIGGER_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
begin
|
||||
axi_read_generator_0: component design_1_axi_read_generator_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => axi_read_generator_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => axi_read_generator_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => axi_read_generator_0_M_AXI_ARCACHE(3 downto 0),
|
||||
M_AXI_ARID(3 downto 0) => axi_read_generator_0_M_AXI_ARID(3 downto 0),
|
||||
M_AXI_ARLEN(3 downto 0) => axi_read_generator_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => axi_read_generator_0_M_AXI_ARPROT(2 downto 0),
|
||||
M_AXI_ARREADY => axi_read_generator_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => axi_read_generator_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => axi_read_generator_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => axi_read_generator_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => axi_read_generator_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => axi_read_generator_0_M_AXI_AWCACHE(3 downto 0),
|
||||
M_AXI_AWID(3 downto 0) => axi_read_generator_0_M_AXI_AWID(3 downto 0),
|
||||
M_AXI_AWLEN(3 downto 0) => axi_read_generator_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => axi_read_generator_0_M_AXI_AWPROT(2 downto 0),
|
||||
M_AXI_AWREADY => axi_read_generator_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => axi_read_generator_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => axi_read_generator_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(3 downto 0) => axi_read_generator_0_M_AXI_BID(3 downto 0),
|
||||
M_AXI_BREADY => axi_read_generator_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => axi_read_generator_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => axi_read_generator_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => axi_read_generator_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(3 downto 0) => axi_read_generator_0_M_AXI_RID(3 downto 0),
|
||||
M_AXI_RLAST => axi_read_generator_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => axi_read_generator_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => axi_read_generator_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => axi_read_generator_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => axi_read_generator_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(3 downto 0) => axi_read_generator_0_M_AXI_WID(3 downto 0),
|
||||
M_AXI_WLAST => axi_read_generator_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => axi_read_generator_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => axi_read_generator_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => axi_read_generator_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXIL_ARADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(14 downto 0),
|
||||
S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_AWADDR(14 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(14 downto 0),
|
||||
S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
TRIGGER => NLW_axi_read_generator_0_TRIGGER_UNCONNECTED
|
||||
);
|
||||
axi_vip_0: component design_1_axi_vip_0_0
|
||||
port map (
|
||||
aclk => clk_rst_generator_0_clk,
|
||||
aresetn => clk_rst_generator_0_rst_n,
|
||||
s_axi_araddr(31 downto 0) => axi_read_generator_0_M_AXI_ARADDR(31 downto 0),
|
||||
s_axi_arburst(1 downto 0) => axi_read_generator_0_M_AXI_ARBURST(1 downto 0),
|
||||
s_axi_arcache(3 downto 0) => axi_read_generator_0_M_AXI_ARCACHE(3 downto 0),
|
||||
s_axi_arid(3 downto 0) => axi_read_generator_0_M_AXI_ARID(3 downto 0),
|
||||
s_axi_arlen(3 downto 0) => axi_read_generator_0_M_AXI_ARLEN(3 downto 0),
|
||||
s_axi_arprot(2 downto 0) => axi_read_generator_0_M_AXI_ARPROT(2 downto 0),
|
||||
s_axi_arready => axi_read_generator_0_M_AXI_ARREADY,
|
||||
s_axi_arsize(2 downto 0) => axi_read_generator_0_M_AXI_ARSIZE(2 downto 0),
|
||||
s_axi_arvalid => axi_read_generator_0_M_AXI_ARVALID,
|
||||
s_axi_awaddr(31 downto 0) => axi_read_generator_0_M_AXI_AWADDR(31 downto 0),
|
||||
s_axi_awburst(1 downto 0) => axi_read_generator_0_M_AXI_AWBURST(1 downto 0),
|
||||
s_axi_awcache(3 downto 0) => axi_read_generator_0_M_AXI_AWCACHE(3 downto 0),
|
||||
s_axi_awid(3 downto 0) => axi_read_generator_0_M_AXI_AWID(3 downto 0),
|
||||
s_axi_awlen(3 downto 0) => axi_read_generator_0_M_AXI_AWLEN(3 downto 0),
|
||||
s_axi_awprot(2 downto 0) => axi_read_generator_0_M_AXI_AWPROT(2 downto 0),
|
||||
s_axi_awready => axi_read_generator_0_M_AXI_AWREADY,
|
||||
s_axi_awsize(2 downto 0) => axi_read_generator_0_M_AXI_AWSIZE(2 downto 0),
|
||||
s_axi_awvalid => axi_read_generator_0_M_AXI_AWVALID,
|
||||
s_axi_bid(3 downto 0) => axi_read_generator_0_M_AXI_BID(3 downto 0),
|
||||
s_axi_bready => axi_read_generator_0_M_AXI_BREADY,
|
||||
s_axi_bresp(1 downto 0) => axi_read_generator_0_M_AXI_BRESP(1 downto 0),
|
||||
s_axi_bvalid => axi_read_generator_0_M_AXI_BVALID,
|
||||
s_axi_rdata(31 downto 0) => axi_read_generator_0_M_AXI_RDATA(31 downto 0),
|
||||
s_axi_rid(3 downto 0) => axi_read_generator_0_M_AXI_RID(3 downto 0),
|
||||
s_axi_rlast => axi_read_generator_0_M_AXI_RLAST,
|
||||
s_axi_rready => axi_read_generator_0_M_AXI_RREADY,
|
||||
s_axi_rresp(1 downto 0) => axi_read_generator_0_M_AXI_RRESP(1 downto 0),
|
||||
s_axi_rvalid => axi_read_generator_0_M_AXI_RVALID,
|
||||
s_axi_wdata(31 downto 0) => axi_read_generator_0_M_AXI_WDATA(31 downto 0),
|
||||
s_axi_wid(3 downto 0) => axi_read_generator_0_M_AXI_WID(3 downto 0),
|
||||
s_axi_wlast => axi_read_generator_0_M_AXI_WLAST,
|
||||
s_axi_wready => axi_read_generator_0_M_AXI_WREADY,
|
||||
s_axi_wstrb(3 downto 0) => axi_read_generator_0_M_AXI_WSTRB(3 downto 0),
|
||||
s_axi_wvalid => axi_read_generator_0_M_AXI_WVALID
|
||||
);
|
||||
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component design_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
+1231
File diff suppressed because it is too large
Load Diff
+70
@@ -0,0 +1,70 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "BRAM_AWIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BRAM_AWIDTH { PARAM_VALUE.BRAM_AWIDTH } {
|
||||
# Procedure called to update BRAM_AWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BRAM_AWIDTH { PARAM_VALUE.BRAM_AWIDTH } {
|
||||
# Procedure called to validate BRAM_AWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to validate DWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
|
||||
# Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
|
||||
# Procedure called to validate IDWIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
|
||||
# Procedure called to update MAX_BURSTLEN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
|
||||
# Procedure called to validate MAX_BURSTLEN
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IDWIDTH { MODELPARAM_VALUE.IDWIDTH PARAM_VALUE.IDWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IDWIDTH}] ${MODELPARAM_VALUE.IDWIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_VALUE.MAX_BURSTLEN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BRAM_AWIDTH { MODELPARAM_VALUE.BRAM_AWIDTH PARAM_VALUE.BRAM_AWIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BRAM_AWIDTH}] ${MODELPARAM_VALUE.BRAM_AWIDTH}
|
||||
}
|
||||
|
||||
+250
@@ -0,0 +1,250 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>crc_axi_master_sim_control</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_control</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>03f1f25e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_control</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>03f1f25e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>start</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>write</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>addr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>size</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>axi_idle</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/crc_axi_master_sim_control_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master_sim_control:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">crc_axi_master_sim_control_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>crc_axi_master_sim_control_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-01-28T21:07:12Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>crc_axi_ram</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>crc_axi_ram</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>7bc1562c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>crc_axi_ram</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>7bc1562c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>waddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AW')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>wdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>we</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>raddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.AW')) - 1)">3</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>re</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>AW</spirit:name>
|
||||
<spirit:displayName>Aw</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AW" spirit:minimum="0">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH" spirit:minimum="0">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/crc_axi_ram_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_25384380</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_ram:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>AW</spirit:name>
|
||||
<spirit:displayName>Aw</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.AW" spirit:minimum="0" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">crc_axi_ram_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>crc_axi_ram_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-01-28T18:09:58Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "AW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AW { PARAM_VALUE.AW } {
|
||||
# Procedure called to update AW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AW { PARAM_VALUE.AW } {
|
||||
# Procedure called to validate AW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.AW { MODELPARAM_VALUE.AW PARAM_VALUE.AW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AW}] ${MODELPARAM_VALUE.AW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
+610
@@ -0,0 +1,610 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim",
|
||||
"name": "crc_axi_master_sim",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axi_vip_0": "",
|
||||
"clk_rst_generator_0": "",
|
||||
"crc_axi_ram_0": "",
|
||||
"crc_axi_master_sim_c_0": "",
|
||||
"crc_axi_master_0": ""
|
||||
},
|
||||
"components": {
|
||||
"axi_vip_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_vip:1.1",
|
||||
"xci_name": "crc_axi_master_sim_axi_vip_0_0",
|
||||
"xci_path": "ip\\crc_axi_master_sim_axi_vip_0_0\\crc_axi_master_sim_axi_vip_0_0.xci",
|
||||
"inst_hier_path": "axi_vip_0",
|
||||
"parameters": {
|
||||
"INTERFACE_MODE": {
|
||||
"value": "SLAVE"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI3"
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "crc_axi_master_sim_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\crc_axi_master_sim_clk_rst_generator_0_0\\crc_axi_master_sim_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0"
|
||||
},
|
||||
"crc_axi_ram_0": {
|
||||
"vlnv": "xilinx.com:module_ref:crc_axi_ram:1.0",
|
||||
"xci_name": "crc_axi_master_sim_crc_axi_ram_0_0",
|
||||
"xci_path": "ip\\crc_axi_master_sim_crc_axi_ram_0_0\\crc_axi_master_sim_crc_axi_ram_0_0.xci",
|
||||
"inst_hier_path": "crc_axi_ram_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "crc_axi_ram",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"type": "clk",
|
||||
"direction": "I"
|
||||
},
|
||||
"waddr": {
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"wdata": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"we": {
|
||||
"direction": "I"
|
||||
},
|
||||
"raddr": {
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"rdata": {
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"re": {
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"crc_axi_master_sim_c_0": {
|
||||
"vlnv": "xilinx.com:module_ref:crc_axi_master_sim_control:1.0",
|
||||
"xci_name": "crc_axi_master_sim_crc_axi_master_sim_c_0_0",
|
||||
"xci_path": "ip\\crc_axi_master_sim_crc_axi_master_sim_c_0_0\\crc_axi_master_sim_crc_axi_master_sim_c_0_0.xci",
|
||||
"inst_hier_path": "crc_axi_master_sim_c_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "crc_axi_master_sim_control",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "resetn",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"start": {
|
||||
"direction": "O"
|
||||
},
|
||||
"write": {
|
||||
"direction": "O"
|
||||
},
|
||||
"addr": {
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"size": {
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"axi_idle": {
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"crc_axi_master_0": {
|
||||
"vlnv": "xilinx.com:module_ref:crc_axi_master:1.0",
|
||||
"xci_name": "crc_axi_master_sim_crc_axi_master_0_2",
|
||||
"xci_path": "ip\\crc_axi_master_sim_crc_axi_master_0_2\\crc_axi_master_sim_crc_axi_master_0_2.xci",
|
||||
"inst_hier_path": "crc_axi_master_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "crc_axi_master",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI3",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"ADDR_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "2",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "2",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "16",
|
||||
"value_src": "auto"
|
||||
}
|
||||
},
|
||||
"address_space_ref": "M_AXI",
|
||||
"base_address": {
|
||||
"minimum": "0x00000000",
|
||||
"maximum": "0xFFFFFFFF",
|
||||
"width": "32"
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": {
|
||||
"physical_name": "M_AXI_AWID",
|
||||
"direction": "O",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"AWADDR": {
|
||||
"physical_name": "M_AXI_AWADDR",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"AWLEN": {
|
||||
"physical_name": "M_AXI_AWLEN",
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"AWSIZE": {
|
||||
"physical_name": "M_AXI_AWSIZE",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"AWBURST": {
|
||||
"physical_name": "M_AXI_AWBURST",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"AWCACHE": {
|
||||
"physical_name": "M_AXI_AWCACHE",
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"AWPROT": {
|
||||
"physical_name": "M_AXI_AWPROT",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "M_AXI_AWVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "M_AXI_AWREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"WID": {
|
||||
"physical_name": "M_AXI_WID",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "M_AXI_WDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "M_AXI_WSTRB",
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WLAST": {
|
||||
"physical_name": "M_AXI_WLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "M_AXI_WVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "M_AXI_WREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"BID": {
|
||||
"physical_name": "M_AXI_BID",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "M_AXI_BRESP",
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "M_AXI_BVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "M_AXI_BREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"ARID": {
|
||||
"physical_name": "M_AXI_ARID",
|
||||
"direction": "O",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "M_AXI_ARADDR",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"ARLEN": {
|
||||
"physical_name": "M_AXI_ARLEN",
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"ARSIZE": {
|
||||
"physical_name": "M_AXI_ARSIZE",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"ARBURST": {
|
||||
"physical_name": "M_AXI_ARBURST",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"ARCACHE": {
|
||||
"physical_name": "M_AXI_ARCACHE",
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"ARPROT": {
|
||||
"physical_name": "M_AXI_ARPROT",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "M_AXI_ARVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "M_AXI_ARREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"RID": {
|
||||
"physical_name": "M_AXI_RID",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "M_AXI_RDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "M_AXI_RRESP",
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RLAST": {
|
||||
"physical_name": "M_AXI_RLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "M_AXI_RVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "M_AXI_RREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXI",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"start": {
|
||||
"direction": "I"
|
||||
},
|
||||
"write": {
|
||||
"direction": "I"
|
||||
},
|
||||
"addr_axi": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"size": {
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"ip_idle": {
|
||||
"direction": "O"
|
||||
},
|
||||
"waddr": {
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"wdata": {
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"we": {
|
||||
"direction": "O"
|
||||
},
|
||||
"raddr": {
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"rdata": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"re": {
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"M_AXI": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"crc_axi_master_0_M_AXI": {
|
||||
"interface_ports": [
|
||||
"crc_axi_master_0/M_AXI",
|
||||
"axi_vip_0/S_AXI"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axi_vip_0/aclk",
|
||||
"crc_axi_ram_0/clk",
|
||||
"crc_axi_master_sim_c_0/clk",
|
||||
"crc_axi_master_0/CLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axi_vip_0/aresetn",
|
||||
"crc_axi_master_sim_c_0/resetn",
|
||||
"crc_axi_master_0/RESETN"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_0_idle": {
|
||||
"ports": [
|
||||
"crc_axi_master_0/ip_idle",
|
||||
"crc_axi_master_sim_c_0/axi_idle"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_0_raddr": {
|
||||
"ports": [
|
||||
"crc_axi_master_0/raddr",
|
||||
"crc_axi_ram_0/raddr"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_0_re": {
|
||||
"ports": [
|
||||
"crc_axi_master_0/re",
|
||||
"crc_axi_ram_0/re"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_0_waddr": {
|
||||
"ports": [
|
||||
"crc_axi_master_0/waddr",
|
||||
"crc_axi_ram_0/waddr"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_0_wdata": {
|
||||
"ports": [
|
||||
"crc_axi_master_0/wdata",
|
||||
"crc_axi_ram_0/wdata"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_0_we": {
|
||||
"ports": [
|
||||
"crc_axi_master_0/we",
|
||||
"crc_axi_ram_0/we"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_sim_c_0_addr": {
|
||||
"ports": [
|
||||
"crc_axi_master_sim_c_0/addr",
|
||||
"crc_axi_master_0/addr_axi"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_sim_c_0_size": {
|
||||
"ports": [
|
||||
"crc_axi_master_sim_c_0/size",
|
||||
"crc_axi_master_0/size"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_sim_c_0_start": {
|
||||
"ports": [
|
||||
"crc_axi_master_sim_c_0/start",
|
||||
"crc_axi_master_0/start"
|
||||
]
|
||||
},
|
||||
"crc_axi_master_sim_c_0_write": {
|
||||
"ports": [
|
||||
"crc_axi_master_sim_c_0/write",
|
||||
"crc_axi_master_0/write"
|
||||
]
|
||||
},
|
||||
"crc_axi_ram_0_rdata": {
|
||||
"ports": [
|
||||
"crc_axi_ram_0/rdata",
|
||||
"crc_axi_master_0/rdata"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+249
@@ -0,0 +1,249 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "crc_axi_master_sim_axi_vip_0_0",
|
||||
"cell_name": "axi_vip_0",
|
||||
"component_reference": "xilinx.com:ip:axi_vip:1.1",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi_vip_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "crc_axi_master_sim_axi_vip_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_MODE": [ { "value": "SLAVE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_USER_BITS_PER_BYTE": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"VIP_PKG_NAME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_INTERFACE_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_NARROW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_LOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_CACHE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_REGION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_QOS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_axi_vip_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WID": [ { "physical_name": "s_axi_wid" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"RESET": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLOCK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "65536",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "crc_axi_master_sim_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "crc_axi_master_sim_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"rst_in": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+213
@@ -0,0 +1,213 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "crc_axi_master_sim_crc_axi_master_0_2",
|
||||
"cell_name": "crc_axi_master_0",
|
||||
"component_reference": "xilinx.com:module_ref:crc_axi_master:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IDWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MAX_BURSTLEN": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BRAM_AWIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "crc_axi_master_sim_crc_axi_master_0_2", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IDWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MAX_BURSTLEN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BRAM_AWIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_0_2" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in" } ],
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"start": [ { "direction": "in" } ],
|
||||
"write": [ { "direction": "in" } ],
|
||||
"addr_axi": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"size": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
|
||||
"ip_idle": [ { "direction": "out" } ],
|
||||
"waddr": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"we": [ { "direction": "out" } ],
|
||||
"raddr": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"rdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"re": [ { "direction": "out" } ],
|
||||
"M_AXI_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_ARID": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"M_AXI_ARLEN": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_ARSIZE": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_ARBURST": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_ARCACHE": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXI_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_RID": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_RLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_AWREADY": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXI_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_AWLEN": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_AWSIZE": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_AWID": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||
"M_AXI_AWBURST": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_AWCACHE": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_WREADY": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXI_WVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_WLAST": [ { "direction": "out" } ],
|
||||
"M_AXI_WID": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_BREADY": [ { "direction": "out" } ],
|
||||
"M_AXI_BVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXI_BID": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "M_AXI_AWID" } ],
|
||||
"AWADDR": [ { "physical_name": "M_AXI_AWADDR" } ],
|
||||
"AWLEN": [ { "physical_name": "M_AXI_AWLEN" } ],
|
||||
"AWSIZE": [ { "physical_name": "M_AXI_AWSIZE" } ],
|
||||
"AWBURST": [ { "physical_name": "M_AXI_AWBURST" } ],
|
||||
"AWCACHE": [ { "physical_name": "M_AXI_AWCACHE" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXI_AWPROT" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXI_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXI_AWREADY" } ],
|
||||
"WID": [ { "physical_name": "M_AXI_WID" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXI_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXI_WSTRB" } ],
|
||||
"WLAST": [ { "physical_name": "M_AXI_WLAST" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXI_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXI_WREADY" } ],
|
||||
"BID": [ { "physical_name": "M_AXI_BID" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXI_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXI_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXI_BREADY" } ],
|
||||
"ARID": [ { "physical_name": "M_AXI_ARID" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXI_ARADDR" } ],
|
||||
"ARLEN": [ { "physical_name": "M_AXI_ARLEN" } ],
|
||||
"ARSIZE": [ { "physical_name": "M_AXI_ARSIZE" } ],
|
||||
"ARBURST": [ { "physical_name": "M_AXI_ARBURST" } ],
|
||||
"ARCACHE": [ { "physical_name": "M_AXI_ARCACHE" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXI_ARPROT" } ],
|
||||
"ARVALID": [ { "physical_name": "M_AXI_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXI_ARREADY" } ],
|
||||
"RID": [ { "physical_name": "M_AXI_RID" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXI_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXI_RRESP" } ],
|
||||
"RLAST": [ { "physical_name": "M_AXI_RLAST" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXI_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXI_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "RESETN" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"M_AXI": {
|
||||
"range": "0x100000000",
|
||||
"display_name": "M_AXI",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "crc_axi_master_sim_crc_axi_master_sim_c_0_0",
|
||||
"cell_name": "crc_axi_master_sim_c_0",
|
||||
"component_reference": "xilinx.com:module_ref:crc_axi_master_sim_control:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_sim_c_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "crc_axi_master_sim_crc_axi_master_sim_c_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_master_sim_c_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"start": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"write": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"addr": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"size": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"axi_idle": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"resetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+75
@@ -0,0 +1,75 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "crc_axi_master_sim_crc_axi_ram_0_0",
|
||||
"cell_name": "crc_axi_ram_0",
|
||||
"component_reference": "xilinx.com:module_ref:crc_axi_ram:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_ram_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"AW": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "crc_axi_master_sim_crc_axi_ram_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"AW": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/crc_axi_master/bd/crc_axi_master_sim/ip/crc_axi_master_sim_crc_axi_ram_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"waddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"wdata": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"we": [ { "direction": "in" } ],
|
||||
"raddr": [ { "direction": "in", "size_left": "3", "size_right": "0" } ],
|
||||
"rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"re": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.88425",
|
||||
"Default View_TopLeft":"-7,0",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axi_vip_0 -pg 1 -lvl 4 -x 970 -y 120 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 160 -defaultsOSRD
|
||||
preplace inst crc_axi_ram_0 -pg 1 -lvl 2 -x 420 -y 420 -defaultsOSRD
|
||||
preplace inst crc_axi_master_sim_c_0 -pg 1 -lvl 2 -x 420 -y 170 -defaultsOSRD
|
||||
preplace inst crc_axi_master_0 -pg 1 -lvl 3 -x 700 -y 160 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 240 80 570 30 870J
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 230 260 560 40 860J
|
||||
preplace netloc crc_axi_ram_0_rdata 1 2 1 570 220n
|
||||
preplace netloc crc_axi_master_0_re 1 1 3 280 300 NJ 300 840
|
||||
preplace netloc crc_axi_master_0_raddr 1 1 3 250 280 NJ 280 830
|
||||
preplace netloc crc_axi_master_0_we 1 1 3 260 20 NJ 20 850
|
||||
preplace netloc crc_axi_master_0_wdata 1 1 3 290 310 NJ 310 870
|
||||
preplace netloc crc_axi_master_0_waddr 1 1 3 270 290 NJ 290 860
|
||||
preplace netloc crc_axi_master_0_idle 1 1 3 250 10 NJ 10 830
|
||||
preplace netloc crc_axi_master_sim_c_0_start 1 2 1 N 140
|
||||
preplace netloc crc_axi_master_sim_c_0_write 1 2 1 N 160
|
||||
preplace netloc crc_axi_master_sim_c_0_addr 1 2 1 N 180
|
||||
preplace netloc crc_axi_master_sim_c_0_size 1 2 1 N 200
|
||||
preplace netloc crc_axi_master_0_M_AXI 1 3 1 N 100
|
||||
levelinfo -pg 1 0 110 420 700 970 1060
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1060 530
|
||||
"
|
||||
}
|
||||
|
||||
@@ -0,0 +1,196 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../crc_axi_master.gen/sources_1/bd/design_1",
|
||||
"name": "design_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axi_vip_0": "",
|
||||
"axi_read_generator_0": "",
|
||||
"clk_rst_generator_0": "",
|
||||
"axil_master_with_rom_0": ""
|
||||
},
|
||||
"components": {
|
||||
"axi_vip_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_vip:1.1",
|
||||
"xci_name": "design_1_axi_vip_0_0",
|
||||
"xci_path": "ip\\design_1_axi_vip_0_0\\design_1_axi_vip_0_0.xci",
|
||||
"inst_hier_path": "axi_vip_0",
|
||||
"parameters": {
|
||||
"ADDR_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"INTERFACE_MODE": {
|
||||
"value": "SLAVE"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI3"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_read_generator_0": {
|
||||
"vlnv": "xilinx.com:user:axi_read_generator:1.0",
|
||||
"xci_name": "design_1_axi_read_generator_0_0",
|
||||
"xci_path": "ip\\design_1_axi_read_generator_0_0\\design_1_axi_read_generator_0_0.xci",
|
||||
"inst_hier_path": "axi_read_generator_0",
|
||||
"parameters": {
|
||||
"DEFAULT_RUN": {
|
||||
"value": "true"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "M_AXI",
|
||||
"base_address": {
|
||||
"minimum": "0x00000000",
|
||||
"maximum": "0xFFFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"M_AXI": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0",
|
||||
"parameters": {
|
||||
"CLOCK_PERIOD": {
|
||||
"value": "8000"
|
||||
},
|
||||
"HAS_CLK_INPUT": {
|
||||
"value": "true"
|
||||
},
|
||||
"HAS_RESET_INPUT": {
|
||||
"value": "true"
|
||||
},
|
||||
"HAS_STOP_INPUT": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axil_master_with_rom_0": {
|
||||
"vlnv": "wg:user:axil_master_with_rom:1.0",
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
|
||||
"inst_hier_path": "axil_master_with_rom_0",
|
||||
"parameters": {
|
||||
"HAS_FINISHED_OUT": {
|
||||
"value": "false"
|
||||
},
|
||||
"HAS_INTERRUPT_IN": {
|
||||
"value": "false"
|
||||
},
|
||||
"REVISION_NO": {
|
||||
"value": "4"
|
||||
},
|
||||
"STIM_FILENAME": {
|
||||
"value": "../../axi_verification_tb_test.mem"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"base_address": {
|
||||
"minimum": "0x00000000",
|
||||
"maximum": "0xFFFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axi_read_generator_0_M_AXI": {
|
||||
"interface_ports": [
|
||||
"axi_read_generator_0/M_AXI",
|
||||
"axi_vip_0/S_AXI"
|
||||
]
|
||||
},
|
||||
"axil_master_with_rom_0_M_AXIL": {
|
||||
"interface_ports": [
|
||||
"axil_master_with_rom_0/M_AXIL",
|
||||
"axi_read_generator_0/S_AXIL"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axi_read_generator_0/CLK",
|
||||
"axi_vip_0/aclk",
|
||||
"axil_master_with_rom_0/M_AXIL_ACLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axi_vip_0/aresetn",
|
||||
"axi_read_generator_0/RESETN",
|
||||
"axil_master_with_rom_0/M_AXIL_ARESETN"
|
||||
]
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"/axi_read_generator_0": {
|
||||
"address_spaces": {
|
||||
"M_AXI": {
|
||||
"segments": {
|
||||
"SEG_axi_vip_0_Reg": {
|
||||
"address_block": "/axi_vip_0/S_AXI/Reg",
|
||||
"offset": "0x44A00000",
|
||||
"range": "64K"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"/axil_master_with_rom_0": {
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"segments": {
|
||||
"SEG_axi_read_generator_0_reg0": {
|
||||
"address_block": "/axi_read_generator_0/S_AXIL/reg0",
|
||||
"offset": "0x44A00000",
|
||||
"range": "64K"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+296
@@ -0,0 +1,296 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axi_read_generator_0_0",
|
||||
"cell_name": "axi_read_generator_0",
|
||||
"component_reference": "xilinx.com:user:axi_read_generator:1.0",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_MEMADDR": [ { "value": "268435456", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_BURSTLEN": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_REQ_PAUSE": [ { "value": "1000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_RUN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEFAULT_PIPELINING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DEFAULT_ARCACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axi_read_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_MEMADDR": [ { "value": "268435456", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_BURSTLEN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_REQ_PAUSE": [ { "value": "1000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_RUN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"DEFAULT_PIPELINING": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"DEFAULT_ARCACHE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "10" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in" } ],
|
||||
"RESETN": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"TRIGGER": [ { "direction": "out" } ],
|
||||
"M_AXI_ARREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"M_AXI_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_ARID": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_ARLEN": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_ARSIZE": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_ARBURST": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_ARCACHE": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXI_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_RID": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_RLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_AWREADY": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXI_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_AWLEN": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_AWSIZE": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_AWID": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_AWBURST": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_AWCACHE": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_WREADY": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXI_WVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_WLAST": [ { "direction": "out" } ],
|
||||
"M_AXI_WID": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_BREADY": [ { "direction": "out" } ],
|
||||
"M_AXI_BVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXI_BID": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIL_AWREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIL_WREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_BVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIL_ARADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIL_ARREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIL_RVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "M_AXI_AWID" } ],
|
||||
"AWADDR": [ { "physical_name": "M_AXI_AWADDR" } ],
|
||||
"AWLEN": [ { "physical_name": "M_AXI_AWLEN" } ],
|
||||
"AWSIZE": [ { "physical_name": "M_AXI_AWSIZE" } ],
|
||||
"AWBURST": [ { "physical_name": "M_AXI_AWBURST" } ],
|
||||
"AWCACHE": [ { "physical_name": "M_AXI_AWCACHE" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXI_AWPROT" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXI_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXI_AWREADY" } ],
|
||||
"WID": [ { "physical_name": "M_AXI_WID" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXI_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXI_WSTRB" } ],
|
||||
"WLAST": [ { "physical_name": "M_AXI_WLAST" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXI_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXI_WREADY" } ],
|
||||
"BID": [ { "physical_name": "M_AXI_BID" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXI_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXI_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXI_BREADY" } ],
|
||||
"ARID": [ { "physical_name": "M_AXI_ARID" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXI_ARADDR" } ],
|
||||
"ARLEN": [ { "physical_name": "M_AXI_ARLEN" } ],
|
||||
"ARSIZE": [ { "physical_name": "M_AXI_ARSIZE" } ],
|
||||
"ARBURST": [ { "physical_name": "M_AXI_ARBURST" } ],
|
||||
"ARCACHE": [ { "physical_name": "M_AXI_ARCACHE" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXI_ARPROT" } ],
|
||||
"ARVALID": [ { "physical_name": "M_AXI_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXI_ARREADY" } ],
|
||||
"RID": [ { "physical_name": "M_AXI_RID" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXI_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXI_RRESP" } ],
|
||||
"RLAST": [ { "physical_name": "M_AXI_RLAST" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXI_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXI_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
|
||||
"AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
|
||||
"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "RESETN" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"M_AXI": {
|
||||
"range": "4294967296",
|
||||
"width": "32"
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0",
|
||||
"range": "32768",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+249
@@ -0,0 +1,249 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axi_vip_0_0",
|
||||
"cell_name": "axi_vip_0",
|
||||
"component_reference": "xilinx.com:ip:axi_vip:1.1",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "design_1_axi_vip_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_MODE": [ { "value": "SLAVE", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_USER_BITS_PER_BYTE": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SUPPORTS_NARROW": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"VIP_PKG_NAME": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_INTERFACE_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_NARROW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_BURST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_LOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_CACHE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_REGION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_QOS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_HAS_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axi_vip_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WID": [ { "physical_name": "s_axi_wid" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"RESET": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"CLOCK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "65536",
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+172
@@ -0,0 +1,172 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"cell_name": "axil_master_with_rom_0",
|
||||
"component_reference": "wg:user:axil_master_with_rom:1.0",
|
||||
"ip_revision": "19",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../axi_verification_tb_test.mem", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../axi_verification_tb_test.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"M_AXIL_ACLK": [ { "direction": "in" } ],
|
||||
"M_AXIL_ARESETN": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIL_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIL_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIL_AWREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_WREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_WVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXIL_BREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_BVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M_AXIL_AWADDR" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXIL_AWPROT" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXIL_ARADDR" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXIL_ARPROT" } ],
|
||||
"ARVALID": [ { "physical_name": "M_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "M_AXIL_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "M_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "M_AXIL_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "0x100000000",
|
||||
"display_name": "M_AXIL",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "8000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "8000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../crc_axi_master.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"rst_in": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.08124",
|
||||
"Default View_TopLeft":"-260,-132",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axi_vip_0 -pg 1 -lvl 4 -x 540 -y 100 -defaultsOSRD
|
||||
preplace inst axi_read_generator_0 -pg 1 -lvl 3 -x 320 -y 80 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -160 -y 90 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 80 -y 70 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 -50 0 220J 0 430
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 -40J 140 210J 160 420
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 200 60n
|
||||
preplace netloc axi_read_generator_0_M_AXI 1 3 1 420 70n
|
||||
levelinfo -pg 1 -270 -160 80 320 540 660
|
||||
pagesize -pg 1 -db -bbox -sgen -270 -200 660 190
|
||||
"
|
||||
}
|
||||
|
||||
@@ -0,0 +1,290 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="8ffdb37a47834950a4b8a9ed2ed5c8b9"/>
|
||||
<Option Name="Part" Val="xc7z020clg400-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
|
||||
<Option Name="ActiveSimSet" Val="crc_axi_master"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../IP"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="39"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="13"/>
|
||||
<Option Name="WTModelSimExportSim" Val="13"/>
|
||||
<Option Name="WTQuestaExportSim" Val="13"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="13"/>
|
||||
<Option Name="WTRivieraExportSim" Val="13"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="13"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../crc_axi_master.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../crc_axi_ram.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../crc_axi_master_sim_control.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<File Path="$PPRDIR/design_1_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/design_1_wrapper_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="crc_axi_master" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/crc_axi_master" RelGenDir="$PGENDIR/crc_axi_master">
|
||||
<File Path="$PSRCDIR/crc_axi_master/bd/crc_axi_master_sim/crc_axi_master_sim.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/crc_axi_master/bd/crc_axi_master_sim/hdl/crc_axi_master_sim_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../crc_axi_master_sim_control.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/crc_axi_master_sim_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="crc_axi_master_sim_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/crc_axi_master_sim_wrapper_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="20">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -0,0 +1,65 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="crc_axi_master_sim_wrapper_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="crc_axi_master_sim_wrapper" />
|
||||
<top_module name="glbl" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,290.000 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,290.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="286"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="89"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="8" />
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/clk_rst_generator_0_clk" type="logic">
|
||||
<obj_property name="ElementShortName">clk_rst_generator_0_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk_rst_generator_0_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/clk_rst_generator_0_rst_n" type="logic">
|
||||
<obj_property name="ElementShortName">clk_rst_generator_0_rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">clk_rst_generator_0_rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="divider" fp_name="divider1228">
|
||||
<obj_property name="label">sim control</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_sim_c_0/start" type="logic">
|
||||
<obj_property name="ElementShortName">start</obj_property>
|
||||
<obj_property name="ObjectShortName">start</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_sim_c_0/write" type="logic">
|
||||
<obj_property name="ElementShortName">write</obj_property>
|
||||
<obj_property name="ObjectShortName">write</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_sim_c_0/addr" type="array">
|
||||
<obj_property name="ElementShortName">addr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">addr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_sim_c_0/size" type="array">
|
||||
<obj_property name="ElementShortName">size[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">size[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/M_AXI" type="protoinst">
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">0=blank 1=#D399FF 2=pink</obj_property>
|
||||
<obj_property name="EnumTransactionValueTable">0=blank;1=Read;2=Write;3=Read/Write</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">turquoise</obj_property>
|
||||
<obj_property name="Render_Data">/crc_axi_master_sim_wrapper/crc_axi_master_sim_i/crc_axi_master_0/M_AXI.readWriteSummary</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<obj_property name="CellHeight">36</obj_property>
|
||||
<obj_property name="ElementShortName">M_AXI</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -0,0 +1,171 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="design_1_wrapper_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="design_1_wrapper" />
|
||||
<top_module name="glbl" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,470.597 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,352.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="286"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="94"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="37" />
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/clk_rst_generator_0/clk" type="logic">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/clk_rst_generator_0/rst_n" type="logic">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXIL</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARREADY" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_ARREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARVALID" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_ARVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARADDR" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARADDR[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARADDR[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARID" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARID[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARID[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARLEN" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARLEN[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARLEN[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARSIZE" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARSIZE[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARSIZE[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARBURST" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARBURST[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARBURST[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARPROT" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARPROT[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARPROT[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_ARCACHE" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_ARCACHE[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_ARCACHE[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_RREADY" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_RREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_RREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_RVALID" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_RVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_RVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_RDATA" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_RDATA[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_RDATA[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_RRESP" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_RRESP[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_RRESP[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_RID" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_RID[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_RID[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_RLAST" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_RLAST</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_RLAST</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWREADY" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_AWREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWVALID" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_AWVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWADDR" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWADDR[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWADDR[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWLEN" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWLEN[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWLEN[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWSIZE" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWSIZE[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWSIZE[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWID" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWID[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWID[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWBURST" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWBURST[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWBURST[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWPROT" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWPROT[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWPROT[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_AWCACHE" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_AWCACHE[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_AWCACHE[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_WREADY" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_WREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_WREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_WVALID" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_WVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_WVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_WDATA" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_WDATA[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_WDATA[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_WSTRB" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_WSTRB[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_WSTRB[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_WLAST" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_WLAST</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_WLAST</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_WID" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_WID[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_WID[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_BREADY" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_BREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_BREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_BVALID" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXI_BVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_BVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_BID" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_BID[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_BID[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/design_1_wrapper/design_1_i/axi_read_generator_0/M_AXI_BRESP" type="array">
|
||||
<obj_property name="ElementShortName">M_AXI_BRESP[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI_BRESP[1:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -0,0 +1,42 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity crc_axi_master_sim_control is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic;
|
||||
|
||||
start : out std_logic := '0';
|
||||
write : out std_logic := '0';
|
||||
addr : out std_logic_vector(31 downto 0) := (others=>'0');
|
||||
size : out std_logic_vector(15 downto 0) := (others=>'0');
|
||||
axi_idle : in std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture rtl of crc_axi_master_sim_control is
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(resetn);
|
||||
|
||||
-- Lesevorgang testen
|
||||
report "TESTE LESEVORGANG";
|
||||
start <= '1';
|
||||
write <= '0';
|
||||
addr <= x"30000000"; -- frei verfuegbarer SDRAM Speicher
|
||||
size <= std_logic_vector(to_unsigned(8, 16));
|
||||
|
||||
wait until rising_edge(clk);
|
||||
|
||||
start <= '0';
|
||||
|
||||
wait until rising_edge(axi_idle);
|
||||
report "ALLE TESTFAELLE ABGESCHLOSSEN";
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@@ -0,0 +1,44 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity crc_axi_ram is
|
||||
generic (
|
||||
AW : positive := 4; -- Wortbreite der Adresse, max. 2^AW Worte
|
||||
DATA_WIDTH : positive := 32 -- Laenge eines Datenworts
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
|
||||
-- Leseport
|
||||
waddr : in std_logic_vector(AW-1 downto 0);
|
||||
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
we : in std_logic;
|
||||
|
||||
-- Schreibport
|
||||
raddr : in std_logic_vector(AW-1 downto 0);
|
||||
rdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
re : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture rtl of crc_axi_ram is
|
||||
|
||||
type mem_t is array(0 to 2**AW-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
signal mem : mem_t := (others=>(others=>'0'));
|
||||
|
||||
begin
|
||||
|
||||
process begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
if re = '1' then
|
||||
rdata <= mem(to_integer(unsigned(raddr)));
|
||||
end if;
|
||||
|
||||
if we = '1' then
|
||||
mem(to_integer(unsigned(waddr))) <= wdata;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -2,10 +2,55 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1737799735"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1737799735"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1737799735"/>
|
||||
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1737799735"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738083020"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738083020"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738083020"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738083020"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 6 [get_pins PS/processing_system7_0/FCLK_CLK0]
|
||||
|
||||
################################################################################
|
||||
+92
@@ -0,0 +1,92 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Jan 28 17:50:14 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1_wrapper.bd
|
||||
--Design : design_1_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_wrapper is
|
||||
port (
|
||||
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_cas_n : inout STD_LOGIC;
|
||||
DDR_ck_n : inout STD_LOGIC;
|
||||
DDR_ck_p : inout STD_LOGIC;
|
||||
DDR_cke : inout STD_LOGIC;
|
||||
DDR_cs_n : inout STD_LOGIC;
|
||||
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_odt : inout STD_LOGIC;
|
||||
DDR_ras_n : inout STD_LOGIC;
|
||||
DDR_reset_n : inout STD_LOGIC;
|
||||
DDR_we_n : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrn : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrp : inout STD_LOGIC;
|
||||
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
FIXED_IO_ps_clk : inout STD_LOGIC;
|
||||
FIXED_IO_ps_porb : inout STD_LOGIC;
|
||||
FIXED_IO_ps_srstb : inout STD_LOGIC
|
||||
);
|
||||
end design_1_wrapper;
|
||||
|
||||
architecture STRUCTURE of design_1_wrapper is
|
||||
component design_1 is
|
||||
port (
|
||||
DDR_cas_n : inout STD_LOGIC;
|
||||
DDR_cke : inout STD_LOGIC;
|
||||
DDR_ck_n : inout STD_LOGIC;
|
||||
DDR_ck_p : inout STD_LOGIC;
|
||||
DDR_cs_n : inout STD_LOGIC;
|
||||
DDR_reset_n : inout STD_LOGIC;
|
||||
DDR_odt : inout STD_LOGIC;
|
||||
DDR_ras_n : inout STD_LOGIC;
|
||||
DDR_we_n : inout STD_LOGIC;
|
||||
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
FIXED_IO_ddr_vrn : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrp : inout STD_LOGIC;
|
||||
FIXED_IO_ps_srstb : inout STD_LOGIC;
|
||||
FIXED_IO_ps_clk : inout STD_LOGIC;
|
||||
FIXED_IO_ps_porb : inout STD_LOGIC
|
||||
);
|
||||
end component design_1;
|
||||
begin
|
||||
design_1_i: component design_1
|
||||
port map (
|
||||
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
|
||||
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
|
||||
DDR_cas_n => DDR_cas_n,
|
||||
DDR_ck_n => DDR_ck_n,
|
||||
DDR_ck_p => DDR_ck_p,
|
||||
DDR_cke => DDR_cke,
|
||||
DDR_cs_n => DDR_cs_n,
|
||||
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
|
||||
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
|
||||
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
|
||||
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
|
||||
DDR_odt => DDR_odt,
|
||||
DDR_ras_n => DDR_ras_n,
|
||||
DDR_reset_n => DDR_reset_n,
|
||||
DDR_we_n => DDR_we_n,
|
||||
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
|
||||
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
|
||||
);
|
||||
end STRUCTURE;
|
||||
+714
-92
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 6 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+12770
File diff suppressed because it is too large
Load Diff
+89
@@ -0,0 +1,89 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Jan 27 23:05:10 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top design_1_auto_pc_0 -prefix
|
||||
// design_1_auto_pc_0_ design_1_auto_pc_0_stub.v
|
||||
// Design : design_1_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+573
@@ -0,0 +1,573 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_PC_0_H_
|
||||
#define IP_DESIGN_1_AUTO_PC_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "design_1_auto_pc_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_DESIGN_1_AUTO_PC_0_H_
|
||||
+354
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 166666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 166666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 166666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_28_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_PC_0_SC_H_
|
||||
#define IP_DESIGN_1_AUTO_PC_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_protocol_converter;
|
||||
|
||||
class DllExport design_1_auto_pc_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_protocol_converter* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
design_1_auto_pc_0_sc(const design_1_auto_pc_0_sc&);
|
||||
const design_1_auto_pc_0_sc& operator=(const design_1_auto_pc_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_DESIGN_1_AUTO_PC_0_SC_H_
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: design_1_auto_pc_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_auto_pc_0 (
|
||||
input bit_as_bool aclk,
|
||||
input bit_as_bool aresetn,
|
||||
input bit [11 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [1 : 0] s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit [3 : 0] s_axi_awqos,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [11 : 0] s_axi_wid,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [11 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [11 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [1 : 0] s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit [3 : 0] s_axi_arqos,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [11 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit [31 : 0] m_axi_awaddr,
|
||||
output bit [2 : 0] m_axi_awprot,
|
||||
output bit_as_bool m_axi_awvalid,
|
||||
input bit_as_bool m_axi_awready,
|
||||
output bit [31 : 0] m_axi_wdata,
|
||||
output bit [3 : 0] m_axi_wstrb,
|
||||
output bit_as_bool m_axi_wvalid,
|
||||
input bit_as_bool m_axi_wready,
|
||||
input bit [1 : 0] m_axi_bresp,
|
||||
input bit_as_bool m_axi_bvalid,
|
||||
output bit_as_bool m_axi_bready,
|
||||
output bit [31 : 0] m_axi_araddr,
|
||||
output bit [2 : 0] m_axi_arprot,
|
||||
output bit_as_bool m_axi_arvalid,
|
||||
input bit_as_bool m_axi_arready,
|
||||
input bit [31 : 0] m_axi_rdata,
|
||||
input bit [1 : 0] m_axi_rresp,
|
||||
input bit_as_bool m_axi_rvalid,
|
||||
output bit_as_bool m_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_auto_pc_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit aclk;
|
||||
input bit aresetn;
|
||||
input bit [11 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [1 : 0] s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit [3 : 0] s_axi_awqos;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [11 : 0] s_axi_wid;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [11 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [1 : 0] s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit [3 : 0] s_axi_arqos;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
output wire m_axi_awvalid;
|
||||
input bit m_axi_awready;
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
output wire m_axi_wvalid;
|
||||
input bit m_axi_wready;
|
||||
input bit [1 : 0] m_axi_bresp;
|
||||
input bit m_axi_bvalid;
|
||||
output wire m_axi_bready;
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
output wire m_axi_arvalid;
|
||||
input bit m_axi_arready;
|
||||
input bit [31 : 0] m_axi_rdata;
|
||||
input bit [1 : 0] m_axi_rresp;
|
||||
input bit m_axi_rvalid;
|
||||
output wire m_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
#ifndef _axi_protocol_converter_
|
||||
#define _axi_protocol_converter_
|
||||
#include <xtlm.h>
|
||||
#include <utils/xtlm_aximm_passthru_module.h>
|
||||
#include <systemc>
|
||||
|
||||
class axi_protocol_converter:public sc_module{
|
||||
public:
|
||||
axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_protocol_converter();
|
||||
SC_HAS_PROCESS(axi_protocol_converter);
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
sc_in<bool> aclk;
|
||||
sc_in<bool> aresetn;
|
||||
private:
|
||||
xtlm::xtlm_aximm_passthru_module *P1;
|
||||
xtlm::xtlm_aximm_passthru_module *P2;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+356
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=28,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WI\
|
||||
DTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 166666672, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 166666672, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 166666672, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_28_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+4472
File diff suppressed because it is too large
Load Diff
+7
@@ -0,0 +1,7 @@
|
||||
###############################################################################################################
|
||||
# Core-Level Timing Constraints for axi_dwidth_converter Component "design_1_auto_us_0"
|
||||
###############################################################################################################
|
||||
#
|
||||
# This component is not configured to perform asynchronous clock-domain-crossing.
|
||||
# No timing core-level constraints are needed.
|
||||
# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 6 -name s_axi_aclk [get_ports s_axi_aclk]
|
||||
|
||||
|
||||
+11797
File diff suppressed because it is too large
Load Diff
+105
@@ -0,0 +1,105 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Tue Jan 28 11:08:46 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top design_1_auto_us_0 -prefix
|
||||
// design_1_auto_us_0_ design_1_auto_us_0_stub.v
|
||||
// Design : design_1_auto_us_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_28_top,Vivado 2023.1" *)
|
||||
module design_1_auto_us_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
|
||||
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
|
||||
s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
|
||||
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
|
||||
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
|
||||
s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen,
|
||||
m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
|
||||
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
|
||||
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
|
||||
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
|
||||
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
|
||||
m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awid[3:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[3:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[3:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awlen[3:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[1:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [3:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [3:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [3:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [3:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [3:0]m_axi_awlen;
|
||||
output [2:0]m_axi_awsize;
|
||||
output [1:0]m_axi_awburst;
|
||||
output [1:0]m_axi_awlock;
|
||||
output [3:0]m_axi_awcache;
|
||||
output [2:0]m_axi_awprot;
|
||||
output [3:0]m_axi_awqos;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [63:0]m_axi_wdata;
|
||||
output [7:0]m_axi_wstrb;
|
||||
output m_axi_wlast;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [3:0]m_axi_arlen;
|
||||
output [2:0]m_axi_arsize;
|
||||
output [1:0]m_axi_arburst;
|
||||
output [1:0]m_axi_arlock;
|
||||
output [3:0]m_axi_arcache;
|
||||
output [2:0]m_axi_arprot;
|
||||
output [3:0]m_axi_arqos;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [63:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rlast;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+688
@@ -0,0 +1,688 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_US_0_H_
|
||||
#define IP_DESIGN_1_AUTO_US_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "design_1_auto_us_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,4,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_DESIGN_1_AUTO_US_0_H_
|
||||
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Reference in New Issue
Block a user