axis_dma: Adresszähler gefixt + Software zwischenstand
This commit is contained in:
Matthias Biermann
+4
-4
@@ -2,10 +2,10 @@
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="axi_crc_dma_ip" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739388837"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739388837"/>
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<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739388837"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739388837"/>
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<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739462143"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739462143"/>
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<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739462143"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739462143"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\axi_crc_dma_ip.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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+1
-1
@@ -2,7 +2,7 @@
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--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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--Date : Wed Feb 12 20:33:56 2025
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--Date : Thu Feb 13 16:55:43 2025
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--Host : BiermannSurface running 64-bit major release (build 9200)
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--Command : generate_target axi_crc_dma_ip_wrapper.bd
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--Design : axi_crc_dma_ip_wrapper
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+3
-3
@@ -1514,7 +1514,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Feb 12 19:37:59 UTC 2025</spirit:value>
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<spirit:value>Thu Feb 13 15:57:18 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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@@ -1545,7 +1545,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Feb 12 19:33:56 UTC 2025</spirit:value>
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<spirit:value>Thu Feb 13 15:55:43 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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@@ -1565,7 +1565,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Feb 12 19:33:56 UTC 2025</spirit:value>
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<spirit:value>Thu Feb 13 15:55:43 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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+45
-67
@@ -2,7 +2,7 @@
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// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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// Date : Wed Feb 12 20:37:59 2025
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// Date : Thu Feb 13 16:57:17 2025
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// Host : BiermannSurface running 64-bit major release (build 9200)
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// Command : write_verilog -force -mode funcsim
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// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0_sim_netlist.v
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@@ -986,8 +986,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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wire \finalXOR_reg[31]_i_2_n_0 ;
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wire \finalXOR_reg[31]_i_3_n_0 ;
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wire \finalXOR_reg[31]_i_4_n_0 ;
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wire [31:3]in15;
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wire [31:3]in16;
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wire [31:5]in15;
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wire [31:5]in16;
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wire [15:1]in8;
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wire [1:0]inOutReflected;
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wire inOut_reflected_reg;
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@@ -1169,8 +1169,6 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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wire read_addr_cnt0_carry__4_n_1;
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wire read_addr_cnt0_carry__4_n_2;
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wire read_addr_cnt0_carry__4_n_3;
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wire read_addr_cnt0_carry__5_n_0;
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wire read_addr_cnt0_carry__5_n_1;
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wire read_addr_cnt0_carry__5_n_2;
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wire read_addr_cnt0_carry__5_n_3;
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wire read_addr_cnt0_carry_i_1_n_0;
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@@ -1261,8 +1259,6 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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wire write_addr0_carry__4_n_1;
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wire write_addr0_carry__4_n_2;
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wire write_addr0_carry__4_n_3;
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wire write_addr0_carry__5_n_0;
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wire write_addr0_carry__5_n_1;
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wire write_addr0_carry__5_n_2;
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wire write_addr0_carry__5_n_3;
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wire write_addr0_carry_i_1_n_0;
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@@ -1351,10 +1347,10 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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wire [3:3]NLW_plusOp__28_carry__2_O_UNCONNECTED;
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wire [3:2]NLW_plusOp_carry__2_CO_UNCONNECTED;
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wire [3:3]NLW_plusOp_carry__2_O_UNCONNECTED;
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wire [3:0]NLW_read_addr_cnt0_carry__6_CO_UNCONNECTED;
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wire [3:1]NLW_read_addr_cnt0_carry__6_O_UNCONNECTED;
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wire [3:0]NLW_write_addr0_carry__6_CO_UNCONNECTED;
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wire [3:1]NLW_write_addr0_carry__6_O_UNCONNECTED;
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wire [3:2]NLW_read_addr_cnt0_carry__5_CO_UNCONNECTED;
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wire [3:3]NLW_read_addr_cnt0_carry__5_O_UNCONNECTED;
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wire [3:2]NLW_write_addr0_carry__5_CO_UNCONNECTED;
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wire [3:3]NLW_write_addr0_carry__5_O_UNCONNECTED;
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(* SOFT_HLUTNM = "soft_lutpair2" *)
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LUT5 #(
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@@ -7303,9 +7299,9 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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(.CI(1'b0),
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.CO({read_addr_cnt0_carry_n_0,read_addr_cnt0_carry_n_1,read_addr_cnt0_carry_n_2,read_addr_cnt0_carry_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,\read_addr_cnt_reg_n_0_[4] ,1'b0}),
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.O(in15[6:3]),
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.S({\read_addr_cnt_reg_n_0_[6] ,\read_addr_cnt_reg_n_0_[5] ,read_addr_cnt0_carry_i_1_n_0,\read_addr_cnt_reg_n_0_[3] }));
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.DI({1'b0,1'b0,\read_addr_cnt_reg_n_0_[6] ,1'b0}),
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.O(in15[8:5]),
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.S({\read_addr_cnt_reg_n_0_[8] ,\read_addr_cnt_reg_n_0_[7] ,read_addr_cnt0_carry_i_1_n_0,\read_addr_cnt_reg_n_0_[5] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__0
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@@ -7313,8 +7309,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({read_addr_cnt0_carry__0_n_0,read_addr_cnt0_carry__0_n_1,read_addr_cnt0_carry__0_n_2,read_addr_cnt0_carry__0_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in15[10:7]),
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.S({\read_addr_cnt_reg_n_0_[10] ,\read_addr_cnt_reg_n_0_[9] ,\read_addr_cnt_reg_n_0_[8] ,\read_addr_cnt_reg_n_0_[7] }));
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.O(in15[12:9]),
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.S({\read_addr_cnt_reg_n_0_[12] ,\read_addr_cnt_reg_n_0_[11] ,\read_addr_cnt_reg_n_0_[10] ,\read_addr_cnt_reg_n_0_[9] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__1
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@@ -7322,8 +7318,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({read_addr_cnt0_carry__1_n_0,read_addr_cnt0_carry__1_n_1,read_addr_cnt0_carry__1_n_2,read_addr_cnt0_carry__1_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in15[14:11]),
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.S({\read_addr_cnt_reg_n_0_[14] ,\read_addr_cnt_reg_n_0_[13] ,\read_addr_cnt_reg_n_0_[12] ,\read_addr_cnt_reg_n_0_[11] }));
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.O(in15[16:13]),
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.S({\read_addr_cnt_reg_n_0_[16] ,\read_addr_cnt_reg_n_0_[15] ,\read_addr_cnt_reg_n_0_[14] ,\read_addr_cnt_reg_n_0_[13] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__2
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@@ -7331,8 +7327,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({read_addr_cnt0_carry__2_n_0,read_addr_cnt0_carry__2_n_1,read_addr_cnt0_carry__2_n_2,read_addr_cnt0_carry__2_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in15[18:15]),
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.S({\read_addr_cnt_reg_n_0_[18] ,\read_addr_cnt_reg_n_0_[17] ,\read_addr_cnt_reg_n_0_[16] ,\read_addr_cnt_reg_n_0_[15] }));
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.O(in15[20:17]),
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.S({\read_addr_cnt_reg_n_0_[20] ,\read_addr_cnt_reg_n_0_[19] ,\read_addr_cnt_reg_n_0_[18] ,\read_addr_cnt_reg_n_0_[17] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__3
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@@ -7340,8 +7336,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({read_addr_cnt0_carry__3_n_0,read_addr_cnt0_carry__3_n_1,read_addr_cnt0_carry__3_n_2,read_addr_cnt0_carry__3_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in15[22:19]),
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.S({\read_addr_cnt_reg_n_0_[22] ,\read_addr_cnt_reg_n_0_[21] ,\read_addr_cnt_reg_n_0_[20] ,\read_addr_cnt_reg_n_0_[19] }));
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.O(in15[24:21]),
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.S({\read_addr_cnt_reg_n_0_[24] ,\read_addr_cnt_reg_n_0_[23] ,\read_addr_cnt_reg_n_0_[22] ,\read_addr_cnt_reg_n_0_[21] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__4
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@@ -7349,30 +7345,21 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({read_addr_cnt0_carry__4_n_0,read_addr_cnt0_carry__4_n_1,read_addr_cnt0_carry__4_n_2,read_addr_cnt0_carry__4_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in15[26:23]),
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.S({\read_addr_cnt_reg_n_0_[26] ,\read_addr_cnt_reg_n_0_[25] ,\read_addr_cnt_reg_n_0_[24] ,\read_addr_cnt_reg_n_0_[23] }));
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.O(in15[28:25]),
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.S({\read_addr_cnt_reg_n_0_[28] ,\read_addr_cnt_reg_n_0_[27] ,\read_addr_cnt_reg_n_0_[26] ,\read_addr_cnt_reg_n_0_[25] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__5
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(.CI(read_addr_cnt0_carry__4_n_0),
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.CO({read_addr_cnt0_carry__5_n_0,read_addr_cnt0_carry__5_n_1,read_addr_cnt0_carry__5_n_2,read_addr_cnt0_carry__5_n_3}),
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.CO({NLW_read_addr_cnt0_carry__5_CO_UNCONNECTED[3:2],read_addr_cnt0_carry__5_n_2,read_addr_cnt0_carry__5_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in15[30:27]),
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.S({\read_addr_cnt_reg_n_0_[30] ,\read_addr_cnt_reg_n_0_[29] ,\read_addr_cnt_reg_n_0_[28] ,\read_addr_cnt_reg_n_0_[27] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 read_addr_cnt0_carry__6
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(.CI(read_addr_cnt0_carry__5_n_0),
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.CO(NLW_read_addr_cnt0_carry__6_CO_UNCONNECTED[3:0]),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O({NLW_read_addr_cnt0_carry__6_O_UNCONNECTED[3:1],in15[31]}),
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.S({1'b0,1'b0,1'b0,\read_addr_cnt_reg_n_0_[31] }));
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.O({NLW_read_addr_cnt0_carry__5_O_UNCONNECTED[3],in15[31:29]}),
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.S({1'b0,\read_addr_cnt_reg_n_0_[31] ,\read_addr_cnt_reg_n_0_[30] ,\read_addr_cnt_reg_n_0_[29] }));
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LUT1 #(
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.INIT(2'h1))
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read_addr_cnt0_carry_i_1
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(.I0(\read_addr_cnt_reg_n_0_[4] ),
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(.I0(\read_addr_cnt_reg_n_0_[6] ),
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.O(read_addr_cnt0_carry_i_1_n_0));
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(* SOFT_HLUTNM = "soft_lutpair42" *)
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LUT3 #(
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@@ -7604,7 +7591,7 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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LUT3 #(
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.INIT(8'hB8))
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\read_addr_cnt[3]_i_1
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(.I0(in15[3]),
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(.I0(\read_addr_cnt_reg_n_0_[3] ),
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.I1(read_state_reg[0]),
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.I2(read_address_reg[3]),
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.O(read_addr_cnt[3]));
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@@ -7612,7 +7599,7 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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LUT3 #(
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.INIT(8'hB8))
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\read_addr_cnt[4]_i_1
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(.I0(in15[4]),
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(.I0(\read_addr_cnt_reg_n_0_[4] ),
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.I1(read_state_reg[0]),
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.I2(read_address_reg[4]),
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.O(read_addr_cnt[4]));
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@@ -8300,9 +8287,9 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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(.CI(1'b0),
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.CO({write_addr0_carry_n_0,write_addr0_carry_n_1,write_addr0_carry_n_2,write_addr0_carry_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,\write_addr_reg_n_0_[4] ,1'b0}),
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.O(in16[6:3]),
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.S({\write_addr_reg_n_0_[6] ,\write_addr_reg_n_0_[5] ,write_addr0_carry_i_1_n_0,\write_addr_reg_n_0_[3] }));
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.DI({1'b0,1'b0,\write_addr_reg_n_0_[6] ,1'b0}),
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.O(in16[8:5]),
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.S({\write_addr_reg_n_0_[8] ,\write_addr_reg_n_0_[7] ,write_addr0_carry_i_1_n_0,\write_addr_reg_n_0_[5] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 write_addr0_carry__0
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@@ -8310,8 +8297,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({write_addr0_carry__0_n_0,write_addr0_carry__0_n_1,write_addr0_carry__0_n_2,write_addr0_carry__0_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in16[10:7]),
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.S({\write_addr_reg_n_0_[10] ,\write_addr_reg_n_0_[9] ,\write_addr_reg_n_0_[8] ,\write_addr_reg_n_0_[7] }));
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.O(in16[12:9]),
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.S({\write_addr_reg_n_0_[12] ,\write_addr_reg_n_0_[11] ,\write_addr_reg_n_0_[10] ,\write_addr_reg_n_0_[9] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 write_addr0_carry__1
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@@ -8319,8 +8306,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({write_addr0_carry__1_n_0,write_addr0_carry__1_n_1,write_addr0_carry__1_n_2,write_addr0_carry__1_n_3}),
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.CYINIT(1'b0),
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.DI({1'b0,1'b0,1'b0,1'b0}),
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.O(in16[14:11]),
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.S({\write_addr_reg_n_0_[14] ,\write_addr_reg_n_0_[13] ,\write_addr_reg_n_0_[12] ,\write_addr_reg_n_0_[11] }));
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.O(in16[16:13]),
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.S({\write_addr_reg_n_0_[16] ,\write_addr_reg_n_0_[15] ,\write_addr_reg_n_0_[14] ,\write_addr_reg_n_0_[13] }));
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(* ADDER_THRESHOLD = "35" *)
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(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
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CARRY4 write_addr0_carry__2
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@@ -8328,8 +8315,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
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.CO({write_addr0_carry__2_n_0,write_addr0_carry__2_n_1,write_addr0_carry__2_n_2,write_addr0_carry__2_n_3}),
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.CYINIT(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0}),
|
||||
.O(in16[18:15]),
|
||||
.S({\write_addr_reg_n_0_[18] ,\write_addr_reg_n_0_[17] ,\write_addr_reg_n_0_[16] ,\write_addr_reg_n_0_[15] }));
|
||||
.O(in16[20:17]),
|
||||
.S({\write_addr_reg_n_0_[20] ,\write_addr_reg_n_0_[19] ,\write_addr_reg_n_0_[18] ,\write_addr_reg_n_0_[17] }));
|
||||
(* ADDER_THRESHOLD = "35" *)
|
||||
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
|
||||
CARRY4 write_addr0_carry__3
|
||||
@@ -8337,8 +8324,8 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
|
||||
.CO({write_addr0_carry__3_n_0,write_addr0_carry__3_n_1,write_addr0_carry__3_n_2,write_addr0_carry__3_n_3}),
|
||||
.CYINIT(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0}),
|
||||
.O(in16[22:19]),
|
||||
.S({\write_addr_reg_n_0_[22] ,\write_addr_reg_n_0_[21] ,\write_addr_reg_n_0_[20] ,\write_addr_reg_n_0_[19] }));
|
||||
.O(in16[24:21]),
|
||||
.S({\write_addr_reg_n_0_[24] ,\write_addr_reg_n_0_[23] ,\write_addr_reg_n_0_[22] ,\write_addr_reg_n_0_[21] }));
|
||||
(* ADDER_THRESHOLD = "35" *)
|
||||
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
|
||||
CARRY4 write_addr0_carry__4
|
||||
@@ -8346,30 +8333,21 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
|
||||
.CO({write_addr0_carry__4_n_0,write_addr0_carry__4_n_1,write_addr0_carry__4_n_2,write_addr0_carry__4_n_3}),
|
||||
.CYINIT(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0}),
|
||||
.O(in16[26:23]),
|
||||
.S({\write_addr_reg_n_0_[26] ,\write_addr_reg_n_0_[25] ,\write_addr_reg_n_0_[24] ,\write_addr_reg_n_0_[23] }));
|
||||
.O(in16[28:25]),
|
||||
.S({\write_addr_reg_n_0_[28] ,\write_addr_reg_n_0_[27] ,\write_addr_reg_n_0_[26] ,\write_addr_reg_n_0_[25] }));
|
||||
(* ADDER_THRESHOLD = "35" *)
|
||||
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
|
||||
CARRY4 write_addr0_carry__5
|
||||
(.CI(write_addr0_carry__4_n_0),
|
||||
.CO({write_addr0_carry__5_n_0,write_addr0_carry__5_n_1,write_addr0_carry__5_n_2,write_addr0_carry__5_n_3}),
|
||||
.CO({NLW_write_addr0_carry__5_CO_UNCONNECTED[3:2],write_addr0_carry__5_n_2,write_addr0_carry__5_n_3}),
|
||||
.CYINIT(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0}),
|
||||
.O(in16[30:27]),
|
||||
.S({\write_addr_reg_n_0_[30] ,\write_addr_reg_n_0_[29] ,\write_addr_reg_n_0_[28] ,\write_addr_reg_n_0_[27] }));
|
||||
(* ADDER_THRESHOLD = "35" *)
|
||||
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
|
||||
CARRY4 write_addr0_carry__6
|
||||
(.CI(write_addr0_carry__5_n_0),
|
||||
.CO(NLW_write_addr0_carry__6_CO_UNCONNECTED[3:0]),
|
||||
.CYINIT(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0}),
|
||||
.O({NLW_write_addr0_carry__6_O_UNCONNECTED[3:1],in16[31]}),
|
||||
.S({1'b0,1'b0,1'b0,\write_addr_reg_n_0_[31] }));
|
||||
.O({NLW_write_addr0_carry__5_O_UNCONNECTED[3],in16[31:29]}),
|
||||
.S({1'b0,\write_addr_reg_n_0_[31] ,\write_addr_reg_n_0_[30] ,\write_addr_reg_n_0_[29] }));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
write_addr0_carry_i_1
|
||||
(.I0(\write_addr_reg_n_0_[4] ),
|
||||
(.I0(\write_addr_reg_n_0_[6] ),
|
||||
.O(write_addr0_carry_i_1_n_0));
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
@@ -8583,7 +8561,7 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\write_addr[3]_i_1
|
||||
(.I0(in16[3]),
|
||||
(.I0(\write_addr_reg_n_0_[3] ),
|
||||
.I1(write_state_reg[0]),
|
||||
.I2(write_address_reg[3]),
|
||||
.O(write_addr[3]));
|
||||
@@ -8591,7 +8569,7 @@ module axi_crc_dma_ip_axis_dma_0_0_axis_dma
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\write_addr[4]_i_1
|
||||
(.I0(in16[4]),
|
||||
(.I0(\write_addr_reg_n_0_[4] ),
|
||||
.I1(write_state_reg[0]),
|
||||
.I2(write_address_reg[4]),
|
||||
.O(write_addr[4]));
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Feb 12 20:37:59 2025
|
||||
// Date : Thu Feb 13 16:57:17 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_ip/ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0_stub.v
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Feb 12 20:33:56 2025
|
||||
--Date : Thu Feb 13 16:55:43 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_ip.bd
|
||||
--Design : axi_crc_dma_ip
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Feb 12 20:33:56 2025
|
||||
--Date : Thu Feb 13 16:55:43 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_ip.bd
|
||||
--Design : axi_crc_dma_ip
|
||||
|
||||
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739388812"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1739388812"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739388812"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739388812"/>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1739462406"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1739462406"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1739462406"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1739462406"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axi_crc_dma_syn_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739388895"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739388895"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739388895"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739388895"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739462525"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739462525"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739462525"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739462525"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axi_crc_dma_syn_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Feb 12 20:34:33 2025
|
||||
--Date : Thu Feb 13 17:01:58 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_syn_1_wrapper.bd
|
||||
--Design : axi_crc_dma_syn_1_wrapper
|
||||
|
||||
+8
-8
@@ -1500,7 +1500,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:55 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:05 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1518,7 +1518,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1538,7 +1538,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1566,7 +1566,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1605,7 +1605,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:51 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1625,7 +1625,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1663,7 +1663,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1683,7 +1683,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:53 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+9
-9
@@ -1511,7 +1511,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:55 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:05 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1530,7 +1530,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1548,7 +1548,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1568,7 +1568,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1596,7 +1596,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1644,7 +1644,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1664,7 +1664,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1708,7 +1708,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1728,7 +1728,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:52 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+3
-3
@@ -1196,7 +1196,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:40:50 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:03:23 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1227,7 +1227,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:35 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1247,7 +1247,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:35 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Feb 12 20:40:50 2025
|
||||
// Date : Thu Feb 13 17:03:23 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_sim_netlist.v
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Feb 12 20:40:50 2025
|
||||
// Date : Thu Feb 13 17:03:23 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_stub.v
|
||||
|
||||
+38
-26
@@ -1179,11 +1179,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:35 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:01:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6c4cf774</spirit:value>
|
||||
<spirit:value>9:8079280e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1197,11 +1197,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:33:24 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 15:55:54 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b20ef634</spirit:value>
|
||||
<spirit:value>9:419227ca</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1215,11 +1215,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:33:19 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 14:53:09 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:966ecf7e</spirit:value>
|
||||
<spirit:value>9:39725971</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1233,11 +1233,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:44:07 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:17 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6c4cf774</spirit:value>
|
||||
<spirit:value>9:8079280e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1252,11 +1252,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:35 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:01:58 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6c4cf774</spirit:value>
|
||||
<spirit:value>9:8079280e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1269,11 +1269,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d32eb077</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
<spirit:value>9:092bd67a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1289,15 +1285,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:35 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 14:54:42 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d32eb077</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
<spirit:value>9:092bd67a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1313,11 +1305,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:35 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:01:59 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:6c4cf774</spirit:value>
|
||||
<spirit:value>9:8079280e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1356,6 +1348,26 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>probe1</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXI_awaddr</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -31511,7 +31523,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_OF_PROBES</spirit:name>
|
||||
<spirit:displayName>Number of Probes</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_OF_PROBES" spirit:order="10700" spirit:configGroups="1 UnGrouped" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_OF_PROBES" spirit:order="10700" spirit:configGroups="1 UnGrouped" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
@@ -36705,7 +36717,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_PROBE1_MU_CNT</spirit:name>
|
||||
<spirit:displayName>C Probe1 Mu Cnt</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE1_MU_CNT" spirit:order="205700" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE1_MU_CNT" spirit:order="205700" spirit:minimum="1" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_PROBE0_MU_CNT</spirit:name>
|
||||
@@ -37885,7 +37897,6 @@
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>System ILA</xilinx:displayName>
|
||||
<xilinx:supportsDeferredElaboration>true</xilinx:supportsDeferredElaboration>
|
||||
<xilinx:coreRevision>14</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:ip:system_ila:1.0_ARCHIVE_LOCATION">/proj/xhdhdstaff/niloyr/debug_tools/IP3_niloyr_cs/DEV/output/internal/vivado/data/ip/xilinx</xilinx:tag>
|
||||
@@ -37966,6 +37977,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_MONITOR_SLOTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_OF_PROBES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE0_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE1_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_APC_EN" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_APC_STS_EN" xilinx:valueSource="user"/>
|
||||
|
||||
+88352
-87854
File diff suppressed because one or more lines are too long
+6
-5
@@ -2,10 +2,10 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Wed Feb 12 20:43:58 2025
|
||||
// Date : Thu Feb 13 16:59:58 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt2/Hardware/axi_crc_dma/axi_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_2/axi_crc_dma_syn_1_system_ila_0_2_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_system_ila_0_2 -prefix
|
||||
// axi_crc_dma_syn_1_system_ila_0_2_ axi_crc_dma_syn_1_system_ila_0_2_stub.v
|
||||
// Design : axi_crc_dma_syn_1_system_ila_0_2
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
@@ -15,7 +15,7 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "bd_e484,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_system_ila_0_2(clk, probe0, SLOT_0_AXI_awaddr,
|
||||
module axi_crc_dma_syn_1_system_ila_0_2(clk, probe0, probe1, SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awprot, SLOT_0_AXI_awvalid, SLOT_0_AXI_awready, SLOT_0_AXI_wdata,
|
||||
SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid, SLOT_0_AXI_wready, SLOT_0_AXI_bresp,
|
||||
SLOT_0_AXI_bvalid, SLOT_0_AXI_bready, SLOT_0_AXI_araddr, SLOT_0_AXI_arprot,
|
||||
@@ -30,10 +30,11 @@ module axi_crc_dma_syn_1_system_ila_0_2(clk, probe0, SLOT_0_AXI_awaddr,
|
||||
SLOT_1_AXI_arcache, SLOT_1_AXI_arprot, SLOT_1_AXI_arqos, SLOT_1_AXI_arvalid,
|
||||
SLOT_1_AXI_arready, SLOT_1_AXI_rid, SLOT_1_AXI_rdata, SLOT_1_AXI_rresp, SLOT_1_AXI_rlast,
|
||||
SLOT_1_AXI_rvalid, SLOT_1_AXI_rready, resetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],SLOT_0_AXI_awaddr[7:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[7:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_AXI_awid[0:0],SLOT_1_AXI_awaddr[31:0],SLOT_1_AXI_awlen[3:0],SLOT_1_AXI_awsize[2:0],SLOT_1_AXI_awburst[1:0],SLOT_1_AXI_awlock[1:0],SLOT_1_AXI_awcache[3:0],SLOT_1_AXI_awprot[2:0],SLOT_1_AXI_awqos[3:0],SLOT_1_AXI_awvalid,SLOT_1_AXI_awready,SLOT_1_AXI_wid[0:0],SLOT_1_AXI_wdata[31:0],SLOT_1_AXI_wstrb[3:0],SLOT_1_AXI_wlast,SLOT_1_AXI_wvalid,SLOT_1_AXI_wready,SLOT_1_AXI_bid[0:0],SLOT_1_AXI_bresp[1:0],SLOT_1_AXI_bvalid,SLOT_1_AXI_bready,SLOT_1_AXI_arid[0:0],SLOT_1_AXI_araddr[31:0],SLOT_1_AXI_arlen[3:0],SLOT_1_AXI_arsize[2:0],SLOT_1_AXI_arburst[1:0],SLOT_1_AXI_arlock[1:0],SLOT_1_AXI_arcache[3:0],SLOT_1_AXI_arprot[2:0],SLOT_1_AXI_arqos[3:0],SLOT_1_AXI_arvalid,SLOT_1_AXI_arready,SLOT_1_AXI_rid[0:0],SLOT_1_AXI_rdata[31:0],SLOT_1_AXI_rresp[1:0],SLOT_1_AXI_rlast,SLOT_1_AXI_rvalid,SLOT_1_AXI_rready,resetn" */
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[0:0],SLOT_0_AXI_awaddr[7:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[7:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_AXI_awid[0:0],SLOT_1_AXI_awaddr[31:0],SLOT_1_AXI_awlen[3:0],SLOT_1_AXI_awsize[2:0],SLOT_1_AXI_awburst[1:0],SLOT_1_AXI_awlock[1:0],SLOT_1_AXI_awcache[3:0],SLOT_1_AXI_awprot[2:0],SLOT_1_AXI_awqos[3:0],SLOT_1_AXI_awvalid,SLOT_1_AXI_awready,SLOT_1_AXI_wid[0:0],SLOT_1_AXI_wdata[31:0],SLOT_1_AXI_wstrb[3:0],SLOT_1_AXI_wlast,SLOT_1_AXI_wvalid,SLOT_1_AXI_wready,SLOT_1_AXI_bid[0:0],SLOT_1_AXI_bresp[1:0],SLOT_1_AXI_bvalid,SLOT_1_AXI_bready,SLOT_1_AXI_arid[0:0],SLOT_1_AXI_araddr[31:0],SLOT_1_AXI_arlen[3:0],SLOT_1_AXI_arsize[2:0],SLOT_1_AXI_arburst[1:0],SLOT_1_AXI_arlock[1:0],SLOT_1_AXI_arcache[3:0],SLOT_1_AXI_arprot[2:0],SLOT_1_AXI_arqos[3:0],SLOT_1_AXI_arvalid,SLOT_1_AXI_arready,SLOT_1_AXI_rid[0:0],SLOT_1_AXI_rdata[31:0],SLOT_1_AXI_rresp[1:0],SLOT_1_AXI_rlast,SLOT_1_AXI_rvalid,SLOT_1_AXI_rready,resetn" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [7:0]SLOT_0_AXI_awaddr;
|
||||
input [2:0]SLOT_0_AXI_awprot;
|
||||
input SLOT_0_AXI_awvalid;
|
||||
|
||||
+113
-93
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x9D6443A34A5D577",
|
||||
"boundary_crc": "0xB19EE1C058093441",
|
||||
"design_src": "SBD",
|
||||
"device": "xc7z020clg400-1",
|
||||
"name": "bd_e484",
|
||||
@@ -329,6 +329,11 @@
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"probe1": {
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
@@ -376,7 +381,7 @@
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "52"
|
||||
"value": "53"
|
||||
},
|
||||
"C_PROBE0_MU_CNT": {
|
||||
"value": "1"
|
||||
@@ -391,19 +396,19 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE10_WIDTH": {
|
||||
"value": "32"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE11_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE11_WIDTH": {
|
||||
"value": "4"
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE12_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE12_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE13_TYPE": {
|
||||
"value": "0"
|
||||
@@ -433,61 +438,64 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE17_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE18_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE18_WIDTH": {
|
||||
"value": "160"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE19_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE19_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "160"
|
||||
},
|
||||
"C_PROBE1_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE20_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE20_WIDTH": {
|
||||
"value": "32"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE21_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE21_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE22_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE22_WIDTH": {
|
||||
"value": "4"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE23_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE23_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE24_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE24_WIDTH": {
|
||||
"value": "4"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE25_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE25_WIDTH": {
|
||||
"value": "3"
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE26_TYPE": {
|
||||
"value": "0"
|
||||
@@ -499,49 +507,49 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE27_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE28_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE28_WIDTH": {
|
||||
"value": "32"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE29_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE29_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE2_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE2_WIDTH": {
|
||||
"value": "8"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE30_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE30_WIDTH": {
|
||||
"value": "4"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE31_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE31_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE32_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE32_WIDTH": {
|
||||
"value": "4"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE33_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE33_WIDTH": {
|
||||
"value": "3"
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE34_TYPE": {
|
||||
"value": "0"
|
||||
@@ -553,19 +561,19 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE35_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE36_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE36_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE37_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE37_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE38_TYPE": {
|
||||
"value": "0"
|
||||
@@ -577,61 +585,61 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE39_WIDTH": {
|
||||
"value": "32"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE3_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE3_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "8"
|
||||
},
|
||||
"C_PROBE40_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE40_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE41_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE41_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE42_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE42_WIDTH": {
|
||||
"value": "32"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE43_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE43_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE44_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE44_WIDTH": {
|
||||
"value": "4"
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE45_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE45_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE46_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE46_WIDTH": {
|
||||
"value": "3"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE47_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE47_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE48_TYPE": {
|
||||
"value": "0"
|
||||
@@ -643,31 +651,37 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE49_WIDTH": {
|
||||
"value": "3"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE4_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE4_WIDTH": {
|
||||
"value": "8"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE50_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE50_WIDTH": {
|
||||
"value": "1"
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE51_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE51_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE52_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE52_WIDTH": {
|
||||
"value": "160"
|
||||
},
|
||||
"C_PROBE5_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE5_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "8"
|
||||
},
|
||||
"C_PROBE6_TYPE": {
|
||||
"value": "0"
|
||||
@@ -685,13 +699,13 @@
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE8_WIDTH": {
|
||||
"value": "32"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE9_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE9_WIDTH": {
|
||||
"value": "2"
|
||||
"value": "32"
|
||||
},
|
||||
"C_TRIGIN_EN": {
|
||||
"value": "false"
|
||||
@@ -1129,31 +1143,31 @@
|
||||
"net_slot_0_apc_pc_asserted": {
|
||||
"ports": [
|
||||
"slot_0_apc/pc_asserted",
|
||||
"ila_lib/probe17"
|
||||
"ila_lib/probe18"
|
||||
]
|
||||
},
|
||||
"net_slot_0_apc_pc_status": {
|
||||
"ports": [
|
||||
"slot_0_apc/pc_status",
|
||||
"ila_lib/probe18"
|
||||
"ila_lib/probe19"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_ar_cnt",
|
||||
"ila_lib/probe1"
|
||||
"ila_lib/probe2"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_ar/dout",
|
||||
"ila_lib/probe15"
|
||||
"ila_lib/probe16"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_araddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_araddr",
|
||||
"ila_lib/probe2"
|
||||
"ila_lib/probe3"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arready": {
|
||||
@@ -1171,19 +1185,19 @@
|
||||
"net_slot_0_axi_aw_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_aw_cnt",
|
||||
"ila_lib/probe3"
|
||||
"ila_lib/probe4"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_aw_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_aw/dout",
|
||||
"ila_lib/probe12"
|
||||
"ila_lib/probe13"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awaddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awaddr",
|
||||
"ila_lib/probe4"
|
||||
"ila_lib/probe5"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awready": {
|
||||
@@ -1201,13 +1215,13 @@
|
||||
"net_slot_0_axi_b_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_b_cnt",
|
||||
"ila_lib/probe5"
|
||||
"ila_lib/probe6"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_b_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_b/dout",
|
||||
"ila_lib/probe14"
|
||||
"ila_lib/probe15"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bready": {
|
||||
@@ -1219,7 +1233,7 @@
|
||||
"net_slot_0_axi_bresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bresp",
|
||||
"ila_lib/probe6"
|
||||
"ila_lib/probe7"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bvalid": {
|
||||
@@ -1231,19 +1245,19 @@
|
||||
"net_slot_0_axi_r_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_r_cnt",
|
||||
"ila_lib/probe7"
|
||||
"ila_lib/probe8"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_r_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_r/dout",
|
||||
"ila_lib/probe16"
|
||||
"ila_lib/probe17"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rdata",
|
||||
"ila_lib/probe8"
|
||||
"ila_lib/probe9"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rready": {
|
||||
@@ -1255,7 +1269,7 @@
|
||||
"net_slot_0_axi_rresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rresp",
|
||||
"ila_lib/probe9"
|
||||
"ila_lib/probe10"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rvalid": {
|
||||
@@ -1267,13 +1281,13 @@
|
||||
"net_slot_0_axi_w_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_w/dout",
|
||||
"ila_lib/probe13"
|
||||
"ila_lib/probe14"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wdata",
|
||||
"ila_lib/probe10"
|
||||
"ila_lib/probe11"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wready": {
|
||||
@@ -1285,7 +1299,7 @@
|
||||
"net_slot_0_axi_wstrb": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wstrb",
|
||||
"ila_lib/probe11"
|
||||
"ila_lib/probe12"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wvalid": {
|
||||
@@ -1297,61 +1311,61 @@
|
||||
"net_slot_1_apc_pc_asserted": {
|
||||
"ports": [
|
||||
"slot_1_apc/pc_asserted",
|
||||
"ila_lib/probe50"
|
||||
"ila_lib/probe51"
|
||||
]
|
||||
},
|
||||
"net_slot_1_apc_pc_status": {
|
||||
"ports": [
|
||||
"slot_1_apc/pc_status",
|
||||
"ila_lib/probe51"
|
||||
"ila_lib/probe52"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_ar_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_ar_cnt",
|
||||
"ila_lib/probe19"
|
||||
"ila_lib/probe20"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_ar_ctrl": {
|
||||
"ports": [
|
||||
"slot_1_ar/dout",
|
||||
"ila_lib/probe48"
|
||||
"ila_lib/probe49"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_araddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_araddr",
|
||||
"ila_lib/probe20"
|
||||
"ila_lib/probe21"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arburst": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_arburst",
|
||||
"ila_lib/probe21"
|
||||
"ila_lib/probe22"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arcache": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_arcache",
|
||||
"ila_lib/probe22"
|
||||
"ila_lib/probe23"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_arid",
|
||||
"ila_lib/probe23"
|
||||
"ila_lib/probe24"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arlen": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_arlen",
|
||||
"ila_lib/probe24"
|
||||
"ila_lib/probe25"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arprot": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_arprot",
|
||||
"ila_lib/probe25"
|
||||
"ila_lib/probe26"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arready": {
|
||||
@@ -1363,7 +1377,7 @@
|
||||
"net_slot_1_axi_arsize": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_arsize",
|
||||
"ila_lib/probe26"
|
||||
"ila_lib/probe27"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_arvalid": {
|
||||
@@ -1375,49 +1389,49 @@
|
||||
"net_slot_1_axi_aw_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_aw_cnt",
|
||||
"ila_lib/probe27"
|
||||
"ila_lib/probe28"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_aw_ctrl": {
|
||||
"ports": [
|
||||
"slot_1_aw/dout",
|
||||
"ila_lib/probe45"
|
||||
"ila_lib/probe46"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awaddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awaddr",
|
||||
"ila_lib/probe28"
|
||||
"ila_lib/probe29"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awburst": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awburst",
|
||||
"ila_lib/probe29"
|
||||
"ila_lib/probe30"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awcache": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awcache",
|
||||
"ila_lib/probe30"
|
||||
"ila_lib/probe31"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awid",
|
||||
"ila_lib/probe31"
|
||||
"ila_lib/probe32"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awlen": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awlen",
|
||||
"ila_lib/probe32"
|
||||
"ila_lib/probe33"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awprot": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awprot",
|
||||
"ila_lib/probe33"
|
||||
"ila_lib/probe34"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awready": {
|
||||
@@ -1429,7 +1443,7 @@
|
||||
"net_slot_1_axi_awsize": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_awsize",
|
||||
"ila_lib/probe34"
|
||||
"ila_lib/probe35"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_awvalid": {
|
||||
@@ -1441,19 +1455,19 @@
|
||||
"net_slot_1_axi_b_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_b_cnt",
|
||||
"ila_lib/probe35"
|
||||
"ila_lib/probe36"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_b_ctrl": {
|
||||
"ports": [
|
||||
"slot_1_b/dout",
|
||||
"ila_lib/probe47"
|
||||
"ila_lib/probe48"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_bid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_bid",
|
||||
"ila_lib/probe36"
|
||||
"ila_lib/probe37"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_bready": {
|
||||
@@ -1465,7 +1479,7 @@
|
||||
"net_slot_1_axi_bresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_bresp",
|
||||
"ila_lib/probe37"
|
||||
"ila_lib/probe38"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_bvalid": {
|
||||
@@ -1477,25 +1491,25 @@
|
||||
"net_slot_1_axi_r_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_r_cnt",
|
||||
"ila_lib/probe38"
|
||||
"ila_lib/probe39"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_r_ctrl": {
|
||||
"ports": [
|
||||
"slot_1_r/dout",
|
||||
"ila_lib/probe49"
|
||||
"ila_lib/probe50"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_rdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_rdata",
|
||||
"ila_lib/probe39"
|
||||
"ila_lib/probe40"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_rid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_rid",
|
||||
"ila_lib/probe40"
|
||||
"ila_lib/probe41"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_rlast": {
|
||||
@@ -1513,7 +1527,7 @@
|
||||
"net_slot_1_axi_rresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_rresp",
|
||||
"ila_lib/probe41"
|
||||
"ila_lib/probe42"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_rvalid": {
|
||||
@@ -1525,19 +1539,19 @@
|
||||
"net_slot_1_axi_w_ctrl": {
|
||||
"ports": [
|
||||
"slot_1_w/dout",
|
||||
"ila_lib/probe46"
|
||||
"ila_lib/probe47"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_wdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_wdata",
|
||||
"ila_lib/probe42"
|
||||
"ila_lib/probe43"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_wid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_wid",
|
||||
"ila_lib/probe43"
|
||||
"ila_lib/probe44"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_wlast": {
|
||||
@@ -1555,7 +1569,7 @@
|
||||
"net_slot_1_axi_wstrb": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axi_wstrb",
|
||||
"ila_lib/probe44"
|
||||
"ila_lib/probe45"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axi_wvalid": {
|
||||
@@ -1570,6 +1584,12 @@
|
||||
"ila_lib/probe0"
|
||||
]
|
||||
},
|
||||
"probe1_1": {
|
||||
"ports": [
|
||||
"probe1",
|
||||
"ila_lib/probe1"
|
||||
]
|
||||
},
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
|
||||
+10
-10
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_e484" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739388890"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739388890"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739388890"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739388890"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739462524"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739462524"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739462524"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739462524"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_e484.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
@@ -19,6 +19,12 @@
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_e484.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_e484_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
@@ -39,12 +45,6 @@
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_e484.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+3
@@ -70,6 +70,7 @@ entity bd_e484_wrapper is
|
||||
SLOT_1_AXI_wvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end bd_e484_wrapper;
|
||||
@@ -79,6 +80,7 @@ architecture STRUCTURE of bd_e484_wrapper is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
resetn : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
@@ -201,6 +203,7 @@ bd_e484_i: component bd_e484
|
||||
SLOT_1_AXI_wvalid => SLOT_1_AXI_wvalid,
|
||||
clk => clk,
|
||||
probe0(0) => probe0(0),
|
||||
probe1(0) => probe1(0),
|
||||
resetn => resetn
|
||||
);
|
||||
end STRUCTURE;
|
||||
|
||||
+138
-137
@@ -979,7 +979,7 @@
|
||||
"C_PROBE55_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE54_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE53_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE52_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE52_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE51_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE50_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE49_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -2002,61 +2002,61 @@
|
||||
"C_PROBE55_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE54_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE53_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE52_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE51_WIDTH": [ { "value": "160", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE50_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE49_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE52_WIDTH": [ { "value": "160", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE51_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE50_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE49_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE48_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE47_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE46_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE45_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE44_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE41_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE40_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE39_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE47_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE46_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE45_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE44_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE41_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE40_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE39_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE38_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE37_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE36_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE35_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE37_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE36_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE35_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE34_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE33_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE32_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE31_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE30_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE29_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE28_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE27_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE33_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE32_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE31_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE30_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE29_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE28_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE27_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE26_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE25_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE24_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE23_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE22_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE21_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE20_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE19_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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@@ -3096,7 +3096,7 @@
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@@ -3135,7 +3135,7 @@
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@@ -3150,68 +3150,68 @@
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"C_PROBE40_WIDTH": [ { "value": "32", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE41_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE42_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE43_WIDTH": [ { "value": "32", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE44_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE45_WIDTH": [ { "value": "4", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE46_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE47_WIDTH": [ { "value": "3", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE48_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE49_WIDTH": [ { "value": "3", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE50_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE51_WIDTH": [ { "value": "160", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE52_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE49_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE50_WIDTH": [ { "value": "3", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE51_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE52_WIDTH": [ { "value": "160", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE53_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE54_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE55_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
@@ -6273,57 +6273,58 @@
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe1": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe2": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe3": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe4": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe5": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe2": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe3": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe4": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe5": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe6": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe7": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe8": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe9": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe10": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe11": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe12": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe8": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe9": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe10": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe11": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe12": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe13": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe14": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe15": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe16": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe17": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe18": [ { "direction": "in", "size_left": "159", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe19": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe20": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe21": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe22": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe23": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe24": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe25": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe17": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe18": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe19": [ { "direction": "in", "size_left": "159", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe20": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe21": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe22": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe23": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe24": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe25": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe26": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe27": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe28": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe29": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe30": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe31": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe32": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe33": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe27": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe28": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe29": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe30": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe31": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe32": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe33": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe34": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe35": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe36": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe37": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe35": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe36": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe37": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe38": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe39": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe40": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe41": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe42": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe43": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe44": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe45": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe46": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe47": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe39": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe40": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe41": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe42": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe43": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe44": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe45": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe46": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe47": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe48": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe49": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe50": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe51": [ { "direction": "in", "size_left": "159", "size_right": "0", "driver_value": "0" } ]
|
||||
"probe49": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe50": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe51": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe52": [ { "direction": "in", "size_left": "159", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"signal_clock": {
|
||||
|
||||
+150
-147
File diff suppressed because it is too large
Load Diff
+42
-41
@@ -56,57 +56,58 @@ clk : IN STD_LOGIC;
|
||||
|
||||
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe26 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe34 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe38 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe48 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe49 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe51 : IN STD_LOGIC_VECTOR(159 DOWNTO 0)
|
||||
probe49 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe50 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe52 : IN STD_LOGIC_VECTOR(159 DOWNTO 0)
|
||||
);
|
||||
END bd_e484_ila_lib_0;
|
||||
|
||||
|
||||
+131
-130
@@ -56,57 +56,58 @@ clk : IN STD_LOGIC;
|
||||
|
||||
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe26 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe34 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe38 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe48 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe49 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe51 : IN STD_LOGIC_VECTOR(159 DOWNTO 0)
|
||||
probe49 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe50 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe52 : IN STD_LOGIC_VECTOR(159 DOWNTO 0)
|
||||
);
|
||||
END bd_e484_ila_lib_0;
|
||||
|
||||
@@ -3225,58 +3226,58 @@ trig_in_ack : OUT STD_LOGIC;
|
||||
trig_out : OUT STD_LOGIC;
|
||||
trig_out_ack : IN STD_LOGIC;
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe26 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe34 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe38 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe48 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe49 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe50 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe51 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe52 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe49 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe50 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe51 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe52 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
|
||||
probe53 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe54 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe55 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
@@ -4258,7 +4259,7 @@ ATTRIBUTE X_CORE_INFO OF bd_e484_ila_lib_0_arch : ARCHITECTURE IS "ila,Vivado 20
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_e484_ila_lib_0_arch : ARCHITECTURE IS "bd_e484_ila_lib_0,ila_v6_2_13_ila,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_e484_ila_lib_0_arch : ARCHITECTURE IS "bd_e484_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=52,C_DATA_DEPTH=4096,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=2,C_PROBE2_WIDTH=8,C_PROBE3_WIDTH=2,C_PROBE4_WIDTH=8,C_PROBE5_WIDTH=2,C_PROBE6_WIDTH=2,C_PROBE7_WIDTH=2,C_PROBE8_WIDTH=32,C_PROBE9_WIDTH=2,C_PROBE10_WIDTH=32,C_PROBE11_WIDTH=4,C_PROBE12_WIDTH=2,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=2,C_PROBE15_WIDTH=2,C_PROBE16_WIDTH=2,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=160,C_PROBE19_WIDTH=2,C_PROBE20_WIDTH=32,C_PROBE21_WIDTH=2,C_PROBE22_WIDTH=4,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=4,C_PROBE25_WIDTH=3,C_PROBE26_WIDTH=3,C_PROBE27_WIDTH=2,C_PROBE28_WIDTH=32,C_PROBE29_WIDTH=2,C_PROBE30_WIDTH=4,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=4,C_PROBE33_WIDTH=3,C_PROBE34_WIDTH=3,C_PROBE35_WIDTH=2,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=2,C_PROBE38_WIDTH=2,C_PROBE39_WIDTH=32,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=2,C_PROBE42_WIDTH=32,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=4,C_PROBE45_WIDTH=2,C_PROBE46_WIDTH=3,C_PROBE47_WIDTH=2,C_PROBE48_WIDTH=2,C_PROBE49_WIDTH=3,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=160,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_e484_ila_lib_0_arch : ARCHITECTURE IS "bd_e484_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=53,C_DATA_DEPTH=4096,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE2_WIDTH=2,C_PROBE3_WIDTH=8,C_PROBE4_WIDTH=2,C_PROBE5_WIDTH=8,C_PROBE6_WIDTH=2,C_PROBE7_WIDTH=2,C_PROBE8_WIDTH=2,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=2,C_PROBE11_WIDTH=32,C_PROBE12_WIDTH=4,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=2,C_PROBE15_WIDTH=2,C_PROBE16_WIDTH=2,C_PROBE17_WIDTH=2,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=160,C_PROBE20_WIDTH=2,C_PROBE21_WIDTH=32,C_PROBE22_WIDTH=2,C_PROBE23_WIDTH=4,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=4,C_PROBE26_WIDTH=3,C_PROBE27_WIDTH=3,C_PROBE28_WIDTH=2,C_PROBE29_WIDTH=32,C_PROBE30_WIDTH=2,C_PROBE31_WIDTH=4,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=4,C_PROBE34_WIDTH=3,C_PROBE35_WIDTH=3,C_PROBE36_WIDTH=2,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=2,C_PROBE39_WIDTH=2,C_PROBE40_WIDTH=32,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=2,C_PROBE43_WIDTH=32,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=4,C_PROBE46_WIDTH=2,C_PROBE47_WIDTH=3,C_PROBE48_WIDTH=2,C_PROBE49_WIDTH=2,C_PROBE50_WIDTH=3,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=160,C_PROBE53_WIDTH=1,"&
|
||||
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
|
||||
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
|
||||
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
|
||||
@@ -4279,7 +4280,7 @@ ATTRIBUTE CORE_GENERATION_INFO OF bd_e484_ila_lib_0_arch : ARCHITECTURE IS "bd_e
|
||||
"C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,"&
|
||||
"C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,"&
|
||||
"C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1,C_PROBE0_TYPE=0,C_PROBE1_TYPE=0,C_PROBE2_TYPE=0,C_PROBE3_TYPE=0,C_PROBE4_TYPE=0,C_PROBE5_TYPE=0,"&
|
||||
"C_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=0,C_PROBE28_TYPE=0,C_PROBE29_TYPE=0,C_PROBE30_TYPE=0,C_PROBE31_TYPE=0,C_PROBE32_TYPE=0,C_PROBE33_TYPE=0,C_PROBE34_TYPE=0,C_PROBE35_TYPE=0,C_PROBE36_TYPE=0,C_PROBE37_TYPE=0,C_PROBE38_TYPE=0,C_PROBE39_TYPE=0,C_PROBE40_TYPE=0,C_PROBE41_TYPE=0,C_PROBE42_TYPE=0,C_PROBE43_TYPE=0,C_PROBE44_TYPE=0,C_PROBE45_TYPE=0,C_PROBE46_TYPE=0,C_PROBE47_TYPE=0,C_PROBE48_TYPE=0,C_PROBE49_TYPE=0,C_PROBE50_TYPE=0,C_PROBE51_TYPE=0,C_PROBE52_TYPE=1,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
|
||||
"C_PROBE6_TYPE=0,C_PROBE7_TYPE=0,C_PROBE8_TYPE=0,C_PROBE9_TYPE=0,C_PROBE10_TYPE=0,C_PROBE11_TYPE=0,C_PROBE12_TYPE=0,C_PROBE13_TYPE=0,C_PROBE14_TYPE=0,C_PROBE15_TYPE=0,C_PROBE16_TYPE=0,C_PROBE17_TYPE=0,C_PROBE18_TYPE=0,C_PROBE19_TYPE=0,C_PROBE20_TYPE=0,C_PROBE21_TYPE=0,C_PROBE22_TYPE=0,C_PROBE23_TYPE=0,C_PROBE24_TYPE=0,C_PROBE25_TYPE=0,C_PROBE26_TYPE=0,C_PROBE27_TYPE=0,C_PROBE28_TYPE=0,C_PROBE29_TYPE=0,C_PROBE30_TYPE=0,C_PROBE31_TYPE=0,C_PROBE32_TYPE=0,C_PROBE33_TYPE=0,C_PROBE34_TYPE=0,C_PROBE35_TYPE=0,C_PROBE36_TYPE=0,C_PROBE37_TYPE=0,C_PROBE38_TYPE=0,C_PROBE39_TYPE=0,C_PROBE40_TYPE=0,C_PROBE41_TYPE=0,C_PROBE42_TYPE=0,C_PROBE43_TYPE=0,C_PROBE44_TYPE=0,C_PROBE45_TYPE=0,C_PROBE46_TYPE=0,C_PROBE47_TYPE=0,C_PROBE48_TYPE=0,C_PROBE49_TYPE=0,C_PROBE50_TYPE=0,C_PROBE51_TYPE=0,C_PROBE52_TYPE=0,C_PROBE53_TYPE=1,C_PROBE54_TYPE=1,C_PROBE55_TYPE=1,C_PROBE56_TYPE=1,C_PROBE57_TYPE=1,C_PROBE58_TYPE=1,C_PROBE59_TYPE=1,C_PROBE60_TYPE=1,C_PROBE61_TYPE=1,C_PROBE62_TYPE=1,C_PROBE63_TYPE=1,C_PROBE64_TYPE=1,C_PROBE65_TYPE=1,C_PROBE66_TYPE=1,C_PROBE67_TYPE=1,C_PROBE68_TYPE=1,C_PROBE69_TYPE=1,C_PROBE70_TYPE=1,C_PROBE71_TYPE=1,C_PROBE72_TYPE=1,C_PROBE73_TYPE=1,C_PROBE74_TYPE=1,C_PROBE75_TYPE=1,C_PROBE76_TYPE=1,C_PROBE77_TYPE=1,C_PROBE78_TYPE=1,C_PROBE79_TYPE=1,C_PROBE80_TYPE=1,C_PROBE81_TYPE=1,C_PROBE82_TYPE=1,C_PROBE83_TYPE=1,C_PROBE84_TYPE=1,C_PROBE85_TYPE=1,C_PROBE86_TYPE=1,C_PROBE87_TYPE=1,C_PROBE88_TYPE=1,C_PROBE89_TYPE=1,C_PROBE90_TYPE=1,C_PROBE91_TYPE=1,C_PROBE92_TYPE=1,C_PROBE93_TYPE=1,C_PROBE94_TYPE=1,C_PROBE95_TYPE=1,C_PROBE96_TYPE=1,C_PROBE97_TYPE=1,C_PROBE98_TYPE=1,C_PROBE99_TYPE=1,C_PROBE100_TYPE=1,C_PROBE101_TYPE=1,C_PROBE102_TYPE=1,C_PROBE103_TYPE=1,C_PROBE104_TYPE=1,C_PROBE105_TYPE=1,"&
|
||||
"C_PROBE106_TYPE=1,C_PROBE107_TYPE=1,C_PROBE108_TYPE=1,C_PROBE109_TYPE=1,C_PROBE110_TYPE=1,C_PROBE111_TYPE=1,C_PROBE112_TYPE=1,C_PROBE113_TYPE=1,C_PROBE114_TYPE=1,C_PROBE115_TYPE=1,C_PROBE116_TYPE=1,C_PROBE117_TYPE=1,C_PROBE118_TYPE=1,C_PROBE119_TYPE=1,C_PROBE120_TYPE=1,C_PROBE121_TYPE=1,C_PROBE122_TYPE=1,C_PROBE123_TYPE=1,C_PROBE124_TYPE=1,C_PROBE125_TYPE=1,C_PROBE126_TYPE=1,C_PROBE127_TYPE=1,C_PROBE128_TYPE=1,C_PROBE129_TYPE=1,C_PROBE130_TYPE=1,C_PROBE131_TYPE=1,C_PROBE132_TYPE=1,C_PROBE133_TYPE=1,C_PROBE134_TYPE=1,C_PROBE135_TYPE=1,C_PROBE136_TYPE=1,C_PROBE137_TYPE=1,C_PROBE138_TYPE=1,C_PROBE139_TYPE=1,C_PROBE140_TYPE=1,C_PROBE141_TYPE=1,C_PROBE142_TYPE=1,C_PROBE143_TYPE=1,C_PROBE144_TYPE=1,C_PROBE145_TYPE=1,C_PROBE146_TYPE=1,C_PROBE147_TYPE=1,C_PROBE148_TYPE=1,C_PROBE149_TYPE=1,C_PROBE150_TYPE=1,C_PROBE151_TYPE=1,C_PROBE152_TYPE=1,C_PROBE153_TYPE=1,C_PROBE154_TYPE=1,C_PROBE155_TYPE=1,C_PROBE156_TYPE=1,C_PROBE157_TYPE=1,C_PROBE158_TYPE=1,C_PROBE159_TYPE=1,C_PROBE160_TYPE=1,C_PROBE161_TYPE=1,C_PROBE162_TYPE=1,C_PROBE163_TYPE=1,C_PROBE164_TYPE=1,C_PROBE165_TYPE=1,C_PROBE166_TYPE=1,C_PROBE167_TYPE=1,C_PROBE168_TYPE=1,C_PROBE169_TYPE=1,C_PROBE170_TYPE=1,C_PROBE171_TYPE=1,C_PROBE172_TYPE=1,C_PROBE173_TYPE=1,C_PROBE174_TYPE=1,C_PROBE175_TYPE=1,C_PROBE176_TYPE=1,C_PROBE177_TYPE=1,C_PROBE178_TYPE=1,C_PROBE179_TYPE=1,C_PROBE180_TYPE=1,C_PROBE181_TYPE=1,C_PROBE182_TYPE=1,C_PROBE183_TYPE=1,C_PROBE184_TYPE=1,C_PROBE185_TYPE=1,C_PROBE186_TYPE=1,C_PROBE187_TYPE=1,C_PROBE188_TYPE=1,C_PROBE189_TYPE=1,C_PROBE190_TYPE=1,C_PROBE191_TYPE=1,C_PROBE192_TYPE=1,C_PROBE193_TYPE=1,C_PROBE194_TYPE=1,C_PROBE195_TYPE=1,C_PROBE196_TYPE=1,C_PROBE197_TYPE=1,C_PROBE198_TYPE=1,C_PROBE199_TYPE=1,C_PROBE200_TYPE=1,C_PROBE201_TYPE=1,C_PROBE202_TYPE=1,C_PROBE203_TYPE=1,C_PROBE204_TYPE=1,C_PROBE205_TYPE=1,"&
|
||||
"C_PROBE206_TYPE=1,C_PROBE207_TYPE=1,C_PROBE208_TYPE=1,C_PROBE209_TYPE=1,C_PROBE210_TYPE=1,C_PROBE211_TYPE=1,C_PROBE212_TYPE=1,C_PROBE213_TYPE=1,C_PROBE214_TYPE=1,C_PROBE215_TYPE=1,C_PROBE216_TYPE=1,C_PROBE217_TYPE=1,C_PROBE218_TYPE=1,C_PROBE219_TYPE=1,C_PROBE220_TYPE=1,C_PROBE221_TYPE=1,C_PROBE222_TYPE=1,C_PROBE223_TYPE=1,C_PROBE224_TYPE=1,C_PROBE225_TYPE=1,C_PROBE226_TYPE=1,C_PROBE227_TYPE=1,C_PROBE228_TYPE=1,C_PROBE229_TYPE=1,C_PROBE230_TYPE=1,C_PROBE231_TYPE=1,C_PROBE232_TYPE=1,C_PROBE233_TYPE=1,C_PROBE234_TYPE=1,C_PROBE235_TYPE=1,C_PROBE236_TYPE=1,C_PROBE237_TYPE=1,C_PROBE238_TYPE=1,C_PROBE239_TYPE=1,C_PROBE240_TYPE=1,C_PROBE241_TYPE=1,C_PROBE242_TYPE=1,C_PROBE243_TYPE=1,C_PROBE244_TYPE=1,C_PROBE245_TYPE=1,C_PROBE246_TYPE=1,C_PROBE247_TYPE=1,C_PROBE248_TYPE=1,C_PROBE249_TYPE=1,C_PROBE250_TYPE=1,C_PROBE251_TYPE=1,C_PROBE252_TYPE=1,C_PROBE253_TYPE=1,C_PROBE254_TYPE=1,C_PROBE255_TYPE=1,C_PROBE256_TYPE=1,C_PROBE257_TYPE=1,C_PROBE258_TYPE=1,C_PROBE259_TYPE=1,C_PROBE260_TYPE=1,C_PROBE261_TYPE=1,C_PROBE262_TYPE=1,C_PROBE263_TYPE=1,C_PROBE264_TYPE=1,C_PROBE265_TYPE=1,C_PROBE266_TYPE=1,C_PROBE267_TYPE=1,C_PROBE268_TYPE=1,C_PROBE269_TYPE=1,C_PROBE270_TYPE=1,C_PROBE271_TYPE=1,C_PROBE272_TYPE=1,C_PROBE273_TYPE=1,C_PROBE274_TYPE=1,C_PROBE275_TYPE=1,C_PROBE276_TYPE=1,C_PROBE277_TYPE=1,C_PROBE278_TYPE=1,C_PROBE279_TYPE=1,C_PROBE280_TYPE=1,C_PROBE281_TYPE=1,C_PROBE282_TYPE=1,C_PROBE283_TYPE=1,C_PROBE284_TYPE=1,C_PROBE285_TYPE=1,C_PROBE286_TYPE=1,C_PROBE287_TYPE=1,C_PROBE288_TYPE=1,C_PROBE289_TYPE=1,C_PROBE290_TYPE=1,C_PROBE291_TYPE=1,C_PROBE292_TYPE=1,C_PROBE293_TYPE=1,C_PROBE294_TYPE=1,C_PROBE295_TYPE=1,C_PROBE296_TYPE=1,C_PROBE297_TYPE=1,C_PROBE298_TYPE=1,C_PROBE299_TYPE=1,C_PROBE300_TYPE=1,C_PROBE301_TYPE=1,C_PROBE302_TYPE=1,C_PROBE303_TYPE=1,C_PROBE304_TYPE=1,C_PROBE305_TYPE=1,"&
|
||||
"C_PROBE306_TYPE=1,C_PROBE307_TYPE=1,C_PROBE308_TYPE=1,C_PROBE309_TYPE=1,C_PROBE310_TYPE=1,C_PROBE311_TYPE=1,C_PROBE312_TYPE=1,C_PROBE313_TYPE=1,C_PROBE314_TYPE=1,C_PROBE315_TYPE=1,C_PROBE316_TYPE=1,C_PROBE317_TYPE=1,C_PROBE318_TYPE=1,C_PROBE319_TYPE=1,C_PROBE320_TYPE=1,C_PROBE321_TYPE=1,C_PROBE322_TYPE=1,C_PROBE323_TYPE=1,C_PROBE324_TYPE=1,C_PROBE325_TYPE=1,C_PROBE326_TYPE=1,C_PROBE327_TYPE=1,C_PROBE328_TYPE=1,C_PROBE329_TYPE=1,C_PROBE330_TYPE=1,C_PROBE331_TYPE=1,C_PROBE332_TYPE=1,C_PROBE333_TYPE=1,C_PROBE334_TYPE=1,C_PROBE335_TYPE=1,C_PROBE336_TYPE=1,C_PROBE337_TYPE=1,C_PROBE338_TYPE=1,C_PROBE339_TYPE=1,C_PROBE340_TYPE=1,C_PROBE341_TYPE=1,C_PROBE342_TYPE=1,C_PROBE343_TYPE=1,C_PROBE344_TYPE=1,C_PROBE345_TYPE=1,C_PROBE346_TYPE=1,C_PROBE347_TYPE=1,C_PROBE348_TYPE=1,C_PROBE349_TYPE=1,C_PROBE350_TYPE=1,C_PROBE351_TYPE=1,C_PROBE352_TYPE=1,C_PROBE353_TYPE=1,C_PROBE354_TYPE=1,C_PROBE355_TYPE=1,C_PROBE356_TYPE=1,C_PROBE357_TYPE=1,C_PROBE358_TYPE=1,C_PROBE359_TYPE=1,C_PROBE360_TYPE=1,C_PROBE361_TYPE=1,C_PROBE362_TYPE=1,C_PROBE363_TYPE=1,C_PROBE364_TYPE=1,C_PROBE365_TYPE=1,C_PROBE366_TYPE=1,C_PROBE367_TYPE=1,C_PROBE368_TYPE=1,C_PROBE369_TYPE=1,C_PROBE370_TYPE=1,C_PROBE371_TYPE=1,C_PROBE372_TYPE=1,C_PROBE373_TYPE=1,C_PROBE374_TYPE=1,C_PROBE375_TYPE=1,C_PROBE376_TYPE=1,C_PROBE377_TYPE=1,C_PROBE378_TYPE=1,C_PROBE379_TYPE=1,C_PROBE380_TYPE=1,C_PROBE381_TYPE=1,C_PROBE382_TYPE=1,C_PROBE383_TYPE=1,C_PROBE384_TYPE=1,C_PROBE385_TYPE=1,C_PROBE386_TYPE=1,C_PROBE387_TYPE=1,C_PROBE388_TYPE=1,C_PROBE389_TYPE=1,C_PROBE390_TYPE=1,C_PROBE391_TYPE=1,C_PROBE392_TYPE=1,C_PROBE393_TYPE=1,C_PROBE394_TYPE=1,C_PROBE395_TYPE=1,C_PROBE396_TYPE=1,C_PROBE397_TYPE=1,C_PROBE398_TYPE=1,C_PROBE399_TYPE=1,C_PROBE400_TYPE=1,C_PROBE401_TYPE=1,C_PROBE402_TYPE=1,C_PROBE403_TYPE=1,C_PROBE404_TYPE=1,C_PROBE405_TYPE=1,"&
|
||||
@@ -4305,7 +4306,7 @@ C_CORE_INFO2 => 0,
|
||||
C_CAPTURE_TYPE => 0,
|
||||
C_MU_TYPE => 0,
|
||||
C_TC_TYPE => 0,
|
||||
C_NUM_OF_PROBES => 52,
|
||||
C_NUM_OF_PROBES => 53,
|
||||
C_DATA_DEPTH => 4096,
|
||||
C_MAJOR_VERSION => 2023,
|
||||
C_MINOR_VERSION => 1,
|
||||
@@ -4329,58 +4330,58 @@ C_TIME_TAG_WIDTH => 32,
|
||||
C_ILA_CLK_FREQ => 100000000,
|
||||
|
||||
C_PROBE0_WIDTH => 1,
|
||||
C_PROBE1_WIDTH => 2,
|
||||
C_PROBE2_WIDTH => 8,
|
||||
C_PROBE3_WIDTH => 2,
|
||||
C_PROBE4_WIDTH => 8,
|
||||
C_PROBE5_WIDTH => 2,
|
||||
C_PROBE1_WIDTH => 1,
|
||||
C_PROBE2_WIDTH => 2,
|
||||
C_PROBE3_WIDTH => 8,
|
||||
C_PROBE4_WIDTH => 2,
|
||||
C_PROBE5_WIDTH => 8,
|
||||
C_PROBE6_WIDTH => 2,
|
||||
C_PROBE7_WIDTH => 2,
|
||||
C_PROBE8_WIDTH => 32,
|
||||
C_PROBE9_WIDTH => 2,
|
||||
C_PROBE10_WIDTH => 32,
|
||||
C_PROBE11_WIDTH => 4,
|
||||
C_PROBE12_WIDTH => 2,
|
||||
C_PROBE8_WIDTH => 2,
|
||||
C_PROBE9_WIDTH => 32,
|
||||
C_PROBE10_WIDTH => 2,
|
||||
C_PROBE11_WIDTH => 32,
|
||||
C_PROBE12_WIDTH => 4,
|
||||
C_PROBE13_WIDTH => 2,
|
||||
C_PROBE14_WIDTH => 2,
|
||||
C_PROBE15_WIDTH => 2,
|
||||
C_PROBE16_WIDTH => 2,
|
||||
C_PROBE17_WIDTH => 1,
|
||||
C_PROBE18_WIDTH => 160,
|
||||
C_PROBE19_WIDTH => 2,
|
||||
C_PROBE20_WIDTH => 32,
|
||||
C_PROBE21_WIDTH => 2,
|
||||
C_PROBE22_WIDTH => 4,
|
||||
C_PROBE23_WIDTH => 1,
|
||||
C_PROBE24_WIDTH => 4,
|
||||
C_PROBE25_WIDTH => 3,
|
||||
C_PROBE17_WIDTH => 2,
|
||||
C_PROBE18_WIDTH => 1,
|
||||
C_PROBE19_WIDTH => 160,
|
||||
C_PROBE20_WIDTH => 2,
|
||||
C_PROBE21_WIDTH => 32,
|
||||
C_PROBE22_WIDTH => 2,
|
||||
C_PROBE23_WIDTH => 4,
|
||||
C_PROBE24_WIDTH => 1,
|
||||
C_PROBE25_WIDTH => 4,
|
||||
C_PROBE26_WIDTH => 3,
|
||||
C_PROBE27_WIDTH => 2,
|
||||
C_PROBE28_WIDTH => 32,
|
||||
C_PROBE29_WIDTH => 2,
|
||||
C_PROBE30_WIDTH => 4,
|
||||
C_PROBE31_WIDTH => 1,
|
||||
C_PROBE32_WIDTH => 4,
|
||||
C_PROBE33_WIDTH => 3,
|
||||
C_PROBE27_WIDTH => 3,
|
||||
C_PROBE28_WIDTH => 2,
|
||||
C_PROBE29_WIDTH => 32,
|
||||
C_PROBE30_WIDTH => 2,
|
||||
C_PROBE31_WIDTH => 4,
|
||||
C_PROBE32_WIDTH => 1,
|
||||
C_PROBE33_WIDTH => 4,
|
||||
C_PROBE34_WIDTH => 3,
|
||||
C_PROBE35_WIDTH => 2,
|
||||
C_PROBE36_WIDTH => 1,
|
||||
C_PROBE37_WIDTH => 2,
|
||||
C_PROBE35_WIDTH => 3,
|
||||
C_PROBE36_WIDTH => 2,
|
||||
C_PROBE37_WIDTH => 1,
|
||||
C_PROBE38_WIDTH => 2,
|
||||
C_PROBE39_WIDTH => 32,
|
||||
C_PROBE40_WIDTH => 1,
|
||||
C_PROBE41_WIDTH => 2,
|
||||
C_PROBE42_WIDTH => 32,
|
||||
C_PROBE43_WIDTH => 1,
|
||||
C_PROBE44_WIDTH => 4,
|
||||
C_PROBE45_WIDTH => 2,
|
||||
C_PROBE46_WIDTH => 3,
|
||||
C_PROBE47_WIDTH => 2,
|
||||
C_PROBE39_WIDTH => 2,
|
||||
C_PROBE40_WIDTH => 32,
|
||||
C_PROBE41_WIDTH => 1,
|
||||
C_PROBE42_WIDTH => 2,
|
||||
C_PROBE43_WIDTH => 32,
|
||||
C_PROBE44_WIDTH => 1,
|
||||
C_PROBE45_WIDTH => 4,
|
||||
C_PROBE46_WIDTH => 2,
|
||||
C_PROBE47_WIDTH => 3,
|
||||
C_PROBE48_WIDTH => 2,
|
||||
C_PROBE49_WIDTH => 3,
|
||||
C_PROBE50_WIDTH => 1,
|
||||
C_PROBE51_WIDTH => 160,
|
||||
C_PROBE52_WIDTH => 1,
|
||||
C_PROBE49_WIDTH => 2,
|
||||
C_PROBE50_WIDTH => 3,
|
||||
C_PROBE51_WIDTH => 1,
|
||||
C_PROBE52_WIDTH => 160,
|
||||
C_PROBE53_WIDTH => 1,
|
||||
C_PROBE54_WIDTH => 1,
|
||||
C_PROBE55_WIDTH => 1,
|
||||
@@ -6428,7 +6429,7 @@ C_PROBE48_TYPE => 0,
|
||||
C_PROBE49_TYPE => 0,
|
||||
C_PROBE50_TYPE => 0,
|
||||
C_PROBE51_TYPE => 0,
|
||||
C_PROBE52_TYPE => 1,
|
||||
C_PROBE52_TYPE => 0,
|
||||
C_PROBE53_TYPE => 1,
|
||||
C_PROBE54_TYPE => 1,
|
||||
C_PROBE55_TYPE => 1,
|
||||
@@ -7461,7 +7462,7 @@ probe48 => probe48,
|
||||
probe49 => probe49,
|
||||
probe50 => probe50,
|
||||
probe51 => probe51,
|
||||
probe52 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe52 => probe52,
|
||||
probe53 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe54 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
probe55 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
|
||||
+4
-4
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:44 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:44 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:44 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:44 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:49 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:49 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -1276,7 +1276,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1296,7 +1296,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1319,7 +1319,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1339,7 +1339,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -1276,7 +1276,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1296,7 +1296,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1319,7 +1319,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1339,7 +1339,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:47 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:46 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:02 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Feb 12 19:34:48 UTC 2025</spirit:value>
|
||||
<spirit:value>Thu Feb 13 16:02:03 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+97
-92
@@ -70,6 +70,7 @@ entity bd_e484 is
|
||||
SLOT_1_AXI_wvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
@@ -83,57 +84,58 @@ architecture STRUCTURE of bd_e484 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 159 downto 0 )
|
||||
probe49 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 159 downto 0 )
|
||||
);
|
||||
end component bd_e484_ila_lib_0;
|
||||
component bd_e484_g_inst_0 is
|
||||
@@ -529,6 +531,7 @@ architecture STRUCTURE of bd_e484 is
|
||||
signal net_slot_1_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal net_slot_1_axi_wvalid : STD_LOGIC;
|
||||
signal probe0_1 : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal probe1_1 : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal resetn_1 : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
@@ -655,6 +658,7 @@ begin
|
||||
Conn_WVALID <= SLOT_0_AXI_wvalid;
|
||||
clk_1 <= clk;
|
||||
probe0_1(0) <= probe0(0);
|
||||
probe1_1(0) <= probe1(0);
|
||||
resetn_1 <= resetn;
|
||||
g_inst: component bd_e484_g_inst_0
|
||||
port map (
|
||||
@@ -775,57 +779,58 @@ ila_lib: component bd_e484_ila_lib_0
|
||||
port map (
|
||||
clk => clk_1,
|
||||
probe0(0) => probe0_1(0),
|
||||
probe1(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
probe10(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
probe11(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
probe12(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
|
||||
probe13(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
|
||||
probe14(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
|
||||
probe15(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe16(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
|
||||
probe17(0) => net_slot_0_apc_pc_asserted,
|
||||
probe18(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0),
|
||||
probe19(1 downto 0) => net_slot_1_axi_ar_cnt(1 downto 0),
|
||||
probe2(7 downto 0) => net_slot_0_axi_araddr(7 downto 0),
|
||||
probe20(31 downto 0) => net_slot_1_axi_araddr(31 downto 0),
|
||||
probe21(1 downto 0) => net_slot_1_axi_arburst(1 downto 0),
|
||||
probe22(3 downto 0) => net_slot_1_axi_arcache(3 downto 0),
|
||||
probe23(0) => net_slot_1_axi_arid(0),
|
||||
probe24(3 downto 0) => net_slot_1_axi_arlen(3 downto 0),
|
||||
probe25(2 downto 0) => net_slot_1_axi_arprot(2 downto 0),
|
||||
probe26(2 downto 0) => net_slot_1_axi_arsize(2 downto 0),
|
||||
probe27(1 downto 0) => net_slot_1_axi_aw_cnt(1 downto 0),
|
||||
probe28(31 downto 0) => net_slot_1_axi_awaddr(31 downto 0),
|
||||
probe29(1 downto 0) => net_slot_1_axi_awburst(1 downto 0),
|
||||
probe3(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
probe30(3 downto 0) => net_slot_1_axi_awcache(3 downto 0),
|
||||
probe31(0) => net_slot_1_axi_awid(0),
|
||||
probe32(3 downto 0) => net_slot_1_axi_awlen(3 downto 0),
|
||||
probe33(2 downto 0) => net_slot_1_axi_awprot(2 downto 0),
|
||||
probe34(2 downto 0) => net_slot_1_axi_awsize(2 downto 0),
|
||||
probe35(1 downto 0) => net_slot_1_axi_b_cnt(1 downto 0),
|
||||
probe36(0) => net_slot_1_axi_bid(0),
|
||||
probe37(1 downto 0) => net_slot_1_axi_bresp(1 downto 0),
|
||||
probe38(1 downto 0) => net_slot_1_axi_r_cnt(1 downto 0),
|
||||
probe39(31 downto 0) => net_slot_1_axi_rdata(31 downto 0),
|
||||
probe4(7 downto 0) => net_slot_0_axi_awaddr(7 downto 0),
|
||||
probe40(0) => net_slot_1_axi_rid(0),
|
||||
probe41(1 downto 0) => net_slot_1_axi_rresp(1 downto 0),
|
||||
probe42(31 downto 0) => net_slot_1_axi_wdata(31 downto 0),
|
||||
probe43(0) => net_slot_1_axi_wid(0),
|
||||
probe44(3 downto 0) => net_slot_1_axi_wstrb(3 downto 0),
|
||||
probe45(1 downto 0) => net_slot_1_axi_aw_ctrl(1 downto 0),
|
||||
probe46(2 downto 0) => net_slot_1_axi_w_ctrl(2 downto 0),
|
||||
probe47(1 downto 0) => net_slot_1_axi_b_ctrl(1 downto 0),
|
||||
probe48(1 downto 0) => net_slot_1_axi_ar_ctrl(1 downto 0),
|
||||
probe49(2 downto 0) => net_slot_1_axi_r_ctrl(2 downto 0),
|
||||
probe5(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
probe50(0) => net_slot_1_apc_pc_asserted,
|
||||
probe51(159 downto 0) => net_slot_1_apc_pc_status(159 downto 0),
|
||||
probe6(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
probe7(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
probe8(31 downto 0) => net_slot_0_axi_rdata(31 downto 0),
|
||||
probe9(1 downto 0) => net_slot_0_axi_rresp(1 downto 0)
|
||||
probe1(0) => probe1_1(0),
|
||||
probe10(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
|
||||
probe11(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
probe12(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
probe13(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
|
||||
probe14(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
|
||||
probe15(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
|
||||
probe16(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe17(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
|
||||
probe18(0) => net_slot_0_apc_pc_asserted,
|
||||
probe19(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0),
|
||||
probe2(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
probe20(1 downto 0) => net_slot_1_axi_ar_cnt(1 downto 0),
|
||||
probe21(31 downto 0) => net_slot_1_axi_araddr(31 downto 0),
|
||||
probe22(1 downto 0) => net_slot_1_axi_arburst(1 downto 0),
|
||||
probe23(3 downto 0) => net_slot_1_axi_arcache(3 downto 0),
|
||||
probe24(0) => net_slot_1_axi_arid(0),
|
||||
probe25(3 downto 0) => net_slot_1_axi_arlen(3 downto 0),
|
||||
probe26(2 downto 0) => net_slot_1_axi_arprot(2 downto 0),
|
||||
probe27(2 downto 0) => net_slot_1_axi_arsize(2 downto 0),
|
||||
probe28(1 downto 0) => net_slot_1_axi_aw_cnt(1 downto 0),
|
||||
probe29(31 downto 0) => net_slot_1_axi_awaddr(31 downto 0),
|
||||
probe3(7 downto 0) => net_slot_0_axi_araddr(7 downto 0),
|
||||
probe30(1 downto 0) => net_slot_1_axi_awburst(1 downto 0),
|
||||
probe31(3 downto 0) => net_slot_1_axi_awcache(3 downto 0),
|
||||
probe32(0) => net_slot_1_axi_awid(0),
|
||||
probe33(3 downto 0) => net_slot_1_axi_awlen(3 downto 0),
|
||||
probe34(2 downto 0) => net_slot_1_axi_awprot(2 downto 0),
|
||||
probe35(2 downto 0) => net_slot_1_axi_awsize(2 downto 0),
|
||||
probe36(1 downto 0) => net_slot_1_axi_b_cnt(1 downto 0),
|
||||
probe37(0) => net_slot_1_axi_bid(0),
|
||||
probe38(1 downto 0) => net_slot_1_axi_bresp(1 downto 0),
|
||||
probe39(1 downto 0) => net_slot_1_axi_r_cnt(1 downto 0),
|
||||
probe4(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
probe40(31 downto 0) => net_slot_1_axi_rdata(31 downto 0),
|
||||
probe41(0) => net_slot_1_axi_rid(0),
|
||||
probe42(1 downto 0) => net_slot_1_axi_rresp(1 downto 0),
|
||||
probe43(31 downto 0) => net_slot_1_axi_wdata(31 downto 0),
|
||||
probe44(0) => net_slot_1_axi_wid(0),
|
||||
probe45(3 downto 0) => net_slot_1_axi_wstrb(3 downto 0),
|
||||
probe46(1 downto 0) => net_slot_1_axi_aw_ctrl(1 downto 0),
|
||||
probe47(2 downto 0) => net_slot_1_axi_w_ctrl(2 downto 0),
|
||||
probe48(1 downto 0) => net_slot_1_axi_b_ctrl(1 downto 0),
|
||||
probe49(1 downto 0) => net_slot_1_axi_ar_ctrl(1 downto 0),
|
||||
probe5(7 downto 0) => net_slot_0_axi_awaddr(7 downto 0),
|
||||
probe50(2 downto 0) => net_slot_1_axi_r_ctrl(2 downto 0),
|
||||
probe51(0) => net_slot_1_apc_pc_asserted,
|
||||
probe52(159 downto 0) => net_slot_1_apc_pc_status(159 downto 0),
|
||||
probe6(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
probe7(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
probe8(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
probe9(31 downto 0) => net_slot_0_axi_rdata(31 downto 0)
|
||||
);
|
||||
slot_0_apc: component bd_e484_slot_0_apc_0
|
||||
port map (
|
||||
|
||||
+97
-92
@@ -70,6 +70,7 @@ entity bd_e484 is
|
||||
SLOT_1_AXI_wvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
@@ -83,57 +84,58 @@ architecture STRUCTURE of bd_e484 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 159 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 159 downto 0 )
|
||||
probe49 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe50 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe51 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe52 : in STD_LOGIC_VECTOR ( 159 downto 0 )
|
||||
);
|
||||
end component bd_e484_ila_lib_0;
|
||||
component bd_e484_g_inst_0 is
|
||||
@@ -529,6 +531,7 @@ architecture STRUCTURE of bd_e484 is
|
||||
signal net_slot_1_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal net_slot_1_axi_wvalid : STD_LOGIC;
|
||||
signal probe0_1 : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal probe1_1 : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal resetn_1 : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
@@ -655,6 +658,7 @@ begin
|
||||
Conn_WVALID <= SLOT_0_AXI_wvalid;
|
||||
clk_1 <= clk;
|
||||
probe0_1(0) <= probe0(0);
|
||||
probe1_1(0) <= probe1(0);
|
||||
resetn_1 <= resetn;
|
||||
g_inst: component bd_e484_g_inst_0
|
||||
port map (
|
||||
@@ -775,57 +779,58 @@ ila_lib: component bd_e484_ila_lib_0
|
||||
port map (
|
||||
clk => clk_1,
|
||||
probe0(0) => probe0_1(0),
|
||||
probe1(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
probe10(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
probe11(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
probe12(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
|
||||
probe13(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
|
||||
probe14(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
|
||||
probe15(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe16(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
|
||||
probe17(0) => net_slot_0_apc_pc_asserted,
|
||||
probe18(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0),
|
||||
probe19(1 downto 0) => net_slot_1_axi_ar_cnt(1 downto 0),
|
||||
probe2(7 downto 0) => net_slot_0_axi_araddr(7 downto 0),
|
||||
probe20(31 downto 0) => net_slot_1_axi_araddr(31 downto 0),
|
||||
probe21(1 downto 0) => net_slot_1_axi_arburst(1 downto 0),
|
||||
probe22(3 downto 0) => net_slot_1_axi_arcache(3 downto 0),
|
||||
probe23(0) => net_slot_1_axi_arid(0),
|
||||
probe24(3 downto 0) => net_slot_1_axi_arlen(3 downto 0),
|
||||
probe25(2 downto 0) => net_slot_1_axi_arprot(2 downto 0),
|
||||
probe26(2 downto 0) => net_slot_1_axi_arsize(2 downto 0),
|
||||
probe27(1 downto 0) => net_slot_1_axi_aw_cnt(1 downto 0),
|
||||
probe28(31 downto 0) => net_slot_1_axi_awaddr(31 downto 0),
|
||||
probe29(1 downto 0) => net_slot_1_axi_awburst(1 downto 0),
|
||||
probe3(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
probe30(3 downto 0) => net_slot_1_axi_awcache(3 downto 0),
|
||||
probe31(0) => net_slot_1_axi_awid(0),
|
||||
probe32(3 downto 0) => net_slot_1_axi_awlen(3 downto 0),
|
||||
probe33(2 downto 0) => net_slot_1_axi_awprot(2 downto 0),
|
||||
probe34(2 downto 0) => net_slot_1_axi_awsize(2 downto 0),
|
||||
probe35(1 downto 0) => net_slot_1_axi_b_cnt(1 downto 0),
|
||||
probe36(0) => net_slot_1_axi_bid(0),
|
||||
probe37(1 downto 0) => net_slot_1_axi_bresp(1 downto 0),
|
||||
probe38(1 downto 0) => net_slot_1_axi_r_cnt(1 downto 0),
|
||||
probe39(31 downto 0) => net_slot_1_axi_rdata(31 downto 0),
|
||||
probe4(7 downto 0) => net_slot_0_axi_awaddr(7 downto 0),
|
||||
probe40(0) => net_slot_1_axi_rid(0),
|
||||
probe41(1 downto 0) => net_slot_1_axi_rresp(1 downto 0),
|
||||
probe42(31 downto 0) => net_slot_1_axi_wdata(31 downto 0),
|
||||
probe43(0) => net_slot_1_axi_wid(0),
|
||||
probe44(3 downto 0) => net_slot_1_axi_wstrb(3 downto 0),
|
||||
probe45(1 downto 0) => net_slot_1_axi_aw_ctrl(1 downto 0),
|
||||
probe46(2 downto 0) => net_slot_1_axi_w_ctrl(2 downto 0),
|
||||
probe47(1 downto 0) => net_slot_1_axi_b_ctrl(1 downto 0),
|
||||
probe48(1 downto 0) => net_slot_1_axi_ar_ctrl(1 downto 0),
|
||||
probe49(2 downto 0) => net_slot_1_axi_r_ctrl(2 downto 0),
|
||||
probe5(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
probe50(0) => net_slot_1_apc_pc_asserted,
|
||||
probe51(159 downto 0) => net_slot_1_apc_pc_status(159 downto 0),
|
||||
probe6(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
probe7(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
probe8(31 downto 0) => net_slot_0_axi_rdata(31 downto 0),
|
||||
probe9(1 downto 0) => net_slot_0_axi_rresp(1 downto 0)
|
||||
probe1(0) => probe1_1(0),
|
||||
probe10(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
|
||||
probe11(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
probe12(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
probe13(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
|
||||
probe14(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
|
||||
probe15(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
|
||||
probe16(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe17(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
|
||||
probe18(0) => net_slot_0_apc_pc_asserted,
|
||||
probe19(159 downto 0) => net_slot_0_apc_pc_status(159 downto 0),
|
||||
probe2(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
probe20(1 downto 0) => net_slot_1_axi_ar_cnt(1 downto 0),
|
||||
probe21(31 downto 0) => net_slot_1_axi_araddr(31 downto 0),
|
||||
probe22(1 downto 0) => net_slot_1_axi_arburst(1 downto 0),
|
||||
probe23(3 downto 0) => net_slot_1_axi_arcache(3 downto 0),
|
||||
probe24(0) => net_slot_1_axi_arid(0),
|
||||
probe25(3 downto 0) => net_slot_1_axi_arlen(3 downto 0),
|
||||
probe26(2 downto 0) => net_slot_1_axi_arprot(2 downto 0),
|
||||
probe27(2 downto 0) => net_slot_1_axi_arsize(2 downto 0),
|
||||
probe28(1 downto 0) => net_slot_1_axi_aw_cnt(1 downto 0),
|
||||
probe29(31 downto 0) => net_slot_1_axi_awaddr(31 downto 0),
|
||||
probe3(7 downto 0) => net_slot_0_axi_araddr(7 downto 0),
|
||||
probe30(1 downto 0) => net_slot_1_axi_awburst(1 downto 0),
|
||||
probe31(3 downto 0) => net_slot_1_axi_awcache(3 downto 0),
|
||||
probe32(0) => net_slot_1_axi_awid(0),
|
||||
probe33(3 downto 0) => net_slot_1_axi_awlen(3 downto 0),
|
||||
probe34(2 downto 0) => net_slot_1_axi_awprot(2 downto 0),
|
||||
probe35(2 downto 0) => net_slot_1_axi_awsize(2 downto 0),
|
||||
probe36(1 downto 0) => net_slot_1_axi_b_cnt(1 downto 0),
|
||||
probe37(0) => net_slot_1_axi_bid(0),
|
||||
probe38(1 downto 0) => net_slot_1_axi_bresp(1 downto 0),
|
||||
probe39(1 downto 0) => net_slot_1_axi_r_cnt(1 downto 0),
|
||||
probe4(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
probe40(31 downto 0) => net_slot_1_axi_rdata(31 downto 0),
|
||||
probe41(0) => net_slot_1_axi_rid(0),
|
||||
probe42(1 downto 0) => net_slot_1_axi_rresp(1 downto 0),
|
||||
probe43(31 downto 0) => net_slot_1_axi_wdata(31 downto 0),
|
||||
probe44(0) => net_slot_1_axi_wid(0),
|
||||
probe45(3 downto 0) => net_slot_1_axi_wstrb(3 downto 0),
|
||||
probe46(1 downto 0) => net_slot_1_axi_aw_ctrl(1 downto 0),
|
||||
probe47(2 downto 0) => net_slot_1_axi_w_ctrl(2 downto 0),
|
||||
probe48(1 downto 0) => net_slot_1_axi_b_ctrl(1 downto 0),
|
||||
probe49(1 downto 0) => net_slot_1_axi_ar_ctrl(1 downto 0),
|
||||
probe5(7 downto 0) => net_slot_0_axi_awaddr(7 downto 0),
|
||||
probe50(2 downto 0) => net_slot_1_axi_r_ctrl(2 downto 0),
|
||||
probe51(0) => net_slot_1_apc_pc_asserted,
|
||||
probe52(159 downto 0) => net_slot_1_apc_pc_status(159 downto 0),
|
||||
probe6(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
probe7(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
probe8(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
probe9(31 downto 0) => net_slot_0_axi_rdata(31 downto 0)
|
||||
);
|
||||
slot_0_apc: component bd_e484_slot_0_apc_0
|
||||
port map (
|
||||
|
||||
+3
@@ -57,6 +57,7 @@ ENTITY axi_crc_dma_syn_1_system_ila_0_2 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
@@ -125,6 +126,7 @@ ARCHITECTURE axi_crc_dma_syn_1_system_ila_0_2_arch OF axi_crc_dma_syn_1_system_i
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
@@ -257,6 +259,7 @@ BEGIN
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe0 => probe0,
|
||||
probe1 => probe1,
|
||||
SLOT_0_AXI_awaddr => SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
|
||||
+4
-1
@@ -57,6 +57,7 @@ ENTITY axi_crc_dma_syn_1_system_ila_0_2 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
@@ -125,6 +126,7 @@ ARCHITECTURE axi_crc_dma_syn_1_system_ila_0_2_arch OF axi_crc_dma_syn_1_system_i
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
@@ -293,7 +295,7 @@ ARCHITECTURE axi_crc_dma_syn_1_system_ila_0_2_arch OF axi_crc_dma_syn_1_system_i
|
||||
"C_PROBE108_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PRO" &
|
||||
"BE81_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C" &
|
||||
"_PROBE52_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH" &
|
||||
"=1,C_PROBE24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=4096,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=" &
|
||||
"=1,C_PROBE24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=4096,C_NUM_OF_PROBES=2,C_XLNX_HW_PROBE_INFO=" &
|
||||
"DEFAULT,Component_Name=axi_crc_dma_syn_1_system_ila_0_2,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_" &
|
||||
"CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PRO" &
|
||||
"BE984_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PRO" &
|
||||
@@ -422,6 +424,7 @@ BEGIN
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe0 => probe0,
|
||||
probe1 => probe1,
|
||||
SLOT_0_AXI_awaddr => SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
|
||||
+5
-2
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Feb 12 20:34:33 2025
|
||||
--Date : Thu Feb 13 17:01:58 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_syn_1.bd
|
||||
--Design : axi_crc_dma_syn_1
|
||||
@@ -2063,6 +2063,7 @@ architecture STRUCTURE of axi_crc_dma_syn_1 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
@@ -2184,11 +2185,12 @@ architecture STRUCTURE of axi_crc_dma_syn_1 is
|
||||
signal axi_crc_dma_INTERRUPT1 : STD_LOGIC;
|
||||
attribute DEBUG : string;
|
||||
attribute DEBUG of axi_crc_dma_INTERRUPT1 : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axi_crc_dma_INTERRUPT1 : signal is std.standard.true;
|
||||
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axi_interconnect_0_M00_AXI_ARADDR : signal is "axi_interconnect_0_M00_AXI xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DEBUG of axi_interconnect_0_M00_AXI_ARADDR : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axi_interconnect_0_M00_AXI_ARADDR : signal is std.standard.true;
|
||||
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axi_interconnect_0_M00_AXI_ARPROT : signal is "axi_interconnect_0_M00_AXI xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
@@ -2647,6 +2649,7 @@ system_ila_0: component axi_crc_dma_syn_1_system_ila_0_2
|
||||
SLOT_1_AXI_wvalid => axis_dma_0_M_AXI_WVALID,
|
||||
clk => processing_system7_0_FCLK_CLK0,
|
||||
probe0(0) => rst_ps7_0_100M_peripheral_aresetn(0),
|
||||
probe1(0) => axi_crc_dma_INTERRUPT1,
|
||||
resetn => rst_ps7_0_100M_peripheral_aresetn(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
|
||||
+5
-2
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Wed Feb 12 20:34:32 2025
|
||||
--Date : Thu Feb 13 17:01:58 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_syn_1.bd
|
||||
--Design : axi_crc_dma_syn_1
|
||||
@@ -2063,6 +2063,7 @@ architecture STRUCTURE of axi_crc_dma_syn_1 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
@@ -2184,11 +2185,12 @@ architecture STRUCTURE of axi_crc_dma_syn_1 is
|
||||
signal axi_crc_dma_INTERRUPT1 : STD_LOGIC;
|
||||
attribute DEBUG : string;
|
||||
attribute DEBUG of axi_crc_dma_INTERRUPT1 : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axi_crc_dma_INTERRUPT1 : signal is std.standard.true;
|
||||
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axi_interconnect_0_M00_AXI_ARADDR : signal is "axi_interconnect_0_M00_AXI xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DEBUG of axi_interconnect_0_M00_AXI_ARADDR : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axi_interconnect_0_M00_AXI_ARADDR : signal is std.standard.true;
|
||||
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axi_interconnect_0_M00_AXI_ARPROT : signal is "axi_interconnect_0_M00_AXI xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
@@ -2647,6 +2649,7 @@ system_ila_0: component axi_crc_dma_syn_1_system_ila_0_2
|
||||
SLOT_1_AXI_wvalid => axis_dma_0_M_AXI_WVALID,
|
||||
clk => processing_system7_0_FCLK_CLK0,
|
||||
probe0(0) => rst_ps7_0_100M_peripheral_aresetn(0),
|
||||
probe1(0) => axi_crc_dma_INTERRUPT1,
|
||||
resetn => rst_ps7_0_100M_peripheral_aresetn(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
|
||||
+3
-3
@@ -537,7 +537,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>bcb275e9</spirit:value>
|
||||
<spirit:value>0df542c6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -550,7 +550,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>bcb275e9</spirit:value>
|
||||
<spirit:value>0df542c6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1491,7 +1491,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-02-12T19:33:35Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-02-13T16:00:08Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
@@ -617,7 +617,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>fee45eb9</spirit:value>
|
||||
<spirit:value>e9142791</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -630,7 +630,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>fee45eb9</spirit:value>
|
||||
<spirit:value>e9142791</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1861,7 +1861,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-02-12T19:32:29Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-02-13T15:55:11Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_Layers":"/axi_crc_dma_ip_wrapp_0_INTERRUPT:true|",
|
||||
"Default View_ScaleFactor":"1.71064",
|
||||
"Default View_TopLeft":"11,-108",
|
||||
"Default View_TopLeft":"11,-109",
|
||||
"Display-PortTypeInterrupt":"true",
|
||||
"Display-PortTypeOthers":"true",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
|
||||
+9
-2
@@ -2716,11 +2716,14 @@
|
||||
"value": "2"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "1"
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE0_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT": {
|
||||
"value": "1"
|
||||
},
|
||||
@@ -3429,11 +3432,15 @@
|
||||
"axi_crc_dma_INTERRUPT1": {
|
||||
"ports": [
|
||||
"axi_crc_dma_ip_wrapp_0/INTERRUPT",
|
||||
"PS/IRQ_F2P"
|
||||
"PS/IRQ_F2P",
|
||||
"system_ila_0/probe1"
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
+3
-2
@@ -1546,7 +1546,7 @@
|
||||
"C_PROBE4_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE3_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE2_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE1_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE1_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE0_TYPE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_PROBE1023_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_PROBE1022_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -2572,7 +2572,7 @@
|
||||
"C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"C_DATA_DEPTH": [ { "value": "4096", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OF_PROBES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OF_PROBES": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axi_crc_dma_syn_1_system_ila_0_2", "resolve_type": "user", "usage": "all" } ],
|
||||
"C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -3866,6 +3866,7 @@
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"probe0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"probe1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXI_awaddr": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXI_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXI_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
|
||||
+14
-14
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"-104,-202",
|
||||
"Default View_TopLeft":"78,-45",
|
||||
"Display-PortTypeClock":"true",
|
||||
"Display-PortTypeInterrupt":"true",
|
||||
"Display-PortTypeOthers":"true",
|
||||
@@ -73,20 +73,20 @@ pagesize -hier PS -db -bbox -sgen 360 30 1890 650
|
||||
"Reduced Jogs_TopLeft":"-70,3",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 4 -x 830 -y 60 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 4 -x 830 -y 90 -defaultsOSRD
|
||||
preplace inst PS -pg 1 -lvl 2 -x 460 -y 110 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 3 -x 720 -y 190 -defaultsOSRD
|
||||
preplace port DDR -pg 1 -lvl 4 -x 850 -y 60 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 4 -x 850 -y 90 -defaultsOSRD
|
||||
preplace inst PS -pg 1 -lvl 2 -x 470 -y 110 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 3 -x 740 -y 190 -defaultsOSRD
|
||||
preplace inst axi_crc_dma_ip_wrapp_0 -pg 1 -lvl 1 -x 170 -y 110 -defaultsOSRD
|
||||
preplace netloc axi_crc_dma_INTERRUPT1 1 1 1 N 120
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 50 210 NJ 210 590
|
||||
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 3 40 220 NJ 220 600
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 3 50 10 NJ 10 610
|
||||
preplace netloc axis_dma_0_M_AXI 1 1 2 330 200 610
|
||||
preplace netloc processing_system7_0_DDR 1 2 2 NJ 70 810
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 2 2 NJ 90 N
|
||||
levelinfo -pg 1 0 170 460 720 830
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 940 290
|
||||
preplace netloc axi_crc_dma_INTERRUPT1 1 1 2 330 220 N
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 40 210 NJ 210 620
|
||||
preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 0 3 50 230 NJ 230 610
|
||||
preplace netloc axi_interconnect_0_M00_AXI 1 0 3 40 10 NJ 10 630
|
||||
preplace netloc axis_dma_0_M_AXI 1 1 2 340 200 600
|
||||
preplace netloc processing_system7_0_DDR 1 2 2 NJ 70 830
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 2 2 620J 80 830
|
||||
levelinfo -pg 1 0 170 470 740 850
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 960 300
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
@@ -112,12 +112,12 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_ip.bd" FileRelPathName="ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_ip_axis_dma_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_ip.bd" FileRelPathName="ip/axi_crc_dma_ip_axis_crc_0_0/axi_crc_dma_ip_axis_crc_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_ip_axis_crc_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_ip.bd" FileRelPathName="ip/axi_crc_dma_ip_axis_dma_0_0/axi_crc_dma_ip_axis_dma_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_ip_axis_dma_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/axi_crc_dma_ip/hdl/axi_crc_dma_ip_wrapper.vhd">
|
||||
<FileInfo>
|
||||
@@ -134,9 +134,6 @@
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_syn_1.bd" FileRelPathName="ip/axi_crc_dma_syn_1_system_ila_0_2/axi_crc_dma_syn_1_system_ila_0_2.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_syn_1_system_ila_0_2"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axi_crc_dma_syn_1.bd" FileRelPathName="ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="axi_crc_dma_syn_1_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -275,12 +272,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_crc_dma_syn_1_system_ila_0_2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crc_dma_syn_1_system_ila_0_2" RelGenDir="$PGENDIR/axi_crc_dma_syn_1_system_ila_0_2">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_crc_dma_syn_1_system_ila_0_2"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0" RelGenDir="$PGENDIR/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0"/>
|
||||
@@ -349,18 +340,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_system_ila_0_2_synth_1" Type="Ft3:Synth" SrcSet="axi_crc_dma_syn_1_system_ila_0_2" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_system_ila_0_2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crc_dma_syn_1_system_ila_0_2_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_system_ila_0_2_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_system_ila_0_2_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
@@ -446,25 +425,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_system_ila_0_2_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_system_ila_0_2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crc_dma_syn_1_system_ila_0_2_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_system_ila_0_2_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_system_ila_0_2_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axi_crc_dma_syn_1_axi_crc_dma_ip_wrapp_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
|
||||
@@ -322,7 +322,7 @@ begin
|
||||
-- Burstlaenge setzen
|
||||
if (data_cnt+1) >= MAX_BURSTLEN then
|
||||
M_AXI_ARLEN <= std_logic_vector(to_unsigned(MAX_BURSTLEN-1, 4));
|
||||
read_addr_cnt := read_addr_cnt + to_unsigned(MAX_BURSTLEN, 32); -- Adresse inkrementieren
|
||||
read_addr_cnt := read_addr_cnt + to_unsigned(4*MAX_BURSTLEN, 32); -- Adresse inkrementieren
|
||||
else
|
||||
M_AXI_ARLEN <= std_logic_vector(data_cnt(3 downto 0));
|
||||
end if;
|
||||
@@ -456,7 +456,7 @@ begin
|
||||
if unsigned(S_AXIS_NUM_AVAIL) >= MAX_BURSTLEN then
|
||||
burst_data_cnt := MAX_BURSTLEN - 1;
|
||||
M_AXI_AWLEN <= std_logic_vector(to_unsigned(MAX_BURSTLEN-1, 4));
|
||||
write_addr := write_addr + to_unsigned(MAX_BURSTLEN, 32); -- increment address
|
||||
write_addr := write_addr + to_unsigned(4*MAX_BURSTLEN, 32); -- increment address
|
||||
else
|
||||
M_AXI_AWLEN <= std_logic_vector(data_cnt(3 downto 0));
|
||||
burst_data_cnt := to_integer(data_cnt);
|
||||
|
||||
+142
-76
@@ -10,125 +10,191 @@
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <time.h>
|
||||
|
||||
#include "axi_crc_dma.h"
|
||||
#include "gip.h"
|
||||
|
||||
#define DEBUG 1
|
||||
|
||||
#define PACKET_SIZE 3
|
||||
#define NUMBER_PACKETS 2
|
||||
#define NUMBER_PACKETS 8
|
||||
|
||||
#define DATA_SIZE ((PACKET_SIZE)*(NUMBER_PACKETS))
|
||||
|
||||
// Berechnen einer 32 Bit CRC-Pruefsumme mit allen Parametern
|
||||
uint32_t calcCRC32(
|
||||
uint8_t* inBytes,
|
||||
size_t size,
|
||||
uint32_t polynomial,
|
||||
uint32_t initialValue,
|
||||
uint32_t finalXOR,
|
||||
uint8_t inputReflected,
|
||||
uint8_t outputReflected
|
||||
uint8_t* inBytes,
|
||||
size_t size,
|
||||
uint32_t polynomial,
|
||||
uint32_t initialValue,
|
||||
uint32_t finalXOR,
|
||||
uint8_t inputReflected,
|
||||
uint8_t outputReflected
|
||||
);
|
||||
|
||||
// UIO & pointers
|
||||
int fdCRC = open("/dev/uio0", O_RDWR);
|
||||
int fdMMVS = open("/dev/uio1", O_RDWR);
|
||||
int fdMem = open("/dev/uio16", O_RDWR);
|
||||
PCRC_Typedef CRC = (PCRC_Typedef)mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fdCRC, 0);
|
||||
PGIP_AXI_2D_MM2VS mmvs = (PGIP_AXI_2D_MM2VS)mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fdMMVS, 0);
|
||||
uint8_t* pMem = (uint8_t*)mmap(NULL, 0x20000000, PROT_READ | PROT_WRITE, MAP_SHARED, fdMem, 0);
|
||||
|
||||
// Speicherbereiche fuer Daten anlegen
|
||||
//volatile static uint32_t data[NUMBER_PACKETS][PACKET_SIZE];
|
||||
//volatile static uint32_t data_CRC[NUMBER_PACKETS][PACKET_SIZE+1];
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
printf("Start Program\n");
|
||||
// some established CRC32 Parameter sets. Source: https://reveng.sourceforge.io/crc-catalogue/ (13.02.2025)
|
||||
const CrcParameterSet CRC32_AIXM = {
|
||||
.Polynomial = 0x814141ab,
|
||||
.InitalValue = 0x0,
|
||||
.FinalXOR = 0x0,
|
||||
.InputReflected = false,
|
||||
.OutputReflected = false
|
||||
};
|
||||
|
||||
uint32_t* data = (uint32_t*) pMem;
|
||||
uint32_t* data_CRC = data + (NUMBER_PACKETS*PACKET_SIZE);
|
||||
const CrcParameterSet CRC32_ISO_HDLC = {
|
||||
.Polynomial = 0x04c11db7,
|
||||
.InitalValue = 0xFFFFFFFF,
|
||||
.FinalXOR = 0xFFFFFFFF,
|
||||
.InputReflected = true,
|
||||
.OutputReflected = true
|
||||
};
|
||||
|
||||
printf("pMem: %x\ndata: %x\ndata_CRC: %x\n\n", pMem, data, data_CRC);
|
||||
const CrcParameterSet CRC32_ISCSI = {
|
||||
.Polynomial = 0x1edc6f41 ,
|
||||
.InitalValue = 0xFFFFFFFF ,
|
||||
.FinalXOR = 0xFFFFFFFF ,
|
||||
.InputReflected = true,
|
||||
.OutputReflected = true
|
||||
};
|
||||
|
||||
const CrcParameterSet CRC32_CD_ROM_EDC = {
|
||||
.Polynomial = 0x8001801b,
|
||||
.InitalValue = 0x0,
|
||||
.FinalXOR = 0x0,
|
||||
.InputReflected = false,
|
||||
.OutputReflected = false
|
||||
};
|
||||
|
||||
// UIO & pointers
|
||||
int fdCRC = open("/dev/uio0", O_RDWR);
|
||||
int fdMem = open("/dev/uio16", O_RDWR);
|
||||
PCRC_DMA_Typedef CRC = (PCRC_DMA_Typedef) mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fdCRC, 0);
|
||||
uint32_t* pMem = (uint32_t*) mmap(NULL, 0x20000000, PROT_READ | PROT_WRITE, MAP_SHARED, fdMem, 0);
|
||||
|
||||
printf("Programm startet\n\n");
|
||||
CrcParameterSet paraSet = CRC32_AIXM;
|
||||
|
||||
// Physische Adressen anlegen
|
||||
uint32_t uio16PhysBase = 0x30000000; // UIO16 physical Baseaddress
|
||||
uint32_t* pDataPhy = (uint32_t*) uio16PhysBase;
|
||||
uint32_t* pDataDestPhy = pDataPhy + DATA_SIZE;
|
||||
|
||||
// Mehrdimensionale Arrays deklarieren und mit virtuellen Adressen initialisieren
|
||||
uint32_t (*data)[PACKET_SIZE] = (uint32_t (*)[PACKET_SIZE]) pMem;
|
||||
uint32_t (*DataDest)[PACKET_SIZE+1] = (uint32_t (*)[PACKET_SIZE+1]) (pMem + DATA_SIZE);
|
||||
|
||||
// Speicher der Ergebnisse der CRC Berechnungen durch Hardware und Software
|
||||
uint32_t crc_sw[NUMBER_PACKETS];
|
||||
uint32_t crc_hw[NUMBER_PACKETS];
|
||||
|
||||
// Testdaten erzeugen
|
||||
printf("Testdaten erzeugen\n");
|
||||
printf("Testdaten erzeugen\n\n");
|
||||
srand(time(NULL));
|
||||
for (int packet = 0; packet < NUMBER_PACKETS; packet++) {
|
||||
for (int word = 0; word < PACKET_SIZE; word++) {
|
||||
*(data+packet+word) = (uint32_t) rand();
|
||||
data[packet][word] = (uint32_t) rand();
|
||||
}
|
||||
}
|
||||
|
||||
// axi_crc_dam Komponete parametrieren
|
||||
CRC->Control |= (1<<1); // INT aktivieren
|
||||
CRC->ReadAddress = (uint32_t) pDataPhy;
|
||||
CRC->WriteAddress = (uint32_t) pDataDestPhy;
|
||||
CRC->PacketSize = PACKET_SIZE - 1;
|
||||
CRC->NumberPackets = NUMBER_PACKETS - 1;
|
||||
CRC_DMA_set_parameters(CRC, ¶Set);
|
||||
|
||||
uint32_t polynomial = 0x4C11DB7;
|
||||
uint32_t InitialValue = 0;
|
||||
// Interrupt zurücksetzen und aktivieren
|
||||
CRC->InterruptStatus = 0;
|
||||
int reenable = 1;
|
||||
write(fdCRC, (void*) &reenable, 4);
|
||||
|
||||
// MM2VS Komponeten parametrieren und starten
|
||||
mmvs->VS2MM_Control &= ~1; // VS2MM: Run-Bit loeschen
|
||||
mmvs->MM2VS_Control &= ~1; // MM2VS: Run-Bit loeschen
|
||||
usleep(500000); // 500 ms warten. Falls das MMVS-IP noch aktiv war, kann es so noch ausstehende Speicherzugriffe beenden
|
||||
|
||||
mmvs->InterruptEnable = 0; // INTs deaktivieren
|
||||
mmvs->InterruptStatus = 0;
|
||||
mmvs->MM2VS_StartAddress = (uint32_t) data;
|
||||
mmvs->MM2VS_HorizontalBytes = 24;
|
||||
mmvs->MM2VS_Stride = 24;
|
||||
mmvs->MM2VS_LineNumber = 0;
|
||||
|
||||
mmvs->VS2MM_StartAddress = (uint32_t) data_CRC;
|
||||
mmvs->VS2MM_HorizontalBytes = 24;
|
||||
mmvs->VS2MM_Stride = 24;
|
||||
mmvs->VS2MM_LineNumber = 0;
|
||||
|
||||
mmvs->MM2VS_Control |= (1<<0);
|
||||
mmvs->VS2MM_Control |= (1<<0);
|
||||
|
||||
|
||||
// AXI_CRC_DMA Hardwarekomponente initialisieren
|
||||
CRC->Control |= (1<<1); // INT aktivieren
|
||||
CRC->Polynomial = polynomial;
|
||||
CRC->InitialValue = InitialValue;
|
||||
CRC->NumberPackets = NUMBER_PACKETS - 1;
|
||||
CRC->PacketSize = PACKET_SIZE - 1;
|
||||
CRC->ReadAddress = (uint32_t) data;
|
||||
CRC->WriteAddress = (uint32_t) data_CRC;
|
||||
CRC->FinalXOR = 0;
|
||||
CRC->InOutReflected = 0;
|
||||
|
||||
// CRC Berechnung mit Hardware durchfuehren
|
||||
printf("Berechnung in Hardware starten\n");
|
||||
// CRC Berechnung mit Hardware starten
|
||||
printf("CRC-Berechnung in Hardware starten\n\n");
|
||||
CRC->Control |= (1<<0);
|
||||
|
||||
// CRC Berechnung in Software durchfuehren
|
||||
printf("Berechnung in Software durchfuehren\n");
|
||||
uint32_t CRCs[NUMBER_PACKETS];
|
||||
for (int i = 0; i < NUMBER_PACKETS; i++) {
|
||||
CRCs[i] = calcCRC32((uint8_t*) data[i], PACKET_SIZE*4, polynomial, InitialValue, 0, 0, 0);
|
||||
printf("CRC-Berechnung in Software durchfuehren\n\n");
|
||||
for (int p = 0; p < NUMBER_PACKETS; p++) {
|
||||
crc_sw[p] = calcCRC32((uint8_t*) (&data[p][0]), PACKET_SIZE*4, paraSet.Polynomial, paraSet.InitalValue, paraSet.FinalXOR, paraSet.InputReflected ? 1 : 0, paraSet.OutputReflected ? 1 : 0);
|
||||
printf("Packet %i:\t0x%08x\n", p, crc_sw[p]);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
// Auf INT warten
|
||||
printf("Auf Interrupt warten\n");
|
||||
printf("Auf Interrupt warten...\n");
|
||||
int pending;
|
||||
int reenable = 1;
|
||||
read(fdCRC, (void*) &pending, 4);
|
||||
CRC->InterruptStatus = 0;
|
||||
write(fdCRC, (void*) &reenable, 4);
|
||||
printf("Interrupt erhalten\n");
|
||||
|
||||
// Ergebnisse vergleichen
|
||||
printf("Ergebnisse vergleichen\n");
|
||||
for (int i = 0; i < NUMBER_PACKETS; i++) {
|
||||
if (CRCs[i] != *(data_CRC+i+PACKET_SIZE)) {
|
||||
printf("Fehler\n");
|
||||
// Hardwareergebnis in Array ablegen
|
||||
for (int p = 0; p < NUMBER_PACKETS; p++) {
|
||||
crc_hw[p] = DataDest[p][PACKET_SIZE];
|
||||
}
|
||||
|
||||
|
||||
#ifdef DEBUG
|
||||
// data und DataDest komplett ausgeben
|
||||
printf("\ndata\tDataDest:\n");
|
||||
for (int p = 0; p < NUMBER_PACKETS; p++) {
|
||||
for (int w = 0; w < PACKET_SIZE+1; w++) {
|
||||
|
||||
// dataDest ausgeben
|
||||
if (w < PACKET_SIZE) {
|
||||
printf("0x%08x: 0x%08x\t0x%08x: 0x%08x\n", &DataDest[p][w], DataDest[p][w], &data[p][w], data[p][w]);
|
||||
} else {
|
||||
printf("0x%08x: 0x%08x\n", &DataDest[p][w], DataDest[p][w]);
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("\n\n");
|
||||
#endif
|
||||
|
||||
|
||||
// Daten und Ergebnisse vergleichen
|
||||
printf("Daten Ergebnisse vergleichen\n\n");
|
||||
bool allPaketsOK = true;
|
||||
for (int p = 0; p < NUMBER_PACKETS; p++) {
|
||||
bool dataOK = true;
|
||||
bool crcOK = true;
|
||||
|
||||
printf("Paket %i:\t", p);
|
||||
|
||||
for (int w = 0; w < PACKET_SIZE; w++) {
|
||||
// Daten vergleichen
|
||||
if (data[p][w] != DataDest[p][w]) {
|
||||
dataOK = false;
|
||||
printf("Fehler bei Datenwort %i\t", w);
|
||||
}
|
||||
}
|
||||
|
||||
if (dataOK) {printf("Daten OK\t");}
|
||||
|
||||
// CRC Ergebnis vergleichen
|
||||
if (crc_hw[p] != crc_sw[p]) {
|
||||
crcOK = false;
|
||||
printf("Fehler bei CRC\t");
|
||||
}
|
||||
|
||||
if (crcOK) {printf("CRC OK\t");}
|
||||
|
||||
printf("CRC: 0x%08x\n", crc_hw[p]);
|
||||
|
||||
if (!(crcOK && dataOK)) {
|
||||
allPaketsOK = false;
|
||||
}
|
||||
}
|
||||
printf("Alle Ergebnisse verglichen\n");
|
||||
|
||||
// MMVS anhalten
|
||||
mmvs->VS2MM_Control &= ~1; // VS2MM: Run-Bit loeschen
|
||||
mmvs->MM2VS_Control &= ~1; // MM2VS: Run-Bit loeschen
|
||||
if (allPaketsOK) {printf("Alle Pakete OK\n\n");}
|
||||
|
||||
printf("Alle Ergebnisse verglichen\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
+40
-37
@@ -25,16 +25,15 @@ uint32_t calcCRC32(
|
||||
// Berechnung der Pruefsummen fuer Testbench
|
||||
void calc_axis_crc_tb();
|
||||
|
||||
|
||||
int main()
|
||||
{
|
||||
// Testweise Pruefsumme berechnen und ausgeben
|
||||
char msg[] = "Hello World!";
|
||||
uint32_t crc = calcCRC32((uint8_t*) msg, strlen(msg), 0xF4ACFB13, 0xFFFFFFFF, 0xFFFFFFFF, 1, 1);
|
||||
uint32_t crc = calcCRC32((uint8_t*) msg, strlen(msg), 0x814141ab, 0, 0, 0, 0);
|
||||
printf("CRC32 of '%s': 0x%08x\n\n", msg, crc);
|
||||
|
||||
char msg2[] = "ABCDEFGHIJKL";
|
||||
crc = calcCRC32((uint8_t*) msg2, strlen(msg2), 0xF4ACFB13, 0xFFFFFFFF, 0xFFFFFFFF, 1, 1);
|
||||
crc = calcCRC32((uint8_t*) msg2, strlen(msg2), 0x814141ab, 0, 0, 0, 0);
|
||||
printf("CRC32 of '%s': 0x%08x\n\n", msg2, crc);
|
||||
|
||||
uint8_t data[128];
|
||||
@@ -52,40 +51,6 @@ int main()
|
||||
return 0;
|
||||
}
|
||||
|
||||
void calc_axis_crc_tb()
|
||||
{
|
||||
char test_data[] = "Hello World!";
|
||||
|
||||
uint32_t testPolynomials[3] = {
|
||||
0x4C11DB7,
|
||||
0x814141AB,
|
||||
0xF4ACFB13,
|
||||
};
|
||||
|
||||
uint32_t initalValues[2] = {
|
||||
0x0,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
uint32_t finalXORs[2] = {
|
||||
0x0,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
for (int p = 0; p < 3; p++) {
|
||||
for (int iV = 0; iV < 2; iV++) {
|
||||
for (int f = 0; f < 2; f++) {
|
||||
for (uint8_t r = 0; r < 2; r++) {
|
||||
uint32_t checksum;
|
||||
checksum = calcCRC32((uint8_t*) test_data, 12, testPolynomials[p], initalValues[iV], finalXORs[f], r, r);
|
||||
//printf("Polynom %d, iV %d: x\"%08x\"\n", p, iV, checksum);
|
||||
printf("x\"%08x\", ", checksum);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
uint8_t calcCRC8(uint8_t* inBytes, size_t size)
|
||||
{
|
||||
@@ -108,6 +73,7 @@ uint8_t calcCRC8(uint8_t* inBytes, size_t size)
|
||||
return crc;
|
||||
}
|
||||
|
||||
|
||||
uint16_t calcCRC16(uint8_t* inBytes, size_t size)
|
||||
{
|
||||
const uint16_t polynomial = 0x1021;
|
||||
@@ -129,6 +95,7 @@ uint16_t calcCRC16(uint8_t* inBytes, size_t size)
|
||||
return crc;
|
||||
}
|
||||
|
||||
|
||||
uint32_t calcCRC32(
|
||||
uint8_t* inBytes,
|
||||
size_t size,
|
||||
@@ -179,3 +146,39 @@ uint32_t calcCRC32(
|
||||
|
||||
return crc ^ finalXOR;
|
||||
}
|
||||
|
||||
|
||||
void calc_axis_crc_tb()
|
||||
{
|
||||
char test_data[] = "Hello World!";
|
||||
|
||||
uint32_t testPolynomials[3] = {
|
||||
0x4C11DB7,
|
||||
0x814141AB,
|
||||
0xF4ACFB13,
|
||||
};
|
||||
|
||||
uint32_t initalValues[2] = {
|
||||
0x0,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
uint32_t finalXORs[2] = {
|
||||
0x0,
|
||||
0xFFFFFFFF,
|
||||
};
|
||||
|
||||
for (int p = 0; p < 3; p++) {
|
||||
for (int iV = 0; iV < 2; iV++) {
|
||||
for (int f = 0; f < 2; f++) {
|
||||
for (uint8_t r = 0; r < 2; r++) {
|
||||
uint32_t checksum;
|
||||
checksum = calcCRC32((uint8_t*) test_data, 12, testPolynomials[p], initalValues[iV], finalXORs[f], r, r);
|
||||
//printf("Polynom %d, iV %d: x\"%08x\"\n", p, iV, checksum);
|
||||
printf("x\"%08x\", ", checksum);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
#include "axi_crc_dma.h"
|
||||
|
||||
void CRC_DMA_set_parameters(const PCRC_DMA_Typedef baseAddr, const CrcParameterSet* set)
|
||||
{
|
||||
baseAddr->Polynomial = set->Polynomial;
|
||||
baseAddr->InitialValue = set->InitalValue;
|
||||
baseAddr->FinalXOR = set->FinalXOR;
|
||||
|
||||
if (set->InputReflected) {
|
||||
baseAddr->InOutReflected |= (1<<0);
|
||||
} else {
|
||||
baseAddr->InOutReflected &= ~(1<<0);
|
||||
}
|
||||
|
||||
if (set->OutputReflected) {
|
||||
baseAddr->InOutReflected |= (1<<1);
|
||||
} else {
|
||||
baseAddr->InOutReflected &= ~(1<<1);
|
||||
}
|
||||
}
|
||||
+7
-12
@@ -53,7 +53,7 @@ typedef struct
|
||||
volatile uint32_t Control; // [0] Run, [1] INT Enable
|
||||
volatile uint32_t InterruptStatus; // [0] INT Status
|
||||
volatile uint32_t ReadAddress; // [31:0] Read Address of Data
|
||||
volatile uint32_t WriteAddress; // [31:0] Write Address of Data
|
||||
volatile uint32_t WriteAddress; // [31:0] Write Address of Data + CRC Checksums
|
||||
volatile uint32_t PacketSize; // [15:0] Size of Packets Minus 1 in 32 Bit words
|
||||
volatile uint32_t NumberPackets; // [15:0] Number of Packets Minus 1
|
||||
volatile uint32_t Polynomial; // [31:0] Polynomial for CRC Calculation
|
||||
@@ -61,25 +61,20 @@ typedef struct
|
||||
volatile uint32_t FinalXOR; // [31:0] Final XOR Value
|
||||
volatile uint32_t InOutReflected; // [0] Input Reflected, [1] Output Reflected
|
||||
volatile uint32_t AxCache; // [3:0] M_AXI AWCache, [7:4] M_AXI ARCache
|
||||
} CRC_Typedef;
|
||||
} CRC_DMA_Typedef;
|
||||
|
||||
typedef CRC_Typedef *PCRC_Typedef;
|
||||
typedef CRC_DMA_Typedef *PCRC_DMA_Typedef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Polynomial;
|
||||
uint32_t InitalValue;
|
||||
uint32_t FinalXOR;
|
||||
bool InputReflected;
|
||||
bool OutputReflected;
|
||||
bool InputReflected;
|
||||
bool OutputReflected;
|
||||
} CrcParameterSet;
|
||||
|
||||
const CrcParameterSet CRC32_AIXM = {
|
||||
.Polynomial = 0x814141ab,
|
||||
.InitalValue = 0x0,
|
||||
.FinalXOR = 0x0,
|
||||
.InputReflected = false,
|
||||
.OutputReflected = false
|
||||
};
|
||||
// load a specific set of CRC parameters into Hardware
|
||||
void CRC_DMA_set_parameters(PCRC_DMA_Typedef baseAddr, const CrcParameterSet* parameterSet);
|
||||
|
||||
#endif /* AXI_CRC_DMA_H_ */
|
||||
|
||||
Reference in New Issue
Block a user