Matthias Biermann
70 lines
2.0 KiB
VHDL
70 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axis_crc is
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generic (
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CRC_WIDTH : positive := 32;
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DWIDTH : positive := 16
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- for crc calculation
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initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0);
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polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0);
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-- AXI Streaming Target Port
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S_AXIS_TVALID : in std_logic;
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S_AXIS_TDATA : in std_logic_vector(DWIDTH-1 downto 0);
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S_AXIS_TLAST : in std_logic := '0';
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S_AXIS_TREADY : out std_logic;
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-- AXI Streaming Initiator Port
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TDATA : out std_logic_vector(DWIDTH-1 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TREADY : in std_logic
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);
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end entity;
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architecture rtl of axis_crc is
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type state_t is (DATA, CHECKSUM);
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signal state : state_t := DATA;
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signal M_AXIS_TVALID_sig : std_logic;
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-- CRC-Pruefsumme
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signal checksum : std_logic_vector(CRC_WIDTH-1);
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begin
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S_AXIS_TREADY <= M_AXIS_TREADY or (not M_AXIS_TVALID_sig) and (state=DATA);
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process
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begin
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wait until rising_edge(CLK);
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if RESETN = '0' then
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state <= DATA;
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checksum <= initial_value;
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else
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case state is
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when DATA =>
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if M_AXIS_TREADY = '1' or M_AXIS_TVALID_sig = '0' then
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M_AXIS_TDATA <= S_AXIS_TDATA;
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M_AXIS_TVALID <= S_AXIS_TVALID;
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M_AXIS_TVALID_sig <= S_AXIS_TVALID;
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M_AXIS_TLAST <= S_AXIS_TLAST;
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end if;
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when CHECKSUM =>
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when others => null;
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end case;
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end if;
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end process;
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end architecture; |