basic axis_crc_tb läuft
This commit is contained in:
Matthias Biermann
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
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||||
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738414004"/>
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||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738414004"/>
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<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738414004"/>
|
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<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738414004"/>
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||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738434920"/>
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<Generation Name="SIMULATION" State="RESET" Timestamp="1738434920"/>
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<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738434920"/>
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<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738434920"/>
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<FileCollection Name="SOURCES" Type="SOURCES"/>
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</CompositeFile>
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</Root>
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+19
-19
@@ -986,36 +986,36 @@
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:coreRevision>19</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
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||||
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+8
-30
@@ -47,7 +47,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>TDATA_NUM_BYTES</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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@@ -206,7 +206,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>TDATA_NUM_BYTES</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
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||||
<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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@@ -466,7 +466,7 @@
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CRC_WIDTH')) - 1)">31</spirit:left>
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<spirit:left spirit:format="long">31</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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||||
<spirit:wireTypeDefs>
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@@ -482,7 +482,7 @@
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CRC_WIDTH')) - 1)">31</spirit:left>
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<spirit:left spirit:format="long">31</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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@@ -510,7 +510,7 @@
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWITH')) - 1)">15</spirit:left>
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||||
<spirit:left spirit:format="long">31</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
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||||
<spirit:wireTypeDefs>
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||||
@@ -568,7 +568,7 @@
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<spirit:wire>
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||||
<spirit:direction>out</spirit:direction>
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||||
<spirit:vector>
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||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWITH')) - 1)">15</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
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||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
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||||
@@ -607,18 +607,6 @@
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||||
</spirit:wire>
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||||
</spirit:port>
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||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
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||||
<spirit:name>CRC_WIDTH</spirit:name>
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||||
<spirit:displayName>Crc Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CRC_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DWITH</spirit:name>
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||||
<spirit:displayName>Dwith</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DWITH" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
@@ -629,16 +617,6 @@
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||||
</spirit:choices>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CRC_WIDTH</spirit:name>
|
||||
<spirit:displayName>Crc Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CRC_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DWITH</spirit:name>
|
||||
<spirit:displayName>Dwith</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DWITH" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_crc_dma_sim_1_axis_crc_0_0</spirit:value>
|
||||
@@ -665,7 +643,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -678,7 +656,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+36
-36
@@ -2476,22 +2476,22 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2499,13 +2499,13 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -2519,36 +2519,36 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+5
-50
@@ -2,55 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axis_crc_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738414012"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738414012"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738414012"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738414012"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axis_crc_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axis_crc_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axis_crc_sim_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\axis_crc_sim_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axis_crc_sim_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\axis_crc_sim_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axis_crc_sim_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738434924"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738434924"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738434924"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738434924"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
-10
@@ -1,10 +0,0 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sat Feb 1 13:46:52 2025
|
||||
--Date : Sat Feb 1 17:06:13 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_crc_sim_1_wrapper.bd
|
||||
--Design : axis_crc_sim_1_wrapper
|
||||
|
||||
+20
-86
@@ -47,7 +47,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -206,7 +206,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -436,40 +436,6 @@
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4c49e31c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axis_crc_sim_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 12:46:52 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:4c49e31c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -478,7 +444,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -490,7 +456,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -500,13 +466,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CRC_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -516,13 +482,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CRC_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -534,7 +500,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -544,13 +510,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWITH')) - 1)">15</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -565,7 +531,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -580,7 +546,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -592,7 +558,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -602,13 +568,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWITH')) - 1)">15</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -620,7 +586,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -632,7 +598,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -641,18 +607,6 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CRC_WIDTH</spirit:name>
|
||||
<spirit:displayName>Crc Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CRC_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DWITH</spirit:name>
|
||||
<spirit:displayName>Dwith</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DWITH" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
@@ -661,28 +615,8 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axis_crc_sim_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CRC_WIDTH</spirit:name>
|
||||
<spirit:displayName>Crc Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CRC_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DWITH</spirit:name>
|
||||
<spirit:displayName>Dwith</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DWITH" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_crc_sim_1_axis_crc_0_0</spirit:value>
|
||||
@@ -709,7 +643,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -722,7 +656,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+6
-14
@@ -60,11 +60,11 @@ ENTITY axis_crc_sim_1_axis_crc_0_0 IS
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
@@ -74,21 +74,17 @@ ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
GENERIC (
|
||||
CRC_WIDTH : INTEGER;
|
||||
DWITH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
@@ -100,21 +96,17 @@ ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_crc
|
||||
GENERIC MAP (
|
||||
CRC_WIDTH => 32,
|
||||
DWITH => 16
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
|
||||
-136
@@ -1,136 +0,0 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_downsizer:1.0
|
||||
-- IP Revision: 2
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_crc_sim_1_axis_downsizer_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
);
|
||||
END axis_crc_sim_1_axis_downsizer_0_0;
|
||||
|
||||
ARCHITECTURE axis_crc_sim_1_axis_downsizer_0_0_arch OF axis_crc_sim_1_axis_downsizer_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_downsizer_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_downsizer IS
|
||||
GENERIC (
|
||||
WIDTH_OUT : INTEGER;
|
||||
SIZE_FACTOR : INTEGER;
|
||||
BIG_ENDIAN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_downsizer;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_downsizer
|
||||
GENERIC MAP (
|
||||
WIDTH_OUT => 16,
|
||||
SIZE_FACTOR => 2,
|
||||
BIG_ENDIAN => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
AXIS_ARESETN => AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER
|
||||
);
|
||||
END axis_crc_sim_1_axis_downsizer_0_0_arch;
|
||||
+10
-7
@@ -302,7 +302,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1454e34a</spirit:value>
|
||||
<spirit:value>9:01a1e6f6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -318,11 +318,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 17:40:16 UTC 2025</spirit:value>
|
||||
<spirit:value>Sat Feb 01 16:06:13 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1454e34a</spirit:value>
|
||||
<spirit:value>9:01a1e6f6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -503,12 +503,12 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PIX_PER_LINE">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PIX_PER_LINE">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINES">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINES">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_FRAMES_PER_FILE</spirit:name>
|
||||
@@ -642,12 +642,12 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINES" spirit:order="2000" spirit:configGroups="0 UnGrouped textEdit">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINES" spirit:order="2000" spirit:configGroups="0 UnGrouped textEdit">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PIX_PER_LINE" spirit:order="2100" spirit:configGroups="0 UnGrouped textEdit">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PIX_PER_LINE" spirit:order="2100" spirit:configGroups="0 UnGrouped textEdit">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FILE_AUTONUMBERING</spirit:name>
|
||||
@@ -720,7 +720,10 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_AUTONUMBERING" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_EXTENSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_LINES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_PIX_PER_LINE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
|
||||
+2
-2
@@ -126,8 +126,8 @@ BEGIN
|
||||
FILE_NAME => "../../../../tst",
|
||||
FILE_EXTENSION => "raw",
|
||||
FILE_AUTONUMBERING => false,
|
||||
NUM_PIX_PER_LINE => 128,
|
||||
NUM_LINES => 128,
|
||||
NUM_PIX_PER_LINE => 3,
|
||||
NUM_LINES => 1,
|
||||
NUM_FRAMES_PER_FILE => 1,
|
||||
RANDOM_TVALID => true,
|
||||
PIXEL_FORMAT => 1,
|
||||
|
||||
+9
-7
@@ -297,7 +297,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ac7016c1</spirit:value>
|
||||
<spirit:value>9:a9b77564</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -313,11 +313,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 17:40:16 UTC 2025</spirit:value>
|
||||
<spirit:value>Sat Feb 01 16:06:13 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ac7016c1</spirit:value>
|
||||
<spirit:value>9:a9b77564</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -457,12 +457,12 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PIX_PER_LINE">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PIX_PER_LINE">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINES">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINES">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_FRAMES_PER_FILE</spirit:name>
|
||||
@@ -556,12 +556,12 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINES" spirit:order="1600">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINES" spirit:order="1600">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PIX_PER_LINE" spirit:order="1700">128</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PIX_PER_LINE" spirit:order="1700">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PIXEL_FORMAT</spirit:name>
|
||||
@@ -625,6 +625,8 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_EXTENSION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_LINES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_PIX_PER_LINE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
|
||||
+2
-2
@@ -115,8 +115,8 @@ BEGIN
|
||||
FILE_EXTENSION => "raw",
|
||||
FILE_AUTONUMBERING => false,
|
||||
PIXEL_FORMAT => 1,
|
||||
NUM_PIX_PER_LINE => 128,
|
||||
NUM_LINES => 128,
|
||||
NUM_PIX_PER_LINE => 3,
|
||||
NUM_LINES => 1,
|
||||
NUM_FRAMES_PER_FILE => 1,
|
||||
NUM_FILES => 1,
|
||||
FRAMING_PIXELS => 0,
|
||||
|
||||
-795
@@ -1,795 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>axis_crc_sim_1_axis_upsizer_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_upsizer</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e18349df</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axis_crc_sim_1_axis_upsizer_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e18349df</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH_IN')) - 1)">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.WIDTH_IN')) * spirit:decode(id('MODELPARAM_VALUE.SIZE_FACTOR'))) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>WIDTH_IN</spirit:name>
|
||||
<spirit:displayName>Width In</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH_IN">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SIZE_FACTOR">2</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_552a89ba</spirit:name>
|
||||
<spirit:enumeration>2</spirit:enumeration>
|
||||
<spirit:enumeration>4</spirit:enumeration>
|
||||
<spirit:enumeration>8</spirit:enumeration>
|
||||
<spirit:enumeration>16</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_5f2cf65b</spirit:name>
|
||||
<spirit:enumeration>1</spirit:enumeration>
|
||||
<spirit:enumeration>8</spirit:enumeration>
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||||
<spirit:enumeration>16</spirit:enumeration>
|
||||
<spirit:enumeration>32</spirit:enumeration>
|
||||
<spirit:enumeration>64</spirit:enumeration>
|
||||
<spirit:enumeration>128</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/dfd1/sources_1/new/axis_upsizer.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
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|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axis_crc_sim_1_axis_upsizer_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_upsizer_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>WIDTH_IN</spirit:name>
|
||||
<spirit:displayName>Width In</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH_IN" spirit:choiceRef="choice_list_5f2cf65b">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIZE_FACTOR" spirit:choiceRef="choice_list_552a89ba">2</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_crc_sim_1_axis_upsizer_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
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|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_upsizer_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>3</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:user:axis_upsizer:1.0_ARCHIVE_LOCATION">d:/Projekte/edvs/vivado/vivado/ip_projects/axis_upsizer/axis_upsizer.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WIDTH_IN" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3243ed51"/>
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||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="39fc288d"/>
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||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="b1ca67f8"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b7579622"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="0d5be49c"/>
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</xilinx:packagingInfo>
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||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
-94
@@ -1,94 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_downsizer is
|
||||
generic
|
||||
(
|
||||
WIDTH_OUT : integer := 8;
|
||||
SIZE_FACTOR : integer := 2;
|
||||
BIG_ENDIAN : boolean := false
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
AXIS_ARESETN : in std_logic;
|
||||
|
||||
-- AXIS SLAVE
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic;
|
||||
|
||||
-- AXIS Master
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(WIDTH_OUT-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
M_AXIS_TUSER : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axis_downsizer is
|
||||
type T_STATE is (BYTE0,BYTE1);
|
||||
signal state : T_STATE := BYTE0;
|
||||
signal last : std_logic;
|
||||
signal data : std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0);
|
||||
signal ui : unsigned(5 downto 0);
|
||||
begin
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTE0 else '0';
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTE0 else '1';
|
||||
M_AXIS_TLAST <= last when ui = to_unsigned(SIZE_FACTOR-1,6) else '0';
|
||||
M_AXIS_TUSER <= S_AXIS_TUSER when state = BYTE0 else '0';
|
||||
|
||||
|
||||
process (S_AXIS_TDATA, ui)
|
||||
variable i: integer;
|
||||
begin
|
||||
i := to_integer(ui);
|
||||
if BIG_ENDIAN then
|
||||
if ui = 0 then
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT*SIZE_FACTOR-1 downto WIDTH_OUT*(SIZE_FACTOR-1));
|
||||
else
|
||||
M_AXIS_TDATA <= data(WIDTH_OUT*(SIZE_FACTOR-i)-1 downto WIDTH_OUT*(SIZE_FACTOR-i-1));
|
||||
end if;
|
||||
else
|
||||
if ui = 0 then
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT-1 downto 0);
|
||||
else
|
||||
M_AXIS_TDATA <= data(WIDTH_OUT*(i+1)-1 downto WIDTH_OUT*i);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
wait until rising_edge (AXIS_ACLK);
|
||||
if AXIS_ARESETN = '0' then
|
||||
state <= BYTE0;
|
||||
else
|
||||
case state is
|
||||
when BYTE0 =>
|
||||
if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then
|
||||
last <= S_AXIS_TLAST;
|
||||
data <= S_AXIS_TDATA;
|
||||
ui <= to_unsigned(1,6);
|
||||
state <= BYTE1;
|
||||
end if;
|
||||
when BYTE1 =>
|
||||
if M_AXIS_TREADY='1' then
|
||||
if ui >= SIZE_FACTOR-1 then
|
||||
state <= BYTE0;
|
||||
ui <= to_unsigned(0,6);
|
||||
else
|
||||
ui <= ui+1;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
-103
@@ -1,103 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_upsizer is
|
||||
generic
|
||||
(
|
||||
WIDTH_IN : integer := 8;
|
||||
SIZE_FACTOR : integer := 2;
|
||||
BIG_ENDIAN : boolean := false
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
AXIS_ARESETN : in std_logic;
|
||||
|
||||
-- AXIS SLAVE
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(WIDTH_IN-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic;
|
||||
|
||||
-- AXIS Master
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
M_AXIS_TUSER : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axis_upsizer is
|
||||
type T_STATE is (BYTE0,BYTE1,BYTEF);
|
||||
signal state : T_STATE := BYTE0;
|
||||
signal user : std_logic;
|
||||
signal data : std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0);
|
||||
begin
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTEF else '1';
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTEF else '0';
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST when state = BYTEF else '0';
|
||||
M_AXIS_TUSER <= user when state = BYTEF else '0';
|
||||
|
||||
process (S_AXIS_TDATA, data)
|
||||
begin
|
||||
if BIG_ENDIAN then
|
||||
for i in 0 to SIZE_FACTOR-1 loop
|
||||
M_AXIS_TDATA(WIDTH_IN*SIZE_FACTOR-1-WIDTH_IN*i downto (WIDTH_IN-1)*SIZE_FACTOR-WIDTH_IN*i) <= data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i);
|
||||
end loop;
|
||||
M_AXIS_TDATA(WIDTH_IN-1 downto 0) <= S_AXIS_TDATA;
|
||||
|
||||
else
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA & data(WIDTH_IN*(SIZE_FACTOR-1)-1 downto 0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
variable i : integer;
|
||||
variable ui : unsigned(5 downto 0);
|
||||
begin
|
||||
wait until rising_edge (AXIS_ACLK);
|
||||
if AXIS_ARESETN = '0' then
|
||||
state <= BYTE0;
|
||||
else
|
||||
case state is
|
||||
when BYTE0 =>
|
||||
if S_AXIS_TVALID = '1' then
|
||||
ui := (others=>'0');
|
||||
i := to_integer(ui);
|
||||
data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA;
|
||||
user <= S_AXIS_TUSER;
|
||||
if S_AXIS_TLAST = '1' then
|
||||
state <= BYTE0;
|
||||
else
|
||||
if (i<SIZE_FACTOR-2) then
|
||||
state <= BYTE1;
|
||||
else
|
||||
state <= BYTEF;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when BYTE1 =>
|
||||
if S_AXIS_TVALID = '1' then
|
||||
ui := ui+1;
|
||||
i := to_integer(ui);
|
||||
data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA;
|
||||
if S_AXIS_TLAST = '1' then
|
||||
state <= BYTE0;
|
||||
elsif (i>=SIZE_FACTOR-2) then
|
||||
state <= BYTEF;
|
||||
end if;
|
||||
end if;
|
||||
when BYTEF =>
|
||||
if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then
|
||||
state <= BYTE0;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
-286
@@ -1,286 +0,0 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sat Feb 1 13:46:51 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_crc_sim_1.bd
|
||||
--Design : axis_crc_sim_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_imp_156I22D is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_tlast : out STD_LOGIC;
|
||||
M_AXIS_tready : in STD_LOGIC;
|
||||
M_AXIS_tuser : out STD_LOGIC;
|
||||
M_AXIS_tvalid : out STD_LOGIC;
|
||||
S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_tlast : in STD_LOGIC;
|
||||
S_AXIS_tready : out STD_LOGIC;
|
||||
S_AXIS_tuser : in STD_LOGIC;
|
||||
S_AXIS_tvalid : in STD_LOGIC
|
||||
);
|
||||
end crc_imp_156I22D;
|
||||
|
||||
architecture STRUCTURE of crc_imp_156I22D is
|
||||
component axis_crc_sim_1_axis_downsizer_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_downsizer_0_0;
|
||||
component axis_crc_sim_1_axis_upsizer_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_upsizer_0_0;
|
||||
component axis_crc_sim_1_xlconstant_1_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_1_0;
|
||||
component axis_crc_sim_1_xlconstant_0_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_0_0;
|
||||
component axis_crc_sim_1_axis_crc_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_crc_0_0;
|
||||
signal AXIS_ACLK_1 : STD_LOGIC;
|
||||
signal AXIS_ARESETN_1 : STD_LOGIC;
|
||||
signal Conn1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_TLAST : STD_LOGIC;
|
||||
signal Conn1_TREADY : STD_LOGIC;
|
||||
signal Conn1_TUSER : STD_LOGIC;
|
||||
signal Conn1_TVALID : STD_LOGIC;
|
||||
signal Conn2_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_TLAST : STD_LOGIC;
|
||||
signal Conn2_TREADY : STD_LOGIC;
|
||||
signal Conn2_TUSER : STD_LOGIC;
|
||||
signal Conn2_TVALID : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC;
|
||||
begin
|
||||
AXIS_ACLK_1 <= AXIS_ACLK;
|
||||
AXIS_ARESETN_1 <= AXIS_ARESETN;
|
||||
Conn1_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0);
|
||||
Conn1_TLAST <= S_AXIS_tlast;
|
||||
Conn1_TUSER <= S_AXIS_tuser;
|
||||
Conn1_TVALID <= S_AXIS_tvalid;
|
||||
Conn2_TREADY <= M_AXIS_tready;
|
||||
M_AXIS_tdata(31 downto 0) <= Conn2_TDATA(31 downto 0);
|
||||
M_AXIS_tlast <= Conn2_TLAST;
|
||||
M_AXIS_tuser <= Conn2_TUSER;
|
||||
M_AXIS_tvalid <= Conn2_TVALID;
|
||||
S_AXIS_tready <= Conn1_TREADY;
|
||||
axis_crc_0: component axis_crc_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => AXIS_ACLK_1,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
RESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID,
|
||||
initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0),
|
||||
polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
axis_downsizer_0: component axis_crc_sim_1_axis_downsizer_0_0
|
||||
port map (
|
||||
AXIS_ACLK => AXIS_ACLK_1,
|
||||
AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED,
|
||||
M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => Conn1_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => Conn1_TLAST,
|
||||
S_AXIS_TREADY => Conn1_TREADY,
|
||||
S_AXIS_TUSER => Conn1_TUSER,
|
||||
S_AXIS_TVALID => Conn1_TVALID
|
||||
);
|
||||
axis_upsizer_0: component axis_crc_sim_1_axis_upsizer_0_0
|
||||
port map (
|
||||
AXIS_ACLK => AXIS_ACLK_1,
|
||||
AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
M_AXIS_TDATA(31 downto 0) => Conn2_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => Conn2_TLAST,
|
||||
M_AXIS_TREADY => Conn2_TREADY,
|
||||
M_AXIS_TUSER => Conn2_TUSER,
|
||||
M_AXIS_TVALID => Conn2_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER => '0',
|
||||
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID
|
||||
);
|
||||
xlconstant_0: component axis_crc_sim_1_xlconstant_0_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
xlconstant_1: component axis_crc_sim_1_xlconstant_1_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_1_dout(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axis_crc_sim_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=3,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef";
|
||||
end axis_crc_sim_1;
|
||||
|
||||
architecture STRUCTURE of axis_crc_sim_1 is
|
||||
component axis_crc_sim_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_clk_rst_generator_0_0;
|
||||
component axis_crc_sim_1_axis_slave_simmodel_0_0 is
|
||||
port (
|
||||
FINISHED : out STD_LOGIC;
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_slave_simmodel_0_0;
|
||||
component axis_crc_sim_1_axis_master_simmodel_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_master_simmodel_0_0;
|
||||
signal AXIS_ARESETN_1 : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_FINISHED : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal crc_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal crc_M_AXIS_TUSER : STD_LOGIC;
|
||||
signal crc_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
|
||||
begin
|
||||
axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => AXIS_ARESETN_1,
|
||||
FINISHED => axis_master_simmodel_0_FINISHED,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0),
|
||||
M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0
|
||||
port map (
|
||||
FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED,
|
||||
S_AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
S_AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => crc_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => crc_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => crc_M_AXIS_TUSER,
|
||||
S_AXIS_TVALID => crc_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => AXIS_ARESETN_1,
|
||||
stop_simulation => axis_master_simmodel_0_FINISHED
|
||||
);
|
||||
crc: entity work.crc_imp_156I22D
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
M_AXIS_tdata(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_tlast => crc_M_AXIS_TLAST,
|
||||
M_AXIS_tready => crc_M_AXIS_TREADY,
|
||||
M_AXIS_tuser => crc_M_AXIS_TUSER,
|
||||
M_AXIS_tvalid => crc_M_AXIS_TVALID,
|
||||
S_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
S_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
S_AXIS_tuser => axis_master_simmodel_0_M_AXIS_TUSER(0),
|
||||
S_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
-286
@@ -1,286 +0,0 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sat Feb 1 13:46:51 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_crc_sim_1.bd
|
||||
--Design : axis_crc_sim_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_imp_156I22D is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
M_AXIS_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_tlast : out STD_LOGIC;
|
||||
M_AXIS_tready : in STD_LOGIC;
|
||||
M_AXIS_tuser : out STD_LOGIC;
|
||||
M_AXIS_tvalid : out STD_LOGIC;
|
||||
S_AXIS_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_tlast : in STD_LOGIC;
|
||||
S_AXIS_tready : out STD_LOGIC;
|
||||
S_AXIS_tuser : in STD_LOGIC;
|
||||
S_AXIS_tvalid : in STD_LOGIC
|
||||
);
|
||||
end crc_imp_156I22D;
|
||||
|
||||
architecture STRUCTURE of crc_imp_156I22D is
|
||||
component axis_crc_sim_1_axis_downsizer_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_downsizer_0_0;
|
||||
component axis_crc_sim_1_axis_upsizer_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_upsizer_0_0;
|
||||
component axis_crc_sim_1_xlconstant_1_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_1_0;
|
||||
component axis_crc_sim_1_xlconstant_0_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_0_0;
|
||||
component axis_crc_sim_1_axis_crc_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_crc_0_0;
|
||||
signal AXIS_ACLK_1 : STD_LOGIC;
|
||||
signal AXIS_ARESETN_1 : STD_LOGIC;
|
||||
signal Conn1_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn1_TLAST : STD_LOGIC;
|
||||
signal Conn1_TREADY : STD_LOGIC;
|
||||
signal Conn1_TUSER : STD_LOGIC;
|
||||
signal Conn1_TVALID : STD_LOGIC;
|
||||
signal Conn2_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn2_TLAST : STD_LOGIC;
|
||||
signal Conn2_TREADY : STD_LOGIC;
|
||||
signal Conn2_TUSER : STD_LOGIC;
|
||||
signal Conn2_TVALID : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_downsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_downsizer_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_downsizer_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_downsizer_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC;
|
||||
begin
|
||||
AXIS_ACLK_1 <= AXIS_ACLK;
|
||||
AXIS_ARESETN_1 <= AXIS_ARESETN;
|
||||
Conn1_TDATA(31 downto 0) <= S_AXIS_tdata(31 downto 0);
|
||||
Conn1_TLAST <= S_AXIS_tlast;
|
||||
Conn1_TUSER <= S_AXIS_tuser;
|
||||
Conn1_TVALID <= S_AXIS_tvalid;
|
||||
Conn2_TREADY <= M_AXIS_tready;
|
||||
M_AXIS_tdata(31 downto 0) <= Conn2_TDATA(31 downto 0);
|
||||
M_AXIS_tlast <= Conn2_TLAST;
|
||||
M_AXIS_tuser <= Conn2_TUSER;
|
||||
M_AXIS_tvalid <= Conn2_TVALID;
|
||||
S_AXIS_tready <= Conn1_TREADY;
|
||||
axis_crc_0: component axis_crc_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => AXIS_ACLK_1,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
RESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID,
|
||||
initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0),
|
||||
polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
axis_downsizer_0: component axis_crc_sim_1_axis_downsizer_0_0
|
||||
port map (
|
||||
AXIS_ACLK => AXIS_ACLK_1,
|
||||
AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_downsizer_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_downsizer_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_downsizer_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => NLW_axis_downsizer_0_M_AXIS_TUSER_UNCONNECTED,
|
||||
M_AXIS_TVALID => axis_downsizer_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => Conn1_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => Conn1_TLAST,
|
||||
S_AXIS_TREADY => Conn1_TREADY,
|
||||
S_AXIS_TUSER => Conn1_TUSER,
|
||||
S_AXIS_TVALID => Conn1_TVALID
|
||||
);
|
||||
axis_upsizer_0: component axis_crc_sim_1_axis_upsizer_0_0
|
||||
port map (
|
||||
AXIS_ACLK => AXIS_ACLK_1,
|
||||
AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
M_AXIS_TDATA(31 downto 0) => Conn2_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => Conn2_TLAST,
|
||||
M_AXIS_TREADY => Conn2_TREADY,
|
||||
M_AXIS_TUSER => Conn2_TUSER,
|
||||
M_AXIS_TVALID => Conn2_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_crc_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER => '0',
|
||||
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID
|
||||
);
|
||||
xlconstant_0: component axis_crc_sim_1_xlconstant_0_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
xlconstant_1: component axis_crc_sim_1_xlconstant_1_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_1_dout(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axis_crc_sim_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=8,numNonXlnxBlks=3,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef";
|
||||
end axis_crc_sim_1;
|
||||
|
||||
architecture STRUCTURE of axis_crc_sim_1 is
|
||||
component axis_crc_sim_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_clk_rst_generator_0_0;
|
||||
component axis_crc_sim_1_axis_slave_simmodel_0_0 is
|
||||
port (
|
||||
FINISHED : out STD_LOGIC;
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_slave_simmodel_0_0;
|
||||
component axis_crc_sim_1_axis_master_simmodel_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_master_simmodel_0_0;
|
||||
signal AXIS_ARESETN_1 : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_FINISHED : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TUSER : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal crc_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal crc_M_AXIS_TUSER : STD_LOGIC;
|
||||
signal crc_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
|
||||
begin
|
||||
axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => AXIS_ARESETN_1,
|
||||
FINISHED => axis_master_simmodel_0_FINISHED,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => axis_master_simmodel_0_M_AXIS_TUSER(0),
|
||||
M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0
|
||||
port map (
|
||||
FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED,
|
||||
S_AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
S_AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => crc_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => crc_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => crc_M_AXIS_TUSER,
|
||||
S_AXIS_TVALID => crc_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => AXIS_ARESETN_1,
|
||||
stop_simulation => axis_master_simmodel_0_FINISHED
|
||||
);
|
||||
crc: entity work.crc_imp_156I22D
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
M_AXIS_tdata(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_tlast => crc_M_AXIS_TLAST,
|
||||
M_AXIS_tready => crc_M_AXIS_TREADY,
|
||||
M_AXIS_tuser => crc_M_AXIS_TUSER,
|
||||
M_AXIS_tvalid => crc_M_AXIS_TVALID,
|
||||
S_AXIS_tdata(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_tlast => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
S_AXIS_tready => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
S_AXIS_tuser => axis_master_simmodel_0_M_AXIS_TUSER(0),
|
||||
S_AXIS_tvalid => axis_master_simmodel_0_M_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axis_master_test" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738431513"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738431513"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738431513"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738431513"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sat Feb 1 17:34:52 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_master_test_wrapper.bd
|
||||
--Design : axis_master_test_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axis_master_test_wrapper is
|
||||
end axis_master_test_wrapper;
|
||||
|
||||
architecture STRUCTURE of axis_master_test_wrapper is
|
||||
component axis_master_test is
|
||||
end component axis_master_test;
|
||||
begin
|
||||
axis_master_test_i: component axis_master_test
|
||||
;
|
||||
end STRUCTURE;
|
||||
+1911
File diff suppressed because it is too large
Load Diff
+165
@@ -0,0 +1,165 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_mixer:1.0
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_master_test_axis_mixer_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
S_AXIS_1_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_1_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_1_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_2_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_2_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_2_TREADY : OUT STD_LOGIC
|
||||
);
|
||||
END axis_master_test_axis_mixer_0_0;
|
||||
|
||||
ARCHITECTURE axis_master_test_axis_mixer_0_0_arch OF axis_master_test_axis_mixer_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_master_test_axis_mixer_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_mixer IS
|
||||
GENERIC (
|
||||
WEIGHT_1 : INTEGER;
|
||||
DATA_WIDTH : INTEGER;
|
||||
HAS_AXI_LITE_IF : BOOLEAN;
|
||||
WEIGHT_2 : INTEGER;
|
||||
FORCE_01_INPUT : BOOLEAN;
|
||||
SHIFT_DEF : INTEGER
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
S_AXIS_1_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_1_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_1_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_2_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_2_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_2_TREADY : OUT STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_mixer;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_RESET ARESETN, ASSOCIATED_BUSIF S_AXIL:S_AXIS_2:S_AXIS_1:M_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_1_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS_1, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_2_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS_2, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TVALID";
|
||||
BEGIN
|
||||
U0 : axis_mixer
|
||||
GENERIC MAP (
|
||||
WEIGHT_1 => 1,
|
||||
DATA_WIDTH => 32,
|
||||
HAS_AXI_LITE_IF => false,
|
||||
WEIGHT_2 => 1,
|
||||
FORCE_01_INPUT => false,
|
||||
SHIFT_DEF => 0
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
S_AXIS_1_TVALID => S_AXIS_1_TVALID,
|
||||
S_AXIS_1_TDATA => S_AXIS_1_TDATA,
|
||||
S_AXIS_1_TREADY => S_AXIS_1_TREADY,
|
||||
S_AXIS_2_TVALID => S_AXIS_2_TVALID,
|
||||
S_AXIS_2_TDATA => S_AXIS_2_TDATA,
|
||||
S_AXIS_2_TREADY => S_AXIS_2_TREADY,
|
||||
S_AXIL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
|
||||
S_AXIL_AWVALID => '0',
|
||||
S_AXIL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXIL_WVALID => '0',
|
||||
S_AXIL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXIL_BREADY => '1',
|
||||
S_AXIL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
|
||||
S_AXIL_ARVALID => '0',
|
||||
S_AXIL_RREADY => '1'
|
||||
);
|
||||
END axis_master_test_axis_mixer_0_0_arch;
|
||||
+1754
File diff suppressed because it is too large
Load Diff
+211
@@ -0,0 +1,211 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_numeric_master_slave_simmodel:1.0
|
||||
-- IP Revision: 18
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_master_test_axis_numeric_master_0_0 IS
|
||||
PORT (
|
||||
CLK : OUT STD_LOGIC;
|
||||
RESETN : OUT STD_LOGIC;
|
||||
M1_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M1_AXIS_TREADY : IN STD_LOGIC;
|
||||
M1_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M2_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M2_AXIS_TREADY : IN STD_LOGIC;
|
||||
M2_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END axis_master_test_axis_numeric_master_0_0;
|
||||
|
||||
ARCHITECTURE axis_master_test_axis_numeric_master_0_0_arch OF axis_master_test_axis_numeric_master_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_master_test_axis_numeric_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_numeric_master_slave_simmodel IS
|
||||
GENERIC (
|
||||
HAS_CLOCK_GENERATOR : BOOLEAN;
|
||||
CLOCK_PERIOD_NS : INTEGER;
|
||||
HAS_RESET_GENERATOR : BOOLEAN;
|
||||
RESET_ACTIVE_CYCLES : INTEGER;
|
||||
HAS_MASTER1 : BOOLEAN;
|
||||
MASTER1_DATA_WIDTH : INTEGER;
|
||||
MASTER1_RANDOM_VALID : BOOLEAN;
|
||||
MASTER1_HAS_LAST : BOOLEAN;
|
||||
MASTER1_LAST_PERIOD : INTEGER;
|
||||
MASTER1_HAS_USER : BOOLEAN;
|
||||
MASTER1_USER_PERIOD : INTEGER;
|
||||
HAS_MASTER2 : BOOLEAN;
|
||||
MASTER2_DATA_WIDTH : INTEGER;
|
||||
MASTER2_RANDOM_VALID : BOOLEAN;
|
||||
MASTER2_HAS_LAST : BOOLEAN;
|
||||
MASTER2_LAST_PERIOD : INTEGER;
|
||||
MASTER2_HAS_USER : BOOLEAN;
|
||||
MASTER2_USER_PERIOD : INTEGER;
|
||||
HAS_SLAVE : BOOLEAN;
|
||||
SLAVE_DATA_WIDTH : INTEGER;
|
||||
SLAVE_RANDOM_READY : BOOLEAN;
|
||||
SLAVE_HAS_LAST : BOOLEAN;
|
||||
SLAVE_HAS_USER : BOOLEAN;
|
||||
SLAVE_WAIT_FOR_SOF : BOOLEAN;
|
||||
FILE_NAME_M1 : STRING;
|
||||
FILE_NAME_M2 : STRING;
|
||||
FILE_NAME_S : STRING;
|
||||
HAS_RESETN_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
CLK : OUT STD_LOGIC;
|
||||
RESETN : OUT STD_LOGIC;
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M1_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M1_AXIS_TREADY : IN STD_LOGIC;
|
||||
M1_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M2_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M2_AXIS_TREADY : IN STD_LOGIC;
|
||||
M2_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_numeric_master_slave_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RESETN, ASSOCIATED_BUSIF S_AXIS:M2_AXIS:M1_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M1_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M1_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M2_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M2_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_numeric_master_slave_simmodel
|
||||
GENERIC MAP (
|
||||
HAS_CLOCK_GENERATOR => true,
|
||||
CLOCK_PERIOD_NS => 10,
|
||||
HAS_RESET_GENERATOR => true,
|
||||
RESET_ACTIVE_CYCLES => 100,
|
||||
HAS_MASTER1 => true,
|
||||
MASTER1_DATA_WIDTH => 32,
|
||||
MASTER1_RANDOM_VALID => true,
|
||||
MASTER1_HAS_LAST => false,
|
||||
MASTER1_LAST_PERIOD => 100,
|
||||
MASTER1_HAS_USER => false,
|
||||
MASTER1_USER_PERIOD => 1000,
|
||||
HAS_MASTER2 => true,
|
||||
MASTER2_DATA_WIDTH => 32,
|
||||
MASTER2_RANDOM_VALID => true,
|
||||
MASTER2_HAS_LAST => false,
|
||||
MASTER2_LAST_PERIOD => 100,
|
||||
MASTER2_HAS_USER => false,
|
||||
MASTER2_USER_PERIOD => 1000,
|
||||
HAS_SLAVE => true,
|
||||
SLAVE_DATA_WIDTH => 32,
|
||||
SLAVE_RANDOM_READY => true,
|
||||
SLAVE_HAS_LAST => false,
|
||||
SLAVE_HAS_USER => false,
|
||||
SLAVE_WAIT_FOR_SOF => false,
|
||||
FILE_NAME_M1 => "../../../../mstr1.txt",
|
||||
FILE_NAME_M2 => "../../../../mstr2.txt",
|
||||
FILE_NAME_S => "../../../../slv.txt",
|
||||
HAS_RESETN_INPUT => false
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
ACLK => '0',
|
||||
ARESETN => '1',
|
||||
M1_AXIS_TVALID => M1_AXIS_TVALID,
|
||||
M1_AXIS_TDATA => M1_AXIS_TDATA,
|
||||
M1_AXIS_TREADY => M1_AXIS_TREADY,
|
||||
M1_AXIS_TLAST => M1_AXIS_TLAST,
|
||||
M1_AXIS_TUSER => M1_AXIS_TUSER,
|
||||
M2_AXIS_TVALID => M2_AXIS_TVALID,
|
||||
M2_AXIS_TDATA => M2_AXIS_TDATA,
|
||||
M2_AXIS_TREADY => M2_AXIS_TREADY,
|
||||
M2_AXIS_TLAST => M2_AXIS_TLAST,
|
||||
M2_AXIS_TUSER => M2_AXIS_TUSER,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER
|
||||
);
|
||||
END axis_master_test_axis_numeric_master_0_0_arch;
|
||||
+240
@@ -0,0 +1,240 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_mixer.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020, update 2022
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_mixer is
|
||||
generic
|
||||
(
|
||||
HAS_AXI_LITE_IF : boolean := false;
|
||||
FORCE_01_INPUT : boolean := false;
|
||||
WEIGHT_1 : positive := 1;
|
||||
WEIGHT_2 : positive := 1;
|
||||
SHIFT_DEF : integer := 0;
|
||||
DATA_WIDTH : integer := 16
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic;
|
||||
|
||||
-- AXIS Master
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
M_AXIS_TREADY : in std_logic := '1';
|
||||
|
||||
-- AXIS Slave 1
|
||||
S_AXIS_1_TVALID : in std_logic := '1';
|
||||
S_AXIS_1_TDATA : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
|
||||
S_AXIS_1_TREADY : out std_logic;
|
||||
|
||||
-- AXIS Slave 2
|
||||
S_AXIS_2_TVALID : in std_logic := '1';
|
||||
S_AXIS_2_TDATA : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
|
||||
S_AXIS_2_TREADY : out std_logic;
|
||||
|
||||
-- AXIL Interface
|
||||
S_AXIL_AWADDR : in std_logic_vector(15 downto 0) := (others=>'0');
|
||||
S_AXIL_AWVALID : in std_logic := '0';
|
||||
S_AXIL_AWREADY : out std_logic;
|
||||
S_AXIL_WDATA : in std_logic_vector(31 downto 0) := (others=>'0');
|
||||
S_AXIL_WVALID : in std_logic := '0';
|
||||
S_AXIL_WREADY : out std_logic;
|
||||
S_AXIL_WSTRB : in std_logic_vector( 3 downto 0) := (others=>'0');
|
||||
S_AXIL_BVALID : out std_logic;
|
||||
S_AXIL_BREADY : in std_logic := '1';
|
||||
S_AXIL_BRESP : out std_logic_vector( 1 downto 0);
|
||||
S_AXIL_ARADDR : in std_logic_vector(15 downto 0) := (others=>'0');
|
||||
S_AXIL_ARVALID : in std_logic := '0';
|
||||
S_AXIL_ARREADY : out std_logic;
|
||||
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
|
||||
S_AXIL_RVALID : out std_logic;
|
||||
S_AXIL_RREADY : in std_logic := '1';
|
||||
S_AXIL_RRESP : out std_logic_vector( 1 downto 0)
|
||||
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_mixer is
|
||||
|
||||
signal weight1 : signed(8 downto 0) := to_signed(WEIGHT_1,9);
|
||||
signal weight2 : signed(8 downto 0) := to_signed(WEIGHT_2,9);
|
||||
signal shift : unsigned(3 downto 0) := to_unsigned(SHIFT_DEF,4);
|
||||
|
||||
begin
|
||||
|
||||
process
|
||||
variable datain1 : signed(DATA_WIDTH-1 downto 0);
|
||||
variable datain2 : signed(DATA_WIDTH-1 downto 0);
|
||||
variable tmp2 : signed(DATA_WIDTH-1+9 downto 0);
|
||||
variable tmp1 : signed(DATA_WIDTH-1+9 downto 0);
|
||||
variable res : signed(DATA_WIDTH-1+10 downto 0);
|
||||
variable shift_i : integer;
|
||||
variable tmp1_valid : boolean := false;
|
||||
variable tmp2_valid : boolean := false;
|
||||
variable out_valid : boolean := false;
|
||||
|
||||
begin
|
||||
wait until rising_edge(ACLK);
|
||||
|
||||
if ARESETN = '0' then
|
||||
|
||||
M_AXIS_TVALID <= '0';
|
||||
S_AXIS_1_TREADY <= '0';
|
||||
S_AXIS_2_TREADY <= '0';
|
||||
tmp1 := to_signed(0,DATA_WIDTH+9);
|
||||
tmp2 := to_signed(0,DATA_WIDTH+9);
|
||||
tmp1_valid := false;
|
||||
tmp2_valid := false;
|
||||
out_valid := false;
|
||||
|
||||
else
|
||||
-- nur für Simulation: Falls U,X etc am Eingang, 0 weitergeben
|
||||
-- synthesis translate_off
|
||||
if FORCE_01_INPUT then
|
||||
for i in DATA_WIDTH-1 downto 0 loop
|
||||
if S_AXIS_1_TDATA(i) = '1' then
|
||||
datain1(i) := '1';
|
||||
else
|
||||
datain1(i) := '0';
|
||||
end if;
|
||||
if S_AXIS_2_TDATA(i) = '1' then
|
||||
datain2(i) := '1';
|
||||
else
|
||||
datain2(i) := '0';
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
-- synthesis translate_on
|
||||
|
||||
-- Datenpuffer tmp1 frei? Dann: ready = 1 und ggf. Daten übernehmen
|
||||
if not tmp1_valid then
|
||||
S_AXIS_1_TREADY <= '1';
|
||||
if S_AXIS_1_TVALID = '1' then
|
||||
tmp1 := signed(S_AXIS_1_TDATA)*weight1;
|
||||
tmp1_valid := true;
|
||||
-- Datenpuffer gefüllt, weitere Daten können nicht übernommen werden
|
||||
-- Falls die Daten konsumiert werden, wird ready unten wieder auf 1 gesetzt
|
||||
S_AXIS_1_TREADY <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Datenpuffer tmp2 frei? Dann: ready = 1 und ggf. Daten übernehmen
|
||||
if not tmp2_valid then
|
||||
S_AXIS_2_TREADY <= '1';
|
||||
if S_AXIS_2_TVALID = '1' then
|
||||
tmp2 := signed(S_AXIS_2_TDATA)*weight2;
|
||||
tmp2_valid := true;
|
||||
-- Datenpuffer gefüllt, weitere Daten können nicht übernommen werden
|
||||
-- Falls die Daten konsumiert werden, wird ready unten wieder auf 1 gesetzt
|
||||
S_AXIS_2_TREADY <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Ausgangsdaten übernommen? Dann: keine neuen Daten verfügbar (valid=0)
|
||||
-- Falls in diesem Taktzyklus neue Ausgangsdaten produziert werden,
|
||||
-- wird valid unten wieder auf 1 gesetzt
|
||||
if M_AXIS_TREADY = '1' then
|
||||
M_AXIS_TVALID <= '0';
|
||||
out_valid := false;
|
||||
end if;
|
||||
|
||||
-- Datenpuffer tmp1 UND tmp2 haben gültige Daten UND Ausgangspuffer ist frei?
|
||||
-- Dann: neue Ausgangsdaten produzieren
|
||||
if tmp1_valid and tmp2_valid and (not out_valid) then
|
||||
|
||||
-- Daten aus Eingangspuffer sind konsumiert
|
||||
-- Daher: Pufferinhalt als ungültig markieren UND Epmfangsbereitschaft signalisieren
|
||||
tmp1_valid := false;
|
||||
tmp2_valid := false;
|
||||
S_AXIS_1_TREADY <= '1';
|
||||
S_AXIS_2_TREADY <= '1';
|
||||
|
||||
-- Neue Ausgangsdaten bereitstellen und als gültig markieren
|
||||
res := (tmp1(DATA_WIDTH-1+9)&tmp1)+(tmp2(DATA_WIDTH-1+9)&tmp2);
|
||||
shift_i := to_integer(shift);
|
||||
if shift_i > 10 then shift_i := 10; end if;
|
||||
M_AXIS_TDATA <= std_logic_vector(res(DATA_WIDTH-1+shift_i downto shift_i));
|
||||
M_AXIS_TVALID <= '1';
|
||||
out_valid := true;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
--------------------------------------------------------------------------------------------------
|
||||
-- AXIL
|
||||
--------------------------------------------------------------------------------------------------
|
||||
|
||||
S_AXIL_BRESP <= (others=>'0'); -- No write errors
|
||||
S_AXIL_RRESP <= (others=>'0'); -- No read errors
|
||||
S_AXIL_ARREADY <= '1'; -- IP is always ready
|
||||
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
|
||||
axilgen: if HAS_AXI_LITE_IF generate
|
||||
process begin
|
||||
wait until rising_edge (ACLK);
|
||||
|
||||
if ARESETN = '0' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
S_AXIL_RVALID <= '0';
|
||||
weight1 <= to_signed(WEIGHT_1,9);
|
||||
weight2 <= to_signed(WEIGHT_2,9);
|
||||
shift <= to_unsigned(8,4);
|
||||
else
|
||||
if S_AXIL_RREADY = '1' then
|
||||
S_AXIL_RVALID <= '0';
|
||||
end if;
|
||||
|
||||
if S_AXIL_ARVALID = '1' then
|
||||
S_AXIL_RDATA <= (others=>'0');
|
||||
case S_AXIL_ARADDR(3 downto 2) is
|
||||
when "00" => S_AXIL_RDATA(7 downto 0) <= std_logic_vector(weight1(7 downto 0));
|
||||
when "01" => S_AXIL_RDATA(7 downto 0) <= std_logic_vector(weight2(7 downto 0));
|
||||
when "10" => S_AXIL_RDATA(3 downto 0) <= std_logic_vector(shift);
|
||||
when others => null;
|
||||
end case;
|
||||
S_AXIL_RVALID <= '1';
|
||||
end if;
|
||||
|
||||
if S_AXIL_BREADY = '1' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
end if;
|
||||
|
||||
if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
|
||||
S_AXIL_BVALID <= '1';
|
||||
case S_AXIL_ARADDR(3 downto 2) is
|
||||
when "00" =>
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
weight1(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0));
|
||||
end if;
|
||||
when "01" =>
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
weight2(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0));
|
||||
end if;
|
||||
when "11" =>
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
shift(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0));
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
end;
|
||||
|
||||
+362
@@ -0,0 +1,362 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.vhdl_c_pkg_tb.all;
|
||||
|
||||
entity axis_numeric_master_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
HAS_CLOCK_GENERATOR : boolean := true;
|
||||
CLOCK_PERIOD_NS : integer := 10;
|
||||
|
||||
HAS_RESET_GENERATOR : boolean := true;
|
||||
HAS_RESETN_INPUT : boolean := false;
|
||||
RESET_ACTIVE_CYCLES : integer := 100;
|
||||
|
||||
HAS_MASTER1 : boolean := true;
|
||||
FILE_NAME_M1 : string := string'("../../../../m1.txt");
|
||||
MASTER1_DATA_WIDTH : integer := 32;
|
||||
MASTER1_RANDOM_VALID : boolean := true;
|
||||
MASTER1_HAS_LAST : boolean := true;
|
||||
MASTER1_LAST_PERIOD : integer := 100;
|
||||
MASTER1_HAS_USER : boolean := true;
|
||||
MASTER1_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_MASTER2 : boolean := true;
|
||||
FILE_NAME_M2 : string := string'("../../../../m1.txt");
|
||||
MASTER2_DATA_WIDTH : integer := 32;
|
||||
MASTER2_RANDOM_VALID : boolean := true;
|
||||
MASTER2_HAS_LAST : boolean := true;
|
||||
MASTER2_LAST_PERIOD : integer := 100;
|
||||
MASTER2_HAS_USER : boolean := true;
|
||||
MASTER2_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_SLAVE : boolean := true;
|
||||
FILE_NAME_S : string := string'("../../../../m1.txt");
|
||||
SLAVE_DATA_WIDTH : integer := 32;
|
||||
SLAVE_RANDOM_READY : boolean := true;
|
||||
SLAVE_HAS_LAST : boolean := true;
|
||||
SLAVE_HAS_USER : boolean := true;
|
||||
SLAVE_WAIT_FOR_SOF : boolean := true
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : out std_logic := '0';
|
||||
RESETN : out std_logic := '1';
|
||||
|
||||
ACLK : in std_logic := '0';
|
||||
ARESETN : in std_logic := '1';
|
||||
|
||||
M1_AXIS_TVALID : out std_logic := '0';
|
||||
M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0');
|
||||
M1_AXIS_TREADY : in std_logic := '1';
|
||||
M1_AXIS_TLAST : out std_logic := '0';
|
||||
M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
M2_AXIS_TVALID : out std_logic := '0';
|
||||
M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0');
|
||||
M2_AXIS_TREADY : in std_logic := '1';
|
||||
M2_AXIS_TLAST : out std_logic := '0';
|
||||
M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
S_AXIS_TVALID : in std_logic := '0';
|
||||
S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0);
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0')
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
architecture sim of axis_numeric_master_slave_simmodel is
|
||||
|
||||
signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF";
|
||||
signal rnd_s : unsigned (31 downto 0) := x"12345678";
|
||||
signal lclk : std_logic := '0';
|
||||
signal local_clk : std_logic := ACLK;
|
||||
signal local_resetn : std_logic := '1';
|
||||
|
||||
signal DBG_M1_FILERELOAD : std_logic := '0';
|
||||
signal DBG_M2_FILERELOAD : std_logic := '0';
|
||||
signal DBG_S_FILERELOAD : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
----------------------------------------
|
||||
-- Clock Generator
|
||||
----------------------------------------
|
||||
genclk: if HAS_CLOCK_GENERATOR generate
|
||||
lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns;
|
||||
CLK <= lclk;
|
||||
local_clk <= lclk;
|
||||
end generate;
|
||||
|
||||
no_genclk: if not HAS_CLOCK_GENERATOR generate
|
||||
local_clk <= ACLK;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Reset Generator
|
||||
----------------------------------------
|
||||
genreset: if HAS_RESET_GENERATOR generate
|
||||
process begin
|
||||
RESETN <= '0';
|
||||
local_resetn <= '0';
|
||||
for i in 1 to RESET_ACTIVE_CYCLES loop
|
||||
wait until rising_edge(local_clk);
|
||||
end loop;
|
||||
RESETN <= '1';
|
||||
local_resetn <= '1';
|
||||
wait;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate
|
||||
local_resetn <= ARESETN;
|
||||
end generate;
|
||||
|
||||
|
||||
----------------------------------------
|
||||
-- Random Number Generator
|
||||
----------------------------------------
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
rnd: process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd_m1;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m1 <= r;
|
||||
r := rnd_m2;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m2 <= r;
|
||||
r := rnd_s;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_s <= r;
|
||||
end process;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 1
|
||||
----------------------------------------
|
||||
genmaster1: if HAS_MASTER1 generate
|
||||
m1: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M1_AXIS_TVALID <= '0';
|
||||
M1_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M1, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M1_AXIS_TVALID <= '1';
|
||||
M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0);
|
||||
M1_AXIS_TLAST <= '0';
|
||||
M1_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER1_LAST_PERIOD then
|
||||
M1_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M1_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M1_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER1_RANDOM_VALID) then
|
||||
M1_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M1_AXIS_TVALID <= '0';
|
||||
DBG_M1_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 2
|
||||
----------------------------------------
|
||||
genmaster2: if HAS_MASTER2 generate
|
||||
m2: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M2_AXIS_TVALID <= '0';
|
||||
M2_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M2, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M2_AXIS_TVALID <= '1';
|
||||
M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0);
|
||||
M2_AXIS_TLAST <= '0';
|
||||
M2_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER2_LAST_PERIOD then
|
||||
M2_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M2_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M2_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER2_RANDOM_VALID) then
|
||||
M2_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M2_AXIS_TVALID <= '0';
|
||||
DBG_M2_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- SLAVE
|
||||
----------------------------------------
|
||||
genslave: if HAS_SLAVE generate
|
||||
s: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable rnd : integer;
|
||||
variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_S_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
S_AXIS_TREADY <= '0';
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
elsif wait_sof then
|
||||
if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then
|
||||
wait_sof := false;
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_S, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S);
|
||||
end if;
|
||||
|
||||
while not feof(fp) and fp /= 0 loop
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge (local_clk);
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
if fp > 0 then
|
||||
fscanf(fp, string'("%x"), data);
|
||||
if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then
|
||||
printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length));
|
||||
if (rnd>0 and SLAVE_RANDOM_READY) then
|
||||
S_AXIS_TREADY <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
S_AXIS_TREADY <= '0';
|
||||
DBG_S_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
end;
|
||||
+2604
File diff suppressed because it is too large
Load Diff
@@ -145,7 +145,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>23871aa0</spirit:value>
|
||||
<spirit:value>14047e48</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -158,7 +158,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>23871aa0</spirit:value>
|
||||
<spirit:value>14047e48</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -203,7 +203,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CRC_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -220,7 +220,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CRC_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -250,7 +250,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWITH')) - 1)">15</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -312,7 +312,7 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DWITH')) - 1)">15</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -354,18 +354,6 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CRC_WIDTH</spirit:name>
|
||||
<spirit:displayName>Crc Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CRC_WIDTH" spirit:minimum="0">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DWITH</spirit:name>
|
||||
<spirit:displayName>Dwith</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DWITH" spirit:minimum="0">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
@@ -380,23 +368,13 @@
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axis_crc_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_2a632c0b</spirit:userFileType>
|
||||
<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CRC_WIDTH</spirit:name>
|
||||
<spirit:displayName>Crc Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CRC_WIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DWITH</spirit:name>
|
||||
<spirit:displayName>Dwith</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DWITH" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_crc_v1_0</spirit:value>
|
||||
@@ -417,7 +395,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-02-01T12:46:45Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-02-01T18:35:25Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
+1
-31
@@ -2,39 +2,9 @@
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "CRC_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DWITH" -parent ${Page_0}
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CRC_WIDTH { PARAM_VALUE.CRC_WIDTH } {
|
||||
# Procedure called to update CRC_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CRC_WIDTH { PARAM_VALUE.CRC_WIDTH } {
|
||||
# Procedure called to validate CRC_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DWITH { PARAM_VALUE.DWITH } {
|
||||
# Procedure called to update DWITH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DWITH { PARAM_VALUE.DWITH } {
|
||||
# Procedure called to validate DWITH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.CRC_WIDTH { MODELPARAM_VALUE.CRC_WIDTH PARAM_VALUE.CRC_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CRC_WIDTH}] ${MODELPARAM_VALUE.CRC_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DWITH { MODELPARAM_VALUE.DWITH PARAM_VALUE.DWITH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DWITH}] ${MODELPARAM_VALUE.DWITH}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,24 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sat Feb 1 18:39:19 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target test_1_wrapper.bd
|
||||
--Design : test_1_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity test_1_wrapper is
|
||||
end test_1_wrapper;
|
||||
|
||||
architecture STRUCTURE of test_1_wrapper is
|
||||
component test_1 is
|
||||
end component test_1;
|
||||
begin
|
||||
test_1_i: component test_1
|
||||
;
|
||||
end STRUCTURE;
|
||||
+33
-45
@@ -46,91 +46,79 @@
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_upsizer:1.0
|
||||
-- IP Revision: 3
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_crc_sim_1_axis_upsizer_0_0 IS
|
||||
ENTITY test_1_axis_crc_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axis_crc_sim_1_axis_upsizer_0_0;
|
||||
END test_1_axis_crc_0_0;
|
||||
|
||||
ARCHITECTURE axis_crc_sim_1_axis_upsizer_0_0_arch OF axis_crc_sim_1_axis_upsizer_0_0 IS
|
||||
ARCHITECTURE test_1_axis_crc_0_0_arch OF test_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_upsizer_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_upsizer IS
|
||||
GENERIC (
|
||||
WIDTH_IN : INTEGER;
|
||||
SIZE_FACTOR : INTEGER;
|
||||
BIG_ENDIAN : BOOLEAN
|
||||
);
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF test_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_upsizer;
|
||||
END COMPONENT axis_crc;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_upsizer
|
||||
GENERIC MAP (
|
||||
WIDTH_IN => 16,
|
||||
SIZE_FACTOR => 2,
|
||||
BIG_ENDIAN => false
|
||||
)
|
||||
U0 : axis_crc
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
AXIS_ARESETN => AXIS_ARESETN,
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axis_crc_sim_1_axis_upsizer_0_0_arch;
|
||||
END test_1_axis_crc_0_0_arch;
|
||||
+81
-191
@@ -2,7 +2,7 @@
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>axis_crc_sim_1_axis_downsizer_0_0</spirit:name>
|
||||
<spirit:name>test_1_axis_crc_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
@@ -27,14 +27,6 @@
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
@@ -55,7 +47,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -82,7 +74,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -194,14 +186,6 @@
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
@@ -249,7 +233,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -340,7 +324,7 @@
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:name>RESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
@@ -350,18 +334,18 @@
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:name>RESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
@@ -371,7 +355,7 @@
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
@@ -381,22 +365,22 @@
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">RESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -405,7 +389,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -414,7 +398,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -423,7 +407,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -432,7 +416,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -441,7 +425,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
@@ -452,68 +436,59 @@
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_downsizer</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:0d47368c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axis_crc_sim_1_axis_downsizer_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:0d47368c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:name>RESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>initial_value</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>polynomial</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -525,7 +500,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -535,13 +510,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.WIDTH_OUT')) * spirit:decode(id('MODELPARAM_VALUE.SIZE_FACTOR'))) - 1)">31</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -556,11 +531,11 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
@@ -571,26 +546,11 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -598,7 +558,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -608,13 +568,13 @@
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH_OUT')) - 1)">15</spirit:left>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -626,7 +586,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -638,7 +598,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -646,36 +606,7 @@
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>WIDTH_OUT</spirit:name>
|
||||
<spirit:displayName>Width Out</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH_OUT">16</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SIZE_FACTOR">2</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
@@ -684,62 +615,26 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9185/sources_1/new/axis_downsizer.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axis_crc_sim_1_axis_downsizer_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_downsizer_v1_0</spirit:description>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>WIDTH_OUT</spirit:name>
|
||||
<spirit:displayName>Width Out</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH_OUT">16</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIZE_FACTOR">2</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_crc_sim_1_axis_downsizer_0_0</spirit:value>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">test_1_axis_crc_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_downsizer_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:user:axis_downsizer:1.0_ARCHIVE_LOCATION">d:/projekte/edvs/vivado/vivado/ip_projects/axis_downsizer/axis_downsizer.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:displayName>axis_crc_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -748,10 +643,11 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -760,20 +656,14 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WIDTH_OUT" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4ed6aff9"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0d56d993"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="745602f7"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c0a09c04"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="bb0d91f4"/>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+196
@@ -0,0 +1,196 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_numeric_master_slave_simmodel:1.0
|
||||
-- IP Revision: 18
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY test_1_axis_numeric_master_0_0 IS
|
||||
PORT (
|
||||
CLK : OUT STD_LOGIC;
|
||||
RESETN : OUT STD_LOGIC;
|
||||
M1_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M1_AXIS_TREADY : IN STD_LOGIC;
|
||||
M1_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END test_1_axis_numeric_master_0_0;
|
||||
|
||||
ARCHITECTURE test_1_axis_numeric_master_0_0_arch OF test_1_axis_numeric_master_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF test_1_axis_numeric_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_numeric_master_slave_simmodel IS
|
||||
GENERIC (
|
||||
HAS_CLOCK_GENERATOR : BOOLEAN;
|
||||
CLOCK_PERIOD_NS : INTEGER;
|
||||
HAS_RESET_GENERATOR : BOOLEAN;
|
||||
RESET_ACTIVE_CYCLES : INTEGER;
|
||||
HAS_MASTER1 : BOOLEAN;
|
||||
MASTER1_DATA_WIDTH : INTEGER;
|
||||
MASTER1_RANDOM_VALID : BOOLEAN;
|
||||
MASTER1_HAS_LAST : BOOLEAN;
|
||||
MASTER1_LAST_PERIOD : INTEGER;
|
||||
MASTER1_HAS_USER : BOOLEAN;
|
||||
MASTER1_USER_PERIOD : INTEGER;
|
||||
HAS_MASTER2 : BOOLEAN;
|
||||
MASTER2_DATA_WIDTH : INTEGER;
|
||||
MASTER2_RANDOM_VALID : BOOLEAN;
|
||||
MASTER2_HAS_LAST : BOOLEAN;
|
||||
MASTER2_LAST_PERIOD : INTEGER;
|
||||
MASTER2_HAS_USER : BOOLEAN;
|
||||
MASTER2_USER_PERIOD : INTEGER;
|
||||
HAS_SLAVE : BOOLEAN;
|
||||
SLAVE_DATA_WIDTH : INTEGER;
|
||||
SLAVE_RANDOM_READY : BOOLEAN;
|
||||
SLAVE_HAS_LAST : BOOLEAN;
|
||||
SLAVE_HAS_USER : BOOLEAN;
|
||||
SLAVE_WAIT_FOR_SOF : BOOLEAN;
|
||||
FILE_NAME_M1 : STRING;
|
||||
FILE_NAME_M2 : STRING;
|
||||
FILE_NAME_S : STRING;
|
||||
HAS_RESETN_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
CLK : OUT STD_LOGIC;
|
||||
RESETN : OUT STD_LOGIC;
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M1_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M1_AXIS_TREADY : IN STD_LOGIC;
|
||||
M1_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M2_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M2_AXIS_TREADY : IN STD_LOGIC;
|
||||
M2_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_numeric_master_slave_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RESETN, ASSOCIATED_BUSIF S_AXIS:M2_AXIS:M1_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M1_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M1_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_numeric_master_slave_simmodel
|
||||
GENERIC MAP (
|
||||
HAS_CLOCK_GENERATOR => true,
|
||||
CLOCK_PERIOD_NS => 10,
|
||||
HAS_RESET_GENERATOR => true,
|
||||
RESET_ACTIVE_CYCLES => 100,
|
||||
HAS_MASTER1 => true,
|
||||
MASTER1_DATA_WIDTH => 32,
|
||||
MASTER1_RANDOM_VALID => true,
|
||||
MASTER1_HAS_LAST => true,
|
||||
MASTER1_LAST_PERIOD => 100,
|
||||
MASTER1_HAS_USER => false,
|
||||
MASTER1_USER_PERIOD => 1000,
|
||||
HAS_MASTER2 => false,
|
||||
MASTER2_DATA_WIDTH => 32,
|
||||
MASTER2_RANDOM_VALID => true,
|
||||
MASTER2_HAS_LAST => false,
|
||||
MASTER2_LAST_PERIOD => 100,
|
||||
MASTER2_HAS_USER => false,
|
||||
MASTER2_USER_PERIOD => 1000,
|
||||
HAS_SLAVE => true,
|
||||
SLAVE_DATA_WIDTH => 32,
|
||||
SLAVE_RANDOM_READY => true,
|
||||
SLAVE_HAS_LAST => true,
|
||||
SLAVE_HAS_USER => false,
|
||||
SLAVE_WAIT_FOR_SOF => false,
|
||||
FILE_NAME_M1 => "../../../../m1.txt",
|
||||
FILE_NAME_M2 => "../../../../m1.txt",
|
||||
FILE_NAME_S => "../../../../m1.txt",
|
||||
HAS_RESETN_INPUT => false
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
ACLK => '0',
|
||||
ARESETN => '1',
|
||||
M1_AXIS_TVALID => M1_AXIS_TVALID,
|
||||
M1_AXIS_TDATA => M1_AXIS_TDATA,
|
||||
M1_AXIS_TREADY => M1_AXIS_TREADY,
|
||||
M1_AXIS_TLAST => M1_AXIS_TLAST,
|
||||
M1_AXIS_TUSER => M1_AXIS_TUSER,
|
||||
M2_AXIS_TREADY => '1',
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER
|
||||
);
|
||||
END test_1_axis_numeric_master_0_0_arch;
|
||||
+1838
File diff suppressed because it is too large
Load Diff
+65
@@ -0,0 +1,65 @@
|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _test_1_xlconstant_0_0_H_
|
||||
#define _test_1_xlconstant_0_0_H_
|
||||
|
||||
#include "xlconstant_v1_1_7.h"
|
||||
#include "systemc.h"
|
||||
class test_1_xlconstant_0_0 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_7<32,0> mod;
|
||||
sc_out< sc_bv<32> > dout;
|
||||
test_1_xlconstant_0_0 (sc_core::sc_module_name name);
|
||||
};
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module test_1_xlconstant_0_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [31 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(32),
|
||||
.CONST_VAL(32'H00000000)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: xl_Constant_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`ifdef XILINX_SIMULATOR
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module test_1_xlconstant_0_0 (
|
||||
output bit [31 : 0 ] dout
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module test_1_xlconstant_0_0 (dout)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
output wire [31 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _xlconstant_v1_1_7_H_
|
||||
#define _xlconstant_v1_1_7_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,long int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_7) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_7) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+206
@@ -0,0 +1,206 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>test_1_xlconstant_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulation</spirit:name>
|
||||
<spirit:displayName>SystemC Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>systemc</spirit:language>
|
||||
<spirit:modelName>xlconstant_v1_1_7</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 16:15:06 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bb996ab6</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>systemc</spirit:language>
|
||||
<spirit:modelName>test_1_xlconstant_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_systemcsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 16:15:06 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bb996ab6</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 16:15:06 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bb996ab6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>test_1_xlconstant_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 16:15:06 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:bb996ab6</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>dout</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CONST_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CONST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Const Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CONST_VAL</spirit:name>
|
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _test_1_xlconstant_1_0_H_
|
||||
#define _test_1_xlconstant_1_0_H_
|
||||
|
||||
#include "xlconstant_v1_1_7.h"
|
||||
#include "systemc.h"
|
||||
class test_1_xlconstant_1_0 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_7<32,0> mod;
|
||||
sc_out< sc_bv<32> > dout;
|
||||
test_1_xlconstant_1_0 (sc_core::sc_module_name name);
|
||||
};
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module test_1_xlconstant_1_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [31 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(32),
|
||||
.CONST_VAL(32'H00000000)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: xl_Constant_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`ifdef XILINX_SIMULATOR
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module test_1_xlconstant_1_0 (
|
||||
output bit [31 : 0 ] dout
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module test_1_xlconstant_1_0 (dout)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
output wire [31 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _xlconstant_v1_1_7_H_
|
||||
#define _xlconstant_v1_1_7_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,long int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_7) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_7) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+206
@@ -0,0 +1,206 @@
|
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||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8609d079</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>tlm</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 16:15:06 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8609d079</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>test_1_xlconstant_1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 17:07:49 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8609d079</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>dout</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CONST_WIDTH')) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CONST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Const Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CONST_VAL</spirit:name>
|
||||
<spirit:displayName>Const Val</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="32">0x00000000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/xlconstant_v1_1_7.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/test_1_xlconstant_1_0.h</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/test_1_xlconstant_1_0.cpp</spirit:name>
|
||||
<spirit:fileType>systemCSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/test_1_xlconstant_1_0_stub.sv</spirit:name>
|
||||
<spirit:fileType>systemVerilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/test_1_xlconstant_1_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Gives a constant signed value.</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">test_1_xlconstant_1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CONST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Const Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CONST_VAL</spirit:name>
|
||||
<spirit:displayName>Const Val</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Constant</xilinx:displayName>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="412efde3"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
//------------------------------------------------------------------------
|
||||
//--
|
||||
//-- Filename : xlconstant.v
|
||||
//--
|
||||
//-- Date : 06/05/12
|
||||
//--
|
||||
//-- Description : VERILOG description of a constant block. This
|
||||
//-- block does not use a core.
|
||||
//--
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
//--
|
||||
//-- Module : xlconstant
|
||||
//--
|
||||
//-- Architecture : behavior
|
||||
//--
|
||||
//-- Description : Top level VERILOG description of constant block
|
||||
//--
|
||||
//------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
module xlconstant_v1_1_7_xlconstant (dout);
|
||||
parameter CONST_VAL = 1;
|
||||
parameter CONST_WIDTH = 1;
|
||||
output [CONST_WIDTH-1:0] dout;
|
||||
|
||||
assign dout = CONST_VAL;
|
||||
endmodule
|
||||
|
||||
|
||||
+362
@@ -0,0 +1,362 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.vhdl_c_pkg_tb.all;
|
||||
|
||||
entity axis_numeric_master_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
HAS_CLOCK_GENERATOR : boolean := true;
|
||||
CLOCK_PERIOD_NS : integer := 10;
|
||||
|
||||
HAS_RESET_GENERATOR : boolean := true;
|
||||
HAS_RESETN_INPUT : boolean := false;
|
||||
RESET_ACTIVE_CYCLES : integer := 100;
|
||||
|
||||
HAS_MASTER1 : boolean := true;
|
||||
FILE_NAME_M1 : string := string'("../../../../m1.txt");
|
||||
MASTER1_DATA_WIDTH : integer := 32;
|
||||
MASTER1_RANDOM_VALID : boolean := true;
|
||||
MASTER1_HAS_LAST : boolean := true;
|
||||
MASTER1_LAST_PERIOD : integer := 100;
|
||||
MASTER1_HAS_USER : boolean := true;
|
||||
MASTER1_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_MASTER2 : boolean := true;
|
||||
FILE_NAME_M2 : string := string'("../../../../m1.txt");
|
||||
MASTER2_DATA_WIDTH : integer := 32;
|
||||
MASTER2_RANDOM_VALID : boolean := true;
|
||||
MASTER2_HAS_LAST : boolean := true;
|
||||
MASTER2_LAST_PERIOD : integer := 100;
|
||||
MASTER2_HAS_USER : boolean := true;
|
||||
MASTER2_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_SLAVE : boolean := true;
|
||||
FILE_NAME_S : string := string'("../../../../m1.txt");
|
||||
SLAVE_DATA_WIDTH : integer := 32;
|
||||
SLAVE_RANDOM_READY : boolean := true;
|
||||
SLAVE_HAS_LAST : boolean := true;
|
||||
SLAVE_HAS_USER : boolean := true;
|
||||
SLAVE_WAIT_FOR_SOF : boolean := true
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : out std_logic := '0';
|
||||
RESETN : out std_logic := '1';
|
||||
|
||||
ACLK : in std_logic := '0';
|
||||
ARESETN : in std_logic := '1';
|
||||
|
||||
M1_AXIS_TVALID : out std_logic := '0';
|
||||
M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0');
|
||||
M1_AXIS_TREADY : in std_logic := '1';
|
||||
M1_AXIS_TLAST : out std_logic := '0';
|
||||
M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
M2_AXIS_TVALID : out std_logic := '0';
|
||||
M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0');
|
||||
M2_AXIS_TREADY : in std_logic := '1';
|
||||
M2_AXIS_TLAST : out std_logic := '0';
|
||||
M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
S_AXIS_TVALID : in std_logic := '0';
|
||||
S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0);
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0')
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
architecture sim of axis_numeric_master_slave_simmodel is
|
||||
|
||||
signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF";
|
||||
signal rnd_s : unsigned (31 downto 0) := x"12345678";
|
||||
signal lclk : std_logic := '0';
|
||||
signal local_clk : std_logic := ACLK;
|
||||
signal local_resetn : std_logic := '1';
|
||||
|
||||
signal DBG_M1_FILERELOAD : std_logic := '0';
|
||||
signal DBG_M2_FILERELOAD : std_logic := '0';
|
||||
signal DBG_S_FILERELOAD : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
----------------------------------------
|
||||
-- Clock Generator
|
||||
----------------------------------------
|
||||
genclk: if HAS_CLOCK_GENERATOR generate
|
||||
lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns;
|
||||
CLK <= lclk;
|
||||
local_clk <= lclk;
|
||||
end generate;
|
||||
|
||||
no_genclk: if not HAS_CLOCK_GENERATOR generate
|
||||
local_clk <= ACLK;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Reset Generator
|
||||
----------------------------------------
|
||||
genreset: if HAS_RESET_GENERATOR generate
|
||||
process begin
|
||||
RESETN <= '0';
|
||||
local_resetn <= '0';
|
||||
for i in 1 to RESET_ACTIVE_CYCLES loop
|
||||
wait until rising_edge(local_clk);
|
||||
end loop;
|
||||
RESETN <= '1';
|
||||
local_resetn <= '1';
|
||||
wait;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate
|
||||
local_resetn <= ARESETN;
|
||||
end generate;
|
||||
|
||||
|
||||
----------------------------------------
|
||||
-- Random Number Generator
|
||||
----------------------------------------
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
rnd: process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd_m1;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m1 <= r;
|
||||
r := rnd_m2;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m2 <= r;
|
||||
r := rnd_s;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_s <= r;
|
||||
end process;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 1
|
||||
----------------------------------------
|
||||
genmaster1: if HAS_MASTER1 generate
|
||||
m1: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M1_AXIS_TVALID <= '0';
|
||||
M1_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M1, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M1_AXIS_TVALID <= '1';
|
||||
M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0);
|
||||
M1_AXIS_TLAST <= '0';
|
||||
M1_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER1_LAST_PERIOD then
|
||||
M1_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M1_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M1_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER1_RANDOM_VALID) then
|
||||
M1_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M1_AXIS_TVALID <= '0';
|
||||
DBG_M1_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 2
|
||||
----------------------------------------
|
||||
genmaster2: if HAS_MASTER2 generate
|
||||
m2: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M2_AXIS_TVALID <= '0';
|
||||
M2_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M2, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M2_AXIS_TVALID <= '1';
|
||||
M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0);
|
||||
M2_AXIS_TLAST <= '0';
|
||||
M2_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER2_LAST_PERIOD then
|
||||
M2_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M2_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M2_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER2_RANDOM_VALID) then
|
||||
M2_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M2_AXIS_TVALID <= '0';
|
||||
DBG_M2_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- SLAVE
|
||||
----------------------------------------
|
||||
genslave: if HAS_SLAVE generate
|
||||
s: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable rnd : integer;
|
||||
variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_S_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
S_AXIS_TREADY <= '0';
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
elsif wait_sof then
|
||||
if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then
|
||||
wait_sof := false;
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_S, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S);
|
||||
end if;
|
||||
|
||||
while not feof(fp) and fp /= 0 loop
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge (local_clk);
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
if fp > 0 then
|
||||
fscanf(fp, string'("%x"), data);
|
||||
if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then
|
||||
printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length));
|
||||
if (rnd>0 and SLAVE_RANDOM_READY) then
|
||||
S_AXIS_TREADY <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
S_AXIS_TREADY <= '0';
|
||||
DBG_S_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
end;
|
||||
+2604
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="test_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738434926"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738434926"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738434926"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738434926"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+6
-6
@@ -774,8 +774,8 @@
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "auto"
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
@@ -810,7 +810,7 @@
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
@@ -833,8 +833,8 @@
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "auto"
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
@@ -869,7 +869,7 @@
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
|
||||
+19
-19
@@ -76,26 +76,26 @@
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+4
-10
@@ -8,14 +8,8 @@
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CRC_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DWITH": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axis_crc_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CRC_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DWITH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
@@ -47,11 +41,11 @@
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
@@ -61,7 +55,7 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -87,7 +81,7 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+36
-36
@@ -168,25 +168,25 @@
|
||||
"address_space_ref": "M_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -242,26 +242,26 @@
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"-51,-91",
|
||||
"Default View_TopLeft":"1191,-40",
|
||||
"Display-PortTypeOthers":"true",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_ExpandedHierarchyInLayout":"",
|
||||
@@ -19,14 +19,14 @@ pagesize -pg 1 -db -bbox -sgen 0 0 1990 480
|
||||
"Interfaces View_TopLeft":"-199,-369",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 590 -y 78 -defaultsOSRD
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 600 -y 78 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 110 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 120 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 2 220 20 490J
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 2 230 30 470J
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 480 58n
|
||||
levelinfo -pg 1 0 110 350 590 670
|
||||
pagesize -pg 1 -db -bbox -sgen 0 -10 2680 420
|
||||
levelinfo -pg 1 0 110 350 600 680
|
||||
pagesize -pg 1 -db -bbox -sgen 0 -10 2700 420
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
+208
-290
@@ -7,20 +7,15 @@
|
||||
"name": "axis_crc_sim_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
"axis_slave_simmodel_0": "",
|
||||
"axis_master_simmodel_0": "",
|
||||
"crc": {
|
||||
"axis_downsizer_0": "",
|
||||
"axis_upsizer_0": "",
|
||||
"xlconstant_1": "",
|
||||
"xlconstant_0": "",
|
||||
"axis_crc_0": ""
|
||||
}
|
||||
"xlconstant_1": "",
|
||||
"xlconstant_0": "",
|
||||
"axis_crc_0": ""
|
||||
},
|
||||
"components": {
|
||||
"clk_rst_generator_0": {
|
||||
@@ -37,6 +32,12 @@
|
||||
"parameters": {
|
||||
"FILE_EXTENSION": {
|
||||
"value": "raw"
|
||||
},
|
||||
"NUM_LINES": {
|
||||
"value": "1"
|
||||
},
|
||||
"NUM_PIX_PER_LINE": {
|
||||
"value": "3"
|
||||
}
|
||||
}
|
||||
},
|
||||
@@ -46,301 +47,206 @@
|
||||
"xci_path": "ip\\axis_crc_sim_1_axis_master_simmodel_0_0\\axis_crc_sim_1_axis_master_simmodel_0_0.xci",
|
||||
"inst_hier_path": "axis_master_simmodel_0",
|
||||
"parameters": {
|
||||
"FILE_AUTONUMBERING": {
|
||||
"value": "false"
|
||||
},
|
||||
"FILE_EXTENSION": {
|
||||
"value": "raw"
|
||||
},
|
||||
"NUM_LINES": {
|
||||
"value": "1"
|
||||
},
|
||||
"NUM_PIX_PER_LINE": {
|
||||
"value": "3"
|
||||
}
|
||||
}
|
||||
},
|
||||
"crc": {
|
||||
"xlconstant_1": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "axis_crc_sim_1_xlconstant_1_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_xlconstant_1_0\\axis_crc_sim_1_xlconstant_1_0.xci",
|
||||
"inst_hier_path": "xlconstant_1",
|
||||
"parameters": {
|
||||
"CONST_WIDTH": {
|
||||
"value": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"xlconstant_0": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "axis_crc_sim_1_xlconstant_0_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_xlconstant_0_0\\axis_crc_sim_1_xlconstant_0_0.xci",
|
||||
"inst_hier_path": "xlconstant_0",
|
||||
"parameters": {
|
||||
"CONST_WIDTH": {
|
||||
"value": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axis_crc_sim_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_axis_crc_0_0\\axis_crc_sim_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"AXIS_ACLK": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I"
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXIS_ARESETN": {
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"axis_downsizer_0": {
|
||||
"vlnv": "xilinx.com:user:axis_downsizer:1.0",
|
||||
"xci_name": "axis_crc_sim_1_axis_downsizer_0_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_axis_downsizer_0_0\\axis_crc_sim_1_axis_downsizer_0_0.xci",
|
||||
"inst_hier_path": "crc/axis_downsizer_0",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"WIDTH_OUT": {
|
||||
"value": "16"
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_upsizer_0": {
|
||||
"vlnv": "xilinx.com:user:axis_upsizer:1.0",
|
||||
"xci_name": "axis_crc_sim_1_axis_upsizer_0_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_axis_upsizer_0_0\\axis_crc_sim_1_axis_upsizer_0_0.xci",
|
||||
"inst_hier_path": "crc/axis_upsizer_0",
|
||||
"parameters": {
|
||||
"WIDTH_IN": {
|
||||
"value": "16"
|
||||
}
|
||||
}
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"xlconstant_1": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "axis_crc_sim_1_xlconstant_1_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_xlconstant_1_0\\axis_crc_sim_1_xlconstant_1_0.xci",
|
||||
"inst_hier_path": "crc/xlconstant_1",
|
||||
"parameters": {
|
||||
"CONST_WIDTH": {
|
||||
"value": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"xlconstant_0": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "axis_crc_sim_1_xlconstant_0_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_xlconstant_0_0\\axis_crc_sim_1_xlconstant_0_0.xci",
|
||||
"inst_hier_path": "crc/xlconstant_0",
|
||||
"parameters": {
|
||||
"CONST_WIDTH": {
|
||||
"value": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "axis_crc_sim_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\axis_crc_sim_1_axis_crc_0_0\\axis_crc_sim_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "crc/axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"axis_downsizer_0/S_AXIS",
|
||||
"S_AXIS"
|
||||
]
|
||||
},
|
||||
"Conn2": {
|
||||
"interface_ports": [
|
||||
"axis_upsizer_0/M_AXIS",
|
||||
"M_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_crc_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_crc_0/M_AXIS",
|
||||
"axis_upsizer_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_downsizer_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_downsizer_0/M_AXIS",
|
||||
"axis_crc_0/S_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"AXIS_ACLK_1": {
|
||||
"ports": [
|
||||
"AXIS_ACLK",
|
||||
"axis_downsizer_0/AXIS_ACLK",
|
||||
"axis_upsizer_0/AXIS_ACLK",
|
||||
"axis_crc_0/CLK"
|
||||
]
|
||||
},
|
||||
"AXIS_ARESETN_1": {
|
||||
"ports": [
|
||||
"AXIS_ARESETN",
|
||||
"axis_downsizer_0/AXIS_ARESETN",
|
||||
"axis_upsizer_0/AXIS_ARESETN",
|
||||
"axis_crc_0/RESETN"
|
||||
]
|
||||
},
|
||||
"xlconstant_0_dout": {
|
||||
"ports": [
|
||||
"xlconstant_0/dout",
|
||||
"axis_crc_0/polynomial"
|
||||
]
|
||||
},
|
||||
"xlconstant_1_dout": {
|
||||
"ports": [
|
||||
"xlconstant_1/dout",
|
||||
"axis_crc_0/initial_value"
|
||||
]
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -349,13 +255,13 @@
|
||||
"axis_master_simmodel_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_master_simmodel_0/M_AXIS",
|
||||
"crc/S_AXIS"
|
||||
"axis_crc_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"crc_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_slave_simmodel_0/S_AXIS",
|
||||
"crc/M_AXIS"
|
||||
"axis_crc_0/M_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
@@ -364,8 +270,8 @@
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axis_slave_simmodel_0/S_AXIS_ARESETN",
|
||||
"crc/AXIS_ARESETN",
|
||||
"axis_master_simmodel_0/ARESETN"
|
||||
"axis_master_simmodel_0/ARESETN",
|
||||
"axis_crc_0/RESETN"
|
||||
]
|
||||
},
|
||||
"axis_master_simmodel_0_FINISHED": {
|
||||
@@ -378,8 +284,20 @@
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_master_simmodel_0/ACLK",
|
||||
"crc/AXIS_ACLK",
|
||||
"axis_slave_simmodel_0/S_AXIS_ACLK"
|
||||
"axis_slave_simmodel_0/S_AXIS_ACLK",
|
||||
"axis_crc_0/CLK"
|
||||
]
|
||||
},
|
||||
"xlconstant_0_dout": {
|
||||
"ports": [
|
||||
"xlconstant_0/dout",
|
||||
"axis_crc_0/polynomial"
|
||||
]
|
||||
},
|
||||
"xlconstant_1_dout": {
|
||||
"ports": [
|
||||
"xlconstant_1/dout",
|
||||
"axis_crc_0/initial_value"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
+4
-10
@@ -8,14 +8,8 @@
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CRC_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DWITH": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_crc_sim_1_axis_crc_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CRC_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DWITH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
@@ -47,11 +41,11 @@
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
@@ -61,7 +55,7 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -87,7 +81,7 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+5
-5
@@ -17,9 +17,9 @@
|
||||
"PIXEL_FORMAT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RANDOM_TVALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FILE_AUTONUMBERING": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"FILE_EXTENSION": [ { "value": "raw", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FILE_NAME": [ { "value": "../../../tst", "resolve_type": "user", "usage": "all" } ],
|
||||
"TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -37,8 +37,8 @@
|
||||
"FILE_NAME": [ { "value": "../../../../tst", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FILE_EXTENSION": [ { "value": "raw", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"RANDOM_TVALID": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"PIXEL_FORMAT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
|
||||
+4
-4
@@ -13,8 +13,8 @@
|
||||
"FRAMING_PIXELS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_FILES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PIXEL_FORMAT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"FILE_EXTENSION": [ { "value": "raw", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -28,8 +28,8 @@
|
||||
"FILE_EXTENSION": [ { "value": "raw", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"PIXEL_FORMAT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "128", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_FILES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FRAMING_PIXELS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_crc_sim_1_xlconstant_0_0",
|
||||
"cell_name": "crc/xlconstant_0",
|
||||
"cell_name": "xlconstant_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0",
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_crc_sim_1_xlconstant_1_0",
|
||||
"cell_name": "crc/xlconstant_1",
|
||||
"cell_name": "xlconstant_1",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0",
|
||||
|
||||
+18
-29
@@ -1,36 +1,25 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.876705",
|
||||
"Default View_TopLeft":"10,-91",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"-180,-69",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 130 -y 490 -defaultsOSRD
|
||||
preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 1660 -y 80 -defaultsOSRD
|
||||
preplace inst axis_master_simmodel_0 -pg 1 -lvl 2 -x 350 -y 490 -defaultsOSRD
|
||||
preplace inst crc -pg 1 -lvl 3 -x 680 -y 240 -defaultsOSRD
|
||||
preplace inst crc|axis_downsizer_0 -pg 1 -lvl 1 -x 750 -y 500 -defaultsOSRD
|
||||
preplace inst crc|axis_upsizer_0 -pg 1 -lvl 3 -x 1310 -y 560 -defaultsOSRD
|
||||
preplace inst crc|xlconstant_1 -pg 1 -lvl 1 -x 750 -y 250 -defaultsOSRD
|
||||
preplace inst crc|xlconstant_0 -pg 1 -lvl 1 -x 750 -y 350 -defaultsOSRD
|
||||
preplace inst crc|axis_crc_0 -pg 1 -lvl 2 -x 1040 -y 540 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 240 410 460 80 NJ
|
||||
preplace netloc AXIS_ARESETN_1 1 1 3 250 420 470 100 NJ
|
||||
preplace netloc axis_master_simmodel_0_FINISHED 1 0 3 20 400 NJ 400 450
|
||||
preplace netloc axis_master_simmodel_0_M_AXIS 1 2 1 N 480
|
||||
preplace netloc crc_M_AXIS 1 3 1 1540 60n
|
||||
preplace netloc crc|AXIS_ACLK_1 1 0 3 630 580 870 640 1180J
|
||||
preplace netloc crc|AXIS_ARESETN_1 1 0 3 620 590 890 650 1190J
|
||||
preplace netloc crc|xlconstant_1_dout 1 1 1 900J 250n
|
||||
preplace netloc crc|xlconstant_0_dout 1 1 1 880J 350n
|
||||
preplace netloc crc|axis_downsizer_0_M_AXIS 1 1 1 N 500
|
||||
preplace netloc crc|axis_crc_0_M_AXIS 1 2 1 N 540
|
||||
preplace netloc crc|Conn1 1 0 1 N 480
|
||||
preplace netloc crc|Conn2 1 3 1 N 560
|
||||
levelinfo -pg 1 0 130 350 680 1660 1800
|
||||
levelinfo -hier crc * 750 1040 1310 *
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1800 680
|
||||
pagesize -hier crc -db -bbox -sgen 590 190 1460 660
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 130 -y 280 -defaultsOSRD
|
||||
preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 920 -y 340 -defaultsOSRD
|
||||
preplace inst axis_master_simmodel_0 -pg 1 -lvl 2 -x 350 -y 290 -defaultsOSRD
|
||||
preplace inst xlconstant_1 -pg 1 -lvl 2 -x 350 -y 80 -defaultsOSRD
|
||||
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 350 -y 180 -defaultsOSRD
|
||||
preplace inst axis_crc_0 -pg 1 -lvl 3 -x 640 -y 320 -defaultsOSRD
|
||||
preplace netloc AXIS_ARESETN_1 1 1 3 240 380 500 420 790J
|
||||
preplace netloc axis_master_simmodel_0_FINISHED 1 0 3 20 360 NJ 360 450
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 250 370 480 430 780J
|
||||
preplace netloc xlconstant_0_dout 1 2 1 460J 180n
|
||||
preplace netloc xlconstant_1_dout 1 2 1 490J 80n
|
||||
preplace netloc axis_master_simmodel_0_M_AXIS 1 2 1 N 280
|
||||
preplace netloc crc_M_AXIS 1 3 1 N 320
|
||||
levelinfo -pg 1 0 130 350 640 920 1040
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1040 440
|
||||
"
|
||||
}
|
||||
|
||||
0
|
||||
|
||||
+117
@@ -0,0 +1,117 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test",
|
||||
"name": "axis_master_test",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"axis_mixer_0": "",
|
||||
"axis_numeric_master_0": ""
|
||||
},
|
||||
"components": {
|
||||
"axis_mixer_0": {
|
||||
"vlnv": "xilinx.com:user:axis_mixer:1.0",
|
||||
"xci_name": "axis_master_test_axis_mixer_0_0",
|
||||
"xci_path": "ip\\axis_master_test_axis_mixer_0_0\\axis_master_test_axis_mixer_0_0.xci",
|
||||
"inst_hier_path": "axis_mixer_0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"WEIGHT_1": {
|
||||
"value": "1"
|
||||
},
|
||||
"WEIGHT_2": {
|
||||
"value": "1"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_numeric_master_0": {
|
||||
"vlnv": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
|
||||
"xci_name": "axis_master_test_axis_numeric_master_0_0",
|
||||
"xci_path": "ip\\axis_master_test_axis_numeric_master_0_0\\axis_master_test_axis_numeric_master_0_0.xci",
|
||||
"inst_hier_path": "axis_numeric_master_0",
|
||||
"parameters": {
|
||||
"FILE_NAME_M1": {
|
||||
"value": "../../../../mstr1.txt"
|
||||
},
|
||||
"FILE_NAME_M2": {
|
||||
"value": "../../../../mstr2.txt"
|
||||
},
|
||||
"FILE_NAME_S": {
|
||||
"value": "../../../../slv.txt"
|
||||
},
|
||||
"MASTER1_HAS_LAST": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER1_HAS_USER": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER1_RANDOM_VALID": {
|
||||
"value": "true"
|
||||
},
|
||||
"MASTER2_HAS_LAST": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER2_HAS_USER": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER2_RANDOM_VALID": {
|
||||
"value": "true"
|
||||
},
|
||||
"SLAVE_HAS_LAST": {
|
||||
"value": "false"
|
||||
},
|
||||
"SLAVE_HAS_USER": {
|
||||
"value": "false"
|
||||
},
|
||||
"SLAVE_RANDOM_READY": {
|
||||
"value": "true"
|
||||
},
|
||||
"SLAVE_WAIT_FOR_SOF": {
|
||||
"value": "false"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axis_mixer_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_mixer_0/M_AXIS",
|
||||
"axis_numeric_master_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_numeric_master_0_M1_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_mixer_0/S_AXIS_1",
|
||||
"axis_numeric_master_0/M1_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_numeric_master_0_M2_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_mixer_0/S_AXIS_2",
|
||||
"axis_numeric_master_0/M2_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"axis_numeric_master_0_CLK": {
|
||||
"ports": [
|
||||
"axis_numeric_master_0/CLK",
|
||||
"axis_mixer_0/ACLK"
|
||||
]
|
||||
},
|
||||
"axis_numeric_master_0_RESETN": {
|
||||
"ports": [
|
||||
"axis_numeric_master_0/RESETN",
|
||||
"axis_mixer_0/ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+84
-47
@@ -1,22 +1,28 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_crc_sim_1_axis_downsizer_0_0",
|
||||
"cell_name": "crc/axis_downsizer_0",
|
||||
"component_reference": "xilinx.com:user:axis_downsizer:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0",
|
||||
"xci_name": "axis_master_test_axis_mixer_0_0",
|
||||
"cell_name": "axis_mixer_0",
|
||||
"component_reference": "xilinx.com:user:axis_mixer:1.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"WIDTH_OUT": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_crc_sim_1_axis_downsizer_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
"WEIGHT_1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_master_test_axis_mixer_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_AXI_LITE_IF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"WEIGHT_2": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FORCE_01_INPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SHIFT_DEF": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"WIDTH_OUT": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
"WEIGHT_1": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_AXI_LITE_IF": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"WEIGHT_2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FORCE_01_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SHIFT_DEF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
@@ -33,9 +39,9 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_downsizer_0_0" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
@@ -44,18 +50,17 @@
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"AXIS_ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_TUSER": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"ACLK": [ { "direction": "in" } ],
|
||||
"ARESETN": [ { "direction": "in" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIS_TUSER": [ { "direction": "out" } ]
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIS_1_TVALID": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIS_1_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_1_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_2_TVALID": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIS_2_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_2_TREADY": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
@@ -63,29 +68,27 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"S_AXIS_1": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
@@ -93,26 +96,49 @@
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
"TDATA": [ { "physical_name": "S_AXIS_1_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_1_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_1_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ARESETN": {
|
||||
"S_AXIS_2": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_2_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_2_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_2_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
@@ -121,25 +147,36 @@
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXIS_ARESETN" } ]
|
||||
"RST": [ { "physical_name": "ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIL:S_AXIS_2:S_AXIS_1:M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
"CLK": [ { "physical_name": "ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0",
|
||||
"range": "65536",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+230
@@ -0,0 +1,230 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_master_test_axis_numeric_master_0_0",
|
||||
"cell_name": "axis_numeric_master_0",
|
||||
"component_reference": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"HAS_MASTER1": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"MASTER1_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_USER_PERIOD": [ { "value": "1000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MASTER2": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"SLAVE_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SLAVE_RANDOM_READY": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"SLAVE_WAIT_FOR_SOF": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"FILE_NAME_M1": [ { "value": "../../../../mstr1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FILE_NAME_M2": [ { "value": "../../../../mstr2.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TREADY": [ { "physical_name": "M1_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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|
||||
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|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M2_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M2_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M2_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M2_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M2_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
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|
||||
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|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "RESETN" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M2_AXIS:M1_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.25",
|
||||
"Default View_TopLeft":"-450,-164",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axis_mixer_0 -pg 1 -lvl 2 -x 350 -y 90 -defaultsOSRD
|
||||
preplace inst axis_numeric_master_0 -pg 1 -lvl 1 -x 130 -y 90 -defaultsOSRD
|
||||
preplace netloc axis_numeric_master_0_CLK 1 1 1 N 100
|
||||
preplace netloc axis_numeric_master_0_RESETN 1 1 1 N 120
|
||||
preplace netloc axis_mixer_0_M_AXIS 1 0 3 20 180 NJ 180 460
|
||||
preplace netloc axis_numeric_master_0_M1_AXIS 1 1 1 N 60
|
||||
preplace netloc axis_numeric_master_0_M2_AXIS 1 1 1 N 80
|
||||
levelinfo -pg 1 0 130 350 480
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 480 190
|
||||
"
|
||||
}
|
||||
0
|
||||
+25
-35
@@ -1,22 +1,14 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axis_crc_sim_1_axis_upsizer_0_0",
|
||||
"cell_name": "crc/axis_upsizer_0",
|
||||
"component_reference": "xilinx.com:user:axis_upsizer:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0",
|
||||
"xci_name": "test_1_axis_crc_0_0",
|
||||
"cell_name": "axis_crc_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"WIDTH_IN": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "axis_crc_sim_1_axis_upsizer_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"WIDTH_IN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
"Component_Name": [ { "value": "test_1_axis_crc_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
@@ -33,29 +25,29 @@
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_upsizer_0_0" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"AXIS_ARESETN": [ { "direction": "in" } ],
|
||||
"CLK": [ { "direction": "in" } ],
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_TUSER": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIS_TUSER": [ { "direction": "out" } ]
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
@@ -63,10 +55,10 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -80,7 +72,6 @@
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
@@ -90,10 +81,10 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -107,12 +98,11 @@
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ARESETN": {
|
||||
"RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
@@ -121,16 +111,16 @@
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXIS_ARESETN" } ]
|
||||
"RST": [ { "physical_name": "RESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -139,7 +129,7 @@
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
+198
@@ -0,0 +1,198 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "test_1_axis_numeric_master_0_0",
|
||||
"cell_name": "axis_numeric_master_0",
|
||||
"component_reference": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_CLOCK_GENERATOR": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLOCK_PERIOD_NS": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_RESET_GENERATOR": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_ACTIVE_CYCLES": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MASTER1": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MASTER1_RANDOM_VALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_HAS_LAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_LAST_PERIOD": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MASTER1_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_USER_PERIOD": [ { "value": "1000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_MASTER2": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MASTER2_RANDOM_VALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_HAS_LAST": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_LAST_PERIOD": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MASTER2_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_USER_PERIOD": [ { "value": "1000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_SLAVE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SLAVE_RANDOM_READY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_HAS_LAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_WAIT_FOR_SOF": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"FILE_NAME_M1": [ { "value": "../../../../m1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FILE_NAME_M2": [ { "value": "../../../../m1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"FILE_NAME_S": [ { "value": "../../../../m1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "test_1_axis_numeric_master_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_RESETN_INPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_CLOCK_GENERATOR": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"CLOCK_PERIOD_NS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_RESET_GENERATOR": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"RESET_ACTIVE_CYCLES": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_MASTER1": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MASTER1_RANDOM_VALID": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_HAS_LAST": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_LAST_PERIOD": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MASTER1_HAS_USER": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER1_USER_PERIOD": [ { "value": "1000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_MASTER2": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MASTER2_RANDOM_VALID": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_LAST_PERIOD": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MASTER2_HAS_USER": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"MASTER2_USER_PERIOD": [ { "value": "1000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_SLAVE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SLAVE_RANDOM_READY": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_HAS_LAST": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_HAS_USER": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SLAVE_WAIT_FOR_SOF": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"FILE_NAME_M1": [ { "value": "../../../../m1.txt", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FILE_NAME_M2": [ { "value": "../../../../m1.txt", "resolve_type": "generated", "usage": "all" } ],
|
||||
"FILE_NAME_S": [ { "value": "../../../../m1.txt", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_RESETN_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"RESETN": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"M1_AXIS_TVALID": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"M1_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M1_AXIS_TREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"M1_AXIS_TLAST": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"M1_AXIS_TUSER": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TUSER": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M1_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M1_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M1_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M1_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M1_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M1_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "RESETN" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M2_AXIS:M1_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "test_1_xlconstant_0_0",
|
||||
"cell_name": "xlconstant_0",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "test_1_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "test_1_xlconstant_1_0",
|
||||
"cell_name": "xlconstant_1",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "test_1_xlconstant_1_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,300 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/test_1",
|
||||
"name": "test_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"xlconstant_0": "",
|
||||
"xlconstant_1": "",
|
||||
"axis_numeric_master_0": "",
|
||||
"axis_crc_0": ""
|
||||
},
|
||||
"components": {
|
||||
"xlconstant_0": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "test_1_xlconstant_0_0",
|
||||
"xci_path": "ip\\test_1_xlconstant_0_0\\test_1_xlconstant_0_0.xci",
|
||||
"inst_hier_path": "xlconstant_0",
|
||||
"parameters": {
|
||||
"CONST_VAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"CONST_WIDTH": {
|
||||
"value": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"xlconstant_1": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"xci_name": "test_1_xlconstant_1_0",
|
||||
"xci_path": "ip\\test_1_xlconstant_1_0\\test_1_xlconstant_1_0.xci",
|
||||
"inst_hier_path": "xlconstant_1",
|
||||
"parameters": {
|
||||
"CONST_VAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"CONST_WIDTH": {
|
||||
"value": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_numeric_master_0": {
|
||||
"vlnv": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
|
||||
"xci_name": "test_1_axis_numeric_master_0_0",
|
||||
"xci_path": "ip\\test_1_axis_numeric_master_0_0\\test_1_axis_numeric_master_0_0.xci",
|
||||
"inst_hier_path": "axis_numeric_master_0",
|
||||
"parameters": {
|
||||
"CLOCK_PERIOD_NS": {
|
||||
"value": "10"
|
||||
},
|
||||
"FILE_NAME_M1": {
|
||||
"value": "../../../../m1.txt"
|
||||
},
|
||||
"FILE_NAME_M2": {
|
||||
"value": "../../../../m1.txt"
|
||||
},
|
||||
"FILE_NAME_S": {
|
||||
"value": "../../../../m1.txt"
|
||||
},
|
||||
"HAS_MASTER2": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER1_HAS_LAST": {
|
||||
"value": "true"
|
||||
},
|
||||
"MASTER1_HAS_USER": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER2_HAS_LAST": {
|
||||
"value": "false"
|
||||
},
|
||||
"MASTER2_HAS_USER": {
|
||||
"value": "false"
|
||||
},
|
||||
"SLAVE_HAS_LAST": {
|
||||
"value": "true"
|
||||
},
|
||||
"SLAVE_HAS_USER": {
|
||||
"value": "false"
|
||||
},
|
||||
"SLAVE_WAIT_FOR_SOF": {
|
||||
"value": "false"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_crc_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"xci_name": "test_1_axis_crc_0_0",
|
||||
"xci_path": "ip\\test_1_axis_crc_0_0\\test_1_axis_crc_0_0.xci",
|
||||
"inst_hier_path": "axis_crc_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_crc",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "4",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"CLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"polynomial": {
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axis_crc_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_crc_0/M_AXIS",
|
||||
"axis_numeric_master_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_numeric_master_0_M1_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_numeric_master_0/M1_AXIS",
|
||||
"axis_crc_0/S_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"axis_numeric_master_0_CLK": {
|
||||
"ports": [
|
||||
"axis_numeric_master_0/CLK",
|
||||
"axis_crc_0/CLK"
|
||||
]
|
||||
},
|
||||
"axis_numeric_master_0_RESETN": {
|
||||
"ports": [
|
||||
"axis_numeric_master_0/RESETN",
|
||||
"axis_crc_0/RESETN"
|
||||
]
|
||||
},
|
||||
"xlconstant_0_dout": {
|
||||
"ports": [
|
||||
"xlconstant_0/dout",
|
||||
"axis_crc_0/initial_value"
|
||||
]
|
||||
},
|
||||
"xlconstant_1_dout": {
|
||||
"ports": [
|
||||
"xlconstant_1/dout",
|
||||
"axis_crc_0/polynomial"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"-85,-16",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst xlconstant_0 -pg 1 -lvl 1 -x 130 -y 260 -defaultsOSRD
|
||||
preplace inst xlconstant_1 -pg 1 -lvl 1 -x 130 -y 360 -defaultsOSRD
|
||||
preplace inst axis_numeric_master_0 -pg 1 -lvl 1 -x 130 -y 80 -defaultsOSRD
|
||||
preplace inst axis_crc_0 -pg 1 -lvl 2 -x 400 -y 100 -defaultsOSRD
|
||||
preplace netloc axis_numeric_master_0_CLK 1 1 1 N 80
|
||||
preplace netloc axis_numeric_master_0_RESETN 1 1 1 N 100
|
||||
preplace netloc xlconstant_0_dout 1 1 1 240J 120n
|
||||
preplace netloc xlconstant_1_dout 1 1 1 250J 140n
|
||||
preplace netloc axis_crc_0_M_AXIS 1 0 3 20 200 NJ 200 540
|
||||
preplace netloc axis_numeric_master_0_M1_AXIS 1 1 1 N 60
|
||||
levelinfo -pg 1 0 130 400 570
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 570 420
|
||||
"
|
||||
}
|
||||
0
|
||||
@@ -61,20 +61,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="8"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="61"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="5"/>
|
||||
<Option Name="WTModelSimExportSim" Val="5"/>
|
||||
<Option Name="WTQuestaExportSim" Val="5"/>
|
||||
<Option Name="WTXSimExportSim" Val="21"/>
|
||||
<Option Name="WTModelSimExportSim" Val="21"/>
|
||||
<Option Name="WTQuestaExportSim" Val="21"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="5"/>
|
||||
<Option Name="WTRivieraExportSim" Val="5"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="5"/>
|
||||
<Option Name="WTVcsExportSim" Val="21"/>
|
||||
<Option Name="WTRivieraExportSim" Val="21"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="21"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -92,27 +92,42 @@
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/bd/axis_master_test/axis_master_test.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/axis_master_test/hdl/axis_master_test_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../axis_crc.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../crc.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../axis_crc.vhd">
|
||||
<File Path="$PPRDIR/../crc.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -134,10 +149,24 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/test_1/test_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/test_1/hdl/test_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_crc_sim_1_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TopModule" Val="axis_master_test_wrapper"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
@@ -148,16 +177,31 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../axis_crc_tb.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axis_crc_sim_1_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/test_1_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axis_crc_tb_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_crc_sim_1_wrapper"/>
|
||||
<Option Name="TopModule" Val="axis_crc_tb"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
@@ -167,6 +211,8 @@
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/axis_crc_sim_1_wrapper_behav.wcfg"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/test_1_wrapper_behav.wcfg"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/axis_crc_tb_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
@@ -176,6 +222,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axis_crc" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/axis_crc" RelGenDir="$PGENDIR/axis_crc">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_crc_sim_1_wrapper"/>
|
||||
|
||||
@@ -12,15 +12,15 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="55,017.585 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="55,029.632 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="55,070.000 ns"></Cursor1Time>
|
||||
<ZoomStartTime time="52,128.529 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="52,179.910 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="52,304.413 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="337"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="639"></ValueColumnWidth>
|
||||
<NameColumnWidth column_width="396"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="200"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="11" />
|
||||
<WVObjectSize size="7" />
|
||||
<wvobject fp_name="/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/clk_rst_generator_0/clk" type="logic">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
@@ -54,35 +54,6 @@
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="divider" fp_name="divider109">
|
||||
<obj_property name="label">AXIS Slave crc</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/crc/axis_crc_0/S_AXIS" type="protoinst">
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00E600</obj_property>
|
||||
<obj_property name="Render_Data">/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/crc/axis_crc_0/S_AXIS.streamWaveData</obj_property>
|
||||
<obj_property name="Number_Overlay">2</obj_property>
|
||||
<obj_property name="Overlay_Object_0">/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/crc/axis_crc_0/S_AXIS.linkStarve</obj_property>
|
||||
<obj_property name="Overlay_Color_0">#99E600</obj_property>
|
||||
<obj_property name="Overlay_Object_1">/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/crc/axis_crc_0/S_AXIS.linkStall</obj_property>
|
||||
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
|
||||
<obj_property name="Detail_Data">/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/crc/axis_crc_0/S_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="ElementShortName">S_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="divider" fp_name="divider108">
|
||||
<obj_property name="label">AXIS Master crc</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/crc/axis_crc_0/M_AXIS" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="divider" fp_name="divider57">
|
||||
<obj_property name="label">ASIX Slave simmodel</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
@@ -102,5 +73,6 @@
|
||||
<obj_property name="Detail_Data">/axis_crc_sim_1_wrapper/axis_crc_sim_1_i/axis_slave_simmodel_0/S_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="ElementShortName">S_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="axis_crc_tb_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="axis_crc_tb" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="130.909 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="170.736 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="150.563 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="219"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="94"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="16" />
|
||||
<wave_markers>
|
||||
<marker time="115000" label="" />
|
||||
</wave_markers>
|
||||
<wvobject fp_name="/axis_crc_tb/CLK" type="logic">
|
||||
<obj_property name="ElementShortName">CLK</obj_property>
|
||||
<obj_property name="ObjectShortName">CLK</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/RESETN" type="logic">
|
||||
<obj_property name="ElementShortName">RESETN</obj_property>
|
||||
<obj_property name="ObjectShortName">RESETN</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/initial_value" type="array">
|
||||
<obj_property name="ElementShortName">initial_value[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">initial_value[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/polynomial" type="array">
|
||||
<obj_property name="ElementShortName">polynomial[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">polynomial[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/S_AXIS_TREADY" type="logic">
|
||||
<obj_property name="ElementShortName">S_AXIS_TREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS_TREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/S_AXIS_TVALID" type="logic">
|
||||
<obj_property name="ElementShortName">S_AXIS_TVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS_TVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/S_AXIS_TDATA" type="array">
|
||||
<obj_property name="ElementShortName">S_AXIS_TDATA[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS_TDATA[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/S_AXIS_TLAST" type="logic">
|
||||
<obj_property name="ElementShortName">S_AXIS_TLAST</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS_TLAST</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="divider" fp_name="divider354">
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/M_AXIS_TREADY" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXIS_TREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS_TREADY</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/M_AXIS_TVALID" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXIS_TVALID</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS_TVALID</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/M_AXIS_TDATA" type="array">
|
||||
<obj_property name="ElementShortName">M_AXIS_TDATA[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS_TDATA[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/M_AXIS_TLAST" type="logic">
|
||||
<obj_property name="ElementShortName">M_AXIS_TLAST</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS_TLAST</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/done" type="other">
|
||||
<obj_property name="ElementShortName">done</obj_property>
|
||||
<obj_property name="ObjectShortName">done</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/CLK_PERIOD" type="other">
|
||||
<obj_property name="ElementShortName">CLK_PERIOD</obj_property>
|
||||
<obj_property name="ObjectShortName">CLK_PERIOD</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axis_crc_tb/uut/state" type="other">
|
||||
<obj_property name="ElementShortName">state</obj_property>
|
||||
<obj_property name="ObjectShortName">state</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -0,0 +1,31 @@
|
||||
00000000
|
||||
00000001
|
||||
00000002
|
||||
00000003
|
||||
00000004
|
||||
00000005
|
||||
00000006
|
||||
00000007
|
||||
00000008
|
||||
00000009
|
||||
0000000A
|
||||
0000000B
|
||||
0000000C
|
||||
0000000D
|
||||
0000000E
|
||||
0000000F
|
||||
00000010
|
||||
00000011
|
||||
00000012
|
||||
00000013
|
||||
00000014
|
||||
00000015
|
||||
00000016
|
||||
00000017
|
||||
00000018
|
||||
00000019
|
||||
0000001A
|
||||
0000001B
|
||||
0000001C
|
||||
0000001D
|
||||
0000001E
|
||||
@@ -0,0 +1,31 @@
|
||||
00000000
|
||||
00000001
|
||||
00000002
|
||||
00000003
|
||||
00000004
|
||||
00000005
|
||||
00000006
|
||||
00000007
|
||||
00000008
|
||||
00000009
|
||||
0000000A
|
||||
0000000B
|
||||
0000000C
|
||||
0000000D
|
||||
0000000E
|
||||
0000000F
|
||||
00000010
|
||||
00000011
|
||||
00000012
|
||||
00000013
|
||||
00000014
|
||||
00000015
|
||||
00000016
|
||||
00000017
|
||||
00000018
|
||||
00000019
|
||||
0000001A
|
||||
0000001B
|
||||
0000001C
|
||||
0000001D
|
||||
0000001E
|
||||
@@ -0,0 +1,31 @@
|
||||
00000004
|
||||
00000005
|
||||
00000006
|
||||
00000007
|
||||
00000008
|
||||
00000009
|
||||
0000000A
|
||||
0000000B
|
||||
0000000C
|
||||
0000000D
|
||||
0000000E
|
||||
0000000F
|
||||
00000010
|
||||
00000011
|
||||
00000012
|
||||
00000013
|
||||
00000014
|
||||
00000015
|
||||
00000016
|
||||
00000017
|
||||
00000018
|
||||
00000019
|
||||
0000001A
|
||||
0000001B
|
||||
0000001C
|
||||
0000001D
|
||||
0000001E
|
||||
0000001F
|
||||
00000020
|
||||
00000021
|
||||
00000022
|
||||
@@ -0,0 +1,31 @@
|
||||
00000004
|
||||
00000006
|
||||
00000008
|
||||
0000000A
|
||||
0000000C
|
||||
0000000E
|
||||
00000010
|
||||
00000012
|
||||
00000014
|
||||
00000016
|
||||
00000018
|
||||
0000001A
|
||||
0000001C
|
||||
0000001E
|
||||
00000020
|
||||
00000022
|
||||
00000024
|
||||
00000026
|
||||
00000028
|
||||
0000002A
|
||||
0000002C
|
||||
0000002E
|
||||
00000030
|
||||
00000032
|
||||
00000034
|
||||
00000036
|
||||
00000038
|
||||
0000003A
|
||||
0000003C
|
||||
0000003E
|
||||
00000040
|
||||
@@ -0,0 +1,58 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="test_1_wrapper_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="test_1_wrapper" />
|
||||
<top_module name="vhdl_c_pkg_tb" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="1,377.088 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,506.583 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,484.642 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="219"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="104"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="2" />
|
||||
<wvobject fp_name="/test_1_wrapper/test_1_i/axis_numeric_master_0/M1_AXIS" type="protoinst">
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00E600</obj_property>
|
||||
<obj_property name="Render_Data">/test_1_wrapper/test_1_i/axis_numeric_master_0/M1_AXIS.streamWaveData</obj_property>
|
||||
<obj_property name="Number_Overlay">2</obj_property>
|
||||
<obj_property name="Overlay_Object_0">/test_1_wrapper/test_1_i/axis_numeric_master_0/M1_AXIS.linkStarve</obj_property>
|
||||
<obj_property name="Overlay_Color_0">#99E600</obj_property>
|
||||
<obj_property name="Overlay_Object_1">/test_1_wrapper/test_1_i/axis_numeric_master_0/M1_AXIS.linkStall</obj_property>
|
||||
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
|
||||
<obj_property name="Detail_Data">/test_1_wrapper/test_1_i/axis_numeric_master_0/M1_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="ElementShortName">M1_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M1_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/test_1_wrapper/test_1_i/axis_crc_0/M_AXIS" type="protoinst">
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00E600</obj_property>
|
||||
<obj_property name="Render_Data">/test_1_wrapper/test_1_i/axis_crc_0/M_AXIS.streamWaveData</obj_property>
|
||||
<obj_property name="Number_Overlay">2</obj_property>
|
||||
<obj_property name="Overlay_Object_0">/test_1_wrapper/test_1_i/axis_crc_0/M_AXIS.linkStarve</obj_property>
|
||||
<obj_property name="Overlay_Color_0">#99E600</obj_property>
|
||||
<obj_property name="Overlay_Object_1">/test_1_wrapper/test_1_i/axis_crc_0/M_AXIS.linkStall</obj_property>
|
||||
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
|
||||
<obj_property name="Detail_Data">/test_1_wrapper/test_1_i/axis_crc_0/M_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="ElementShortName">M_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
+80
-41
@@ -3,27 +3,23 @@ use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_crc is
|
||||
generic (
|
||||
CRC_WIDTH : positive := 32;
|
||||
DWIDTH : positive := 16
|
||||
);
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic;
|
||||
|
||||
-- for crc calculation
|
||||
initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0);
|
||||
polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0);
|
||||
initial_value : in std_logic_vector(31 downto 0);
|
||||
polynomial : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
@@ -31,48 +27,91 @@ end entity;
|
||||
|
||||
architecture rtl of axis_crc is
|
||||
|
||||
type state_t is (DATA, CHECKSUM);
|
||||
type state_t is (IDLE, SECOND_HALF, CHECKSUM);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
signal M_AXIS_TVALID_sig : std_logic;
|
||||
signal crc_reset : std_logic;
|
||||
signal crc_enable : std_logic;
|
||||
signal crc_sum : std_logic_vector(CRC_WIDTH-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY or (not M_AXIS_TVALID_sig);
|
||||
|
||||
process
|
||||
-- fuer CRC-Berechnung
|
||||
variable CRC : std_logic_vector(31 downto 0);
|
||||
variable MSB : std_logic;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
|
||||
variable last : std_logic;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if RESETN = '0' then
|
||||
state <= IDLE;
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TVALID <= '0';
|
||||
CRC := initial_value;
|
||||
|
||||
if M_AXIS_TREADY = '1' or M_AXIS_TVALID_sig = '0' then
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA;
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
M_AXIS_TVALID_sig <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
else
|
||||
if M_AXIS_TREADY = '1' then
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TLAST <= '0';
|
||||
end if;
|
||||
|
||||
case state is
|
||||
when IDLE =>
|
||||
if S_AXIS_TVALID = '1' then
|
||||
data := S_AXIS_TDATA;
|
||||
last := S_AXIS_TLAST;
|
||||
|
||||
-- obere 16 Bit in die CRC Summe reinrechnen
|
||||
for i in 31 downto 16 loop
|
||||
-- Pruefen ob MSB gesetzt ist
|
||||
MSB := CRC(CRC'length-1);
|
||||
-- neues Bit reinschieben
|
||||
CRC := CRC(CRC'length-2 downto 0) & data(i);
|
||||
-- XOR Verknuepfung
|
||||
if MSB = '1' then
|
||||
CRC := CRC XOR polynomial;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
S_AXIS_TREADY <= '0';
|
||||
state <= SECOND_HALF;
|
||||
end if;
|
||||
|
||||
when SECOND_HALF =>
|
||||
-- untere 16 Bit in die CRC Summe reinrechnen
|
||||
for i in 15 downto 0 loop
|
||||
-- Pruefen ob MSB gesetzt ist
|
||||
MSB := CRC(CRC'length-1);
|
||||
-- neues Bit reinschieben
|
||||
CRC := CRC(CRC'length-2 downto 0) & data(i);
|
||||
-- XOR Verknuepfung
|
||||
if MSB = '1' then
|
||||
CRC := CRC XOR polynomial;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
-- Daten an M_AXIS ausgeben
|
||||
M_AXIS_TVALID <= '1';
|
||||
M_AXIS_TDATA <= data;
|
||||
|
||||
if last = '1' then
|
||||
state <= CHECKSUM;
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
state <= IDLE;
|
||||
end if;
|
||||
|
||||
when CHECKSUM =>
|
||||
-- CRC Pruefsumme ausgeben
|
||||
M_AXIS_TVALID <= '1';
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TLAST <= '1';
|
||||
M_AXIS_TDATA <= CRC;
|
||||
|
||||
state <= IDLE;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- CRC Berechnung
|
||||
------------------------------------------------------------
|
||||
CRC_Inst: entity work.CRC
|
||||
generic (
|
||||
CRC_WIDTH <= CRC_WIDTH;
|
||||
DWIDTH <= DWIDTH
|
||||
);
|
||||
port (
|
||||
clk <= CLK;
|
||||
-- Kontrollsignale
|
||||
reset <= (not RESETN) or crc_reset;
|
||||
enable <= crc_enable;
|
||||
initial_value <= initial_value;
|
||||
polynomial <= polynomial;
|
||||
-- Datensignale
|
||||
data <= S_AXIS_TDATA;
|
||||
checksum <= crc_sum
|
||||
);
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,70 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_crc is
|
||||
generic (
|
||||
CRC_WIDTH : positive := 32;
|
||||
DWIDTH : positive := 16
|
||||
);
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic;
|
||||
|
||||
-- for crc calculation
|
||||
initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0);
|
||||
polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0);
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture rtl of axis_crc is
|
||||
|
||||
type state_t is (DATA, CHECKSUM);
|
||||
signal state : state_t := DATA;
|
||||
|
||||
signal M_AXIS_TVALID_sig : std_logic;
|
||||
|
||||
-- CRC-Pruefsumme
|
||||
signal checksum : std_logic_vector(CRC_WIDTH-1);
|
||||
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY or (not M_AXIS_TVALID_sig) and (state=DATA);
|
||||
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if RESETN = '0' then
|
||||
state <= DATA;
|
||||
checksum <= initial_value;
|
||||
else
|
||||
case state is
|
||||
when DATA =>
|
||||
if M_AXIS_TREADY = '1' or M_AXIS_TVALID_sig = '0' then
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA;
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
M_AXIS_TVALID_sig <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
end if;
|
||||
|
||||
when CHECKSUM =>
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,128 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_crc_tb is
|
||||
end entity;
|
||||
|
||||
architecture testbench of axis_crc_tb is
|
||||
|
||||
-- Signal Definitions
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESETN : std_logic := '0';
|
||||
|
||||
signal initial_value : std_logic_vector(31 downto 0) := x"00000000";
|
||||
signal polynomial : std_logic_vector(31 downto 0) := x"04C11DB7"; -- Standard CRC-32 Poly
|
||||
|
||||
-- AXIS Input Signals (Stimulus)
|
||||
signal S_AXIS_TVALID : std_logic := '0';
|
||||
signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal S_AXIS_TLAST : std_logic := '0';
|
||||
signal S_AXIS_TREADY : std_logic;
|
||||
|
||||
-- AXIS Output Signals (DUT Response)
|
||||
signal M_AXIS_TVALID : std_logic;
|
||||
signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
|
||||
signal M_AXIS_TLAST : std_logic;
|
||||
signal M_AXIS_TREADY : std_logic := '1';
|
||||
|
||||
-- Clock Process (100 MHz)
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal done : boolean := false;
|
||||
|
||||
type data_array is array (0 to 1) of std_logic_vector(31 downto 0);
|
||||
constant test_data : data_array := (
|
||||
x"11223344", -- Test Value 1
|
||||
x"55667788" -- Test Value 2
|
||||
-- x"AABBCCDD", -- Test Value 3
|
||||
-- x"11223344" -- Test Value 4
|
||||
);
|
||||
|
||||
signal received_crc : std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- DUT Instantiation
|
||||
uut: entity work.axis_crc
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
|
||||
-- AXI Streaming Target (Input)
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
|
||||
-- AXI Streaming Initiator (Output)
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
|
||||
-- Clock Process
|
||||
clk_process : process
|
||||
begin
|
||||
while not done loop
|
||||
CLK <= '0';
|
||||
wait for CLK_PERIOD / 2;
|
||||
CLK <= '1';
|
||||
wait for CLK_PERIOD / 2;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
-- Test Process
|
||||
stim : process
|
||||
begin
|
||||
-- Reset Sequence
|
||||
RESETN <= '0';
|
||||
wait for 50 ns;
|
||||
RESETN <= '1';
|
||||
wait for 50 ns;
|
||||
|
||||
-- Send Data over S_AXIS
|
||||
for i in test_data'range loop
|
||||
S_AXIS_TDATA <= test_data(i);
|
||||
S_AXIS_TVALID <= '1';
|
||||
|
||||
if i = test_data'length-1 then
|
||||
S_AXIS_TLAST <= '1';
|
||||
else
|
||||
S_AXIS_TLAST <= '0';
|
||||
end if;
|
||||
|
||||
wait until rising_edge(CLK) and S_AXIS_TREADY = '1';
|
||||
S_AXIS_TVALID <= '0';
|
||||
end loop;
|
||||
|
||||
S_AXIS_TLAST <= '0';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
-- Wait for M_AXIS Data
|
||||
for i in test_data'range loop
|
||||
wait until rising_edge(CLK) and M_AXIS_TVALID = '1';
|
||||
assert M_AXIS_TDATA = test_data(i) report "ERROR: Mismatched Data at index " & integer'image(i) severity warning;
|
||||
end loop;
|
||||
|
||||
-- Wait for CRC
|
||||
wait until rising_edge(CLK) and M_AXIS_TVALID = '1' and M_AXIS_TLAST = '1';
|
||||
received_crc <= M_AXIS_TDATA;
|
||||
|
||||
-- Print Results
|
||||
report "All data matches expected values!";
|
||||
report "Received CRC: " & integer'image(to_integer(unsigned(received_crc)));
|
||||
|
||||
done <= true;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@@ -0,0 +1,132 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_crc_tb is
|
||||
end entity;
|
||||
|
||||
architecture testbench of axis_crc_tb is
|
||||
|
||||
-- Signal Definitions
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESETN : std_logic := '0';
|
||||
|
||||
signal initial_value : std_logic_vector(31 downto 0) := x"00000000";
|
||||
signal polynomial : std_logic_vector(31 downto 0) := x"04C11DB7"; -- Standard CRC-32 Poly
|
||||
|
||||
-- AXIS Input Signals (Stimulus)
|
||||
signal S_AXIS_TVALID : std_logic := '0';
|
||||
signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal S_AXIS_TLAST : std_logic := '0';
|
||||
signal S_AXIS_TREADY : std_logic;
|
||||
|
||||
-- AXIS Output Signals (DUT Response)
|
||||
signal M_AXIS_TVALID : std_logic;
|
||||
signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
|
||||
signal M_AXIS_TLAST : std_logic;
|
||||
signal M_AXIS_TREADY : std_logic := '1';
|
||||
|
||||
-- Clock Process (100 MHz)
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal done : boolean := false;
|
||||
|
||||
type data_array is array (natural range <>) of std_logic_vector(31 downto 0);
|
||||
constant test_data : data_array := (
|
||||
x"11223344", -- Test Value 1
|
||||
x"55667788" -- Test Value 2
|
||||
-- x"AABBCCDD", -- Test Value 3
|
||||
-- x"11223344" -- Test Value 4
|
||||
);
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- DUT Instantiation
|
||||
uut: entity work.axis_crc
|
||||
port map (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
|
||||
-- AXI Streaming Target (Input)
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
|
||||
-- AXI Streaming Initiator (Output)
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
|
||||
-- Clock Process
|
||||
clk_process : process
|
||||
begin
|
||||
while not done loop
|
||||
CLK <= '0';
|
||||
wait for CLK_PERIOD / 2;
|
||||
CLK <= '1';
|
||||
wait for CLK_PERIOD / 2;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
-- Test Process
|
||||
test_process : process
|
||||
|
||||
variable received_crc : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
-- Reset Sequence
|
||||
RESETN <= '0';
|
||||
wait for 50 ns;
|
||||
RESETN <= '1';
|
||||
wait for 50 ns;
|
||||
|
||||
-- Send Data over S_AXIS
|
||||
for i in test_data'range loop
|
||||
S_AXIS_TDATA <= test_data(i);
|
||||
S_AXIS_TVALID <= '1';
|
||||
S_AXIS_TLAST <= '0';
|
||||
wait until rising_edge(CLK) and S_AXIS_TREADY = '1';
|
||||
S_AXIS_TVALID <= '0';
|
||||
end loop;
|
||||
|
||||
-- Send TLAST with Last Data
|
||||
S_AXIS_TDATA <= test_data(3);
|
||||
S_AXIS_TVALID <= '1';
|
||||
S_AXIS_TLAST <= '1';
|
||||
wait until rising_edge(CLK) and S_AXIS_TREADY = '1';
|
||||
S_AXIS_TVALID <= '0';
|
||||
S_AXIS_TLAST <= '0';
|
||||
|
||||
-- Wait for M_AXIS Data
|
||||
for i in test_data'range loop
|
||||
wait until rising_edge(CLK) and M_AXIS_TVALID = '1';
|
||||
assert M_AXIS_DATA = test_data(i) report "ERROR: Mismatched Data at index " & integer'image(i) severity failure;
|
||||
end loop;
|
||||
|
||||
-- Wait for CRC
|
||||
wait until rising_edge(CLK) and M_AXIS_TVALID = '1' and M_AXIS_TLAST = '1';
|
||||
received_crc := M_AXIS_TDATA;
|
||||
|
||||
-- Check Data
|
||||
for i in 0 to 3 loop
|
||||
assert received_data(i) = test_data(i)
|
||||
report "ERROR: Mismatched Data at index " & integer'image(i)
|
||||
severity failure;
|
||||
end loop;
|
||||
|
||||
-- Print Results
|
||||
report "All data matches expected values!";
|
||||
report "Received CRC: " & integer'image(to_integer(unsigned(received_crc)));
|
||||
|
||||
done <= true;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
+247
-247
@@ -1,247 +1,247 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: design_1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.2
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source design_1_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7vx485tffg1157-1
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name design_1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:user:axis_mixer:1.0\
|
||||
xilinx.com:user:axis_numeric_master_slave_simmodel:1.0\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
|
||||
# Create ports
|
||||
|
||||
# Create instance: axis_mixer_0, and set properties
|
||||
set axis_mixer_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_mixer:1.0 axis_mixer_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.WEIGHT_1 {1} \
|
||||
CONFIG.WEIGHT_2 {1} \
|
||||
] $axis_mixer_0
|
||||
|
||||
# Create instance: axis_numeric_master_0, and set properties
|
||||
set axis_numeric_master_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_numeric_master_slave_simmodel:1.0 axis_numeric_master_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FILE_NAME_M1 {../../../../mstr1.txt} \
|
||||
CONFIG.FILE_NAME_M2 {../../../../mstr2.txt} \
|
||||
CONFIG.FILE_NAME_S {../../../../slv.txt} \
|
||||
CONFIG.MASTER1_HAS_LAST {false} \
|
||||
CONFIG.MASTER1_HAS_USER {false} \
|
||||
CONFIG.MASTER1_RANDOM_VALID {true} \
|
||||
CONFIG.MASTER2_HAS_LAST {false} \
|
||||
CONFIG.MASTER2_HAS_USER {false} \
|
||||
CONFIG.MASTER2_RANDOM_VALID {true} \
|
||||
CONFIG.SLAVE_HAS_LAST {false} \
|
||||
CONFIG.SLAVE_HAS_USER {false} \
|
||||
CONFIG.SLAVE_RANDOM_READY {true} \
|
||||
CONFIG.SLAVE_WAIT_FOR_SOF {false} \
|
||||
] $axis_numeric_master_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axis_mixer_0_M_AXIS [get_bd_intf_pins axis_mixer_0/M_AXIS] [get_bd_intf_pins axis_numeric_master_0/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_numeric_master_0_M1_AXIS [get_bd_intf_pins axis_mixer_0/S_AXIS_1] [get_bd_intf_pins axis_numeric_master_0/M1_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_numeric_master_0_M2_AXIS [get_bd_intf_pins axis_mixer_0/S_AXIS_2] [get_bd_intf_pins axis_numeric_master_0/M2_AXIS]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axis_numeric_master_0_CLK [get_bd_pins axis_mixer_0/ACLK] [get_bd_pins axis_numeric_master_0/CLK]
|
||||
connect_bd_net -net axis_numeric_master_0_RESETN [get_bd_pins axis_mixer_0/ARESETN] [get_bd_pins axis_numeric_master_0/RESETN]
|
||||
|
||||
# Create address segments
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: design_1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2023.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source design_1_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7vx485tffg1157-1
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name design_1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:user:axis_mixer:1.0\
|
||||
xilinx.com:user:axis_numeric_master_slave_simmodel:1.0\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
|
||||
# Create ports
|
||||
|
||||
# Create instance: axis_mixer_0, and set properties
|
||||
set axis_mixer_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_mixer:1.0 axis_mixer_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.WEIGHT_1 {1} \
|
||||
CONFIG.WEIGHT_2 {1} \
|
||||
] $axis_mixer_0
|
||||
|
||||
# Create instance: axis_numeric_master_0, and set properties
|
||||
set axis_numeric_master_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axis_numeric_master_slave_simmodel:1.0 axis_numeric_master_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FILE_NAME_M1 {../../../../mstr1.txt} \
|
||||
CONFIG.FILE_NAME_M2 {../../../../mstr2.txt} \
|
||||
CONFIG.FILE_NAME_S {../../../../slv.txt} \
|
||||
CONFIG.MASTER1_HAS_LAST {false} \
|
||||
CONFIG.MASTER1_HAS_USER {false} \
|
||||
CONFIG.MASTER1_RANDOM_VALID {true} \
|
||||
CONFIG.MASTER2_HAS_LAST {false} \
|
||||
CONFIG.MASTER2_HAS_USER {false} \
|
||||
CONFIG.MASTER2_RANDOM_VALID {true} \
|
||||
CONFIG.SLAVE_HAS_LAST {false} \
|
||||
CONFIG.SLAVE_HAS_USER {false} \
|
||||
CONFIG.SLAVE_RANDOM_READY {true} \
|
||||
CONFIG.SLAVE_WAIT_FOR_SOF {false} \
|
||||
] $axis_numeric_master_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axis_mixer_0_M_AXIS [get_bd_intf_pins axis_mixer_0/M_AXIS] [get_bd_intf_pins axis_numeric_master_0/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_numeric_master_0_M1_AXIS [get_bd_intf_pins axis_mixer_0/S_AXIS_1] [get_bd_intf_pins axis_numeric_master_0/M1_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_numeric_master_0_M2_AXIS [get_bd_intf_pins axis_mixer_0/S_AXIS_2] [get_bd_intf_pins axis_numeric_master_0/M2_AXIS]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axis_numeric_master_0_CLK [get_bd_pins axis_mixer_0/ACLK] [get_bd_pins axis_numeric_master_0/CLK]
|
||||
connect_bd_net -net axis_numeric_master_0_RESETN [get_bd_pins axis_mixer_0/ARESETN] [get_bd_pins axis_numeric_master_0/RESETN]
|
||||
|
||||
# Create address segments
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
|
||||
+364
-362
@@ -1,362 +1,364 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.vhdl_c_pkg_tb.all;
|
||||
|
||||
entity axis_numeric_master_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
HAS_CLOCK_GENERATOR : boolean := true;
|
||||
CLOCK_PERIOD_NS : integer := 10;
|
||||
|
||||
HAS_RESET_GENERATOR : boolean := true;
|
||||
HAS_RESETN_INPUT : boolean := false;
|
||||
RESET_ACTIVE_CYCLES : integer := 100;
|
||||
|
||||
HAS_MASTER1 : boolean := true;
|
||||
FILE_NAME_M1 : string := string'("../../../../m1.txt");
|
||||
MASTER1_DATA_WIDTH : integer := 32;
|
||||
MASTER1_RANDOM_VALID : boolean := true;
|
||||
MASTER1_HAS_LAST : boolean := true;
|
||||
MASTER1_LAST_PERIOD : integer := 100;
|
||||
MASTER1_HAS_USER : boolean := true;
|
||||
MASTER1_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_MASTER2 : boolean := true;
|
||||
FILE_NAME_M2 : string := string'("../../../../m1.txt");
|
||||
MASTER2_DATA_WIDTH : integer := 32;
|
||||
MASTER2_RANDOM_VALID : boolean := true;
|
||||
MASTER2_HAS_LAST : boolean := true;
|
||||
MASTER2_LAST_PERIOD : integer := 100;
|
||||
MASTER2_HAS_USER : boolean := true;
|
||||
MASTER2_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_SLAVE : boolean := true;
|
||||
FILE_NAME_S : string := string'("../../../../m1.txt");
|
||||
SLAVE_DATA_WIDTH : integer := 32;
|
||||
SLAVE_RANDOM_READY : boolean := true;
|
||||
SLAVE_HAS_LAST : boolean := true;
|
||||
SLAVE_HAS_USER : boolean := true;
|
||||
SLAVE_WAIT_FOR_SOF : boolean := true
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : out std_logic := '0';
|
||||
RESETN : out std_logic := '1';
|
||||
|
||||
ACLK : in std_logic := '0';
|
||||
ARESETN : in std_logic := '1';
|
||||
|
||||
M1_AXIS_TVALID : out std_logic := '0';
|
||||
M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0');
|
||||
M1_AXIS_TREADY : in std_logic := '1';
|
||||
M1_AXIS_TLAST : out std_logic := '0';
|
||||
M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
M2_AXIS_TVALID : out std_logic := '0';
|
||||
M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0');
|
||||
M2_AXIS_TREADY : in std_logic := '1';
|
||||
M2_AXIS_TLAST : out std_logic := '0';
|
||||
M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
S_AXIS_TVALID : in std_logic := '0';
|
||||
S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0);
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0')
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
architecture sim of axis_numeric_master_slave_simmodel is
|
||||
|
||||
signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF";
|
||||
signal rnd_s : unsigned (31 downto 0) := x"12345678";
|
||||
signal lclk : std_logic := '0';
|
||||
signal local_clk : std_logic := ACLK;
|
||||
signal local_resetn : std_logic := '1';
|
||||
|
||||
signal DBG_M1_FILERELOAD : std_logic := '0';
|
||||
signal DBG_M2_FILERELOAD : std_logic := '0';
|
||||
signal DBG_S_FILERELOAD : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
----------------------------------------
|
||||
-- Clock Generator
|
||||
----------------------------------------
|
||||
genclk: if HAS_CLOCK_GENERATOR generate
|
||||
lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns;
|
||||
CLK <= lclk;
|
||||
local_clk <= lclk;
|
||||
end generate;
|
||||
|
||||
no_genclk: if not HAS_CLOCK_GENERATOR generate
|
||||
local_clk <= ACLK;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Reset Generator
|
||||
----------------------------------------
|
||||
genreset: if HAS_RESET_GENERATOR generate
|
||||
process begin
|
||||
RESETN <= '0';
|
||||
local_resetn <= '0';
|
||||
for i in 1 to RESET_ACTIVE_CYCLES loop
|
||||
wait until rising_edge(local_clk);
|
||||
end loop;
|
||||
RESETN <= '1';
|
||||
local_resetn <= '1';
|
||||
wait;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate
|
||||
local_resetn <= ARESETN;
|
||||
end generate;
|
||||
|
||||
|
||||
----------------------------------------
|
||||
-- Random Number Generator
|
||||
----------------------------------------
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
rnd: process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd_m1;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m1 <= r;
|
||||
r := rnd_m2;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m2 <= r;
|
||||
r := rnd_s;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_s <= r;
|
||||
end process;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 1
|
||||
----------------------------------------
|
||||
genmaster1: if HAS_MASTER1 generate
|
||||
m1: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M1_AXIS_TVALID <= '0';
|
||||
M1_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M1, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M1_AXIS_TVALID <= '1';
|
||||
M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0);
|
||||
M1_AXIS_TLAST <= '0';
|
||||
M1_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER1_LAST_PERIOD then
|
||||
M1_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M1_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M1_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER1_RANDOM_VALID) then
|
||||
M1_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M1_AXIS_TVALID <= '0';
|
||||
DBG_M1_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 2
|
||||
----------------------------------------
|
||||
genmaster2: if HAS_MASTER2 generate
|
||||
m2: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M2_AXIS_TVALID <= '0';
|
||||
M2_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M2, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M2_AXIS_TVALID <= '1';
|
||||
M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0);
|
||||
M2_AXIS_TLAST <= '0';
|
||||
M2_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER2_LAST_PERIOD then
|
||||
M2_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M2_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M2_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER2_RANDOM_VALID) then
|
||||
M2_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M2_AXIS_TVALID <= '0';
|
||||
DBG_M2_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- SLAVE
|
||||
----------------------------------------
|
||||
genslave: if HAS_SLAVE generate
|
||||
s: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable rnd : integer;
|
||||
variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_S_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
S_AXIS_TREADY <= '0';
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
elsif wait_sof then
|
||||
if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then
|
||||
wait_sof := false;
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_S, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S);
|
||||
end if;
|
||||
|
||||
while not feof(fp) and fp /= 0 loop
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge (local_clk);
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
if fp > 0 then
|
||||
fscanf(fp, string'("%x"), data);
|
||||
if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then
|
||||
printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length));
|
||||
if (rnd>0 and SLAVE_RANDOM_READY) then
|
||||
S_AXIS_TREADY <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
S_AXIS_TREADY <= '0';
|
||||
DBG_S_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
end;
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.vhdl_c_pkg_tb.all;
|
||||
|
||||
entity axis_numeric_master_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
HAS_CLOCK_GENERATOR : boolean := true;
|
||||
CLOCK_PERIOD_NS : integer := 10;
|
||||
|
||||
HAS_RESET_GENERATOR : boolean := true;
|
||||
HAS_RESETN_INPUT : boolean := false;
|
||||
RESET_ACTIVE_CYCLES : integer := 100;
|
||||
|
||||
HAS_MASTER1 : boolean := true;
|
||||
FILE_NAME_M1 : string := string'("../../../../m1.txt");
|
||||
MASTER1_DATA_WIDTH : integer := 32;
|
||||
MASTER1_RANDOM_VALID : boolean := true;
|
||||
MASTER1_HAS_LAST : boolean := true;
|
||||
MASTER1_LAST_PERIOD : integer := 100;
|
||||
MASTER1_HAS_USER : boolean := true;
|
||||
MASTER1_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_MASTER2 : boolean := true;
|
||||
FILE_NAME_M2 : string := string'("../../../../m1.txt");
|
||||
MASTER2_DATA_WIDTH : integer := 32;
|
||||
MASTER2_RANDOM_VALID : boolean := true;
|
||||
MASTER2_HAS_LAST : boolean := true;
|
||||
MASTER2_LAST_PERIOD : integer := 100;
|
||||
MASTER2_HAS_USER : boolean := true;
|
||||
MASTER2_USER_PERIOD : integer := 1000;
|
||||
|
||||
HAS_SLAVE : boolean := true;
|
||||
FILE_NAME_S : string := string'("../../../../m1.txt");
|
||||
SLAVE_DATA_WIDTH : integer := 32;
|
||||
SLAVE_RANDOM_READY : boolean := true;
|
||||
SLAVE_HAS_LAST : boolean := true;
|
||||
SLAVE_HAS_USER : boolean := true;
|
||||
SLAVE_WAIT_FOR_SOF : boolean := true
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : out std_logic := '0';
|
||||
RESETN : out std_logic := '1';
|
||||
|
||||
ACLK : in std_logic := '0';
|
||||
ARESETN : in std_logic := '1';
|
||||
|
||||
M1_AXIS_TVALID : out std_logic := '0';
|
||||
M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0');
|
||||
M1_AXIS_TREADY : in std_logic := '1';
|
||||
M1_AXIS_TLAST : out std_logic := '0';
|
||||
M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
M2_AXIS_TVALID : out std_logic := '0';
|
||||
M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0');
|
||||
M2_AXIS_TREADY : in std_logic := '1';
|
||||
M2_AXIS_TLAST : out std_logic := '0';
|
||||
M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
|
||||
|
||||
S_AXIS_TVALID : in std_logic := '0';
|
||||
S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0);
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0')
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
architecture sim of axis_numeric_master_slave_simmodel is
|
||||
|
||||
signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF";
|
||||
signal rnd_s : unsigned (31 downto 0) := x"12345678";
|
||||
signal lclk : std_logic := '0';
|
||||
signal local_clk : std_logic := ACLK;
|
||||
signal local_resetn : std_logic := '1';
|
||||
|
||||
signal DBG_M1_FILERELOAD : std_logic := '0';
|
||||
signal DBG_M2_FILERELOAD : std_logic := '0';
|
||||
signal DBG_S_FILERELOAD : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
----------------------------------------
|
||||
-- Clock Generator
|
||||
----------------------------------------
|
||||
genclk: if HAS_CLOCK_GENERATOR generate
|
||||
lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns;
|
||||
CLK <= lclk;
|
||||
local_clk <= lclk;
|
||||
end generate;
|
||||
|
||||
no_genclk: if not HAS_CLOCK_GENERATOR generate
|
||||
local_clk <= ACLK;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Reset Generator
|
||||
----------------------------------------
|
||||
genreset: if HAS_RESET_GENERATOR generate
|
||||
process begin
|
||||
RESETN <= '0';
|
||||
local_resetn <= '0';
|
||||
for i in 1 to RESET_ACTIVE_CYCLES loop
|
||||
wait until rising_edge(local_clk);
|
||||
end loop;
|
||||
RESETN <= '1';
|
||||
local_resetn <= '1';
|
||||
wait;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate
|
||||
local_resetn <= ARESETN;
|
||||
end generate;
|
||||
|
||||
|
||||
----------------------------------------
|
||||
-- Random Number Generator
|
||||
----------------------------------------
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
rnd: process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd_m1;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m1 <= r;
|
||||
r := rnd_m2;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_m2 <= r;
|
||||
r := rnd_s;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd_s <= r;
|
||||
end process;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 1
|
||||
----------------------------------------
|
||||
genmaster1: if HAS_MASTER1 generate
|
||||
m1: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M1_AXIS_TVALID <= '0';
|
||||
M1_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M1, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M1_AXIS_TVALID <= '1';
|
||||
M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0);
|
||||
M1_AXIS_TLAST <= '0';
|
||||
M1_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER1_LAST_PERIOD then
|
||||
M1_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M1_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M1_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER1_RANDOM_VALID) then
|
||||
M1_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M1_AXIS_TVALID <= '0';
|
||||
DBG_M1_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- Master 2
|
||||
----------------------------------------
|
||||
genmaster2: if HAS_MASTER2 generate
|
||||
m2: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable rnd : integer;
|
||||
variable data_cnt_last : integer := 1;
|
||||
variable data_cnt_user : integer := 1;
|
||||
variable valid_out : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_M1_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
valid_out := '0';
|
||||
M2_AXIS_TVALID <= '0';
|
||||
M2_AXIS_TDATA <= (others=>'0');
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_M2, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2);
|
||||
wait;
|
||||
end if;
|
||||
|
||||
while not feof(fp) loop
|
||||
valid_out := '1';
|
||||
fscanf(fp, string'("%x"), data);
|
||||
M2_AXIS_TVALID <= '1';
|
||||
M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0);
|
||||
M2_AXIS_TLAST <= '0';
|
||||
M2_AXIS_TUSER(0) <= '0';
|
||||
if data_cnt_last >= MASTER2_LAST_PERIOD then
|
||||
M2_AXIS_TLAST <= '1';
|
||||
data_cnt_last := 0;
|
||||
end if;
|
||||
if data_cnt_user >= MASTER1_USER_PERIOD then
|
||||
M2_AXIS_TUSER(0) <= '1';
|
||||
data_cnt_user := 0;
|
||||
end if;
|
||||
data_cnt_last := data_cnt_last + 1;
|
||||
data_cnt_user := data_cnt_user + 1;
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
while M2_AXIS_TREADY /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
|
||||
if (rnd>0 and MASTER2_RANDOM_VALID) then
|
||||
M2_AXIS_TVALID <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
M2_AXIS_TVALID <= '0';
|
||||
DBG_M2_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
----------------------------------------
|
||||
-- SLAVE
|
||||
----------------------------------------
|
||||
genslave: if HAS_SLAVE generate
|
||||
s: process
|
||||
variable fp : CFILE := 0;
|
||||
variable data : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable rnd : integer;
|
||||
variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
DBG_S_FILERELOAD <= '0';
|
||||
if (local_resetn = '0') then
|
||||
S_AXIS_TREADY <= '0';
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
end if;
|
||||
wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
|
||||
elsif wait_sof then
|
||||
if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then
|
||||
wait_sof := false;
|
||||
end if;
|
||||
else
|
||||
if fp > 0 then
|
||||
fclose(fp);
|
||||
fp := 0;
|
||||
end if;
|
||||
fp := fopen(FILE_NAME_S, "r");
|
||||
if fp = 0 then
|
||||
printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S);
|
||||
end if;
|
||||
|
||||
while not feof(fp) and fp /= 0 loop
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge (local_clk);
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
if fp > 0 then
|
||||
fscanf(fp, string'("%x"), data);
|
||||
if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then
|
||||
printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA);
|
||||
printf("hallo");
|
||||
report "verification error";
|
||||
end if;
|
||||
end if;
|
||||
|
||||
rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length));
|
||||
if (rnd>0 and SLAVE_RANDOM_READY) then
|
||||
S_AXIS_TREADY <= '0';
|
||||
for i in 0 to rnd loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
end loop;
|
||||
S_AXIS_TREADY <= '0';
|
||||
DBG_S_FILERELOAD <= '1';
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
end;
|
||||
|
||||
Reference in New Issue
Block a user