Matthias Biermann
133 lines
4.0 KiB
VHDL
133 lines
4.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axis_crc_tb is
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end entity;
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architecture testbench of axis_crc_tb is
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-- Signal Definitions
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signal CLK : std_logic := '0';
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signal RESETN : std_logic := '0';
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signal initial_value : std_logic_vector(31 downto 0) := x"00000000";
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signal polynomial : std_logic_vector(31 downto 0) := x"04C11DB7"; -- Standard CRC-32 Poly
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-- AXIS Input Signals (Stimulus)
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signal S_AXIS_TVALID : std_logic := '0';
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signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
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signal S_AXIS_TLAST : std_logic := '0';
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signal S_AXIS_TREADY : std_logic;
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-- AXIS Output Signals (DUT Response)
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signal M_AXIS_TVALID : std_logic;
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signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
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signal M_AXIS_TLAST : std_logic;
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signal M_AXIS_TREADY : std_logic := '1';
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-- Clock Process (100 MHz)
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constant CLK_PERIOD : time := 10 ns;
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signal done : boolean := false;
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type data_array is array (natural range <>) of std_logic_vector(31 downto 0);
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constant test_data : data_array := (
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x"11223344", -- Test Value 1
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x"55667788" -- Test Value 2
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-- x"AABBCCDD", -- Test Value 3
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-- x"11223344" -- Test Value 4
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);
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begin
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-- DUT Instantiation
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uut: entity work.axis_crc
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port map (
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CLK => CLK,
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RESETN => RESETN,
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initial_value => initial_value,
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polynomial => polynomial,
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-- AXI Streaming Target (Input)
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S_AXIS_TVALID => S_AXIS_TVALID,
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S_AXIS_TDATA => S_AXIS_TDATA,
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S_AXIS_TLAST => S_AXIS_TLAST,
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S_AXIS_TREADY => S_AXIS_TREADY,
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-- AXI Streaming Initiator (Output)
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M_AXIS_TVALID => M_AXIS_TVALID,
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M_AXIS_TDATA => M_AXIS_TDATA,
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M_AXIS_TLAST => M_AXIS_TLAST,
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M_AXIS_TREADY => M_AXIS_TREADY
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);
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-- Clock Process
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clk_process : process
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begin
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while not done loop
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CLK <= '0';
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wait for CLK_PERIOD / 2;
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CLK <= '1';
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wait for CLK_PERIOD / 2;
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end loop;
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wait;
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end process;
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-- Test Process
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test_process : process
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variable received_crc : std_logic_vector(31 downto 0);
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begin
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-- Reset Sequence
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RESETN <= '0';
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wait for 50 ns;
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RESETN <= '1';
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wait for 50 ns;
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-- Send Data over S_AXIS
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for i in test_data'range loop
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S_AXIS_TDATA <= test_data(i);
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S_AXIS_TVALID <= '1';
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S_AXIS_TLAST <= '0';
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wait until rising_edge(CLK) and S_AXIS_TREADY = '1';
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S_AXIS_TVALID <= '0';
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end loop;
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-- Send TLAST with Last Data
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S_AXIS_TDATA <= test_data(3);
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S_AXIS_TVALID <= '1';
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S_AXIS_TLAST <= '1';
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wait until rising_edge(CLK) and S_AXIS_TREADY = '1';
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S_AXIS_TVALID <= '0';
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S_AXIS_TLAST <= '0';
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-- Wait for M_AXIS Data
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for i in test_data'range loop
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wait until rising_edge(CLK) and M_AXIS_TVALID = '1';
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assert M_AXIS_DATA = test_data(i) report "ERROR: Mismatched Data at index " & integer'image(i) severity failure;
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end loop;
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-- Wait for CRC
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wait until rising_edge(CLK) and M_AXIS_TVALID = '1' and M_AXIS_TLAST = '1';
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received_crc := M_AXIS_TDATA;
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-- Check Data
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for i in 0 to 3 loop
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assert received_data(i) = test_data(i)
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report "ERROR: Mismatched Data at index " & integer'image(i)
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severity failure;
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end loop;
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-- Print Results
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report "All data matches expected values!";
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report "Received CRC: " & integer'image(to_integer(unsigned(received_crc)));
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done <= true;
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wait;
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end process;
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end architecture;
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