Matthias Biermann
259 lines
7.6 KiB
VHDL
259 lines
7.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Mem_to_CRC is
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generic (
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logLength : integer
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);
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port (
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CLK : in std_logic;
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RST : in std_logic;
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-- Control IO
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ready : out std_logic := '0';
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start : in std_logic;
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startAddress : in std_logic_vector(31 downto 0);
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lengthM1 : in std_logic_vector(logLength-1 downto 0);
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-- Wishbone Master
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D_DAT_O : out std_logic_vector(31 downto 0) := (others => '0') ;
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D_DAT_I : in std_logic_vector(31 downto 0);
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D_STB_O : out std_logic := '0';
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D_ADR_O : out unsigned(31 downto 0) := (others => '0') ;
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D_SEL_O : out std_logic_vector( 3 downto 0);
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D_WE_O : out std_logic;
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D_ACK_I : in std_logic;
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-- CRC output
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checksum : out std_logic_vector(31 downto 0) := (others => '0')
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);
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end entity;
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architecture arch of Mem_to_CRC is
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--Signale zwischen Steuerwerk und Rechenwerk
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signal lengthEN : std_logic := '0';
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signal lengthLD : std_logic := '0';
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signal lengthTC : std_logic := '0';
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signal dataEN : std_logic := '0';
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signal CRCEN : std_logic := '0';
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signal CRCRST : std_logic := '0';
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signal startAddressEN : std_logic := '0';
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signal startAddressLD : std_logic := '0';
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signal startBytesEN : std_logic := '0';
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signal startBytesLD : std_logic := '0';
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signal startBytesTC : std_logic := '0';
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begin
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Rechenwerk: block
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-- Register
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signal dataByte3 : std_logic_vector(7 downto 0) := (others => '0');
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signal dataByte2 : std_logic_vector(7 downto 0) := (others => '0');
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signal dataByte1 : std_logic_vector(7 downto 0) := (others => '0');
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signal dataByte0 : std_logic_vector(7 downto 0) := (others => '0');
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signal toCRC : std_logic_vector(7 downto 0) := (others => '0');
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signal byteSelect : std_logic_vector(1 downto 0) := (others => '0');
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begin
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--Zaehler der Anzahl der Datenbytes
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CounterLength: process(CLK)
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variable counterValue: unsigned(logLength - 1 downto 0) := (others => '0');
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begin
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if rising_edge(CLK) then
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if lengthLD = '1' then --Laden
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counterValue := unsigned(lengthM1);
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elsif lengthEN = '1' then --runterzaehlen
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counterValue := counterValue - 1;
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end if;
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if counterValue = 0 then --TC setzen
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lengthTC <= '1';
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else
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lengthTC <= '0';
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end if;
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end if;
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end process;
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--Zaehler fuer Adressen
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CounterAddress: process(CLK)
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variable counterValue : unsigned(31 downto 2) := (others => '0');
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begin
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if rising_edge(CLK) then
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if startAddressLD = '1' then
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counterValue := unsigned(startAddress(31 downto 2)); --Speicher laden
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elsif startAddressEN = '1' then
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counterValue := counterValue + 1; --hochzaehlen
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end if;
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--Variabel ausgeben und auf 32 Bit erweitern
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D_ADR_O <= counterValue & "00";
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end if;
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end process;
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--Modulozaehler fuer die einzelnen Bytes
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CounterBytes: process(CLK)
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variable counterValue : unsigned(1 downto 0) := (others => '0');
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begin
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if rising_edge(CLK) then
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if startBytesLD = '1' then
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counterValue := unsigned(startAddress(1 downto 0)); --Speicher laden
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elsif startBytesEN = '1' and counterValue < 3 then --hochzaehlen
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counterValue := counterValue + 1;
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elsif startBytesEN = '1' and counterValue = 3 then
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counterValue := (others => '0'); --zuruecksetzen
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end if;
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if counterValue = 3 then --TC setzen
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startBytesTC <= '1';
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else
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startBytesTC <= '0';
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end if;
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--Variabel ausgeben und zum Multiplexer fuehren
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byteSelect <= std_logic_vector(counterValue);
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end if;
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end process;
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--vier Pufferregister fuer das Datenwort -> vier Datenbytes
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SeparateDataWords: process(CLK)
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begin
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if rising_edge(CLK) then
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if DataEN = '1' then
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dataByte3 <= D_DAT_I(31 downto 24);
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dataByte2 <= D_DAT_I(23 downto 16);
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dataByte1 <= D_DAT_I(15 downto 8);
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dataByte0 <= D_DAT_I(7 downto 0);
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end if;
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end if;
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end process;
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--Multiplexer für das Ansteuern des ersten Datenbytes
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ByteSelectMUX: process(byteSelect, dataByte0, dataByte1, dataByte2, dataByte3)
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begin
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toCRC <= (others => '0');
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case byteSelect is
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when "11" => toCRC <= dataByte3;
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when "10" => toCRC <= dataByte2;
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when "01" => toCRC <= dataByte1;
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when "00" => toCRC <= dataByte0;
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when others => toCRC <= (others => '-');
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end case;
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end process;
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--Feste Ausgaenge
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D_SEL_O <= "1111";
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D_WE_O <= '0';
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------------------------------------------------------------
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-- CRC Berechnung
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------------------------------------------------------------
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CRC_Inst: entity work.CRC
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generic map (
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crcLength => 32,
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inDataLength => 8,
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polynomial => x"04C11DB7",
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initialValue => x"00000000"
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)
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port map (
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CLK => CLK,
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reset => CRCRST,
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enable => CRCEN,
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inData => toCRC(7 downto 0),
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checksum => checksum(31 downto 0)
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);
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end block;
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Steuerwerk : block
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-- Typ fuer die Zustandswerte
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type state_t is (S_IDLE, S_READ_WORD, S_CALCULATE_CRC, S_ERROR);
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-- Interne Signale des Rechenwerks
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signal state : state_t := S_IDLE;
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signal state_next : state_t;
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begin
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-- Prozess zur Berechnung des Folgezustandes und der Mealy-Ausgaenge
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Transition: process(RST, state, start, D_ACK_I, startBytesTC, lengthTC)
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begin
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-- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
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state_next <= S_ERROR;
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lengthEN <= '0';
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lengthLD <= '0';
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dataEN <= '0';
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CRCRST <= '0';
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startAddressEN <= '0';
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startAddressLD <= '0';
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startBytesEN <= '0';
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startBytesLD <= '0';
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-- Berechnung des Folgezustandes und der Mealy-Ausgaenge
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case state is
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when S_IDLE =>
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if RST = '1' then
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state_next <= S_IDLE;
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elsif start = '1' then
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state_next <= S_READ_WORD;
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lengthLD <= '1';
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CRCRST <= '1';
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startAddressLD <= '1';
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startBytesLD <= '1';
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elsif start = '0' then
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state_next <= S_IDLE;
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end if;
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when S_READ_WORD =>
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if RST = '1' then
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state_next <= S_IDLE;
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elsif D_ACK_I = '0' then
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state_next <= S_READ_WORD;
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elsif D_ACK_I = '1' then
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state_next <= S_CALCULATE_CRC;
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dataEN <= '1';
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end if;
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when S_CALCULATE_CRC =>
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if RST = '1' then
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state_next <= S_IDLE;
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elsif startBytesTC = '0' and lengthTC = '0' then
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state_next <= S_CALCULATE_CRC;
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lengthEN <= '1';
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startBytesEN <= '1';
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elsif startBytesTC = '1' and lengthTC = '0' then
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state_next <= S_READ_WORD;
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lengthEN <= '1';
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startBytesEN <= '1';
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startAddressEN <= '1';
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elsif lengthTC = '1' then
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state_next <= S_IDLE;
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end if;
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when others =>
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lengthEN <= 'X';
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lengthLD <= 'X';
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dataEN <= 'X';
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CRCRST <= 'X';
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startAddressEN <= 'X';
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startAddressLD <= 'X';
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startBytesEN <= 'X';
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startBytesLD <= 'X';
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end case;
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end process;
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-- Register fuer Zustand und Moore-Ausgaenge
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Reg: process (CLK)
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begin
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if rising_edge(CLK) then
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-- Zustandsregister
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state <= state_next;
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-- Berechnung der Moore-Ausgaenge
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--Default-Werte
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ready <= '0';
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CRCEN <= '0';
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D_STB_O <= '0';
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case state_next is
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when S_IDLE =>
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ready <= '1';
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when S_READ_WORD =>
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D_STB_O <= '1';
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when S_CALCULATE_CRC =>
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CRCEN <= '1';
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when others =>
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ready <= 'X';
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CRCEN <= 'X';
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D_STB_O <= 'X';
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end case;
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end if;
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end process;
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end block;
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end architecture;
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