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CRC timing test + entity of axi_crc component

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This commit is contained in:
Matthias Biermann
2025-01-25 11:53:10 +01:00
parent 8d3ae6374f
commit 4e34f728b4
45 changed files with 121401 additions and 321 deletions
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CRC_Hardware/CRC.vhd → Hardware/CRC.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CRC is
generic (
crcLength : positive;
inDataLength : positive;
polynomial : std_logic_vector;
initialValue : std_logic_vector
);
port (
CLK : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
-- Datensignale
inData : in std_logic_vector(inDataLength-1 downto 0);
checksum : out std_logic_vector(crcLength-1 downto 0)
);
end CRC;
architecture rtl of CRC is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (inData, checksum_i)
variable mix: std_logic_vector(crcLength-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in inData'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & inData(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (CLK)
begin
if rising_edge(CLK) then
if reset = '1' then
checksum_i <= initialValue;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CRC is
generic (
crcLength : positive;
inDataLength : positive
);
port (
CLK : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
initialValue : in std_logic_vector(crcLength-1 downto 0);
polynomial : in std_logic_vector(crcLength-1 downto 0);
-- Datensignale
inData : in std_logic_vector(inDataLength-1 downto 0);
checksum : out std_logic_vector(crcLength-1 downto 0)
);
end CRC;
architecture rtl of CRC is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (inData, checksum_i)
variable mix: std_logic_vector(crcLength-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in inData'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & inData(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (CLK)
begin
if rising_edge(CLK) then
if reset = '1' then
checksum_i <= initialValue;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end architecture;
CRC_Hardware/Mem_to_CRC.vhd → Hardware/Mem_to_CRC.vhd
+258 -258
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@@ -1,258 +1,258 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Mem_to_CRC is
generic (
logLength : integer
);
port (
CLK : in std_logic;
RST : in std_logic;
-- Control IO
ready : out std_logic := '0';
start : in std_logic;
startAddress : in std_logic_vector(31 downto 0);
lengthM1 : in std_logic_vector(logLength-1 downto 0);
-- Wishbone Master
D_DAT_O : out std_logic_vector(31 downto 0) := (others => '0') ;
D_DAT_I : in std_logic_vector(31 downto 0);
D_STB_O : out std_logic := '0';
D_ADR_O : out unsigned(31 downto 0) := (others => '0') ;
D_SEL_O : out std_logic_vector( 3 downto 0);
D_WE_O : out std_logic;
D_ACK_I : in std_logic;
-- CRC output
checksum : out std_logic_vector(31 downto 0) := (others => '0')
);
end entity;
architecture arch of Mem_to_CRC is
--Signale zwischen Steuerwerk und Rechenwerk
signal lengthEN : std_logic := '0';
signal lengthLD : std_logic := '0';
signal lengthTC : std_logic := '0';
signal dataEN : std_logic := '0';
signal CRCEN : std_logic := '0';
signal CRCRST : std_logic := '0';
signal startAddressEN : std_logic := '0';
signal startAddressLD : std_logic := '0';
signal startBytesEN : std_logic := '0';
signal startBytesLD : std_logic := '0';
signal startBytesTC : std_logic := '0';
begin
Rechenwerk: block
-- Register
signal dataByte3 : std_logic_vector(7 downto 0) := (others => '0');
signal dataByte2 : std_logic_vector(7 downto 0) := (others => '0');
signal dataByte1 : std_logic_vector(7 downto 0) := (others => '0');
signal dataByte0 : std_logic_vector(7 downto 0) := (others => '0');
signal toCRC : std_logic_vector(7 downto 0) := (others => '0');
signal byteSelect : std_logic_vector(1 downto 0) := (others => '0');
begin
--Zaehler der Anzahl der Datenbytes
CounterLength: process(CLK)
variable counterValue: unsigned(logLength - 1 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
if lengthLD = '1' then --Laden
counterValue := unsigned(lengthM1);
elsif lengthEN = '1' then --runterzaehlen
counterValue := counterValue - 1;
end if;
if counterValue = 0 then --TC setzen
lengthTC <= '1';
else
lengthTC <= '0';
end if;
end if;
end process;
--Zaehler fuer Adressen
CounterAddress: process(CLK)
variable counterValue : unsigned(31 downto 2) := (others => '0');
begin
if rising_edge(CLK) then
if startAddressLD = '1' then
counterValue := unsigned(startAddress(31 downto 2)); --Speicher laden
elsif startAddressEN = '1' then
counterValue := counterValue + 1; --hochzaehlen
end if;
--Variabel ausgeben und auf 32 Bit erweitern
D_ADR_O <= counterValue & "00";
end if;
end process;
--Modulozaehler fuer die einzelnen Bytes
CounterBytes: process(CLK)
variable counterValue : unsigned(1 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
if startBytesLD = '1' then
counterValue := unsigned(startAddress(1 downto 0)); --Speicher laden
elsif startBytesEN = '1' and counterValue < 3 then --hochzaehlen
counterValue := counterValue + 1;
elsif startBytesEN = '1' and counterValue = 3 then
counterValue := (others => '0'); --zuruecksetzen
end if;
if counterValue = 3 then --TC setzen
startBytesTC <= '1';
else
startBytesTC <= '0';
end if;
--Variabel ausgeben und zum Multiplexer fuehren
byteSelect <= std_logic_vector(counterValue);
end if;
end process;
--vier Pufferregister fuer das Datenwort -> vier Datenbytes
SeparateDataWords: process(CLK)
begin
if rising_edge(CLK) then
if DataEN = '1' then
dataByte3 <= D_DAT_I(31 downto 24);
dataByte2 <= D_DAT_I(23 downto 16);
dataByte1 <= D_DAT_I(15 downto 8);
dataByte0 <= D_DAT_I(7 downto 0);
end if;
end if;
end process;
--Multiplexer für das Ansteuern des ersten Datenbytes
ByteSelectMUX: process(byteSelect, dataByte0, dataByte1, dataByte2, dataByte3)
begin
toCRC <= (others => '0');
case byteSelect is
when "11" => toCRC <= dataByte3;
when "10" => toCRC <= dataByte2;
when "01" => toCRC <= dataByte1;
when "00" => toCRC <= dataByte0;
when others => toCRC <= (others => '-');
end case;
end process;
--Feste Ausgaenge
D_SEL_O <= "1111";
D_WE_O <= '0';
------------------------------------------------------------
-- CRC Berechnung
------------------------------------------------------------
CRC_Inst: entity work.CRC
generic map (
crcLength => 32,
inDataLength => 8,
polynomial => x"04C11DB7",
initialValue => x"00000000"
)
port map (
CLK => CLK,
reset => CRCRST,
enable => CRCEN,
inData => toCRC(7 downto 0),
checksum => checksum(31 downto 0)
);
end block;
Steuerwerk : block
-- Typ fuer die Zustandswerte
type state_t is (S_IDLE, S_READ_WORD, S_CALCULATE_CRC, S_ERROR);
-- Interne Signale des Rechenwerks
signal state : state_t := S_IDLE;
signal state_next : state_t;
begin
-- Prozess zur Berechnung des Folgezustandes und der Mealy-Ausgaenge
Transition: process(RST, state, start, D_ACK_I, startBytesTC, lengthTC)
begin
-- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
state_next <= S_ERROR;
lengthEN <= '0';
lengthLD <= '0';
dataEN <= '0';
CRCRST <= '0';
startAddressEN <= '0';
startAddressLD <= '0';
startBytesEN <= '0';
startBytesLD <= '0';
-- Berechnung des Folgezustandes und der Mealy-Ausgaenge
case state is
when S_IDLE =>
if RST = '1' then
state_next <= S_IDLE;
elsif start = '1' then
state_next <= S_READ_WORD;
lengthLD <= '1';
CRCRST <= '1';
startAddressLD <= '1';
startBytesLD <= '1';
elsif start = '0' then
state_next <= S_IDLE;
end if;
when S_READ_WORD =>
if RST = '1' then
state_next <= S_IDLE;
elsif D_ACK_I = '0' then
state_next <= S_READ_WORD;
elsif D_ACK_I = '1' then
state_next <= S_CALCULATE_CRC;
dataEN <= '1';
end if;
when S_CALCULATE_CRC =>
if RST = '1' then
state_next <= S_IDLE;
elsif startBytesTC = '0' and lengthTC = '0' then
state_next <= S_CALCULATE_CRC;
lengthEN <= '1';
startBytesEN <= '1';
elsif startBytesTC = '1' and lengthTC = '0' then
state_next <= S_READ_WORD;
lengthEN <= '1';
startBytesEN <= '1';
startAddressEN <= '1';
elsif lengthTC = '1' then
state_next <= S_IDLE;
end if;
when others =>
lengthEN <= 'X';
lengthLD <= 'X';
dataEN <= 'X';
CRCRST <= 'X';
startAddressEN <= 'X';
startAddressLD <= 'X';
startBytesEN <= 'X';
startBytesLD <= 'X';
end case;
end process;
-- Register fuer Zustand und Moore-Ausgaenge
Reg: process (CLK)
begin
if rising_edge(CLK) then
-- Zustandsregister
state <= state_next;
-- Berechnung der Moore-Ausgaenge
--Default-Werte
ready <= '0';
CRCEN <= '0';
D_STB_O <= '0';
case state_next is
when S_IDLE =>
ready <= '1';
when S_READ_WORD =>
D_STB_O <= '1';
when S_CALCULATE_CRC =>
CRCEN <= '1';
when others =>
ready <= 'X';
CRCEN <= 'X';
D_STB_O <= 'X';
end case;
end if;
end process;
end block;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Mem_to_CRC is
generic (
logLength : integer
);
port (
CLK : in std_logic;
RST : in std_logic;
-- Control IO
ready : out std_logic := '0';
start : in std_logic;
startAddress : in std_logic_vector(31 downto 0);
lengthM1 : in std_logic_vector(logLength-1 downto 0);
-- Wishbone Master
D_DAT_O : out std_logic_vector(31 downto 0) := (others => '0') ;
D_DAT_I : in std_logic_vector(31 downto 0);
D_STB_O : out std_logic := '0';
D_ADR_O : out unsigned(31 downto 0) := (others => '0') ;
D_SEL_O : out std_logic_vector( 3 downto 0);
D_WE_O : out std_logic;
D_ACK_I : in std_logic;
-- CRC output
checksum : out std_logic_vector(31 downto 0) := (others => '0')
);
end entity;
architecture arch of Mem_to_CRC is
--Signale zwischen Steuerwerk und Rechenwerk
signal lengthEN : std_logic := '0';
signal lengthLD : std_logic := '0';
signal lengthTC : std_logic := '0';
signal dataEN : std_logic := '0';
signal CRCEN : std_logic := '0';
signal CRCRST : std_logic := '0';
signal startAddressEN : std_logic := '0';
signal startAddressLD : std_logic := '0';
signal startBytesEN : std_logic := '0';
signal startBytesLD : std_logic := '0';
signal startBytesTC : std_logic := '0';
begin
Rechenwerk: block
-- Register
signal dataByte3 : std_logic_vector(7 downto 0) := (others => '0');
signal dataByte2 : std_logic_vector(7 downto 0) := (others => '0');
signal dataByte1 : std_logic_vector(7 downto 0) := (others => '0');
signal dataByte0 : std_logic_vector(7 downto 0) := (others => '0');
signal toCRC : std_logic_vector(7 downto 0) := (others => '0');
signal byteSelect : std_logic_vector(1 downto 0) := (others => '0');
begin
--Zaehler der Anzahl der Datenbytes
CounterLength: process(CLK)
variable counterValue: unsigned(logLength - 1 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
if lengthLD = '1' then --Laden
counterValue := unsigned(lengthM1);
elsif lengthEN = '1' then --runterzaehlen
counterValue := counterValue - 1;
end if;
if counterValue = 0 then --TC setzen
lengthTC <= '1';
else
lengthTC <= '0';
end if;
end if;
end process;
--Zaehler fuer Adressen
CounterAddress: process(CLK)
variable counterValue : unsigned(31 downto 2) := (others => '0');
begin
if rising_edge(CLK) then
if startAddressLD = '1' then
counterValue := unsigned(startAddress(31 downto 2)); --Speicher laden
elsif startAddressEN = '1' then
counterValue := counterValue + 1; --hochzaehlen
end if;
--Variabel ausgeben und auf 32 Bit erweitern
D_ADR_O <= counterValue & "00";
end if;
end process;
--Modulozaehler fuer die einzelnen Bytes
CounterBytes: process(CLK)
variable counterValue : unsigned(1 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
if startBytesLD = '1' then
counterValue := unsigned(startAddress(1 downto 0)); --Speicher laden
elsif startBytesEN = '1' and counterValue < 3 then --hochzaehlen
counterValue := counterValue + 1;
elsif startBytesEN = '1' and counterValue = 3 then
counterValue := (others => '0'); --zuruecksetzen
end if;
if counterValue = 3 then --TC setzen
startBytesTC <= '1';
else
startBytesTC <= '0';
end if;
--Variabel ausgeben und zum Multiplexer fuehren
byteSelect <= std_logic_vector(counterValue);
end if;
end process;
--vier Pufferregister fuer das Datenwort -> vier Datenbytes
SeparateDataWords: process(CLK)
begin
if rising_edge(CLK) then
if DataEN = '1' then
dataByte3 <= D_DAT_I(31 downto 24);
dataByte2 <= D_DAT_I(23 downto 16);
dataByte1 <= D_DAT_I(15 downto 8);
dataByte0 <= D_DAT_I(7 downto 0);
end if;
end if;
end process;
--Multiplexer für das Ansteuern des ersten Datenbytes
ByteSelectMUX: process(byteSelect, dataByte0, dataByte1, dataByte2, dataByte3)
begin
toCRC <= (others => '0');
case byteSelect is
when "11" => toCRC <= dataByte3;
when "10" => toCRC <= dataByte2;
when "01" => toCRC <= dataByte1;
when "00" => toCRC <= dataByte0;
when others => toCRC <= (others => '-');
end case;
end process;
--Feste Ausgaenge
D_SEL_O <= "1111";
D_WE_O <= '0';
------------------------------------------------------------
-- CRC Berechnung
------------------------------------------------------------
CRC_Inst: entity work.CRC
generic map (
crcLength => 32,
inDataLength => 8,
polynomial => x"04C11DB7",
initialValue => x"00000000"
)
port map (
CLK => CLK,
reset => CRCRST,
enable => CRCEN,
inData => toCRC(7 downto 0),
checksum => checksum(31 downto 0)
);
end block;
Steuerwerk : block
-- Typ fuer die Zustandswerte
type state_t is (S_IDLE, S_READ_WORD, S_CALCULATE_CRC, S_ERROR);
-- Interne Signale des Rechenwerks
signal state : state_t := S_IDLE;
signal state_next : state_t;
begin
-- Prozess zur Berechnung des Folgezustandes und der Mealy-Ausgaenge
Transition: process(RST, state, start, D_ACK_I, startBytesTC, lengthTC)
begin
-- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
state_next <= S_ERROR;
lengthEN <= '0';
lengthLD <= '0';
dataEN <= '0';
CRCRST <= '0';
startAddressEN <= '0';
startAddressLD <= '0';
startBytesEN <= '0';
startBytesLD <= '0';
-- Berechnung des Folgezustandes und der Mealy-Ausgaenge
case state is
when S_IDLE =>
if RST = '1' then
state_next <= S_IDLE;
elsif start = '1' then
state_next <= S_READ_WORD;
lengthLD <= '1';
CRCRST <= '1';
startAddressLD <= '1';
startBytesLD <= '1';
elsif start = '0' then
state_next <= S_IDLE;
end if;
when S_READ_WORD =>
if RST = '1' then
state_next <= S_IDLE;
elsif D_ACK_I = '0' then
state_next <= S_READ_WORD;
elsif D_ACK_I = '1' then
state_next <= S_CALCULATE_CRC;
dataEN <= '1';
end if;
when S_CALCULATE_CRC =>
if RST = '1' then
state_next <= S_IDLE;
elsif startBytesTC = '0' and lengthTC = '0' then
state_next <= S_CALCULATE_CRC;
lengthEN <= '1';
startBytesEN <= '1';
elsif startBytesTC = '1' and lengthTC = '0' then
state_next <= S_READ_WORD;
lengthEN <= '1';
startBytesEN <= '1';
startAddressEN <= '1';
elsif lengthTC = '1' then
state_next <= S_IDLE;
end if;
when others =>
lengthEN <= 'X';
lengthLD <= 'X';
dataEN <= 'X';
CRCRST <= 'X';
startAddressEN <= 'X';
startAddressLD <= 'X';
startBytesEN <= 'X';
startBytesLD <= 'X';
end case;
end process;
-- Register fuer Zustand und Moore-Ausgaenge
Reg: process (CLK)
begin
if rising_edge(CLK) then
-- Zustandsregister
state <= state_next;
-- Berechnung der Moore-Ausgaenge
--Default-Werte
ready <= '0';
CRCEN <= '0';
D_STB_O <= '0';
case state_next is
when S_IDLE =>
ready <= '1';
when S_READ_WORD =>
D_STB_O <= '1';
when S_CALCULATE_CRC =>
CRCEN <= '1';
when others =>
ready <= 'X';
CRCEN <= 'X';
D_STB_O <= 'X';
end case;
end if;
end process;
end block;
end architecture;
Hardware/axi_crc/axi_crc.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
eof:
Hardware/axi_crc/axi_crc.hw/axi_crc.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
Hardware/axi_crc/axi_crc.srcs/sources_1/new/axi_crc.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity axi_crc is
generic (
DATA_WIDTH : integer := 32; -- Datenwortbreite
ID_WIDTH : integer := 4; -- AXI ID Wortbreite
ID_WIDTH : integer := 4; -- AXI ID Wortbreite
);
port (
CLK : in std_logic;
RESETN : in std_logic;
INTERRUPT : out std_logic;
-- AXI Master Interface (Memory)
M_AXI_ARREADY : in std_logic := '1';
M_AXI_ARVALID : out std_logic;
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARID : out std_logic_vector(ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
M_AXI_RREADY : out std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector( 1 downto 0);
M_AXI_RID : in std_logic_vector(ID_WIDTH-1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_AWREADY : in std_logic := '0';
M_AXI_AWVALID : out std_logic;
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
M_AXI_AWID : out std_logic_vector(ID_WIDTH-1 downto 0);
M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
M_AXI_WREADY : in std_logic := '0';
M_AXI_WVALID : out std_logic;
M_AXI_WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WID : out std_logic_vector(ID_WIDTH-1 downto 0);
M_AXI_BREADY : out std_logic;
M_AXI_BVALID : in std_logic := '0';
M_AXI_BID : in std_logic_vector( ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector( 1 downto 0);
-- AXI-Lite Slave Interface
S_AXIL_AWADDR : in std_logic_vector(7 downto 0);
S_AXIL_AWVALID : in std_logic;
S_AXIL_AWREADY : out std_logic;
S_AXIL_WDATA : in std_logic_vector(31 downto 0);
S_AXIL_WVALID : in std_logic;
S_AXIL_WREADY : out std_logic;
S_AXIL_WSTRB : in std_logic_vector((32/8)-1 downto 0);
S_AXIL_BVALID : out std_logic;
S_AXIL_BREADY : in std_logic;
S_AXIL_BRESP : out std_logic_vector(1 downto 0);
S_AXIL_ARADDR : in std_logic_vector(7 downto 0);
S_AXIL_ARVALID : in std_logic;
S_AXIL_ARREADY : out std_logic;
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
S_AXIL_RVALID : out std_logic;
S_AXIL_RREADY : in std_logic;
S_AXIL_RRESP : out std_logic_vector(1 downto 0);
);
end axi_crc;
architecture rtl of axi_crc is
begin
end Behavioral;
Hardware/axi_crc/axi_crc.srcs/sources_1/new/crc.vhd
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@@ -0,0 +1,63 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity crc is
generic (
crcLength : positive;
inDataLength : positive
);
port (
clk : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
initialValue : in std_logic_vector(crcLength-1 downto 0);
polynomial : in std_logic_vector(crcLength-1 downto 0);
-- Datensignale
inData : in std_logic_vector(inDataLength-1 downto 0);
checksum : out std_logic_vector(crcLength-1 downto 0)
);
end crc;
architecture Behavioral of crc is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (inData, checksum_i)
variable mix: std_logic_vector(crcLength-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in inData'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & inData(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
checksum_i <= initialValue;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end Behavioral;
Hardware/axi_crc/axi_crc.xpr
+224
View File
@@ -0,0 +1,224 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="31">
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<Filter Type="Srcs"/>
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<FileInfo>
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<Config>
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<Option Name="TopModule" Val="axi_crc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
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<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_crc"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
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<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
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<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
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<Option Name="Description" Val="ModelSim Simulator"/>
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
IP/.gitignore
+89
View File
@@ -0,0 +1,89 @@
# Created by https://www.toptal.com/developers/gitignore/api/vivado
# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
### Vivado ###
#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########
#Exclude all
*
!*/
!.gitignore
###########################################################################
## VIVADO
#Source files:
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.sv
!*.bd
!*.edif
#IP files
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#.xcix: Core container file
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
!*.xcix
#*.dcp(checkpoint files)
!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#System Generator
!*.mdl
!*.slx
!*.bxml
#Simulation logic analyzer
!*.wcfg
!*.coe
#MIG
!*.prj
!*.mem
#Project files
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#Constraint files
#Do NOT ignore *.xdc files
!*.xdc
#TCL - files
!*.tcl
#Journal - files
!*.jou
#Reports
!*.rpt
!*.txt
!*.vdi
#C-files
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
# End of https://www.toptal.com/developers/gitignore/api/vivado
# Vidado project directories which are not needed
.Xil/
*.cache/
*.hw/
*.ip_user_files/
*.runs/
*.sim/
# design checkpoint file
*.dcp
# ignore Vivado log files
*.log
*.jou
vivado_pid*.str
# DO NOT ignore images as bitmap files
!*.bmp
Konzept/crc_dauer.py
+5
View File
@@ -0,0 +1,5 @@
dataSize = 1_000_000
T_ns = 8
T_s = T_ns * 1e-9
print(dataSize*T_s)
Support/CRC_Test/.gitignore
+89
View File
@@ -0,0 +1,89 @@
# Created by https://www.toptal.com/developers/gitignore/api/vivado
# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
### Vivado ###
#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########
#Exclude all
*
!*/
!.gitignore
###########################################################################
## VIVADO
#Source files:
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.sv
!*.bd
!*.edif
#IP files
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#.xcix: Core container file
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
!*.xcix
#*.dcp(checkpoint files)
!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#System Generator
!*.mdl
!*.slx
!*.bxml
#Simulation logic analyzer
!*.wcfg
!*.coe
#MIG
!*.prj
!*.mem
#Project files
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#Constraint files
#Do NOT ignore *.xdc files
!*.xdc
#TCL - files
!*.tcl
#Journal - files
!*.jou
#Reports
!*.rpt
!*.txt
!*.vdi
#C-files
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
# End of https://www.toptal.com/developers/gitignore/api/vivado
# Vidado project directories which are not needed
.Xil/
*.cache/
*.hw/
*.ip_user_files/
*.runs/
*.sim/
# design checkpoint file
*.dcp
# ignore Vivado log files
*.log
*.jou
vivado_pid*.str
# DO NOT ignore images as bitmap files
!*.bmp
Support/CRC_Test/CRC_Test.srcs/constrs_1/new/CRC_Test.xdc
+59
View File
@@ -0,0 +1,59 @@
create_clock -add -name clk_pin -period 8.00 [get_ports clk ];
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports clk]; # Board Clock
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports reset]; # Button 0
#Pmod Header JA (XADC)
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
#Pmod Header JB (Zybo Z7-20 only)
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
#Pmod Header JC
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
#Pmod Header JD
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
#Pmod Header JE
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
Support/CRC_Test/CRC_Test.srcs/sources_1/new/CRC_Bench.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.01.2025 12:38:34
-- Design Name:
-- Module Name: CRC_Bench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CRC_Bench is
port (
clk : in std_logic; -- 125 MHz Takt
reset : in std_logic; -- Reset, high-
ja : in std_logic_vector(7 downto 0);
jb : in std_logic_vector(7 downto 0);
jc : in std_logic_vector(7 downto 0);
jd : out std_logic_vector(7 downto 0);
je : out std_logic_vector(7 downto 0)
);
end CRC_Bench;
architecture Behavioral of CRC_Bench is
constant CLK_PERIOD : time := 20 ns;
constant crcLength : positive := 32;
constant inDataLength : positive := 8;
signal enable : std_logic;
signal initialValue : std_logic_vector(crcLength-1 downto 0) := x"00000000";
signal polynomial : std_logic_vector(crcLength-1 downto 0) := x"04C11DB7";
signal inData : std_logic_vector(inDataLength-1 downto 0);
signal checksum : std_logic_vector(crcLength-1 downto 0);
begin
uut: entity work.CRC
generic map (
crcLength => crcLength,
inDataLength => inDataLength
)
port map (
CLK => clk,
reset => reset,
enable => enable,
polynomial => polynomial,
initialValue => initialValue,
inData => inData,
checksum => checksum
);
enable <= '1';
initialValue <= x"00000000";
polynomial(31 downto 16) <= jb & jc;
inData(7 downto 0) <= ja;
je <= checksum(31 downto 24);
end Behavioral;
Support/CRC_Test/CRC_Test.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-abschlussprojekt/Support/CRC_Test/CRC_Test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../CRC_Hardware/CRC.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/CRC_Bench.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CRC_Bench"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/CRC_Test.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CRC_Bench"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/CRC_Bench.dcp">
<FileInfo>
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</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
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<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
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<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/CRC_Bench.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
Support/Milestone4/es-m4-axi/.gitignore
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# Created by https://www.toptal.com/developers/gitignore/api/vivado
# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
### Vivado ###
#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########
#Exclude all
*
!*/
!.gitignore
###########################################################################
## VIVADO
#Source files:
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.sv
!*.bd
!*.edif
#IP files
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#.xcix: Core container file
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
!*.xcix
#*.dcp(checkpoint files)
!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#System Generator
!*.mdl
!*.slx
!*.bxml
#Simulation logic analyzer
!*.wcfg
!*.coe
#MIG
!*.prj
!*.mem
#Project files
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#Constraint files
#Do NOT ignore *.xdc files
!*.xdc
#TCL - files
!*.tcl
#Journal - files
!*.jou
#Reports
!*.rpt
!*.txt
!*.vdi
#C-files
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
# End of https://www.toptal.com/developers/gitignore/api/vivado
# Vidado project directories which are not needed
.Xil/
*.cache/
*.hw/
*.ip_user_files/
*.runs/
*.sim/
# design checkpoint file
*.dcp
# ignore Vivado log files
*.log
*.jou
vivado_pid*.str
# DO NOT ignore images as bitmap files
!*.bmp
Support/Milestone4/es-m4-axi/es-m4-axi.gen/sources_1/bd/design_1/design_1.bxml
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<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1737799735"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1737799735"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1737799735"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1737799735"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Support/Milestone4/es-m4-axi/es-m4-axi.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xml
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>design_1_rst_ps7_0_50M_0</spirit:name>
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<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clock</spirit:name>
<spirit:displayName>Clock</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>slowest_sync_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">166666672</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
<spirit:vendorExtensions>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
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<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">design_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>ext_reset</spirit:name>
<spirit:displayName>Ext_Reset</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ext_reset_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:presence>required</xilinx:presence>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>aux_reset</spirit:name>
<spirit:displayName>aux_reset</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>aux_reset_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>dbg_reset</spirit:name>
<spirit:displayName>DBG_Reset</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mb_debug_sys_rst</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>mb_rst</spirit:name>
<spirit:displayName>MB_rst</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mb_reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TYPE</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>bus_struct_reset</spirit:name>
<spirit:displayName>bus_struct_reset</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>bus_struct_reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TYPE</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>interconnect_low_rst</spirit:name>
<spirit:displayName>interconnect_low_rst</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>interconnect_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TYPE</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>peripheral_high_rst</spirit:name>
<spirit:displayName>peripheral_high_rst</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>peripheral_reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TYPE</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>peripheral_low_rst</spirit:name>
<spirit:displayName>peripheral_low_rst</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>peripheral_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TYPE</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>slowest_sync_clk</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ext_reset_in</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>aux_reset_in</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>mb_debug_sys_rst</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>dcm_locked</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>mb_reset</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>bus_struct_reset</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">0</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_BUS_RST&apos;)) - 1)">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>peripheral_reset</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">0</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_RST&apos;)) - 1)">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>interconnect_aresetn</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">0</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN&apos;)) - 1)">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>peripheral_aresetn</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">0</spirit:left>
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_ARESETN&apos;)) - 1)">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
<spirit:name>C_FAMILY</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
<spirit:displayName>Ext Rst Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
<spirit:displayName>Aux Rst Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic">
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
<spirit:displayName>Ext Reset High</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic">
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
<spirit:displayName>Aux Reset High</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_NUM_BUS_RST</spirit:name>
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_NUM_PERP_RST</spirit:name>
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_ac75ef1e</spirit:name>
<spirit:enumeration>Custom</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:description>Processor Reset System</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_NUM_PERP_RST</spirit:name>
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_NUM_BUS_RST</spirit:name>
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
<spirit:displayName>Aux Reset High</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
<spirit:displayName>Ext Reset High</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
<spirit:displayName>Aux Rst Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
<spirit:displayName>Ext Rst Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_rst_ps7_0_50M_0</spirit:value>
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<spirit:parameter>
<spirit:name>USE_BOARD_FLOW</spirit:name>
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
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</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>Processor System Reset</xilinx:displayName>
<xilinx:coreRevision>13</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
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</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
Support/Milestone4/es-m4-axi/es-m4-axi.gen/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xml
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/design_1.bd
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.xci
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "design_1_auto_pc_0",
"cell_name": "PS/axi_interconnect_4/s00_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "28",
"gen_directory": "../../../../../../es-m4-axi.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0",
"parameters": {
"component_parameters": {
"SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Component_Name": [ { "value": "design_1_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
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"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
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"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
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"PACKAGE": [ { "value": "clg400" } ],
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"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
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"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
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"s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
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},
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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}
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},
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"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
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}
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}
Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0/design_1_axi_interconnect_0_0.xci
+352
View File
@@ -0,0 +1,352 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "design_1_axi_interconnect_0_0",
"cell_name": "PS/axi_interconnect_0",
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"ip_revision": "29",
"gen_directory": "../../../../../../es-m4-axi.gen/sources_1/bd/design_1/ip/design_1_axi_interconnect_0_0",
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+352
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@@ -0,0 +1,352 @@
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_2_0/design_1_axi_interconnect_2_0.xci
+352
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@@ -0,0 +1,352 @@
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_interconnect_3_0/design_1_axi_interconnect_3_0.xci
+352
View File
@@ -0,0 +1,352 @@
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+352
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@@ -0,0 +1,352 @@
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_read_generator_0_0/design_1_axi_read_generator_0_0.xci
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@@ -0,0 +1,296 @@
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_read_generator_1_0/design_1_axi_read_generator_1_0.xci
+296
View File
@@ -0,0 +1,296 @@
{
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_read_generator_2_0/design_1_axi_read_generator_2_0.xci
+296
View File
@@ -0,0 +1,296 @@
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_axi_read_generator_3_0/design_1_axi_read_generator_3_0.xci
+296
View File
@@ -0,0 +1,296 @@
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"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
}
},
"RESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "RESETN" } ]
}
},
"CLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "166666672", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "CLK" } ]
}
}
},
"address_spaces": {
"M_AXI": {
"range": "4294967296",
"width": "64"
}
},
"memory_maps": {
"S_AXIL": {
"address_blocks": {
"reg0": {
"base_address": "0",
"range": "32768",
"usage": "register"
}
}
}
}
}
}
}
Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci
+1937
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0/design_1_rst_ps7_0_50M_0.xci
+195
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "design_1_rst_ps7_0_50M_0",
"cell_name": "PS/rst_ps7_0_50M",
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
"ip_revision": "13",
"gen_directory": "../../../../../../es-m4-axi.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0",
"parameters": {
"component_parameters": {
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "design_1_rst_ps7_0_50M_0", "resolve_type": "user", "usage": "all" } ],
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "13" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../es-m4-axi.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_50M_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"slowest_sync_clk": [ { "direction": "in" } ],
"ext_reset_in": [ { "direction": "in" } ],
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
},
"interfaces": {
"clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"FREQ_HZ": [ { "value": "166666672", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "design_1_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
}
},
"ext_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "ext_reset_in" } ]
}
},
"aux_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aux_reset_in" } ]
}
},
"dbg_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
}
},
"mb_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "mb_reset" } ]
}
},
"bus_struct_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "bus_struct_reset" } ]
}
},
"interconnect_low_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "interconnect_aresetn" } ]
}
},
"peripheral_high_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "peripheral_reset" } ]
}
},
"peripheral_low_rst": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "peripheral_aresetn" } ]
}
}
}
}
}
}
Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci
+1640
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Support/Milestone4/es-m4-axi/es-m4-axi.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
+28
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{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"2.0",
"Default View_TopLeft":"-38,-50",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
preplace port DDR -pg 1 -lvl 3 -x 580 -y 60 -defaultsOSRD
preplace port FIXED_IO -pg 1 -lvl 3 -x 580 -y 90 -defaultsOSRD
preplace inst PS -pg 1 -lvl 2 -x 400 -y 140 -defaultsOSRD
preplace inst READ_GEN -pg 1 -lvl 1 -x 170 -y 140 -defaultsOSRD
preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 40 280 NJ 280 520
preplace netloc rst_ps7_0_50M_peripheral_aresetn 1 0 3 20 300 NJ 300 540
preplace netloc PS_M00_AXI 1 0 3 50 270 NJ 270 560
preplace netloc PS_M01_AXI 1 0 3 60 10 NJ 10 520
preplace netloc PS_M02_AXI 1 0 3 60 260 NJ 260 530
preplace netloc READ_GEN_M_AXI1 1 1 1 N 130
preplace netloc READ_GEN_M_AXI2 1 1 1 N 150
preplace netloc READ_GEN_M_AXI3 1 1 1 N 170
preplace netloc axi_read_generator_2_M_AXI 1 1 1 N 110
preplace netloc processing_system7_0_DDR 1 2 1 560J 60n
preplace netloc processing_system7_0_FIXED_IO 1 2 1 NJ 90
preplace netloc ps7_0_axi_periph_M03_AXI 1 0 3 30 290 NJ 290 550
levelinfo -pg 1 0 170 400 580
pagesize -pg 1 -db -bbox -sgen 0 0 690 310
"
}
Support/Milestone4/es-m4-axi/es-m4-axi.xpr
+212
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@@ -0,0 +1,212 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-abschlussprojekt/Support/Milestone4/es-m4-axi/es-m4-axi.xpr">
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
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<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../IP"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>