Matthias Biermann
79 lines
2.4 KiB
VHDL
79 lines
2.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axis_crc is
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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-- for crc calculation
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initial_value : in std_logic_vector(31 downto 0);
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polynomial : in std_logic_vector(31 downto 0);
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-- AXI Streaming Target Port
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S_AXIS_TVALID : in std_logic;
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S_AXIS_TDATA : in std_logic_vector(16 downto 0);
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S_AXIS_TLAST : in std_logic := '0';
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S_AXIS_TREADY : out std_logic;
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-- AXI Streaming Initiator Port
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M_AXIS_TVALID : out std_logic;
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M_AXIS_TDATA : out std_logic_vector(16 downto 0);
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M_AXIS_TLAST : out std_logic;
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M_AXIS_TREADY : in std_logic
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);
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end entity;
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architecture rtl of axis_audio_filter3 is
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signal m_valid_sig : std_logic := '0';
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begin
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S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
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process
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-- fuer CRC-Berechnung
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variable CRC : std_logic_vector(31 downto 0);
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variable MSB : std_logic;
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variable data : std_logic_vector(31 downto 0);
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variable last : std_logic;
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begin
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wait until rising_edge(AXIS_ACLK);
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if RESETN = '0' then
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CRC := initial_value;
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else
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if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
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M_AXIS_TVALID <= S_AXIS_TVALID;
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if HAS_LAST then
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M_AXIS_TLAST <= S_AXIS_TLAST;
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end if;
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m_valid_sig <= S_AXIS_TVALID;
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if S_AXIS_TVALID = '1' then
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-- 16 Bit in die CRC Summe reinrechnen
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for i in 31 downto 16 loop
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-- Pruefen ob MSB gesetzt ist
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MSB := CRC(CRC'length-1);
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-- neues Bit reinschieben
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CRC := CRC(CRC'length-2 downto 0) & data(i);
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-- XOR Verknuepfung
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if MSB = '1' then
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CRC := CRC XOR polynomial;
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end if;
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end loop;
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S_AXIS_TREADY <= '0';
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state <= SECOND_HALF;
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end if;
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M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
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end if;
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end if;
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end if;
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end process;
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end;
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