axis_crc Fehler gefixt
This commit is contained in:
Matthias Biermann
+4
-4
@@ -2,10 +2,10 @@
|
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<Root MajorVersion="0" MinorVersion="40">
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||||
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738454412"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738454413"/>
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||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738454412"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738454413"/>
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||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738469743"/>
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||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738469743"/>
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||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738469743"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738469743"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\axi_crc_dma_sim_1.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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+1
-1
@@ -2,7 +2,7 @@
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--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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||||
--Date : Sun Feb 2 01:00:12 2025
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--Date : Sun Feb 2 05:15:42 2025
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--Host : BiermannSurface running 64-bit major release (build 9200)
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--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
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--Design : axi_crc_dma_sim_1_wrapper
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+1
-1
@@ -664,7 +664,7 @@
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<spirit:parameters>
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||||
<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
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<spirit:value>Sun Feb 02 02:02:02 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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+6
-5
@@ -581,7 +581,7 @@
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:8286588d</spirit:value>
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<spirit:value>9:be22c7e7</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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@@ -597,11 +597,11 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
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<spirit:value>Sun Feb 02 02:12:31 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:8286588d</spirit:value>
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<spirit:value>9:be22c7e7</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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@@ -983,7 +983,7 @@
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:name>REVISION_NO</spirit:name>
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<spirit:displayName>Revision No</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">1</spirit:value>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">8</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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</spirit:model>
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@@ -1039,7 +1039,7 @@
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<spirit:parameter>
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<spirit:name>REVISION_NO</spirit:name>
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<spirit:displayName>Revision No</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">1</spirit:value>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">8</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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@@ -1086,6 +1086,7 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.REVISION_NO" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.STIM_FILENAME" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
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</xilinx:coreExtensions>
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+1
-1
@@ -149,7 +149,7 @@ BEGIN
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STIM_FILENAME => "../../axi_crc_dma_sim.mem",
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HAS_FINISHED_OUT => false,
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HAS_INTERRUPT_IN => true,
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REVISION_NO => 1
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REVISION_NO => 8
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)
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PORT MAP (
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interrupt_in => interrupt_in,
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+1
-1
@@ -461,7 +461,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
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<spirit:value>Sun Feb 02 04:07:29 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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+58
-3
@@ -1424,6 +1424,37 @@
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>INTERRUPT</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>INTERRUPT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>INTERRUPT</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>SENSITIVITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" spirit:choiceRef="choice_list_99a1d2b9">LEVEL_HIGH</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PortWidth</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PortWidth">1</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:addressSpaces>
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<spirit:addressSpace>
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@@ -1457,7 +1488,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:e65ec1c3</spirit:value>
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||||
<spirit:value>9:91ac5338</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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@@ -1473,11 +1504,11 @@
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<spirit:parameters>
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<spirit:parameter>
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||||
<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Sat Feb 01 23:59:43 UTC 2025</spirit:value>
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||||
<spirit:value>Sun Feb 02 04:15:43 UTC 2025</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:e65ec1c3</spirit:value>
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||||
<spirit:value>9:91ac5338</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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@@ -1507,6 +1538,21 @@
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>INTERRUPT</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>initial_value</spirit:name>
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<spirit:wire>
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@@ -2516,6 +2562,13 @@
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</spirit:modelParameters>
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</spirit:model>
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<spirit:choices>
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<spirit:choice>
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<spirit:name>choice_list_99a1d2b9</spirit:name>
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<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
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<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
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<spirit:enumeration>EDGE_RISING</spirit:enumeration>
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<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
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</spirit:choice>
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<spirit:choice>
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<spirit:name>choice_list_9d8b0d81</spirit:name>
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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@@ -2582,6 +2635,8 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.PortWidth" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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||||
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+5
@@ -57,6 +57,7 @@ ENTITY axi_crc_dma_sim_1_axis_dma_0_0 IS
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PORT (
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CLK : IN STD_LOGIC;
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RESETN : IN STD_LOGIC;
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INTERRUPT : OUT STD_LOGIC;
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initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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@@ -138,6 +139,7 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0
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PORT (
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CLK : IN STD_LOGIC;
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RESETN : IN STD_LOGIC;
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INTERRUPT : OUT STD_LOGIC;
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initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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@@ -207,6 +209,8 @@ ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0
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ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
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ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
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ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
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ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
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ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
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ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
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@@ -287,6 +291,7 @@ BEGIN
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PORT MAP (
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CLK => CLK,
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RESETN => RESETN,
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INTERRUPT => INTERRUPT,
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initial_value => initial_value,
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polynomial => polynomial,
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FIFO_NUM_FREE => FIFO_NUM_FREE,
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+1
-1
@@ -1167,7 +1167,7 @@
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<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
|
||||
<spirit:value>Sun Feb 02 01:19:48 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+21
-14
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 01:00:12 2025
|
||||
--Date : Sun Feb 2 05:15:42 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1.bd
|
||||
--Design : axi_crc_dma_sim_1
|
||||
@@ -15,6 +15,7 @@ use UNISIM.VCOMPONENTS.ALL;
|
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entity axi_crc_dma_imp_1PQG7GB is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -124,6 +125,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
@@ -235,6 +237,11 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_WVALID : STD_LOGIC;
|
||||
signal RESETN_1 : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dma_0_INTERRUPT : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
@@ -251,10 +258,6 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
@@ -286,6 +289,7 @@ begin
|
||||
Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
|
||||
Conn2_RVALID <= M_AXI_rvalid;
|
||||
Conn2_WREADY <= M_AXI_wready;
|
||||
INTERRUPT <= axis_dma_0_INTERRUPT;
|
||||
M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0);
|
||||
M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0);
|
||||
M_AXI_arid(0) <= Conn2_ARID(0);
|
||||
@@ -315,10 +319,10 @@ begin
|
||||
axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => CLK_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
RESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
|
||||
@@ -332,6 +336,7 @@ axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
|
||||
CLK => CLK_1,
|
||||
FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
|
||||
INTERRUPT => axis_dma_0_INTERRUPT,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
|
||||
@@ -426,11 +431,11 @@ axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0
|
||||
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
S_AXIS_ACLK => CLK_1,
|
||||
S_AXIS_ARESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
|
||||
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -514,6 +519,7 @@ architecture STRUCTURE of axi_crc_dma_sim_1 is
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axi3_slave_verif_0_0;
|
||||
signal axi_crc_dma_INTERRUPT : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -598,6 +604,7 @@ axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0
|
||||
axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
INTERRUPT => axi_crc_dma_INTERRUPT,
|
||||
M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0),
|
||||
@@ -667,7 +674,7 @@ axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => '0'
|
||||
interrupt_in => axi_crc_dma_INTERRUPT
|
||||
);
|
||||
clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
|
||||
+21
-14
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 01:00:12 2025
|
||||
--Date : Sun Feb 2 05:15:42 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1.bd
|
||||
--Design : axi_crc_dma_sim_1
|
||||
@@ -15,6 +15,7 @@ use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axi_crc_dma_imp_1PQG7GB is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -124,6 +125,7 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
INTERRUPT : out STD_LOGIC;
|
||||
initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
@@ -235,6 +237,11 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn2_WVALID : STD_LOGIC;
|
||||
signal RESETN_1 : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_crc_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_crc_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_dma_0_INTERRUPT : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
@@ -251,10 +258,6 @@ architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
|
||||
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
@@ -286,6 +289,7 @@ begin
|
||||
Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
|
||||
Conn2_RVALID <= M_AXI_rvalid;
|
||||
Conn2_WREADY <= M_AXI_wready;
|
||||
INTERRUPT <= axis_dma_0_INTERRUPT;
|
||||
M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0);
|
||||
M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0);
|
||||
M_AXI_arid(0) <= Conn2_ARID(0);
|
||||
@@ -315,10 +319,10 @@ begin
|
||||
axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => CLK_1,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
RESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
|
||||
@@ -332,6 +336,7 @@ axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
|
||||
CLK => CLK_1,
|
||||
FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
|
||||
INTERRUPT => axis_dma_0_INTERRUPT,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
|
||||
@@ -426,11 +431,11 @@ axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0
|
||||
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
|
||||
S_AXIS_ACLK => CLK_1,
|
||||
S_AXIS_ARESETN => RESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_crc_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_crc_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_crc_0_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
|
||||
S_AXIS_TVALID => axis_crc_0_M_AXIS_TVALID,
|
||||
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -514,6 +519,7 @@ architecture STRUCTURE of axi_crc_dma_sim_1 is
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component axi_crc_dma_sim_1_axi3_slave_verif_0_0;
|
||||
signal axi_crc_dma_INTERRUPT : STD_LOGIC;
|
||||
signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -598,6 +604,7 @@ axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0
|
||||
axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
INTERRUPT => axi_crc_dma_INTERRUPT,
|
||||
M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0),
|
||||
@@ -667,7 +674,7 @@ axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => '0'
|
||||
interrupt_in => axi_crc_dma_INTERRUPT
|
||||
);
|
||||
clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
|
||||
+5
-50
@@ -2,55 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axis_crc_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738454377"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738454377"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738454377"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738454377"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axis_crc_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axis_crc_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axis_crc_sim_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\axis_crc_sim_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axis_crc_sim_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\axis_crc_sim_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axis_crc_sim_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738469242"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738469242"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738469242"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738469242"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
-10
@@ -1,10 +0,0 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 00:16:45 2025
|
||||
--Date : Sun Feb 2 04:32:07 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_crc_sim_1_wrapper.bd
|
||||
--Design : axis_crc_sim_1_wrapper
|
||||
|
||||
+12
-119
@@ -436,83 +436,6 @@
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7d52f37a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3fed59a8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3fed59a8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axis_crc_sim_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 23:16:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7d52f37a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axis_crc_sim_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 01 23:59:37 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3fed59a8</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -521,8 +444,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -534,8 +456,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -551,8 +472,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -568,8 +488,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -581,8 +500,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -598,8 +516,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -614,8 +531,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -630,8 +546,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -643,8 +558,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -660,8 +574,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -673,8 +586,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -686,8 +598,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -704,24 +615,6 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axis_crc_sim_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/axis_crc_sim_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
|
||||
-132
@@ -1,132 +0,0 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_crc_sim_1_axis_crc_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axis_crc_sim_1_axis_crc_0_0;
|
||||
|
||||
ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_crc;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_crc_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_crc
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axis_crc_sim_1_axis_crc_0_0_arch;
|
||||
-151
@@ -1,151 +0,0 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 00:16:45 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_crc_sim_1.bd
|
||||
--Design : axis_crc_sim_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axis_crc_sim_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef";
|
||||
end axis_crc_sim_1;
|
||||
|
||||
architecture STRUCTURE of axis_crc_sim_1 is
|
||||
component axis_crc_sim_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_clk_rst_generator_0_0;
|
||||
component axis_crc_sim_1_axis_slave_simmodel_0_0 is
|
||||
port (
|
||||
FINISHED : out STD_LOGIC;
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_slave_simmodel_0_0;
|
||||
component axis_crc_sim_1_axis_master_simmodel_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_master_simmodel_0_0;
|
||||
component axis_crc_sim_1_xlconstant_1_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_1_0;
|
||||
component axis_crc_sim_1_xlconstant_0_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_0_0;
|
||||
component axis_crc_sim_1_axis_crc_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_crc_0_0;
|
||||
signal AXIS_ARESETN_1 : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_FINISHED : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal crc_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal crc_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
|
||||
begin
|
||||
axis_crc_0: component axis_crc_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => crc_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => crc_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => crc_M_AXIS_TVALID,
|
||||
RESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID,
|
||||
initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0),
|
||||
polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => AXIS_ARESETN_1,
|
||||
FINISHED => axis_master_simmodel_0_FINISHED,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0),
|
||||
M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0
|
||||
port map (
|
||||
FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED,
|
||||
S_AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
S_AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => crc_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => crc_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => crc_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => AXIS_ARESETN_1,
|
||||
stop_simulation => axis_master_simmodel_0_FINISHED
|
||||
);
|
||||
xlconstant_0: component axis_crc_sim_1_xlconstant_0_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
xlconstant_1: component axis_crc_sim_1_xlconstant_1_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_1_dout(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
-151
@@ -1,151 +0,0 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 00:16:45 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axis_crc_sim_1.bd
|
||||
--Design : axis_crc_sim_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axis_crc_sim_1 is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef";
|
||||
end axis_crc_sim_1;
|
||||
|
||||
architecture STRUCTURE of axis_crc_sim_1 is
|
||||
component axis_crc_sim_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_clk_rst_generator_0_0;
|
||||
component axis_crc_sim_1_axis_slave_simmodel_0_0 is
|
||||
port (
|
||||
FINISHED : out STD_LOGIC;
|
||||
S_AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_slave_simmodel_0_0;
|
||||
component axis_crc_sim_1_axis_master_simmodel_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_axis_master_simmodel_0_0;
|
||||
component axis_crc_sim_1_xlconstant_1_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_1_0;
|
||||
component axis_crc_sim_1_xlconstant_0_0 is
|
||||
port (
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
end component axis_crc_sim_1_xlconstant_0_0;
|
||||
component axis_crc_sim_1_axis_crc_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component axis_crc_sim_1_axis_crc_0_0;
|
||||
signal AXIS_ARESETN_1 : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_FINISHED : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_M_AXIS_TLAST : STD_LOGIC;
|
||||
signal crc_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal crc_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
|
||||
begin
|
||||
axis_crc_0: component axis_crc_sim_1_axis_crc_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => crc_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => crc_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => crc_M_AXIS_TVALID,
|
||||
RESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID,
|
||||
initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0),
|
||||
polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => AXIS_ARESETN_1,
|
||||
FINISHED => axis_master_simmodel_0_FINISHED,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
|
||||
M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0),
|
||||
M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0
|
||||
port map (
|
||||
FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED,
|
||||
S_AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
S_AXIS_ARESETN => AXIS_ARESETN_1,
|
||||
S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TLAST => crc_M_AXIS_TLAST,
|
||||
S_AXIS_TREADY => crc_M_AXIS_TREADY,
|
||||
S_AXIS_TUSER(0) => '0',
|
||||
S_AXIS_TVALID => crc_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => AXIS_ARESETN_1,
|
||||
stop_simulation => axis_master_simmodel_0_FINISHED
|
||||
);
|
||||
xlconstant_0: component axis_crc_sim_1_xlconstant_0_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_0_dout(31 downto 0)
|
||||
);
|
||||
xlconstant_1: component axis_crc_sim_1_xlconstant_1_0
|
||||
port map (
|
||||
dout(31 downto 0) => xlconstant_1_dout(31 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
+3
-3
@@ -305,7 +305,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>6d6387c1</spirit:value>
|
||||
<spirit:value>4b08b998</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -318,7 +318,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>6d6387c1</spirit:value>
|
||||
<spirit:value>4b08b998</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -906,7 +906,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-02-01T20:40:20Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-02-02T02:01:58Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
@@ -145,7 +145,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b45c4280</spirit:value>
|
||||
<spirit:value>8ca8a756</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -158,7 +158,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>b45c4280</spirit:value>
|
||||
<spirit:value>8ca8a756</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -395,7 +395,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-02-01T19:31:07Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-02-02T04:07:21Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
@@ -561,6 +561,28 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>INTERRUPT</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>INTERRUPT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>INTERRUPT</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SENSITIVITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" spirit:choiceRef="choice_list_9ca20931">LEVEL_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:addressSpaces>
|
||||
<spirit:addressSpace>
|
||||
@@ -595,7 +617,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>ba1cd223</spirit:value>
|
||||
<spirit:value>2b97c8af</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -608,7 +630,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>ba1cd223</spirit:value>
|
||||
<spirit:value>2b97c8af</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -648,6 +670,22 @@
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>INTERRUPT</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>initial_value</spirit:name>
|
||||
<spirit:wire>
|
||||
@@ -1725,6 +1763,13 @@
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9ca20931</spirit:name>
|
||||
<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
|
||||
<spirit:enumeration>EDGE_RISING</spirit:enumeration>
|
||||
<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
@@ -1789,7 +1834,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-02-01T23:59:34Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-02-02T04:15:37Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
+40
-7
@@ -43,6 +43,10 @@
|
||||
"RESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"INTERRUPT": {
|
||||
"type": "intr",
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
@@ -861,6 +865,20 @@
|
||||
}
|
||||
}
|
||||
},
|
||||
"INTERRUPT": {
|
||||
"type": "intr",
|
||||
"direction": "O",
|
||||
"parameters": {
|
||||
"SENSITIVITY": {
|
||||
"value": "LEVEL_HIGH",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PortWidth": {
|
||||
"value": "1",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"initial_value": {
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
@@ -905,6 +923,12 @@
|
||||
"M_AXI"
|
||||
]
|
||||
},
|
||||
"axis_crc_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_crc_0/M_AXIS",
|
||||
"axis_fifo_1/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_dma_0/M_AXIS",
|
||||
@@ -922,12 +946,6 @@
|
||||
"axis_fifo_1/M_AXIS",
|
||||
"axis_dma_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_upsizer_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_crc_0/M_AXIS",
|
||||
"axis_fifo_1/S_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
@@ -948,11 +966,17 @@
|
||||
"axis_fifo_0/M_AXIS_ARESETN",
|
||||
"axis_fifo_1/S_AXIS_ARESETN",
|
||||
"axis_fifo_1/M_AXIS_ARESETN",
|
||||
"axis_crc_0/RESETN",
|
||||
"axis_fifo_0/S_AXIS_ARESETN",
|
||||
"axis_crc_0/RESETN",
|
||||
"axis_dma_0/RESETN"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_INTERRUPT": {
|
||||
"ports": [
|
||||
"axis_dma_0/INTERRUPT",
|
||||
"INTERRUPT"
|
||||
]
|
||||
},
|
||||
"axis_dma_0_initial_value": {
|
||||
"ports": [
|
||||
"axis_dma_0/initial_value",
|
||||
@@ -985,6 +1009,9 @@
|
||||
"xci_path": "ip\\axi_crc_dma_sim_1_axil_master_with_rom_0_0\\axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci",
|
||||
"inst_hier_path": "axil_master_with_rom_0",
|
||||
"parameters": {
|
||||
"REVISION_NO": {
|
||||
"value": "8"
|
||||
},
|
||||
"STIM_FILENAME": {
|
||||
"value": "../../axi_crc_dma_sim.mem"
|
||||
}
|
||||
@@ -1311,6 +1338,12 @@
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"axi_crc_dma_INTERRUPT": {
|
||||
"ports": [
|
||||
"axi_crc_dma/INTERRUPT",
|
||||
"axil_master_with_rom_0/interrupt_in"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
|
||||
+2
-2
@@ -12,13 +12,13 @@
|
||||
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
"REVISION_NO": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
"REVISION_NO": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "axi_crc_dma_sim_1_axis_crc_0_0",
|
||||
"cell_name": "axi_crc_dma/axis_crc_0",
|
||||
"cell_name": "axis_crc_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_crc:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0",
|
||||
|
||||
+13
@@ -52,6 +52,7 @@
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in" } ],
|
||||
"RESETN": [ { "direction": "in" } ],
|
||||
"INTERRUPT": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"initial_value": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"polynomial": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"FIFO_NUM_FREE": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
@@ -331,6 +332,18 @@
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"INTERRUPT": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "INTERRUPT" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
|
||||
+32
-12
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.25",
|
||||
"Default View_TopLeft":"-146,-50",
|
||||
"Default View_ScaleFactor":"0.947325",
|
||||
"Default View_TopLeft":"333,-198",
|
||||
"Display-PortTypeOthers":"true",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_ExpandedHierarchyInLayout":"",
|
||||
@@ -19,16 +19,36 @@ pagesize -pg 1 -db -bbox -sgen 0 0 1990 480
|
||||
"Interfaces View_TopLeft":"-199,-369",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 620 -y 240 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 210 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 130 -defaultsOSRD
|
||||
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 850 -y 260 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 230 290 510 310 720J
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 220 300 520 320 730J
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 470 210n
|
||||
preplace netloc axi_crc_dma_M_AXI 1 3 1 N 240
|
||||
levelinfo -pg 1 0 110 350 620 850 940
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 940 340
|
||||
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 660 -y -60 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 360 -y 310 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 220 -defaultsOSRD
|
||||
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 2220 -y 340 -defaultsOSRD
|
||||
preplace inst axi_crc_dma|axis_fifo_0 -pg 1 -lvl 1 -x 790 -y 0 -defaultsOSRD
|
||||
preplace inst axi_crc_dma|axis_fifo_1 -pg 1 -lvl 3 -x 1450 -y 60 -defaultsOSRD
|
||||
preplace inst axi_crc_dma|axis_crc_0 -pg 1 -lvl 2 -x 1120 -y 300 -defaultsOSRD
|
||||
preplace inst axi_crc_dma|axis_dma_0 -pg 1 -lvl 4 -x 1800 -y 200 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 230 190 480 -140 2130J
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 220 390 500 420 2130J
|
||||
preplace netloc axi_crc_dma_INTERRUPT 1 1 3 240 430 NJ 430 2110
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 490 170n
|
||||
preplace netloc axi_crc_dma_M_AXI 1 3 1 2120 180n
|
||||
preplace netloc axi_crc_dma|CLK_1 1 0 4 630 180 950 180 1290 190 NJ
|
||||
preplace netloc axi_crc_dma|RESETN_1 1 0 4 640 160 960 160 1300 180 1610J
|
||||
preplace netloc axi_crc_dma|axis_fifo_0_S_NUM_FREE 1 1 3 980 -40 N -40 1620J
|
||||
preplace netloc axi_crc_dma|axis_fifo_1_M_NUM_AVAIL 1 3 1 1600 80n
|
||||
preplace netloc axi_crc_dma|axis_dma_0_INTERRUPT 1 4 1 N 200
|
||||
preplace netloc axi_crc_dma|axis_dma_0_initial_value 1 1 4 970 190 1280J 310 NJ 310 1980
|
||||
preplace netloc axi_crc_dma|axis_dma_0_polynomial 1 1 4 980 200 1260J 320 NJ 320 1970
|
||||
preplace netloc axi_crc_dma|Conn1 1 0 4 NJ 170 NJ 170 N 170 NJ
|
||||
preplace netloc axi_crc_dma|axis_dma_0_M_AXIS 1 0 5 640 -100 NJ -100 N -100 NJ -100 1970
|
||||
preplace netloc axi_crc_dma|axis_fifo_1_M_AXIS 1 3 1 1630 40n
|
||||
preplace netloc axi_crc_dma|Conn2 1 4 1 N 180
|
||||
preplace netloc axi_crc_dma|axis_fifo_0_M_AXIS 1 1 1 940 -20n
|
||||
preplace netloc axi_crc_dma|axis_crc_0_M_AXIS 1 2 1 1270 20n
|
||||
levelinfo -pg 1 0 110 360 660 2220 2310
|
||||
levelinfo -hier axi_crc_dma * 790 1120 1450 1800 *
|
||||
pagesize -pg 1 -db -bbox -sgen 0 -150 2340 690
|
||||
pagesize -hier axi_crc_dma -db -bbox -sgen 580 -110 2010 400
|
||||
"
|
||||
}
|
||||
{
|
||||
|
||||
@@ -7,8 +7,7 @@
|
||||
"name": "axis_crc_sim_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"2.0",
|
||||
"Default View_TopLeft":"187,103",
|
||||
"Default View_ScaleFactor":"1.25",
|
||||
"Default View_TopLeft":"-162,-36",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
|
||||
@@ -61,20 +61,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="85"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="151"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="32"/>
|
||||
<Option Name="WTModelSimExportSim" Val="32"/>
|
||||
<Option Name="WTQuestaExportSim" Val="32"/>
|
||||
<Option Name="WTXSimExportSim" Val="62"/>
|
||||
<Option Name="WTModelSimExportSim" Val="62"/>
|
||||
<Option Name="WTQuestaExportSim" Val="62"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="32"/>
|
||||
<Option Name="WTRivieraExportSim" Val="32"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="32"/>
|
||||
<Option Name="WTVcsExportSim" Val="62"/>
|
||||
<Option Name="WTRivieraExportSim" Val="62"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="62"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -110,9 +110,6 @@
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_axis_crc_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="axis_crc_sim_1.bd" FileRelPathName="ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xci">
|
||||
<Proxy FileSetName="axis_crc_sim_1_axis_master_simmodel_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -197,16 +194,14 @@
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../axis_crc_tb.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_crc_sim_1_wrapper"/>
|
||||
<Option Name="TopModule" Val="axis_crc_tb"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
@@ -276,12 +271,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="axis_crc_sim_1_axis_crc_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axis_crc_sim_1_axis_crc_0_0" RelGenDir="$PGENDIR/axis_crc_sim_1_axis_crc_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="axis_crc_sim_1_axis_crc_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -344,17 +333,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axis_crc_sim_1_axis_crc_0_0_synth_1" Type="Ft3:Synth" SrcSet="axis_crc_sim_1_axis_crc_0_0" Part="xc7z020clg400-1" ConstrsSet="axis_crc_sim_1_axis_crc_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_crc_sim_1_axis_crc_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_crc_sim_1_axis_crc_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
@@ -429,25 +407,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axis_crc_sim_1_axis_crc_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="axis_crc_sim_1_axis_crc_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axis_crc_sim_1_axis_crc_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/axis_crc_sim_1_axis_crc_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/axis_crc_sim_1_axis_crc_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
|
||||
@@ -3,14 +3,19 @@
|
||||
0000000000000000000000000000110000000001
|
||||
0011000000000000000000000000000000001111
|
||||
0000000000000000000000000001000000000001
|
||||
0000000000000000000000000001010000001111
|
||||
0000000000000000000000000011000100001111
|
||||
0000000000000000000000000001010000000001
|
||||
0000000000000000000000000011000100001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000100000000000000001000111100001111
|
||||
0000000000000000000000000000000000000110
|
||||
0000000000000000000000000110010000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000000000000000000000000000000100001111
|
||||
0000000000000000000000000001000000000001
|
||||
0000000000000000000000000000000000001111
|
||||
0000000000000000000000000001010000000001
|
||||
0000000000000000000000000000010100001111
|
||||
0000000000000000000000000001100000000001
|
||||
0000010011000001000111011011011100001111
|
||||
0000000000000000000000000001110000000001
|
||||
0000000000000000000000000000000000001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000100000000000000001000111100001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000000000000000
|
||||
|
||||
@@ -6,20 +6,23 @@
|
||||
<db_ref path="axi_crc_dma_sim_1_wrapper_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="axi_crc_dma_sim_1_wrapper" />
|
||||
<top_module name="glbl" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="1,340.490 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="1,821.479 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,505.039 ns"></Cursor1Time>
|
||||
<ZoomStartTime time="19,822.741 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="20,035.452 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="19,863.452 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="291"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="105"></ValueColumnWidth>
|
||||
<ValueColumnWidth column_width="85"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="8" />
|
||||
<WVObjectSize size="12" />
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/INTERRUPT" type="logic">
|
||||
<obj_property name="ElementShortName">INTERRUPT</obj_property>
|
||||
<obj_property name="ObjectShortName">INTERRUPT</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/S_AXIL" type="protoinst">
|
||||
<obj_property name="ElementShortName">S_AXIL</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIL</obj_property>
|
||||
@@ -80,10 +83,33 @@
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXI" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXI</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXI</obj_property>
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">0=blank 1=#D399FF 2=pink</obj_property>
|
||||
<obj_property name="EnumTransactionValueTable">0=blank;1=Read;2=Write;3=Read/Write</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">turquoise</obj_property>
|
||||
<obj_property name="Render_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXI.readWriteSummary</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<obj_property name="CellHeight">36</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXIS" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00E600</obj_property>
|
||||
<obj_property name="Render_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXIS.streamWaveData</obj_property>
|
||||
<obj_property name="Number_Overlay">2</obj_property>
|
||||
<obj_property name="Overlay_Object_0">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXIS.linkStarve</obj_property>
|
||||
<obj_property name="Overlay_Color_0">#99E600</obj_property>
|
||||
<obj_property name="Overlay_Object_1">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXIS.linkStall</obj_property>
|
||||
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
|
||||
<obj_property name="Detail_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/M_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/S_AXIS" type="protoinst">
|
||||
<obj_property name="ElementShortName">S_AXIS</obj_property>
|
||||
@@ -101,4 +127,55 @@
|
||||
<obj_property name="ElementShortName">write_state</obj_property>
|
||||
<obj_property name="ObjectShortName">write_state</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/FIFO_NUM_FREE" type="array">
|
||||
<obj_property name="ElementShortName">FIFO_NUM_FREE[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">FIFO_NUM_FREE[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_dma_0/FIFO_NUM_AVAIL" type="array">
|
||||
<obj_property name="ElementShortName">FIFO_NUM_AVAIL[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">FIFO_NUM_AVAIL[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="group3495" type="group">
|
||||
<obj_property name="label">axis_crc</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/S_AXIS" type="protoinst">
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00E600</obj_property>
|
||||
<obj_property name="Render_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/S_AXIS.streamWaveData</obj_property>
|
||||
<obj_property name="Number_Overlay">2</obj_property>
|
||||
<obj_property name="Overlay_Object_0">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/S_AXIS.linkStarve</obj_property>
|
||||
<obj_property name="Overlay_Color_0">#99E600</obj_property>
|
||||
<obj_property name="Overlay_Object_1">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/S_AXIS.linkStall</obj_property>
|
||||
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
|
||||
<obj_property name="Detail_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/S_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="ElementShortName">S_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/M_AXIS" type="protoinst">
|
||||
<obj_property name="children_use_element_short_name">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
|
||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="CustomSignalColor">#00E600</obj_property>
|
||||
<obj_property name="Render_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/M_AXIS.streamWaveData</obj_property>
|
||||
<obj_property name="Number_Overlay">2</obj_property>
|
||||
<obj_property name="Overlay_Object_0">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/M_AXIS.linkStarve</obj_property>
|
||||
<obj_property name="Overlay_Color_0">#99E600</obj_property>
|
||||
<obj_property name="Overlay_Object_1">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/M_AXIS.linkStall</obj_property>
|
||||
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
|
||||
<obj_property name="Detail_Data">/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/M_AXIS.streamTooltipData</obj_property>
|
||||
<obj_property name="ElementShortName">M_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/axi_crc_dma_sim_1_wrapper/axi_crc_dma_sim_1_i/axi_crc_dma/axis_crc_0/U0/state" type="other">
|
||||
<obj_property name="ElementShortName">state</obj_property>
|
||||
<obj_property name="ObjectShortName">state</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
||||
@@ -60,6 +60,7 @@ begin
|
||||
|
||||
process(CLK)
|
||||
variable burst_count : integer range 0 to MAX_BURSTLEN := 0;
|
||||
variable dummy_data : unsigned(31 downto 0) := (others=>'0');
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESETN = '0' then
|
||||
@@ -91,7 +92,8 @@ begin
|
||||
-- READ RESPONSE Phase
|
||||
when READ_RESP =>
|
||||
S_AXI_RVALID <= '1';
|
||||
S_AXI_RDATA <= std_logic_vector(to_unsigned(burst_count, DWIDTH)); -- Dummy Daten
|
||||
S_AXI_RDATA <= std_logic_vector(dummy_data); -- Dummy Daten
|
||||
dummy_data := dummy_data + 1;
|
||||
S_AXI_RRESP <= "00"; -- OKAY response
|
||||
|
||||
if S_AXI_RREADY = '1' then
|
||||
|
||||
+29
-23
@@ -27,18 +27,19 @@ end entity;
|
||||
|
||||
architecture rtl of axis_crc is
|
||||
|
||||
type state_t is (IDLE, SECOND_HALF, CHECKSUM);
|
||||
type state_t is (IDLE, SECOND_HALF, PROVIDE_DATA, CHECKSUM);
|
||||
signal state : state_t := IDLE;
|
||||
|
||||
signal crc_sig : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
process
|
||||
-- fuer CRC-Berechnung
|
||||
variable CRC : std_logic_vector(31 downto 0);
|
||||
variable MSB : std_logic;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
variable CRC : std_logic_vector(31 downto 0);
|
||||
variable MSB : std_logic;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
|
||||
variable last : std_logic;
|
||||
variable last : std_logic;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
@@ -46,20 +47,17 @@ begin
|
||||
state <= IDLE;
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TVALID <= '0';
|
||||
CRC := initial_value;
|
||||
M_AXIS_TLAST <= '0';
|
||||
crc_sig <= initial_value;
|
||||
|
||||
else
|
||||
if M_AXIS_TREADY = '1' then
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TLAST <= '0';
|
||||
end if;
|
||||
|
||||
case state is
|
||||
when IDLE =>
|
||||
if S_AXIS_TVALID = '1' then
|
||||
data := S_AXIS_TDATA;
|
||||
last := S_AXIS_TLAST;
|
||||
|
||||
CRC := crc_sig;
|
||||
-- obere 16 Bit in die CRC Summe reinrechnen
|
||||
for i in 31 downto 16 loop
|
||||
-- Pruefen ob MSB gesetzt ist
|
||||
@@ -88,26 +86,34 @@ begin
|
||||
CRC := CRC XOR polynomial;
|
||||
end if;
|
||||
end loop;
|
||||
crc_sig <= CRC;
|
||||
|
||||
-- Daten an M_AXIS ausgeben
|
||||
M_AXIS_TVALID <= '1';
|
||||
M_AXIS_TDATA <= data;
|
||||
|
||||
if last = '1' then
|
||||
state <= CHECKSUM;
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
state <= IDLE;
|
||||
state <= PROVIDE_DATA;
|
||||
|
||||
when PROVIDE_DATA =>
|
||||
if M_AXIS_TREADY = '1' then
|
||||
if last = '1' then
|
||||
M_AXIS_TLAST <= '1';
|
||||
M_AXIS_TDATA <= crc_sig;
|
||||
state <= CHECKSUM;
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TVALID <= '0';
|
||||
state <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when CHECKSUM =>
|
||||
-- CRC Pruefsumme ausgeben
|
||||
M_AXIS_TVALID <= '1';
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TLAST <= '1';
|
||||
M_AXIS_TDATA <= CRC;
|
||||
if M_AXIS_TREADY = '1' then
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TLAST <= '0';
|
||||
|
||||
state <= IDLE;
|
||||
state <= IDLE;
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
@@ -0,0 +1,78 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axis_crc is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic;
|
||||
|
||||
-- for crc calculation
|
||||
initial_value : in std_logic_vector(31 downto 0);
|
||||
polynomial : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(16 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(16 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture rtl of axis_audio_filter3 is
|
||||
signal m_valid_sig : std_logic := '0';
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
|
||||
|
||||
process
|
||||
-- fuer CRC-Berechnung
|
||||
variable CRC : std_logic_vector(31 downto 0);
|
||||
variable MSB : std_logic;
|
||||
variable data : std_logic_vector(31 downto 0);
|
||||
|
||||
variable last : std_logic;
|
||||
begin
|
||||
wait until rising_edge(AXIS_ACLK);
|
||||
if RESETN = '0' then
|
||||
CRC := initial_value;
|
||||
else
|
||||
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
|
||||
if HAS_LAST then
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
end if;
|
||||
|
||||
m_valid_sig <= S_AXIS_TVALID;
|
||||
|
||||
if S_AXIS_TVALID = '1' then
|
||||
-- 16 Bit in die CRC Summe reinrechnen
|
||||
for i in 31 downto 16 loop
|
||||
-- Pruefen ob MSB gesetzt ist
|
||||
MSB := CRC(CRC'length-1);
|
||||
-- neues Bit reinschieben
|
||||
CRC := CRC(CRC'length-2 downto 0) & data(i);
|
||||
-- XOR Verknuepfung
|
||||
if MSB = '1' then
|
||||
CRC := CRC XOR polynomial;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
S_AXIS_TREADY <= '0';
|
||||
state <= SECOND_HALF;
|
||||
end if;
|
||||
|
||||
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end;
|
||||
+116
-21
@@ -15,6 +15,8 @@ entity axis_dma is
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic;
|
||||
|
||||
INTERRUPT : out std_logic := '0';
|
||||
|
||||
-- for crc calulaction
|
||||
initial_value : out std_logic_vector(31 downto 0);
|
||||
polynomial : out std_logic_vector(31 downto 0);
|
||||
@@ -111,20 +113,20 @@ architecture rtl of axis_dma is
|
||||
signal control_state : control_state_t := IDLE;
|
||||
|
||||
-- M_AXI Read Data state machine
|
||||
type read_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT, WAIT_BURST_FINISHED);
|
||||
type read_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT, READ_DATA, FINISHED);
|
||||
signal read_state : read_state_t := IDLE;
|
||||
|
||||
-- M_AXI Write Data state machine
|
||||
type write_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT, WAIT_BURST_FINISHED);
|
||||
type write_state_t is (IDLE, REQ, WAIT_REQ_ACCEPT, WRITE_DATA);
|
||||
signal write_state : write_state_t := IDLE;
|
||||
|
||||
-- control signals
|
||||
signal packets_cnt : unsigned(15 downto 0);
|
||||
signal data_cnt : unsigned(31 downto 0);
|
||||
signal read_addr : unsigned(31 downto 0);
|
||||
signal write_addr : unsigned(31 downto 0);
|
||||
signal read_addr_cnt : unsigned(31 downto 0);
|
||||
signal write_addr_cnt : unsigned(31 downto 0);
|
||||
signal interrupt_reset : std_logic;
|
||||
|
||||
signal packet_last_word : std_logic := '0';
|
||||
begin
|
||||
|
||||
-------------------------------------------
|
||||
@@ -136,6 +138,9 @@ begin
|
||||
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
|
||||
polynomial <= polynomial_reg;
|
||||
initial_value <= initial_value_reg;
|
||||
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
@@ -191,6 +196,9 @@ begin
|
||||
S_AXIL_BVALID <= '0';
|
||||
end if;
|
||||
|
||||
run_reg <= '0';
|
||||
interrupt_reset <= '0';
|
||||
|
||||
if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
|
||||
S_AXIL_BVALID <= '1';
|
||||
|
||||
@@ -202,9 +210,7 @@ begin
|
||||
end if;
|
||||
elsif S_AXIL_AWADDR = x"04" then
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
if S_AXIL_WDATA(0) = '0' then
|
||||
interrupt_reset <= '1';
|
||||
end if;
|
||||
interrupt_reset <= S_AXIL_WDATA(0);
|
||||
end if;
|
||||
elsif S_AXIL_AWADDR = x"08" then
|
||||
if S_AXIL_WSTRB = "1111" then
|
||||
@@ -249,11 +255,11 @@ begin
|
||||
case control_state is
|
||||
when IDLE =>
|
||||
if run_reg = '1' then
|
||||
packets_cnt <= unsigned(packet_number_reg);
|
||||
data_cnt <= unsigned(packet_size_reg) * unsigned(packet_number_reg);
|
||||
read_addr <= unsigned(read_address_reg);
|
||||
write_addr <= unsigned(write_address_reg);
|
||||
control_state <= RUN;
|
||||
-- packets_cnt <= unsigned(packet_number_reg);
|
||||
-- data_cnt <= unsigned(packet_size_reg) * unsigned(packet_number_reg);
|
||||
-- read_addr_cnt <= unsigned(read_address_reg);
|
||||
write_addr_cnt <= unsigned(write_address_reg);
|
||||
control_state <= RUN;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
@@ -272,22 +278,118 @@ begin
|
||||
M_AXI_RREADY <= '1';
|
||||
|
||||
process
|
||||
variable packets_cnt : unsigned(15 downto 0); -- Anzahl der verbleibenden Pakete Minus 1
|
||||
variable packet_data_cnt : unsigned(15 downto 0); -- Anzahl der verbleibenden Worte Minus 1 beim aktuellen Packet
|
||||
variable data_cnt : unsigned(31 downto 0); -- Anzahl der insgesamt verbleibenden Worte Minus 1
|
||||
variable read_addr_cnt : unsigned(31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if RESETN = '0' then
|
||||
read_state <= IDLE;
|
||||
packets_cnt := (others=>'0');
|
||||
data_cnt := (others=>'0');
|
||||
read_addr_cnt := (others=>'0');
|
||||
|
||||
M_AXI_ARVALID <= '0';
|
||||
M_AXI_ARADDR <= (others=>'0');
|
||||
M_AXI_ARLEN <= (others=>'0');
|
||||
|
||||
read_state <= IDLE;
|
||||
else
|
||||
case read_state is
|
||||
when IDLE =>
|
||||
if run_reg = '1' then
|
||||
packets_cnt := unsigned(packet_number_reg);
|
||||
packet_data_cnt := unsigned(packet_size_reg);
|
||||
data_cnt := (unsigned(packet_size_reg)+1) * (unsigned(packet_number_reg)+1) - 1;
|
||||
read_addr_cnt := unsigned(read_address_reg);
|
||||
read_state <= REQ;
|
||||
end if;
|
||||
|
||||
when REQ =>
|
||||
if (unsigned(FIFO_NUM_FREE) >= MAX_BURSTLEN) then
|
||||
M_AXI_ARADDR <= std_logic_vector(read_addr_cnt);
|
||||
M_AXI_ARVALID <= '1';
|
||||
|
||||
-- set burst length
|
||||
if data_cnt >= MAX_BURSTLEN then
|
||||
M_AXI_ARLEN <= std_logic_vector(to_unsigned(MAX_BURSTLEN-1, 4));
|
||||
read_addr_cnt := read_addr_cnt + to_unsigned(MAX_BURSTLEN, 32); -- increment address
|
||||
else
|
||||
M_AXI_ARLEN <= std_logic_vector(data_cnt(3 downto 0));
|
||||
end if;
|
||||
|
||||
read_state <= WAIT_REQ_ACCEPT;
|
||||
end if;
|
||||
|
||||
when WAIT_REQ_ACCEPT =>
|
||||
if M_AXI_ARREADY = '1' then
|
||||
M_AXI_ARVALID <= '0';
|
||||
|
||||
if packet_data_cnt = 0 then
|
||||
packet_last_word <= '1';
|
||||
end if;
|
||||
|
||||
read_state <= READ_DATA;
|
||||
end if;
|
||||
|
||||
when READ_DATA =>
|
||||
if M_AXI_RVALID = '1' then
|
||||
if packet_data_cnt = 1 then
|
||||
packet_last_word <= '1';
|
||||
end if;
|
||||
|
||||
if packet_data_cnt = 0 then
|
||||
packet_last_word <= '0';
|
||||
if packets_cnt = 0 then
|
||||
|
||||
else
|
||||
packets_cnt := packets_cnt - 1;
|
||||
packet_data_cnt := unsigned(packet_size_reg);
|
||||
end if;
|
||||
else
|
||||
packet_data_cnt := packet_data_cnt - 1;
|
||||
end if;
|
||||
|
||||
if M_AXI_RLAST = '1' then
|
||||
packet_last_word <= '0';
|
||||
if data_cnt = 0 then
|
||||
if interrupt_enable_reg = '1' then
|
||||
read_state <= FINISHED;
|
||||
else
|
||||
read_state <= IDLE;
|
||||
end if;
|
||||
else
|
||||
read_state <= REQ;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
data_cnt := data_cnt - 1;
|
||||
end if;
|
||||
|
||||
when FINISHED =>
|
||||
INTERRUPT <= '1';
|
||||
|
||||
if interrupt_reset = '1' then
|
||||
INTERRUPT <= '0';
|
||||
read_state <= IDLE;
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- M_AXIS und S_AXIS Interface connections
|
||||
-------------------------------------------
|
||||
|
||||
M_AXIS_TVALID <= M_AXI_RVALID;
|
||||
M_AXIS_TDATA <= M_AXI_RDATA;
|
||||
M_AXIS_TLAST <= M_AXI_RVALID and packet_last_word;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- M_AXI Write data to DRAM state machine
|
||||
-------------------------------------------
|
||||
@@ -315,11 +417,4 @@ begin
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-------------------------------------------
|
||||
-- M_AXIS und S_AXIS Interface connections
|
||||
-------------------------------------------
|
||||
|
||||
|
||||
end architecture;
|
||||
@@ -3,14 +3,19 @@
|
||||
0000000000000000000000000000110000000001
|
||||
0011000000000000000000000000000000001111
|
||||
0000000000000000000000000001000000000001
|
||||
0000000000000000000000000001010000001111
|
||||
0000000000000000000000000011000100001111
|
||||
0000000000000000000000000001010000000001
|
||||
0000000000000000000000000011000100001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000100000000000000001000111100001111
|
||||
0000000000000000000000000000000000000110
|
||||
0000000000000000000000000110010000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000000000000000000000000000000100001111
|
||||
0000000000000000000000000001000000000001
|
||||
0000000000000000000000000000000000001111
|
||||
0000000000000000000000000001010000000001
|
||||
0000000000000000000000000000010100001111
|
||||
0000000000000000000000000001100000000001
|
||||
0000010011000001000111011011011100001111
|
||||
0000000000000000000000000001110000000001
|
||||
0000000000000000000000000000000000001111
|
||||
0000000000000000000000000000000000000001
|
||||
0000000100000000000000001000111100001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000000000000000
|
||||
|
||||
@@ -1,8 +1,11 @@
|
||||
wal 0x08 0x20000000
|
||||
wal 0x0C 0x30000000
|
||||
wal 0x10 20
|
||||
wal 0x14 5
|
||||
wal 0x18 0x04C11DB7
|
||||
wal 0x1c 00000000
|
||||
wal 0x10 49
|
||||
wal 0x14 49
|
||||
wal 0 0x0100008F
|
||||
wfi
|
||||
slp 100
|
||||
wal 0x04 1
|
||||
wal 0x10 0
|
||||
wal 0x14 0
|
||||
wal 0 0x0100008F
|
||||
slp 375000000
|
||||
|
||||
Reference in New Issue
Block a user