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axis_dma angefangen

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This commit is contained in:
Matthias Biermann
2025-02-02 01:01:23 +01:00
parent 027c4dd5ba
commit 0f8be1a934
115 changed files with 9703 additions and 18041 deletions
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Hardware/CRC.vhd
-63
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@@ -1,63 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity crc is
generic (
CRC_WIDTH : positive;
DWIDTH : positive
);
port (
clk : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
initial_value : in std_logic_vector(CRC_WIDTH-1 downto 0);
polynomial : in std_logic_vector(CRC_WIDTH-1 downto 0);
-- Datensignale
data : in std_logic_vector(DWIDTH-1 downto 0);
checksum : out std_logic_vector(CRC_WIDTH-1 downto 0)
);
end crc;
architecture rtl of crc is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(CRC_WIDTH-1 downto 0);
signal nextChecksum : std_logic_vector(CRC_WIDTH-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (data, checksum_i)
variable mix: std_logic_vector(CRC_WIDTH-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in data'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & data(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
checksum_i <= initial_value;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end architecture;
Hardware/aci_crc_dma/.gitignore
+4 -1
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@@ -86,4 +86,7 @@
vivado_pid*.str
# DO NOT ignore images as bitmap files
!*.bmp
!*.bmp
# do not ignore stimuli file for axil_master_with_rom IP
!*.stm
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bxml
+50 -5
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@@ -2,10 +2,55 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738434920"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1738434920"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738434920"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738434920"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738454412"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738454413"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738454412"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738454413"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\axi_crc_dma_sim_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axi_crc_dma_sim_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axi_crc_dma_sim_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\axi_crc_dma_sim_1.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axi_crc_dma_sim_1.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\axi_crc_dma_sim_1.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axi_crc_dma_sim_1.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1_ooc.xdc
+10
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@@ -0,0 +1,10 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
################################################################################
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/hdl/axis_master_test_wrapper.vhd → Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/hdl/axi_crc_dma_sim_1_wrapper.vhd
+9 -9
View File
@@ -2,23 +2,23 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sat Feb 1 17:34:52 2025
--Date : Sun Feb 2 01:00:12 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axis_master_test_wrapper.bd
--Design : axis_master_test_wrapper
--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
--Design : axi_crc_dma_sim_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axis_master_test_wrapper is
end axis_master_test_wrapper;
entity axi_crc_dma_sim_1_wrapper is
end axi_crc_dma_sim_1_wrapper;
architecture STRUCTURE of axis_master_test_wrapper is
component axis_master_test is
end component axis_master_test;
architecture STRUCTURE of axi_crc_dma_sim_1_wrapper is
component axi_crc_dma_sim_1 is
end component axi_crc_dma_sim_1;
begin
axis_master_test_i: component axis_master_test
axi_crc_dma_sim_1_i: component axi_crc_dma_sim_1
;
end STRUCTURE;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xml
+1256
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File diff suppressed because it is too large Load Diff
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/sim/axi_crc_dma_sim_1_axi3_slave_verif_0_0.vhd
+204
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@@ -0,0 +1,204 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axi3_slave_verif:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_sim_1_axi3_slave_verif_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END axi_crc_dma_sim_1_axi3_slave_verif_0_0;
ARCHITECTURE axi_crc_dma_sim_1_axi3_slave_verif_0_0_arch OF axi_crc_dma_sim_1_axi3_slave_verif_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axi3_slave_verif_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi3_slave_verif IS
GENERIC (
DWIDTH : INTEGER;
IDWIDTH : INTEGER;
MAX_BURSTLEN : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi3_slave_verif;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXI_ARVALID: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS" &
"_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
BEGIN
U0 : axi3_slave_verif
GENERIC MAP (
DWIDTH => 32,
IDWIDTH => 1,
MAX_BURSTLEN => 16
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARID => S_AXI_ARID,
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RID => S_AXI_RID,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WLAST => S_AXI_WLAST,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BRESP => S_AXI_BRESP
);
END axi_crc_dma_sim_1_axi3_slave_verif_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xml
+90 -27
View File
@@ -187,7 +187,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIL.FREQ_HZ">100000000</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIL.FREQ_HZ"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -565,6 +565,47 @@
</spirit:addressSpace>
</spirit:addressSpaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axil_master_with_rom</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:8286588d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axi_crc_dma_sim_1_axil_master_with_rom_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:8286588d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>interrupt_in</spirit:name>
@@ -573,7 +614,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -595,7 +636,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -614,7 +655,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -626,7 +667,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -641,7 +682,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -656,7 +697,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -672,7 +713,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -688,7 +729,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -700,7 +741,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -712,7 +753,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -731,7 +772,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -750,7 +791,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -765,7 +806,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -780,7 +821,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -796,7 +837,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -812,7 +853,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -824,7 +865,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -839,7 +880,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -855,7 +896,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -871,7 +912,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -883,7 +924,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -895,7 +936,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -914,7 +955,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -927,7 +968,7 @@
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
<spirit:name>STIM_FILENAME</spirit:name>
<spirit:displayName>Stim Filename</spirit:displayName>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STIM_FILENAME">../../stimuli.mem</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.STIM_FILENAME">../../axi_crc_dma_sim.mem</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>HAS_FINISHED_OUT</spirit:name>
@@ -953,12 +994,33 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/85f6/sources_1/new/axilm_rom.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/85f6/sources_1/new/axil_master_with_rom.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axil_master_with_rom</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>STIM_FILENAME</spirit:name>
<spirit:displayName>Stim Filename</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STIM_FILENAME">../../stimuli.mem</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STIM_FILENAME">../../axi_crc_dma_sim.mem</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
@@ -992,7 +1054,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.FREQ_HZ" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -1024,6 +1086,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIL_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.STIM_FILENAME" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/sim/axi_crc_dma_sim_1_axil_master_with_rom_0_0.vhd
+178
View File
@@ -0,0 +1,178 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:axil_master_with_rom:1.0
-- IP Revision: 19
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_sim_1_axil_master_with_rom_0_0 IS
PORT (
interrupt_in : IN STD_LOGIC;
M_AXIL_ACLK : IN STD_LOGIC;
M_AXIL_ARESETN : IN STD_LOGIC;
M_AXIL_ARREADY : IN STD_LOGIC;
M_AXIL_ARVALID : OUT STD_LOGIC;
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_RREADY : OUT STD_LOGIC;
M_AXIL_RVALID : IN STD_LOGIC;
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXIL_AWREADY : IN STD_LOGIC;
M_AXIL_AWVALID : OUT STD_LOGIC;
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_WREADY : IN STD_LOGIC;
M_AXIL_WVALID : OUT STD_LOGIC;
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIL_BREADY : OUT STD_LOGIC;
M_AXIL_BVALID : IN STD_LOGIC;
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END axi_crc_dma_sim_1_axil_master_with_rom_0_0;
ARCHITECTURE axi_crc_dma_sim_1_axil_master_with_rom_0_0_arch OF axi_crc_dma_sim_1_axil_master_with_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axil_master_with_rom IS
GENERIC (
STIM_FILENAME : STRING;
HAS_FINISHED_OUT : BOOLEAN;
HAS_INTERRUPT_IN : BOOLEAN;
REVISION_NO : INTEGER
);
PORT (
interrupt_in : IN STD_LOGIC;
finished_o : OUT STD_LOGIC;
M_AXIL_ACLK : IN STD_LOGIC;
M_AXIL_ARESETN : IN STD_LOGIC;
M_AXIL_ARREADY : IN STD_LOGIC;
M_AXIL_ARVALID : OUT STD_LOGIC;
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_RREADY : OUT STD_LOGIC;
M_AXIL_RVALID : IN STD_LOGIC;
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXIL_AWREADY : IN STD_LOGIC;
M_AXIL_AWVALID : OUT STD_LOGIC;
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_WREADY : IN STD_LOGIC;
M_AXIL_WVALID : OUT STD_LOGIC;
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIL_BREADY : OUT STD_LOGIC;
M_AXIL_BVALID : IN STD_LOGIC;
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axil_master_with_rom;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
"SERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
BEGIN
U0 : axil_master_with_rom
GENERIC MAP (
STIM_FILENAME => "../../axi_crc_dma_sim.mem",
HAS_FINISHED_OUT => false,
HAS_INTERRUPT_IN => true,
REVISION_NO => 1
)
PORT MAP (
interrupt_in => interrupt_in,
M_AXIL_ACLK => M_AXIL_ACLK,
M_AXIL_ARESETN => M_AXIL_ARESETN,
M_AXIL_ARREADY => M_AXIL_ARREADY,
M_AXIL_ARVALID => M_AXIL_ARVALID,
M_AXIL_ARADDR => M_AXIL_ARADDR,
M_AXIL_ARPROT => M_AXIL_ARPROT,
M_AXIL_RREADY => M_AXIL_RREADY,
M_AXIL_RVALID => M_AXIL_RVALID,
M_AXIL_RDATA => M_AXIL_RDATA,
M_AXIL_RRESP => M_AXIL_RRESP,
M_AXIL_AWREADY => M_AXIL_AWREADY,
M_AXIL_AWVALID => M_AXIL_AWVALID,
M_AXIL_AWADDR => M_AXIL_AWADDR,
M_AXIL_AWPROT => M_AXIL_AWPROT,
M_AXIL_WREADY => M_AXIL_WREADY,
M_AXIL_WVALID => M_AXIL_WVALID,
M_AXIL_WDATA => M_AXIL_WDATA,
M_AXIL_WSTRB => M_AXIL_WSTRB,
M_AXIL_BREADY => M_AXIL_BREADY,
M_AXIL_BVALID => M_AXIL_BVALID,
M_AXIL_BRESP => M_AXIL_BRESP
);
END axi_crc_dma_sim_1_axil_master_with_rom_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xml
+56 -12
View File
@@ -436,6 +436,40 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_crc</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f02b2d15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axi_crc_dma_sim_1_axis_crc_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f02b2d15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CLK</spirit:name>
@@ -444,7 +478,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -456,7 +490,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -472,7 +506,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -488,7 +522,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -500,7 +534,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -516,7 +550,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -531,7 +565,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -546,7 +580,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -558,7 +592,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -574,7 +608,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -586,7 +620,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -598,7 +632,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -615,6 +649,16 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/sim/test_1_axis_crc_0_0.vhd → Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/sim/axi_crc_dma_sim_1_axis_crc_0_0.vhd
+8 -8
View File
@@ -53,7 +53,7 @@ LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test_1_axis_crc_0_0 IS
ENTITY axi_crc_dma_sim_1_axis_crc_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
@@ -68,11 +68,11 @@ ENTITY test_1_axis_crc_0_0 IS
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END test_1_axis_crc_0_0;
END axi_crc_dma_sim_1_axis_crc_0_0;
ARCHITECTURE test_1_axis_crc_0_0_arch OF test_1_axis_crc_0_0 IS
ARCHITECTURE axi_crc_dma_sim_1_axis_crc_0_0_arch OF axi_crc_dma_sim_1_axis_crc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF test_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_crc IS
PORT (
CLK : IN STD_LOGIC;
@@ -91,19 +91,19 @@ ARCHITECTURE test_1_axis_crc_0_0_arch OF test_1_axis_crc_0_0 IS
END COMPONENT axis_crc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_crc
@@ -121,4 +121,4 @@ BEGIN
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
END test_1_axis_crc_0_0_arch;
END axi_crc_dma_sim_1_axis_crc_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xml
+205 -99
View File
@@ -1448,6 +1448,40 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_dma</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e65ec1c3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axi_crc_dma_sim_1_axis_dma_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:43 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e65ec1c3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CLK</spirit:name>
@@ -1456,7 +1490,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1468,7 +1502,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1484,7 +1518,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1500,7 +1534,39 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>FIFO_NUM_FREE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>FIFO_NUM_AVAIL</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1516,7 +1582,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1531,7 +1597,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1546,7 +1612,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1562,7 +1628,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1577,7 +1643,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1592,7 +1658,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1608,7 +1674,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1623,7 +1689,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1635,7 +1701,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1654,7 +1720,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1670,7 +1736,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1685,7 +1751,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1700,7 +1766,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1716,7 +1782,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1728,7 +1794,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1740,7 +1806,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1759,7 +1825,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1771,7 +1837,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1786,7 +1852,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1805,7 +1871,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1821,7 +1887,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1837,7 +1903,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1853,7 +1919,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1869,7 +1935,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1885,7 +1951,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1901,7 +1967,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1913,7 +1979,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1925,7 +1991,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1944,7 +2010,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1963,7 +2029,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1982,7 +2048,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1997,7 +2063,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2012,7 +2078,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2027,7 +2093,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2046,7 +2112,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2062,7 +2128,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2078,7 +2144,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2094,7 +2160,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2110,7 +2176,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2126,7 +2192,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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@@ -2142,7 +2208,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2154,7 +2220,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2169,7 +2235,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2188,7 +2254,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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@@ -2204,7 +2270,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2216,7 +2282,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2232,7 +2298,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2244,7 +2310,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2256,7 +2322,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2275,7 +2341,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -2294,7 +2360,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2309,7 +2375,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2325,7 +2391,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2340,7 +2406,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2355,7 +2421,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2367,7 +2433,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2383,7 +2449,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2395,7 +2461,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -2407,7 +2473,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -2432,6 +2498,21 @@
<spirit:displayName>Max Burstlen</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH" spirit:minimum="0" spirit:rangeType="long">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>polynomial_default</spirit:name>
<spirit:displayName>Polynomial Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.polynomial_default" spirit:bitStringLength="32">0x04C11DB7</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>initial_value_default</spirit:name>
<spirit:displayName>Initial Value Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.initial_value_default" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
@@ -2441,6 +2522,16 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axis_dma:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -2458,6 +2549,21 @@
<spirit:displayName>Max Burstlen</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:minimum="0" spirit:rangeType="long">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>polynomial_default</spirit:name>
<spirit:displayName>Polynomial Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.polynomial_default" spirit:bitStringLength="32">0x04C11DB7</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>initial_value_default</spirit:name>
<spirit:displayName>Initial Value Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.initial_value_default" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_crc_dma_sim_1_axis_dma_0_0</spirit:value>
@@ -2476,22 +2582,22 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
@@ -2499,13 +2605,13 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -2519,36 +2625,36 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/sim/axi_crc_dma_sim_1_axis_dma_0_0.vhd
+354
View File
@@ -0,0 +1,354 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_sim_1_axis_dma_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_RREADY : OUT STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END axi_crc_dma_sim_1_axis_dma_0_0;
ARCHITECTURE axi_crc_dma_sim_1_axis_dma_0_0_arch OF axi_crc_dma_sim_1_axis_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_dma IS
GENERIC (
DWIDTH : INTEGER;
IDWIDTH : INTEGER;
MAX_BURSTLEN : INTEGER;
FIFO_AWIDTH : INTEGER;
polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0);
initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_RREADY : OUT STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS" &
"_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
"ITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_dma
GENERIC MAP (
DWIDTH => 32,
IDWIDTH => 1,
MAX_BURSTLEN => 16,
FIFO_AWIDTH => 8,
polynomial_default => X"04C11DB7",
initial_value_default => X"00000000"
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
initial_value => initial_value,
polynomial => polynomial,
FIFO_NUM_FREE => FIFO_NUM_FREE,
FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
S_AXIL_AWADDR => S_AXIL_AWADDR,
S_AXIL_AWVALID => S_AXIL_AWVALID,
S_AXIL_AWREADY => S_AXIL_AWREADY,
S_AXIL_WDATA => S_AXIL_WDATA,
S_AXIL_WVALID => S_AXIL_WVALID,
S_AXIL_WREADY => S_AXIL_WREADY,
S_AXIL_WSTRB => S_AXIL_WSTRB,
S_AXIL_BVALID => S_AXIL_BVALID,
S_AXIL_BREADY => S_AXIL_BREADY,
S_AXIL_BRESP => S_AXIL_BRESP,
S_AXIL_ARADDR => S_AXIL_ARADDR,
S_AXIL_ARVALID => S_AXIL_ARVALID,
S_AXIL_ARREADY => S_AXIL_ARREADY,
S_AXIL_RDATA => S_AXIL_RDATA,
S_AXIL_RVALID => S_AXIL_RVALID,
S_AXIL_RREADY => S_AXIL_RREADY,
S_AXIL_RRESP => S_AXIL_RRESP,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_RREADY => M_AXI_RREADY,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RID => M_AXI_RID,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WID => M_AXI_WID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BID => M_AXI_BID,
M_AXI_BRESP => M_AXI_BRESP,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
END axi_crc_dma_sim_1_axis_dma_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xml
-721
View File
@@ -1,721 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>axi_crc_dma_sim_1_axis_downsizer_0_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>M_AXIS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TUSER</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>TDATA_NUM_BYTES</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TDEST_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TREADY</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TKEEP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TLAST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S_AXIS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TUSER</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>TDATA_NUM_BYTES</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TDEST_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TREADY</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
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<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
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<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
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<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
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<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
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<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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<spirit:port>
<spirit:name>AXIS_ACLK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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</spirit:port>
<spirit:port>
<spirit:name>AXIS_ARESETN</spirit:name>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TVALID</spirit:name>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TDATA</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.WIDTH_OUT&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.SIZE_FACTOR&apos;))) - 1)">31</spirit:left>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TLAST</spirit:name>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
<spirit:name>S_AXIS_TREADY</spirit:name>
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<spirit:port>
<spirit:name>S_AXIS_TUSER</spirit:name>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
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<spirit:port>
<spirit:name>M_AXIS_TVALID</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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</spirit:wire>
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<spirit:port>
<spirit:name>M_AXIS_TDATA</spirit:name>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.WIDTH_OUT&apos;)) - 1)">15</spirit:left>
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<spirit:name>M_AXIS_TREADY</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIZE_FACTOR">2</spirit:value>
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<spirit:name>BIG_ENDIAN</spirit:name>
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<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_crc_dma_sim_1_axis_downsizer_0_0</spirit:value>
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xml
+115 -39
View File
@@ -1134,6 +1134,48 @@
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@@ -1142,7 +1184,7 @@
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1164,7 +1206,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1190,7 +1232,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1212,7 +1254,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1238,7 +1280,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1264,7 +1306,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1286,7 +1328,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1308,7 +1350,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1334,7 +1376,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1356,7 +1398,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1378,7 +1420,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1400,7 +1442,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1423,7 +1465,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1446,7 +1488,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1465,7 +1507,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1484,7 +1526,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1507,7 +1549,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1526,7 +1568,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1545,7 +1587,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1564,7 +1606,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1576,7 +1618,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1588,7 +1630,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1604,7 +1646,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1616,7 +1658,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1628,7 +1670,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1644,7 +1686,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1654,13 +1696,13 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">10</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1672,7 +1714,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1684,7 +1726,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1696,7 +1738,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1712,7 +1754,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1724,7 +1766,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1736,7 +1778,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1752,7 +1794,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1762,13 +1804,13 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">10</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1788,7 +1830,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH">11</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FIFO_DWIDTH</spirit:name>
@@ -1809,6 +1851,39 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/91a4/dmem_dp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/91a4/bmem_dp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/91a4/generic_fifo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/91a4/axis_fifo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_sim_1_axis_fifo_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_fifo_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -1824,7 +1899,7 @@
<spirit:parameter>
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:order="1300" spirit:configGroups="0 UnGrouped radioGroup" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">11</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:order="1300" spirit:configGroups="0 UnGrouped radioGroup" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FIFO_USE_BLOCKRAM</spirit:name>
@@ -1892,6 +1967,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_AWIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/sim/axi_crc_dma_sim_1_axis_fifo_0_0.vhd
+186
View File
@@ -0,0 +1,186 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: Gehrke:user:axis_fifo:1.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_sim_1_axis_fifo_0_0 IS
PORT (
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END axi_crc_dma_sim_1_axis_fifo_0_0;
ARCHITECTURE axi_crc_dma_sim_1_axis_fifo_0_0_arch OF axi_crc_dma_sim_1_axis_fifo_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_fifo_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_fifo IS
GENERIC (
FIFO_HAS_AXIL_IF : BOOLEAN;
FIFO_USE_BLOCKRAM : BOOLEAN;
FIFO_AWIDTH : INTEGER;
FIFO_DWIDTH : INTEGER;
FIFO_TUSERWIDTH : INTEGER
);
PORT (
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axis_fifo;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_fifo
GENERIC MAP (
FIFO_HAS_AXIL_IF => false,
FIFO_USE_BLOCKRAM => true,
FIFO_AWIDTH => 8,
FIFO_DWIDTH => 32,
FIFO_TUSERWIDTH => 1
)
PORT MAP (
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TUSER => S_AXIS_TUSER,
S_NUM_FREE => S_NUM_FREE,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_ARESETN => M_AXIS_ARESETN,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TUSER => M_AXIS_TUSER,
M_NUM_AVAIL => M_NUM_AVAIL
);
END axi_crc_dma_sim_1_axis_fifo_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xml
+115 -39
View File
@@ -1134,6 +1134,48 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
<spirit:displayName>VHDL Simulation</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_fifo</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d953da0f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axi_crc_dma_sim_1_axis_fifo_1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:19:22 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d953da0f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>S_AXI_ACLK</spirit:name>
@@ -1142,7 +1184,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1164,7 +1206,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1190,7 +1232,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1212,7 +1254,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1238,7 +1280,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1264,7 +1306,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1286,7 +1328,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1308,7 +1350,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1334,7 +1376,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1356,7 +1398,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1378,7 +1420,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1400,7 +1442,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1423,7 +1465,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1446,7 +1488,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1465,7 +1507,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1484,7 +1526,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1507,7 +1549,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1526,7 +1568,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1545,7 +1587,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1564,7 +1606,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1576,7 +1618,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1588,7 +1630,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1604,7 +1646,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1616,7 +1658,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1628,7 +1670,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1644,7 +1686,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1654,13 +1696,13 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">10</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1672,7 +1714,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1684,7 +1726,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1696,7 +1738,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1712,7 +1754,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1724,7 +1766,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1736,7 +1778,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1752,7 +1794,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1762,13 +1804,13 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">10</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.FIFO_AWIDTH&apos;)) - 1)">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1788,7 +1830,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH">11</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FIFO_DWIDTH</spirit:name>
@@ -1809,6 +1851,39 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/91a4/dmem_dp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/91a4/bmem_dp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/91a4/generic_fifo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/91a4/axis_fifo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_sim_1_axis_fifo_1_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_fifo_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
@@ -1824,7 +1899,7 @@
<spirit:parameter>
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:order="1300" spirit:configGroups="0 UnGrouped radioGroup" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">11</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:order="1300" spirit:configGroups="0 UnGrouped radioGroup" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FIFO_USE_BLOCKRAM</spirit:name>
@@ -1892,6 +1967,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_AWIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/sim/axi_crc_dma_sim_1_axis_fifo_1_0.vhd
+186
View File
@@ -0,0 +1,186 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: Gehrke:user:axis_fifo:1.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_sim_1_axis_fifo_1_0 IS
PORT (
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END axi_crc_dma_sim_1_axis_fifo_1_0;
ARCHITECTURE axi_crc_dma_sim_1_axis_fifo_1_0_arch OF axi_crc_dma_sim_1_axis_fifo_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_axis_fifo_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_fifo IS
GENERIC (
FIFO_HAS_AXIL_IF : BOOLEAN;
FIFO_USE_BLOCKRAM : BOOLEAN;
FIFO_AWIDTH : INTEGER;
FIFO_DWIDTH : INTEGER;
FIFO_TUSERWIDTH : INTEGER
);
PORT (
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axis_fifo;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_fifo
GENERIC MAP (
FIFO_HAS_AXIL_IF => false,
FIFO_USE_BLOCKRAM => true,
FIFO_AWIDTH => 8,
FIFO_DWIDTH => 32,
FIFO_TUSERWIDTH => 1
)
PORT MAP (
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TUSER => S_AXIS_TUSER,
S_NUM_FREE => S_NUM_FREE,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_ARESETN => M_AXIS_ARESETN,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TUSER => M_AXIS_TUSER,
M_NUM_AVAIL => M_NUM_AVAIL
);
END axi_crc_dma_sim_1_axis_fifo_1_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xml
-737
View File
@@ -1,737 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>axi_crc_dma_sim_1_axis_upsizer_0_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>M_AXIS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TUSER</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>TDATA_NUM_BYTES</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TDEST_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TREADY</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TKEEP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TLAST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S_AXIS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TUSER</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TUSER</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>TDATA_NUM_BYTES</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TDEST_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TREADY</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TKEEP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TLAST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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<spirit:name>INSERT_VIP</spirit:name>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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<spirit:port>
<spirit:name>AXIS_ACLK</spirit:name>
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<spirit:name>AXIS_ARESETN</spirit:name>
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<spirit:wireTypeDef>
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</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TDATA</spirit:name>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.WIDTH_IN&apos;)) - 1)">15</spirit:left>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
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<spirit:port>
<spirit:name>S_AXIS_TLAST</spirit:name>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
<spirit:name>S_AXIS_TREADY</spirit:name>
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<spirit:wireTypeDef>
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</spirit:wire>
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<spirit:port>
<spirit:name>S_AXIS_TUSER</spirit:name>
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<spirit:wireTypeDef>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:port>
<spirit:name>M_AXIS_TVALID</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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</spirit:wire>
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<spirit:port>
<spirit:name>M_AXIS_TDATA</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.WIDTH_IN&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.SIZE_FACTOR&apos;))) - 1)">31</spirit:left>
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<spirit:name>M_AXIS_TUSER</spirit:name>
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<spirit:displayName>Width In</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH_IN">16</spirit:value>
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<spirit:displayName>Size Factor</spirit:displayName>
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<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_crc_dma_sim_1_axis_upsizer_0_0</spirit:value>
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/axi_crc_dma_sim_1_clk_rst_generator_0_0.xml
+63 -5
View File
@@ -5,6 +5,47 @@
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<spirit:version>1.0</spirit:version>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
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<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:47ca4f62</spirit:value>
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@@ -13,7 +54,7 @@
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -69,7 +110,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -81,7 +122,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -120,6 +161,23 @@
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axi_crc_dma_sim_1_clk_rst_generator_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>clk_rst_generator</spirit:description>
<spirit:parameters>
<spirit:parameter>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_clk_rst_generator_0_0/sim/axi_crc_dma_sim_1_clk_rst_generator_0_0.vhd
+99
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@@ -0,0 +1,99 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:clk_rst_generator:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axi_crc_dma_sim_1_clk_rst_generator_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END axi_crc_dma_sim_1_clk_rst_generator_0_0;
ARCHITECTURE axi_crc_dma_sim_1_clk_rst_generator_0_0_arch OF axi_crc_dma_sim_1_clk_rst_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clk_rst_generator IS
GENERIC (
CLOCK_PERIOD : INTEGER;
HAS_CLK_INPUT : BOOLEAN;
HAS_RESET_INPUT : BOOLEAN;
HAS_STOP_INPUT : BOOLEAN
);
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END COMPONENT clk_rst_generator;
BEGIN
U0 : clk_rst_generator
GENERIC MAP (
CLOCK_PERIOD => 10000,
HAS_CLK_INPUT => true,
HAS_RESET_INPUT => true,
HAS_STOP_INPUT => true
)
PORT MAP (
clk_in => clk_in,
rst_in => rst_in,
clk => clk,
rst_n => rst_n,
stop_simulation => stop_simulation
);
END axi_crc_dma_sim_1_clk_rst_generator_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axil_master_with_rom.vhd
+285
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@@ -0,0 +1,285 @@
------------------------------------------------------------------------------
-- axil_master_with_rom.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
----------------------------------------------------------
-- AXIL-Master
--
-- Transactions des Masters werden durch ein ladbares ROM definiert
-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet
-- Das ROM besitzt eine Wortbreite von 40 bit
-- Für einen Befehl werden 1 bis 2 Worte verwendet
-- Nur 'wal' verwendet 2 40 - Bit - Worte
--
-- Die Codierung ist nachfolgend dargestellt :
-- command wal : <39 : 8> Adresse <3 : 0> Befehl(wal = 1)
-- <39 : 8> Daten <3 : 0> Befehl WStrobe
-- command ral : <39 : 8> Adresse <3 : 0> Befehl(ral = 2)
-- command wfi : Befehl(wfi = 6)
-- command ral : <15 : 8> Wartezyklen <3 : 0> Befehl(slp = 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axil_master_with_rom is
generic
(
HAS_INTERRUPT_IN : boolean := true;
HAS_FINISHED_OUT : boolean := false;
REVISION_NO : integer := 1;
STIM_FILENAME : string := "../../stimuli.mem"
);
port
(
interrupt_in : in std_logic:='0';
finished_o : out std_logic;
M_AXIL_ACLK : in std_logic;
M_AXIL_ARESETN : in std_logic;
M_AXIL_ARREADY : in std_logic;
M_AXIL_ARVALID : out std_logic;
M_AXIL_ARADDR : out std_logic_vector(31 downto 0);
M_AXIL_ARPROT : out std_logic_vector(2 downto 0);
M_AXIL_RREADY : out std_logic;
M_AXIL_RVALID : in std_logic;
M_AXIL_RDATA : in std_logic_vector(31 downto 0);
M_AXIL_RRESP : in std_logic_vector(1 downto 0);
M_AXIL_AWREADY : in std_logic;
M_AXIL_AWVALID : out std_logic;
M_AXIL_AWADDR : out std_logic_vector(31 downto 0);
M_AXIL_AWPROT : out std_logic_vector(2 downto 0);
M_AXIL_WREADY : in std_logic;
M_AXIL_WVALID : out std_logic;
M_AXIL_WDATA : out std_logic_vector(31 downto 0);
M_AXIL_WSTRB : out std_logic_vector(3 downto 0);
M_AXIL_BREADY : out std_logic;
M_AXIL_BVALID : in std_logic;
M_AXIL_BRESP : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of axil_master_with_rom is
type TSTATE is (INIT,INIT_WAIT,
GET_COMMAND,
WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP,
RD_ADDR,RD_DATA,
WAIT_FOR_INT,
SLEEP,SLEEP_WAIT,
FINISHED
);
signal state : TSTATE := INIT;
constant ADDR_WIDTH_CMD_ROM : integer := 12;
signal mdata : std_logic_vector(39 downto 0);
signal maddr : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0);
begin
cmdrom : entity work.axilm_rom
generic map (
FILENAME => STIM_FILENAME,
DW => 40,
AW => ADDR_WIDTH_CMD_ROM
)
port map (
clk => M_AXIL_ACLK,
a => maddr,
q => mdata
);
process
variable cnt8 : unsigned( 7 downto 0);
variable cnt32 : unsigned(31 downto 0);
variable addr_accepted : boolean;
variable data_accepted : boolean;
begin
wait until rising_edge(M_AXIL_ACLK);
if M_AXIL_ARESETN = '0' then
state <= INIT;
M_AXIL_ARVALID <= '0';
M_AXIL_ARADDR <= (others=>'X');
M_AXIL_ARPROT <= (others=>'0');
M_AXIL_RREADY <= '0';
M_AXIL_AWVALID <= '0';
M_AXIL_AWADDR <= (others=>'X');
M_AXIL_AWPROT <= (others=>'0');
M_AXIL_WVALID <= '0';
M_AXIL_WDATA <= (others=>'X');
M_AXIL_WSTRB <= (others=>'X');
M_AXIL_BREADY <= '0';
finished_o <= '0';
else
case state is
----
-- Init
----
when INIT =>
finished_o <= '0';
cnt8 := x"10";
maddr <= (others=>'0');
M_AXIL_ARVALID <= '0';
M_AXIL_ARADDR <= (others=>'X');
M_AXIL_ARPROT <= (others=>'0');
M_AXIL_RREADY <= '0';
M_AXIL_AWVALID <= '0';
M_AXIL_AWADDR <= (others=>'X');
M_AXIL_AWPROT <= (others=>'0');
M_AXIL_WVALID <= '0';
M_AXIL_WDATA <= (others=>'X');
M_AXIL_WSTRB <= (others=>'X');
M_AXIL_BREADY <= '0';
state <= INIT_WAIT;
when INIT_WAIT =>
cnt8 := cnt8 - 1;
if cnt8 = 0 then
state <= GET_COMMAND;
end if;
when GET_COMMAND =>
case (mdata(3 downto 0)) is
when x"0" => state <= FINISHED;
when x"1" => state <= WR_ADDR;
when x"2" => state <= RD_ADDR;
when x"6" => state <= WAIT_FOR_INT;
when x"7" => state <= SLEEP;
when others => maddr <= std_logic_vector(unsigned(maddr) + 1);
end case;
----
-- Write
----
when WR_ADDR =>
M_AXIL_AWVALID <= '1';
M_AXIL_AWADDR <= mdata(39 downto 8);
M_AXIL_ARVALID <= '0';
M_AXIL_ARADDR <= (others => 'X');
maddr <= std_logic_vector(unsigned(maddr) + 1);
addr_accepted := false;
data_accepted := false;
state <= WR_ADDR_WAIT1;
when WR_ADDR_WAIT1 =>
if (M_AXIL_AWREADY = '1') then
M_AXIL_AWVALID <= '0';
addr_accepted := true;
end if;
state <= WR_ADDR_WAIT2;
when WR_ADDR_WAIT2 =>
if (M_AXIL_AWREADY = '1') then
M_AXIL_AWVALID <= '0';
addr_accepted := true;
end if;
state <= WR_DATA;
when WR_DATA =>
if (M_AXIL_AWREADY = '1') then
M_AXIL_AWVALID <= '0';
addr_accepted := true;
end if;
M_AXIL_WSTRB <= mdata( 3 downto 0);
M_AXIL_WDATA <= mdata(39 downto 8);
M_AXIL_WVALID <= '1';
state <= WR_DATA_WAIT;
when WR_DATA_WAIT =>
if (M_AXIL_AWREADY = '1') then
M_AXIL_AWVALID <= '0';
addr_accepted := true;
end if;
if (M_AXIL_WREADY = '1') then
M_AXIL_WVALID <= '0';
data_accepted := true;
end if;
if (addr_accepted and data_accepted) then
maddr <= std_logic_vector(unsigned(maddr) + 1);
M_AXIL_AWVALID <= '0';
M_AXIL_WSTRB <= (others=>'X');
M_AXIL_WDATA <= (others=>'X');
M_AXIL_WVALID <= '0';
M_AXIL_BREADY <= '1';
state <= WR_RESP;
end if;
when WR_RESP =>
if M_AXIL_BVALID = '1' then
M_AXIL_BREADY <= '0';
state <= GET_COMMAND;
end if;
----
-- Read
----
when RD_ADDR =>
M_AXIL_ARVALID <= '1';
M_AXIL_ARADDR <= mdata(39 downto 8);
M_AXIL_AWVALID <= 'X';
M_AXIL_AWADDR <= (others => 'X');
M_AXIL_RREADY <= '1';
addr_accepted := false;
state <= RD_DATA;
when RD_DATA =>
if (M_AXIL_ARREADY = '1') then
M_AXIL_ARVALID <= '0';
addr_accepted := true;
end if;
if (M_AXIL_RVALID = '1') then
M_AXIL_RREADY <= '0';
data_accepted := true;
end if;
if (addr_accepted and data_accepted) then
maddr <= std_logic_vector(unsigned(maddr) + 1);
M_AXIL_ARVALID <= '0';
M_AXIL_RREADY <= '0';
M_AXIL_ARADDR <= (others => 'X');
state <= GET_COMMAND;
end if;
when WAIT_FOR_INT =>
if (interrupt_in = '1') then
maddr <= std_logic_vector(unsigned(maddr) + 1);
state <= GET_COMMAND;
end if;
when SLEEP =>
cnt32 := unsigned(mdata(39 downto 8));
-- synthesis translate_off
cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern
-- synthesis translate_on
maddr <= std_logic_vector(unsigned(maddr) + 1);
state <= SLEEP_WAIT;
when SLEEP_WAIT =>
if (cnt32 /= 0) then
cnt32 := cnt32 - 1;
else
state <= GET_COMMAND;
end if;
when FINISHED =>
finished_o <= '1';
end case;
end if;
end process;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/85f6/sources_1/new/axilm_rom.vhd
+65
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@@ -0,0 +1,65 @@
------------------------------------------------------------------------------
-- axilm_rom.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
----------------------------------------------------------
-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity axilm_rom is
generic (
FILENAME : string;
DW : integer; -- Data Width
AW : integer -- Address Width
);
port (
clk : in std_logic; -- Clock
a : in std_logic_vector(AW-1 downto 0); -- Address
q : out std_logic_vector(DW-1 downto 0) -- Data out port
);
end;
architecture rtl of axilm_rom is
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
impure function InitMemFromFile(MemFileName : in string) return tmem is
FILE MemFile : text is in MemFileName;
variable MemFileLine : line;
variable mem : tmem;
begin
for i in tmem'range loop
readline(MemFile, MemFileLine);
read(MemFileLine, mem(i));
end loop;
return mem;
end function;
constant mem : tmem := InitMemFromFile(
-- synthesis translate_off
"../../" &
-- synthesis translate_on
FILENAME);
begin
process
begin
wait until rising_edge(clk);
q <= mem(to_integer(unsigned(a)));
end process;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/axis_fifo.vhd
+230
View File
@@ -0,0 +1,230 @@
--------------------------------------------------------------------------
--
-- AXI Stream FIFO
--
-- Prof. Dr.-Ing. W. Gehrke (c) 2013
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity axis_fifo is
generic
(
FIFO_HAS_AXIL_IF : boolean := false;
FIFO_USE_BLOCKRAM : boolean := true;
FIFO_AWIDTH : integer := 11;
FIFO_DWIDTH : integer := 32;
FIFO_TUSERWIDTH : integer := 1
);
port
(
-- AXI-L Slave Port
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(7 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(7 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Streaming Target Port
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TVALID : in std_logic;
S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TUSER : in std_logic_vector(FIFO_TUSERWIDTH-1 downto 0);
S_NUM_FREE : out std_logic_vector(FIFO_AWIDTH-1 downto 0); -- Free Entries
-- AXI Streaming Initiator Port
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TUSER : out std_logic_vector(FIFO_TUSERWIDTH-1 downto 0);
M_NUM_AVAIL : out std_logic_vector(FIFO_AWIDTH-1 downto 0) -- Allocated Entries
);
end;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of axis_fifo is
type T_AXIL_STATE is (IDLE,WAIT_BREADY,WAIT_RREADY);
signal axil_state : T_AXIL_STATE := IDLE;
signal fifo_wrclk : std_logic;
signal fifo_wrrst : std_logic;
signal fifo_wren : std_logic;
signal fifo_wrfull : std_logic;
signal fifo_wrdat : std_logic_vector(FIFO_DWIDTH+FIFO_TUSERWIDTH downto 0);
signal fifo_wrnum : std_logic_vector(FIFO_AWIDTH-1 downto 0);
signal fifo_rdclk : std_logic;
signal fifo_rdrst : std_logic := '0';
signal fifo_rden : std_logic;
signal fifo_rdempty : std_logic;
signal fifo_rddat : std_logic_vector(FIFO_DWIDTH+FIFO_TUSERWIDTH downto 0);
signal fifo_rdnum : std_logic_vector(FIFO_AWIDTH-1 downto 0);
signal fifo_reset_req : std_logic;
signal fifo_reset_req_sync : std_logic;
signal status_reg : std_logic_vector (31 downto 0):= (others=>'0');
begin
fifo_wrclk <= S_AXIS_ACLK;
fifo_wrrst <= not S_AXIS_ARESETN;
fifo_wren <= S_AXIS_TVALID;
S_AXIS_TREADY <= not fifo_wrfull;
fifo_wrdat <= S_AXIS_TUSER & S_AXIS_TLAST & S_AXIS_TDATA;
S_NUM_FREE <= fifo_wrnum;
fifo_rdclk <= M_AXIS_ACLK;
fifo_rdrst <= (not M_AXIS_ARESETN) or fifo_reset_req_sync;
fifo_rden <= M_AXIS_TREADY;
M_AXIS_TVALID <= not fifo_rdempty;
M_AXIS_TDATA <= fifo_rddat(FIFO_DWIDTH-1 downto 0);
M_AXIS_TUSER <= fifo_rddat(FIFO_DWIDTH+FIFO_TUSERWIDTH downto FIFO_DWIDTH+1);
M_AXIS_TLAST <= fifo_rddat(FIFO_DWIDTH);
M_NUM_AVAIL <= fifo_rdnum;
status_gen1: if FIFO_AWIDTH <= 14 generate
status_reg(2*FIFO_AWIDTH+3 downto 0) <= fifo_wrnum & fifo_rdnum & '0' & fifo_wrfull & fifo_rdempty & fifo_reset_req;
end generate;
status_gen2: if FIFO_AWIDTH > 14 generate
status_reg <= fifo_wrnum(13 downto 0) & fifo_rdnum(13 downto 0) & '0' & fifo_wrfull & fifo_rdempty & fifo_reset_req;
end generate;
fifo : entity work.generic_fifo
generic map (
USE_BLOCKRAM=> FIFO_USE_BLOCKRAM, -- Block RAM (1) or Distributed Memory (0)
DW => FIFO_DWIDTH+FIFO_TUSERWIDTH+1, -- Data Width
AW => FIFO_AWIDTH -- Address Width
)
port map (
-- Write Port
wrclk => fifo_wrclk, -- Clock
wrrst => fifo_wrrst, -- Reset
wrdat => fifo_wrdat, -- Data in
wren => fifo_wren, -- Write enable
wrfull => fifo_wrfull, -- Full indicator
wrnum => fifo_wrnum,
-- Read Port
rdclk => fifo_rdclk, -- Clock
rdrst => fifo_rdrst, -- Reset
rden => fifo_rden, -- Read enable
rddat => fifo_rddat, -- Data out port
rdempty => fifo_rdempty, -- Empty indicator
rdnum => fifo_rdnum
);
process begin
wait until rising_edge (fifo_rdclk);
fifo_reset_req_sync <= fifo_reset_req;
end process;
axil_ngen: if not FIFO_HAS_AXIL_IF generate
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others=>'0');
S_AXI_RRESP <= (others=>'0');
S_AXI_RVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others=>'0');
S_AXI_BVALID <= '0';
S_AXI_AWREADY <= '0';
fifo_reset_req <= '0';
end generate;
axil_gen: if FIFO_HAS_AXIL_IF generate
axil_if : process
variable reg_num : integer;
begin
wait until rising_edge (S_AXI_ACLK);
if S_AXI_ARESETN = '0' then
S_AXI_AWREADY <= '0';
S_AXI_ARREADY <= '0';
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_RVALID <= '0';
S_AXI_RDATA <= (others=>'0');
fifo_reset_req <= '0';
else
case axil_state is
when IDLE =>
S_AXI_AWREADY <= '1';
S_AXI_WREADY <= '1';
S_AXI_ARREADY <= '1';
S_AXI_BVALID <= '0';
S_AXI_RVALID <= '0';
if S_AXI_AWVALID = '1' then
if S_AXI_WVALID = '1' then
fifo_reset_req <= S_AXI_WDATA(0);
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_ARREADY <= '0';
S_AXI_BVALID <= '1';
axil_state <= WAIT_BREADY;
end if;
elsif S_AXI_ARVALID = '1' then
S_AXI_RDATA <= status_reg;
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RVALID <= '1';
axil_state <= WAIT_RREADY;
end if;
when WAIT_BREADY =>
if S_AXI_BREADY = '1' then
S_AXI_AWREADY <= '1';
S_AXI_WREADY <= '1';
S_AXI_ARREADY <= '1';
S_AXI_BVALID <= '0';
axil_state <= IDLE;
end if;
when WAIT_RREADY =>
if S_AXI_RREADY = '1' then
S_AXI_AWREADY <= '1';
S_AXI_WREADY <= '1';
S_AXI_ARREADY <= '1';
S_AXI_RVALID <= '0';
axil_state <= IDLE;
end if;
end case;
end if;
end process;
end generate;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/bmem_dp.vhd
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--------------------------------------------------------------------------
--
-- Dual-ported Synchronous Memory (Block Memory)
--
-- Prof. Dr.-Ing. W. Gehrke (c) 2011
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bmem_dp is
generic (
DW : integer := 16; -- Data Width
AW : integer := 10 -- Address Width
);
port (
-- Port 1
clk1 : in std_logic; -- Clock
en1 : in std_logic; -- Enable
a1 : in std_logic_vector(AW-1 downto 0); -- Address
d1 : in std_logic_vector(DW-1 downto 0); -- Data in
we1 : in std_logic; -- Write enable
q1 : out std_logic_vector(DW-1 downto 0); -- Data out port
-- Port 2
clk2 : in std_logic; -- Clock
en2 : in std_logic; -- Enable
a2 : in std_logic_vector(AW-1 downto 0); -- Address
d2 : in std_logic_vector(DW-1 downto 0); -- Data in
we2 : in std_logic; -- Write enable
q2 : out std_logic_vector(DW-1 downto 0) -- Data out port
);
end;
architecture rtl of bmem_dp is
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
shared variable mem : tmem := ((others=> (others=>'0')));
signal q1_sig : std_logic_vector(DW-1 downto 0) := (others=>'0');
signal q2_sig : std_logic_vector(DW-1 downto 0) := (others=>'0');
begin
q1 <= q1_sig;
q2 <= q2_sig;
-- Port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (en1 = '1') then
if (we1 = '1') then
mem(to_integer(unsigned(a1))) := d1;
end if;
q1_sig <= mem(to_integer(unsigned(a1)));
end if;
end if;
end process;
-- Port 2
process (clk2)
begin
if (clk2'event and clk2 = '1') then
if (en2 = '1') then
if (we2 = '1') then
mem(to_integer(unsigned(a2))) := d2;
end if;
q2_sig <= mem(to_integer(unsigned(a2)));
end if;
end if;
end process;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/dmem_dp.vhd
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--------------------------------------------------------------------------
--
-- Dual-ported Asynchronous-Read Synchronous-Write Memory (Distributed Memory)
--
-- Prof. Dr.-Ing. W. Gehrke (c) 2011
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem_dp is
generic (
DW : integer := 16; -- Data Width
AW : integer := 10 -- Address Width
);
port (
-- Port 1
clk1 : in std_logic; -- Clock
en1 : in std_logic; -- Enable
a1 : in std_logic_vector(AW-1 downto 0); -- Address
d1 : in std_logic_vector(DW-1 downto 0); -- Data in
we1 : in std_logic; -- Write enable
q1 : out std_logic_vector(DW-1 downto 0); -- Data out port
-- Port 2
clk2 : in std_logic; -- Clock
en2 : in std_logic; -- Enable
a2 : in std_logic_vector(AW-1 downto 0); -- Address
d2 : in std_logic_vector(DW-1 downto 0); -- Data in
we2 : in std_logic; -- Write enable
q2 : out std_logic_vector(DW-1 downto 0) -- Data out port
);
end;
architecture rtl of dmem_dp is
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
shared variable mem : tmem;
begin
-- Port 1
process (clk1,a1)
begin
q1 <= mem(to_integer(unsigned(a1)));
if (clk1'event and clk1 = '1') then
if (en1 = '1') then
if (we1 = '1') then
mem(to_integer(unsigned(a1))) := d1;
end if;
end if;
end if;
end process;
-- Port 2
process (clk2,a2)
begin
q2 <= mem(to_integer(unsigned(a2)));
if (clk2'event and clk2 = '1') then
if (en2 = '1') then
if (we2 = '1') then
mem(to_integer(unsigned(a2))) := d2;
end if;
end if;
end if;
end process;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/91a4/generic_fifo.vhd
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--------------------------------------------------------------------------
--
-- FIFO incl. Clock Domain Crossing
--
--
-- Prof. Dr.-Ing. W. Gehrke (c) 2013
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity generic_fifo is
generic (
USE_BLOCKRAM: boolean := true;
DW : integer := 32; -- Data Width
AW : integer := 10 -- Address Width
);
port (
-- Write Port
wrclk : in std_logic; -- Clock
wrrst : in std_logic; -- Reset
wrdat : in std_logic_vector(DW-1 downto 0); -- Data in
wren : in std_logic; -- Write enable
wrfull : out std_logic; -- Full indicator
wrnum : out std_logic_vector(AW-1 downto 0); -- Free Entries
-- Read Port
rdclk : in std_logic; -- Clock
rdrst : in std_logic; -- Reset
rden : in std_logic; -- Read enable
rddat : out std_logic_vector(DW-1 downto 0); -- Data out port
rdempty : out std_logic; -- Empty indicator
rdnum : out std_logic_vector(AW-1 downto 0) -- Allocated Entries
);
end;
architecture rtl of generic_fifo is
constant zero : std_logic_vector (DW-1 downto 0) := (others=>'0');
signal full : std_logic := '0';
signal empty : std_logic := '1';
signal mem_wren : std_logic := '0';
signal wrrst_sync : std_logic := '0';
signal rdrst_sync : std_logic := '0';
signal wp_bin : std_logic_vector (AW downto 0) := (others=>'0');
signal wp_bin_next : std_logic_vector (AW downto 0) := (others=>'0');
signal wp_gray : std_logic_vector (AW downto 0) := (others=>'0');
signal wp_gray_sync : std_logic_vector (AW downto 0) := (others=>'0');
signal wp_bin_sync : std_logic_vector (AW downto 0) := (others=>'0');
signal w_num_free : std_logic_vector (AW-1 downto 0) := (others=>'1');
signal rp_bin : std_logic_vector (AW downto 0) := (others=>'0');
signal rp_bin_reg : std_logic_vector (AW downto 0) := (others=>'0');
signal rp_bin_next : std_logic_vector (AW downto 0) := (others=>'0');
signal rp_gray : std_logic_vector (AW downto 0) := (others=>'0');
signal rp_gray_sync : std_logic_vector (AW downto 0) := (others=>'0');
signal rp_bin_sync : std_logic_vector (AW downto 0) := (others=>'0');
signal r_num_avail : std_logic_vector (AW-1 downto 0) := (others=>'0');
signal rddat_dm : std_logic_vector(DW-1 downto 0);
begin
bl_gen: if USE_BLOCKRAM generate
fifomem : entity work.bmem_dp
generic map(
DW => DW, -- Data Width
AW => AW -- Address Width
)
port map(
-- Port 1
clk1 => wrclk, -- Clock
en1 => '1', -- Enable
a1 => wp_bin(AW-1 downto 0), -- Address
d1 => wrdat, -- Data in
we1 => mem_wren, -- Write enable
q1 => open, -- Data out port
-- Port 2
clk2 => rdclk, -- Clock
en2 => '1', -- Enable
a2 => rp_bin(AW-1 downto 0), -- Address
d2 => zero, -- Data in
we2 => '0', -- Write enable
q2 => rddat -- Data out port
);
end generate;
dm_gen: if not USE_BLOCKRAM generate
fifomem : entity work.dmem_dp
generic map(
DW => DW, -- Data Width
AW => AW -- Address Width
)
port map(
-- Port 1
clk1 => wrclk, -- Clock
en1 => '1', -- Enable
a1 => wp_bin(AW-1 downto 0), -- Address
d1 => wrdat, -- Data in
we1 => mem_wren, -- Write enable
q1 => open, -- Data out port
-- Port 2
clk2 => rdclk, -- Clock
en2 => '1', -- Enable
a2 => rp_bin(AW-1 downto 0), -- Address
d2 => zero, -- Data in
we2 => '0', -- Write enable
q2 => rddat_dm -- Data out port
);
process begin
wait until rising_edge(rdclk);
rddat <= rddat_dm;
end process;
end generate;
----------------------------------------------
-- FIFO Write Logic
----------------------------------------------
wp_gray <= '0' & wp_bin(AW downto 1) xor wp_bin; -- Gray Code conversion
full <= '1' when (wp_bin(AW-1 downto 0) = rp_bin_sync(AW-1 downto 0)) and (wp_bin(AW) /= rp_bin_sync(AW)) else '0';
wrfull <= full;
wrnum <= w_num_free;
mem_wren <= wren and (not full);
sync_wr : process begin
wait until rising_edge(wrclk);
rp_gray_sync <= rp_gray;
rdrst_sync <= rdrst;
end process;
fifo_fulln_wr : process begin
wait until rising_edge(wrclk);
if wp_bin = rp_bin_sync then
w_num_free <= (others=>'1');
else
w_num_free <= std_logic_vector(unsigned(rp_bin_sync(AW-1 downto 0)) - unsigned(wp_bin(AW-1 downto 0)));
end if;
end process;
fifo_wr : process begin
wait until rising_edge(wrclk);
if wrrst = '1' or rdrst_sync = '1' then
wp_bin <= (others=>'0');
wp_bin_next <= std_logic_vector(to_unsigned(1,AW+1));
else
if wren = '1' and full = '0' then
wp_bin <= wp_bin_next;
wp_bin_next <= std_logic_vector(unsigned(wp_bin_next)+1);
end if;
end if;
end process;
gray2bin_rp: process (rp_gray_sync)
variable temp : std_logic_vector(AW downto 0);
begin
temp := rp_gray_sync;
for i in AW-1 downto 0 loop
temp(i) := rp_gray_sync(i) xor temp(i+1);
end loop;
rp_bin_sync <= temp;
end process;
----------------------------------------------
-- FIFO Read Logic
----------------------------------------------
rp_gray <= '0' & rp_bin(AW downto 1) xor rp_bin; -- Gray Code conversion
empty <= '1' when rp_bin_reg = wp_bin_sync else '0';
rdempty <= empty;
rp_bin <= rp_bin_next when rden = '1' and empty = '0' else rp_bin_reg;
rdnum <= r_num_avail;
sync_rd : process begin
wait until rising_edge(rdclk);
wp_gray_sync <= wp_gray;
wrrst_sync <= wrrst;
end process;
fifo_fulln_rd : process begin
wait until rising_edge(rdclk);
if rp_bin_reg = wp_bin_sync then -- empty check -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16
r_num_avail <= (others=>'0');
elsif wp_bin_sync = (not rp_bin_reg(AW)) & rp_bin_reg(AW-1 downto 0) then --full check -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16
r_num_avail <= (others=>'1');
else
r_num_avail <= std_logic_vector(unsigned(wp_bin_sync(AW-1 downto 0)) - unsigned(rp_bin_reg(AW-1 downto 0))); -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16
end if;
end process;
fifo_rd : process begin
wait until rising_edge(rdclk);
if rdrst = '1' or wrrst_sync = '1' then
rp_bin_reg <= (others=>'0');
rp_bin_next <= std_logic_vector(to_unsigned(1,AW+1));
else
rp_bin_reg <= rp_bin;
if rden = '1' and empty = '0' then
rp_bin_next <= std_logic_vector(unsigned(rp_bin_next)+1);
end if;
end if;
end process;
gray2bin_wp: process (wp_gray_sync)
variable temp : std_logic_vector(AW downto 0);
begin
temp := wp_gray_sync;
for i in AW-1 downto 0 loop
temp(i) := wp_gray_sync(i) xor temp(i+1);
end loop;
wp_bin_sync <= temp;
end process;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ipshared/9a97/sources_1/new/clk_rst_generator.vhd
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------------------------------------------------------------------------------
-- clk_rst_generator.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_rst_generator is
generic
(
CLOCK_PERIOD : integer := 10000;
HAS_CLK_INPUT : boolean := true;
HAS_RESET_INPUT : boolean := true;
HAS_STOP_INPUT : boolean := true
);
port
(
clk_in : in std_logic := '1';
rst_in : in std_logic := '0';
clk : out std_logic;
rst_n : out std_logic;
stop_simulation : in std_logic := '0'
);
end;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of clk_rst_generator is
signal clk_sim : std_logic := '1';
signal clk_in_sig : std_logic := '1';
signal clk_sig : std_logic := '1';
signal rst_sig : std_logic := '0';
signal rst_in_sync : std_logic := '0';
begin
clk <= clk_sig;
rst_n <= not rst_sig;
---------------------------------------------------------------
---------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------
---------------------------------------------------------------
clk_sig <= clk_in_sig and clk_sim;
-- Dies ist kein gated Clock!
-- Fuer die Synthese ist clk_sim konstant '1'
-- somit wird die UND-Verknuepfung 'wegoptimiert'
-- und was übrig bleibt, ist ein 'Draht'
-- synthesis translate_off
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
-- synthesis translate_on
process (clk_in) begin
clk_in_sig <= clk_in;
-- synthesis translate_off
clk_in_sig <= '1';
-- synthesis translate_on
end process;
---------------------------------------------------------------
---------------------------------------------------------------
-- RESET GENERATION
---------------------------------------------------------------
---------------------------------------------------------------
process
variable rescnt : unsigned (6 downto 0) := (others=>'1');
begin
wait until rising_edge(clk_sig);
rst_in_sync <= rst_in;
if rst_in_sync = '1' then
rescnt := (others=>'1');
end if;
if rescnt = 0 then
rst_sig <= '0';
else
rescnt := rescnt - 1;
rst_sig <= '1';
end if;
end process;
---------------------------------------------------------------
---------------------------------------------------------------
-- STOP SIMULATION INPUT (simulation only)
---------------------------------------------------------------
---------------------------------------------------------------
-- synthesis translate_off
process (stop_simulation) begin
if stop_simulation = '1' then
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
end if;
end process;
-- synthesis translate_on
end rtl;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/sim/axi_crc_dma_sim_1.vhd
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--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Feb 2 01:00:12 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1.bd
--Design : axi_crc_dma_sim_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_crc_dma_imp_1PQG7GB is
port (
CLK : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_arready : out STD_LOGIC;
S_AXIL_arvalid : in STD_LOGIC;
S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_awready : out STD_LOGIC;
S_AXIL_awvalid : in STD_LOGIC;
S_AXIL_bready : in STD_LOGIC;
S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_bvalid : out STD_LOGIC;
S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_rready : in STD_LOGIC;
S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_rvalid : out STD_LOGIC;
S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_wready : out STD_LOGIC;
S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_wvalid : in STD_LOGIC
);
end axi_crc_dma_imp_1PQG7GB;
architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
component axi_crc_dma_sim_1_axis_fifo_0_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_sim_1_axis_fifo_0_0;
component axi_crc_dma_sim_1_axis_fifo_1_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_sim_1_axis_fifo_1_0;
component axi_crc_dma_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_crc_0_0;
component axi_crc_dma_sim_1_axis_dma_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 );
FIFO_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARREADY : in STD_LOGIC;
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_RREADY : out STD_LOGIC;
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_RLAST : in STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WREADY : in STD_LOGIC;
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WLAST : out STD_LOGIC;
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BREADY : out STD_LOGIC;
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_dma_0_0;
signal CLK_1 : STD_LOGIC;
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_ARREADY : STD_LOGIC;
signal Conn1_ARVALID : STD_LOGIC;
signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_AWREADY : STD_LOGIC;
signal Conn1_AWVALID : STD_LOGIC;
signal Conn1_BREADY : STD_LOGIC;
signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn1_BVALID : STD_LOGIC;
signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_RREADY : STD_LOGIC;
signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn1_RVALID : STD_LOGIC;
signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_WREADY : STD_LOGIC;
signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn1_WVALID : STD_LOGIC;
signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal Conn2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_ARREADY : STD_LOGIC;
signal Conn2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn2_ARVALID : STD_LOGIC;
signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_AWREADY : STD_LOGIC;
signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn2_AWVALID : STD_LOGIC;
signal Conn2_BREADY : STD_LOGIC;
signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_BVALID : STD_LOGIC;
signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal Conn2_RLAST : STD_LOGIC;
signal Conn2_RREADY : STD_LOGIC;
signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_RVALID : STD_LOGIC;
signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_WLAST : STD_LOGIC;
signal Conn2_WREADY : STD_LOGIC;
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_WVALID : STD_LOGIC;
signal RESETN_1 : STD_LOGIC;
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_axis_dma_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
CLK_1 <= CLK;
Conn1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0);
Conn1_ARVALID <= S_AXIL_arvalid;
Conn1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0);
Conn1_AWVALID <= S_AXIL_awvalid;
Conn1_BREADY <= S_AXIL_bready;
Conn1_RREADY <= S_AXIL_rready;
Conn1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0);
Conn1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0);
Conn1_WVALID <= S_AXIL_wvalid;
Conn2_ARREADY <= M_AXI_arready;
Conn2_AWREADY <= M_AXI_awready;
Conn2_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
Conn2_BVALID <= M_AXI_bvalid;
Conn2_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
Conn2_RID(0) <= M_AXI_rid(0);
Conn2_RLAST <= M_AXI_rlast;
Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
Conn2_RVALID <= M_AXI_rvalid;
Conn2_WREADY <= M_AXI_wready;
M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0);
M_AXI_arid(0) <= Conn2_ARID(0);
M_AXI_arlen(3 downto 0) <= Conn2_ARLEN(3 downto 0);
M_AXI_arsize(2 downto 0) <= Conn2_ARSIZE(2 downto 0);
M_AXI_arvalid <= Conn2_ARVALID;
M_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= Conn2_AWBURST(1 downto 0);
M_AXI_awlen(3 downto 0) <= Conn2_AWLEN(3 downto 0);
M_AXI_awsize(2 downto 0) <= Conn2_AWSIZE(2 downto 0);
M_AXI_awvalid <= Conn2_AWVALID;
M_AXI_bready <= Conn2_BREADY;
M_AXI_rready <= Conn2_RREADY;
M_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0);
M_AXI_wlast <= Conn2_WLAST;
M_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0);
M_AXI_wvalid <= Conn2_WVALID;
RESETN_1 <= RESETN;
S_AXIL_arready <= Conn1_ARREADY;
S_AXIL_awready <= Conn1_AWREADY;
S_AXIL_bresp(1 downto 0) <= Conn1_BRESP(1 downto 0);
S_AXIL_bvalid <= Conn1_BVALID;
S_AXIL_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0);
S_AXIL_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0);
S_AXIL_rvalid <= Conn1_RVALID;
S_AXIL_wready <= Conn1_WREADY;
axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
port map (
CLK => CLK_1,
M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
RESETN => RESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
port map (
CLK => CLK_1,
FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
M_AXI_ARADDR(31 downto 0) => Conn2_ARADDR(31 downto 0),
M_AXI_ARBURST(1 downto 0) => Conn2_ARBURST(1 downto 0),
M_AXI_ARCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_ARID(0) => Conn2_ARID(0),
M_AXI_ARLEN(3 downto 0) => Conn2_ARLEN(3 downto 0),
M_AXI_ARPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_ARREADY => Conn2_ARREADY,
M_AXI_ARSIZE(2 downto 0) => Conn2_ARSIZE(2 downto 0),
M_AXI_ARVALID => Conn2_ARVALID,
M_AXI_AWADDR(31 downto 0) => Conn2_AWADDR(31 downto 0),
M_AXI_AWBURST(1 downto 0) => Conn2_AWBURST(1 downto 0),
M_AXI_AWCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_AWID(0) => NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED(0),
M_AXI_AWLEN(3 downto 0) => Conn2_AWLEN(3 downto 0),
M_AXI_AWPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_AWREADY => Conn2_AWREADY,
M_AXI_AWSIZE(2 downto 0) => Conn2_AWSIZE(2 downto 0),
M_AXI_AWVALID => Conn2_AWVALID,
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_BREADY => Conn2_BREADY,
M_AXI_BRESP(1 downto 0) => Conn2_BRESP(1 downto 0),
M_AXI_BVALID => Conn2_BVALID,
M_AXI_RDATA(31 downto 0) => Conn2_RDATA(31 downto 0),
M_AXI_RID(0) => Conn2_RID(0),
M_AXI_RLAST => Conn2_RLAST,
M_AXI_RREADY => Conn2_RREADY,
M_AXI_RRESP(1 downto 0) => Conn2_RRESP(1 downto 0),
M_AXI_RVALID => Conn2_RVALID,
M_AXI_WDATA(31 downto 0) => Conn2_WDATA(31 downto 0),
M_AXI_WID(31 downto 0) => NLW_axis_dma_0_M_AXI_WID_UNCONNECTED(31 downto 0),
M_AXI_WLAST => Conn2_WLAST,
M_AXI_WREADY => Conn2_WREADY,
M_AXI_WSTRB(3 downto 0) => Conn2_WSTRB(3 downto 0),
M_AXI_WVALID => Conn2_WVALID,
RESETN => RESETN_1,
S_AXIL_ARADDR(7 downto 0) => Conn1_ARADDR(7 downto 0),
S_AXIL_ARREADY => Conn1_ARREADY,
S_AXIL_ARVALID => Conn1_ARVALID,
S_AXIL_AWADDR(7 downto 0) => Conn1_AWADDR(7 downto 0),
S_AXIL_AWREADY => Conn1_AWREADY,
S_AXIL_AWVALID => Conn1_AWVALID,
S_AXIL_BREADY => Conn1_BREADY,
S_AXIL_BRESP(1 downto 0) => Conn1_BRESP(1 downto 0),
S_AXIL_BVALID => Conn1_BVALID,
S_AXIL_RDATA(31 downto 0) => Conn1_RDATA(31 downto 0),
S_AXIL_RREADY => Conn1_RREADY,
S_AXIL_RRESP(1 downto 0) => Conn1_RRESP(1 downto 0),
S_AXIL_RVALID => Conn1_RVALID,
S_AXIL_WDATA(31 downto 0) => Conn1_WDATA(31 downto 0),
S_AXIL_WREADY => Conn1_WREADY,
S_AXIL_WSTRB(3 downto 0) => Conn1_WSTRB(3 downto 0),
S_AXIL_WVALID => Conn1_WVALID,
S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0
port map (
M_AXIS_ACLK => CLK_1,
M_AXIS_ARESETN => RESETN_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0),
S_AXIS_ACLK => CLK_1,
S_AXIS_ARESETN => RESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0)
);
axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0
port map (
M_AXIS_ACLK => CLK_1,
M_AXIS_ARESETN => RESETN_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
S_AXIS_ACLK => CLK_1,
S_AXIS_ARESETN => RESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_crc_dma_sim_1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=7,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=6,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1.hwdef";
end axi_crc_dma_sim_1;
architecture STRUCTURE of axi_crc_dma_sim_1 is
component axi_crc_dma_sim_1_axil_master_with_rom_0_0 is
port (
interrupt_in : in STD_LOGIC;
M_AXIL_ACLK : in STD_LOGIC;
M_AXIL_ARESETN : in STD_LOGIC;
M_AXIL_ARREADY : in STD_LOGIC;
M_AXIL_ARVALID : out STD_LOGIC;
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_RREADY : out STD_LOGIC;
M_AXIL_RVALID : in STD_LOGIC;
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXIL_AWREADY : in STD_LOGIC;
M_AXIL_AWVALID : out STD_LOGIC;
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_WREADY : in STD_LOGIC;
M_AXIL_WVALID : out STD_LOGIC;
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIL_BREADY : out STD_LOGIC;
M_AXIL_BVALID : in STD_LOGIC;
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component axi_crc_dma_sim_1_axil_master_with_rom_0_0;
component axi_crc_dma_sim_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end component axi_crc_dma_sim_1_clk_rst_generator_0_0;
component axi_crc_dma_sim_1_axi3_slave_verif_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_RLAST : out STD_LOGIC;
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WLAST : in STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component axi_crc_dma_sim_1_axi3_slave_verif_0_0;
signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_crc_dma_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_crc_dma_M_AXI_ARREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_crc_dma_M_AXI_ARVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_crc_dma_M_AXI_AWREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_crc_dma_M_AXI_AWVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_BREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_BVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_crc_dma_M_AXI_RLAST : STD_LOGIC;
signal axi_crc_dma_M_AXI_RREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_RVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_WLAST : STD_LOGIC;
signal axi_crc_dma_M_AXI_WREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_crc_dma_M_AXI_WVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal clk_rst_generator_0_rst_n : STD_LOGIC;
signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0
port map (
CLK => clk_rst_generator_0_clk,
RESETN => clk_rst_generator_0_rst_n,
S_AXI_ARADDR(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
S_AXI_ARBURST(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
S_AXI_ARID(0) => axi_crc_dma_M_AXI_ARID(0),
S_AXI_ARLEN(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
S_AXI_ARREADY => axi_crc_dma_M_AXI_ARREADY,
S_AXI_ARSIZE(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
S_AXI_ARVALID => axi_crc_dma_M_AXI_ARVALID,
S_AXI_AWADDR(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
S_AXI_AWBURST(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
S_AXI_AWLEN(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
S_AXI_AWREADY => axi_crc_dma_M_AXI_AWREADY,
S_AXI_AWSIZE(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
S_AXI_AWVALID => axi_crc_dma_M_AXI_AWVALID,
S_AXI_BREADY => axi_crc_dma_M_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
S_AXI_BVALID => axi_crc_dma_M_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
S_AXI_RID(0) => axi_crc_dma_M_AXI_RID(0),
S_AXI_RLAST => axi_crc_dma_M_AXI_RLAST,
S_AXI_RREADY => axi_crc_dma_M_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
S_AXI_RVALID => axi_crc_dma_M_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
S_AXI_WLAST => axi_crc_dma_M_AXI_WLAST,
S_AXI_WREADY => axi_crc_dma_M_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => axi_crc_dma_M_AXI_WVALID
);
axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB
port map (
CLK => clk_rst_generator_0_clk,
M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0),
M_AXI_arlen(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
M_AXI_arready => axi_crc_dma_M_AXI_ARREADY,
M_AXI_arsize(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
M_AXI_arvalid => axi_crc_dma_M_AXI_ARVALID,
M_AXI_awaddr(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
M_AXI_awlen(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
M_AXI_awready => axi_crc_dma_M_AXI_AWREADY,
M_AXI_awsize(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
M_AXI_awvalid => axi_crc_dma_M_AXI_AWVALID,
M_AXI_bready => axi_crc_dma_M_AXI_BREADY,
M_AXI_bresp(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
M_AXI_bvalid => axi_crc_dma_M_AXI_BVALID,
M_AXI_rdata(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
M_AXI_rid(0) => axi_crc_dma_M_AXI_RID(0),
M_AXI_rlast => axi_crc_dma_M_AXI_RLAST,
M_AXI_rready => axi_crc_dma_M_AXI_RREADY,
M_AXI_rresp(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
M_AXI_rvalid => axi_crc_dma_M_AXI_RVALID,
M_AXI_wdata(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
M_AXI_wlast => axi_crc_dma_M_AXI_WLAST,
M_AXI_wready => axi_crc_dma_M_AXI_WREADY,
M_AXI_wstrb(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
M_AXI_wvalid => axi_crc_dma_M_AXI_WVALID,
RESETN => clk_rst_generator_0_rst_n,
S_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
S_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
S_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
S_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
S_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
S_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
S_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY,
S_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
S_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
S_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
S_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY,
S_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
S_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
S_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
S_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY,
S_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
S_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID
);
axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0
port map (
M_AXIL_ACLK => clk_rst_generator_0_clk,
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
interrupt_in => '0'
);
clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0
port map (
clk => clk_rst_generator_0_clk,
clk_in => '1',
rst_in => '0',
rst_n => clk_rst_generator_0_rst_n,
stop_simulation => '0'
);
end STRUCTURE;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/synth/axi_crc_dma_sim_1.vhd
+680
View File
@@ -0,0 +1,680 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Feb 2 01:00:12 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axi_crc_dma_sim_1.bd
--Design : axi_crc_dma_sim_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_crc_dma_imp_1PQG7GB is
port (
CLK : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXIL_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_arready : out STD_LOGIC;
S_AXIL_arvalid : in STD_LOGIC;
S_AXIL_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_awready : out STD_LOGIC;
S_AXIL_awvalid : in STD_LOGIC;
S_AXIL_bready : in STD_LOGIC;
S_AXIL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_bvalid : out STD_LOGIC;
S_AXIL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_rready : in STD_LOGIC;
S_AXIL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_rvalid : out STD_LOGIC;
S_AXIL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_wready : out STD_LOGIC;
S_AXIL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_wvalid : in STD_LOGIC
);
end axi_crc_dma_imp_1PQG7GB;
architecture STRUCTURE of axi_crc_dma_imp_1PQG7GB is
component axi_crc_dma_sim_1_axis_fifo_0_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_sim_1_axis_fifo_0_0;
component axi_crc_dma_sim_1_axis_fifo_1_0 is
port (
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
S_NUM_FREE : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
M_NUM_AVAIL : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component axi_crc_dma_sim_1_axis_fifo_1_0;
component axi_crc_dma_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_crc_0_0;
component axi_crc_dma_sim_1_axis_dma_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : out STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : out STD_LOGIC_VECTOR ( 31 downto 0 );
FIFO_NUM_FREE : in STD_LOGIC_VECTOR ( 7 downto 0 );
FIFO_NUM_AVAIL : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARREADY : in STD_LOGIC;
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_RREADY : out STD_LOGIC;
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_RLAST : in STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WREADY : in STD_LOGIC;
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WLAST : out STD_LOGIC;
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BREADY : out STD_LOGIC;
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axi_crc_dma_sim_1_axis_dma_0_0;
signal CLK_1 : STD_LOGIC;
signal Conn1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_ARREADY : STD_LOGIC;
signal Conn1_ARVALID : STD_LOGIC;
signal Conn1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_AWREADY : STD_LOGIC;
signal Conn1_AWVALID : STD_LOGIC;
signal Conn1_BREADY : STD_LOGIC;
signal Conn1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn1_BVALID : STD_LOGIC;
signal Conn1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_RREADY : STD_LOGIC;
signal Conn1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn1_RVALID : STD_LOGIC;
signal Conn1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn1_WREADY : STD_LOGIC;
signal Conn1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn1_WVALID : STD_LOGIC;
signal Conn2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal Conn2_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_ARREADY : STD_LOGIC;
signal Conn2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn2_ARVALID : STD_LOGIC;
signal Conn2_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_AWREADY : STD_LOGIC;
signal Conn2_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Conn2_AWVALID : STD_LOGIC;
signal Conn2_BREADY : STD_LOGIC;
signal Conn2_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_BVALID : STD_LOGIC;
signal Conn2_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal Conn2_RLAST : STD_LOGIC;
signal Conn2_RREADY : STD_LOGIC;
signal Conn2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal Conn2_RVALID : STD_LOGIC;
signal Conn2_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Conn2_WLAST : STD_LOGIC;
signal Conn2_WREADY : STD_LOGIC;
signal Conn2_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Conn2_WVALID : STD_LOGIC;
signal RESETN_1 : STD_LOGIC;
signal axis_dma_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_dma_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_dma_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_dma_0_initial_value : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_dma_0_polynomial : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_0_S_NUM_FREE : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_fifo_1_M_AXIS_TLAST : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TREADY : STD_LOGIC;
signal axis_fifo_1_M_AXIS_TVALID : STD_LOGIC;
signal axis_fifo_1_M_NUM_AVAIL : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axis_upsizer_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_upsizer_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_upsizer_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_upsizer_0_M_AXIS_TVALID : STD_LOGIC;
signal NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_axis_dma_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
CLK_1 <= CLK;
Conn1_ARADDR(31 downto 0) <= S_AXIL_araddr(31 downto 0);
Conn1_ARVALID <= S_AXIL_arvalid;
Conn1_AWADDR(31 downto 0) <= S_AXIL_awaddr(31 downto 0);
Conn1_AWVALID <= S_AXIL_awvalid;
Conn1_BREADY <= S_AXIL_bready;
Conn1_RREADY <= S_AXIL_rready;
Conn1_WDATA(31 downto 0) <= S_AXIL_wdata(31 downto 0);
Conn1_WSTRB(3 downto 0) <= S_AXIL_wstrb(3 downto 0);
Conn1_WVALID <= S_AXIL_wvalid;
Conn2_ARREADY <= M_AXI_arready;
Conn2_AWREADY <= M_AXI_awready;
Conn2_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
Conn2_BVALID <= M_AXI_bvalid;
Conn2_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
Conn2_RID(0) <= M_AXI_rid(0);
Conn2_RLAST <= M_AXI_rlast;
Conn2_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
Conn2_RVALID <= M_AXI_rvalid;
Conn2_WREADY <= M_AXI_wready;
M_AXI_araddr(31 downto 0) <= Conn2_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= Conn2_ARBURST(1 downto 0);
M_AXI_arid(0) <= Conn2_ARID(0);
M_AXI_arlen(3 downto 0) <= Conn2_ARLEN(3 downto 0);
M_AXI_arsize(2 downto 0) <= Conn2_ARSIZE(2 downto 0);
M_AXI_arvalid <= Conn2_ARVALID;
M_AXI_awaddr(31 downto 0) <= Conn2_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= Conn2_AWBURST(1 downto 0);
M_AXI_awlen(3 downto 0) <= Conn2_AWLEN(3 downto 0);
M_AXI_awsize(2 downto 0) <= Conn2_AWSIZE(2 downto 0);
M_AXI_awvalid <= Conn2_AWVALID;
M_AXI_bready <= Conn2_BREADY;
M_AXI_rready <= Conn2_RREADY;
M_AXI_wdata(31 downto 0) <= Conn2_WDATA(31 downto 0);
M_AXI_wlast <= Conn2_WLAST;
M_AXI_wstrb(3 downto 0) <= Conn2_WSTRB(3 downto 0);
M_AXI_wvalid <= Conn2_WVALID;
RESETN_1 <= RESETN;
S_AXIL_arready <= Conn1_ARREADY;
S_AXIL_awready <= Conn1_AWREADY;
S_AXIL_bresp(1 downto 0) <= Conn1_BRESP(1 downto 0);
S_AXIL_bvalid <= Conn1_BVALID;
S_AXIL_rdata(31 downto 0) <= Conn1_RDATA(31 downto 0);
S_AXIL_rresp(1 downto 0) <= Conn1_RRESP(1 downto 0);
S_AXIL_rvalid <= Conn1_RVALID;
S_AXIL_wready <= Conn1_WREADY;
axis_crc_0: component axi_crc_dma_sim_1_axis_crc_0_0
port map (
CLK => CLK_1,
M_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
RESETN => RESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_dma_0: component axi_crc_dma_sim_1_axis_dma_0_0
port map (
CLK => CLK_1,
FIFO_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
FIFO_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0),
M_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
M_AXI_ARADDR(31 downto 0) => Conn2_ARADDR(31 downto 0),
M_AXI_ARBURST(1 downto 0) => Conn2_ARBURST(1 downto 0),
M_AXI_ARCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_ARID(0) => Conn2_ARID(0),
M_AXI_ARLEN(3 downto 0) => Conn2_ARLEN(3 downto 0),
M_AXI_ARPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_ARREADY => Conn2_ARREADY,
M_AXI_ARSIZE(2 downto 0) => Conn2_ARSIZE(2 downto 0),
M_AXI_ARVALID => Conn2_ARVALID,
M_AXI_AWADDR(31 downto 0) => Conn2_AWADDR(31 downto 0),
M_AXI_AWBURST(1 downto 0) => Conn2_AWBURST(1 downto 0),
M_AXI_AWCACHE(3 downto 0) => NLW_axis_dma_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_AWID(0) => NLW_axis_dma_0_M_AXI_AWID_UNCONNECTED(0),
M_AXI_AWLEN(3 downto 0) => Conn2_AWLEN(3 downto 0),
M_AXI_AWPROT(2 downto 0) => NLW_axis_dma_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_AWREADY => Conn2_AWREADY,
M_AXI_AWSIZE(2 downto 0) => Conn2_AWSIZE(2 downto 0),
M_AXI_AWVALID => Conn2_AWVALID,
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_BREADY => Conn2_BREADY,
M_AXI_BRESP(1 downto 0) => Conn2_BRESP(1 downto 0),
M_AXI_BVALID => Conn2_BVALID,
M_AXI_RDATA(31 downto 0) => Conn2_RDATA(31 downto 0),
M_AXI_RID(0) => Conn2_RID(0),
M_AXI_RLAST => Conn2_RLAST,
M_AXI_RREADY => Conn2_RREADY,
M_AXI_RRESP(1 downto 0) => Conn2_RRESP(1 downto 0),
M_AXI_RVALID => Conn2_RVALID,
M_AXI_WDATA(31 downto 0) => Conn2_WDATA(31 downto 0),
M_AXI_WID(31 downto 0) => NLW_axis_dma_0_M_AXI_WID_UNCONNECTED(31 downto 0),
M_AXI_WLAST => Conn2_WLAST,
M_AXI_WREADY => Conn2_WREADY,
M_AXI_WSTRB(3 downto 0) => Conn2_WSTRB(3 downto 0),
M_AXI_WVALID => Conn2_WVALID,
RESETN => RESETN_1,
S_AXIL_ARADDR(7 downto 0) => Conn1_ARADDR(7 downto 0),
S_AXIL_ARREADY => Conn1_ARREADY,
S_AXIL_ARVALID => Conn1_ARVALID,
S_AXIL_AWADDR(7 downto 0) => Conn1_AWADDR(7 downto 0),
S_AXIL_AWREADY => Conn1_AWREADY,
S_AXIL_AWVALID => Conn1_AWVALID,
S_AXIL_BREADY => Conn1_BREADY,
S_AXIL_BRESP(1 downto 0) => Conn1_BRESP(1 downto 0),
S_AXIL_BVALID => Conn1_BVALID,
S_AXIL_RDATA(31 downto 0) => Conn1_RDATA(31 downto 0),
S_AXIL_RREADY => Conn1_RREADY,
S_AXIL_RRESP(1 downto 0) => Conn1_RRESP(1 downto 0),
S_AXIL_RVALID => Conn1_RVALID,
S_AXIL_WDATA(31 downto 0) => Conn1_WDATA(31 downto 0),
S_AXIL_WREADY => Conn1_WREADY,
S_AXIL_WSTRB(3 downto 0) => Conn1_WSTRB(3 downto 0),
S_AXIL_WVALID => Conn1_WVALID,
S_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
S_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
S_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
initial_value(31 downto 0) => axis_dma_0_initial_value(31 downto 0),
polynomial(31 downto 0) => axis_dma_0_polynomial(31 downto 0)
);
axis_fifo_0: component axi_crc_dma_sim_1_axis_fifo_0_0
port map (
M_AXIS_ACLK => CLK_1,
M_AXIS_ARESETN => RESETN_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_0_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_0_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_0_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => NLW_axis_fifo_0_M_NUM_AVAIL_UNCONNECTED(7 downto 0),
S_AXIS_ACLK => CLK_1,
S_AXIS_ARESETN => RESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_dma_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_dma_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_dma_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_dma_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => axis_fifo_0_S_NUM_FREE(7 downto 0)
);
axis_fifo_1: component axi_crc_dma_sim_1_axis_fifo_1_0
port map (
M_AXIS_ACLK => CLK_1,
M_AXIS_ARESETN => RESETN_1,
M_AXIS_TDATA(31 downto 0) => axis_fifo_1_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_fifo_1_M_AXIS_TLAST,
M_AXIS_TREADY => axis_fifo_1_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_fifo_1_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_fifo_1_M_AXIS_TVALID,
M_NUM_AVAIL(7 downto 0) => axis_fifo_1_M_NUM_AVAIL(7 downto 0),
S_AXIS_ACLK => CLK_1,
S_AXIS_ARESETN => RESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_upsizer_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_upsizer_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_upsizer_0_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => axis_upsizer_0_M_AXIS_TVALID,
S_NUM_FREE(7 downto 0) => NLW_axis_fifo_1_S_NUM_FREE_UNCONNECTED(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axi_crc_dma_sim_1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axi_crc_dma_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=7,numNonXlnxBlks=4,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_clkrst_cnt=6,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of axi_crc_dma_sim_1 : entity is "axi_crc_dma_sim_1.hwdef";
end axi_crc_dma_sim_1;
architecture STRUCTURE of axi_crc_dma_sim_1 is
component axi_crc_dma_sim_1_axil_master_with_rom_0_0 is
port (
interrupt_in : in STD_LOGIC;
M_AXIL_ACLK : in STD_LOGIC;
M_AXIL_ARESETN : in STD_LOGIC;
M_AXIL_ARREADY : in STD_LOGIC;
M_AXIL_ARVALID : out STD_LOGIC;
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_RREADY : out STD_LOGIC;
M_AXIL_RVALID : in STD_LOGIC;
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXIL_AWREADY : in STD_LOGIC;
M_AXIL_AWVALID : out STD_LOGIC;
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_WREADY : in STD_LOGIC;
M_AXIL_WVALID : out STD_LOGIC;
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIL_BREADY : out STD_LOGIC;
M_AXIL_BVALID : in STD_LOGIC;
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component axi_crc_dma_sim_1_axil_master_with_rom_0_0;
component axi_crc_dma_sim_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end component axi_crc_dma_sim_1_clk_rst_generator_0_0;
component axi_crc_dma_sim_1_axi3_slave_verif_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_RLAST : out STD_LOGIC;
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WLAST : in STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component axi_crc_dma_sim_1_axi3_slave_verif_0_0;
signal axi_crc_dma_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_crc_dma_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_crc_dma_M_AXI_ARREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_crc_dma_M_AXI_ARVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_crc_dma_M_AXI_AWREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_crc_dma_M_AXI_AWVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_BREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_BVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_crc_dma_M_AXI_RLAST : STD_LOGIC;
signal axi_crc_dma_M_AXI_RREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_crc_dma_M_AXI_RVALID : STD_LOGIC;
signal axi_crc_dma_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_crc_dma_M_AXI_WLAST : STD_LOGIC;
signal axi_crc_dma_M_AXI_WREADY : STD_LOGIC;
signal axi_crc_dma_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_crc_dma_M_AXI_WVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal clk_rst_generator_0_rst_n : STD_LOGIC;
signal NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
axi3_slave_verif_0: component axi_crc_dma_sim_1_axi3_slave_verif_0_0
port map (
CLK => clk_rst_generator_0_clk,
RESETN => clk_rst_generator_0_rst_n,
S_AXI_ARADDR(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
S_AXI_ARBURST(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
S_AXI_ARID(0) => axi_crc_dma_M_AXI_ARID(0),
S_AXI_ARLEN(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
S_AXI_ARREADY => axi_crc_dma_M_AXI_ARREADY,
S_AXI_ARSIZE(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
S_AXI_ARVALID => axi_crc_dma_M_AXI_ARVALID,
S_AXI_AWADDR(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
S_AXI_AWBURST(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
S_AXI_AWLEN(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
S_AXI_AWREADY => axi_crc_dma_M_AXI_AWREADY,
S_AXI_AWSIZE(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
S_AXI_AWVALID => axi_crc_dma_M_AXI_AWVALID,
S_AXI_BREADY => axi_crc_dma_M_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
S_AXI_BVALID => axi_crc_dma_M_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
S_AXI_RID(0) => axi_crc_dma_M_AXI_RID(0),
S_AXI_RLAST => axi_crc_dma_M_AXI_RLAST,
S_AXI_RREADY => axi_crc_dma_M_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
S_AXI_RVALID => axi_crc_dma_M_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
S_AXI_WLAST => axi_crc_dma_M_AXI_WLAST,
S_AXI_WREADY => axi_crc_dma_M_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => axi_crc_dma_M_AXI_WVALID
);
axi_crc_dma: entity work.axi_crc_dma_imp_1PQG7GB
port map (
CLK => clk_rst_generator_0_clk,
M_AXI_araddr(31 downto 0) => axi_crc_dma_M_AXI_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => axi_crc_dma_M_AXI_ARBURST(1 downto 0),
M_AXI_arid(0) => axi_crc_dma_M_AXI_ARID(0),
M_AXI_arlen(3 downto 0) => axi_crc_dma_M_AXI_ARLEN(3 downto 0),
M_AXI_arready => axi_crc_dma_M_AXI_ARREADY,
M_AXI_arsize(2 downto 0) => axi_crc_dma_M_AXI_ARSIZE(2 downto 0),
M_AXI_arvalid => axi_crc_dma_M_AXI_ARVALID,
M_AXI_awaddr(31 downto 0) => axi_crc_dma_M_AXI_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => axi_crc_dma_M_AXI_AWBURST(1 downto 0),
M_AXI_awlen(3 downto 0) => axi_crc_dma_M_AXI_AWLEN(3 downto 0),
M_AXI_awready => axi_crc_dma_M_AXI_AWREADY,
M_AXI_awsize(2 downto 0) => axi_crc_dma_M_AXI_AWSIZE(2 downto 0),
M_AXI_awvalid => axi_crc_dma_M_AXI_AWVALID,
M_AXI_bready => axi_crc_dma_M_AXI_BREADY,
M_AXI_bresp(1 downto 0) => axi_crc_dma_M_AXI_BRESP(1 downto 0),
M_AXI_bvalid => axi_crc_dma_M_AXI_BVALID,
M_AXI_rdata(31 downto 0) => axi_crc_dma_M_AXI_RDATA(31 downto 0),
M_AXI_rid(0) => axi_crc_dma_M_AXI_RID(0),
M_AXI_rlast => axi_crc_dma_M_AXI_RLAST,
M_AXI_rready => axi_crc_dma_M_AXI_RREADY,
M_AXI_rresp(1 downto 0) => axi_crc_dma_M_AXI_RRESP(1 downto 0),
M_AXI_rvalid => axi_crc_dma_M_AXI_RVALID,
M_AXI_wdata(31 downto 0) => axi_crc_dma_M_AXI_WDATA(31 downto 0),
M_AXI_wlast => axi_crc_dma_M_AXI_WLAST,
M_AXI_wready => axi_crc_dma_M_AXI_WREADY,
M_AXI_wstrb(3 downto 0) => axi_crc_dma_M_AXI_WSTRB(3 downto 0),
M_AXI_wvalid => axi_crc_dma_M_AXI_WVALID,
RESETN => clk_rst_generator_0_rst_n,
S_AXIL_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
S_AXIL_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
S_AXIL_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
S_AXIL_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
S_AXIL_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
S_AXIL_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
S_AXIL_bready => axil_master_with_rom_0_M_AXIL_BREADY,
S_AXIL_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
S_AXIL_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
S_AXIL_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
S_AXIL_rready => axil_master_with_rom_0_M_AXIL_RREADY,
S_AXIL_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
S_AXIL_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
S_AXIL_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
S_AXIL_wready => axil_master_with_rom_0_M_AXIL_WREADY,
S_AXIL_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
S_AXIL_wvalid => axil_master_with_rom_0_M_AXIL_WVALID
);
axil_master_with_rom_0: component axi_crc_dma_sim_1_axil_master_with_rom_0_0
port map (
M_AXIL_ACLK => clk_rst_generator_0_clk,
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
M_AXIL_ARPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_ARPROT_UNCONNECTED(2 downto 0),
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
M_AXIL_AWPROT(2 downto 0) => NLW_axil_master_with_rom_0_M_AXIL_AWPROT_UNCONNECTED(2 downto 0),
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
interrupt_in => '0'
);
clk_rst_generator_0: component axi_crc_dma_sim_1_clk_rst_generator_0_0
port map (
clk => clk_rst_generator_0_clk,
clk_in => '1',
rst_in => '0',
rst_n => clk_rst_generator_0_rst_n,
stop_simulation => '0'
);
end STRUCTURE;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bxml
+50 -5
View File
@@ -2,10 +2,55 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axis_crc_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738434924"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1738434924"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738434924"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738434924"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738454377"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738454377"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738454377"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738454377"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\axis_crc_sim_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axis_crc_sim_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axis_crc_sim_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\axis_crc_sim_1.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="axis_crc_sim_1.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\axis_crc_sim_1.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\axis_crc_sim_1.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1_ooc.xdc
+10
View File
@@ -0,0 +1,10 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
################################################################################
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/hdl/axis_crc_sim_1_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sat Feb 1 17:06:13 2025
--Date : Sun Feb 2 00:16:45 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axis_crc_sim_1_wrapper.bd
--Design : axis_crc_sim_1_wrapper
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/axis_crc_sim_1_axis_crc_0_0.xml
+119 -12
View File
@@ -436,6 +436,83 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_crc</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7d52f37a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axis_crc</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:3fed59a8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:3fed59a8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_crc_sim_1_axis_crc_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:16:45 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7d52f37a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_crc_sim_1_axis_crc_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:37 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:3fed59a8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CLK</spirit:name>
@@ -444,7 +521,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -456,7 +534,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -472,7 +551,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -488,7 +568,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -500,7 +581,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -516,7 +598,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -531,7 +614,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -546,7 +630,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -558,7 +643,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -574,7 +660,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -586,7 +673,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -598,7 +686,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -615,6 +704,24 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/axis_crc_sim_1_axis_crc_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axis_crc_sim_1_axis_crc_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_crc_0_0/synth/axis_crc_sim_1_axis_crc_0_0.vhd
+132
View File
@@ -0,0 +1,132 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_crc_sim_1_axis_crc_0_0 IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END axis_crc_sim_1_axis_crc_0_0;
ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_crc IS
PORT (
CLK : IN STD_LOGIC;
RESETN : IN STD_LOGIC;
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_crc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_crc_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc_sim_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_crc
PORT MAP (
CLK => CLK,
RESETN => RESETN,
initial_value => initial_value,
polynomial => polynomial,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
END axis_crc_sim_1_axis_crc_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/axis_crc_sim_1_axis_master_simmodel_0_0.xml
+79
View File
@@ -286,6 +286,17 @@
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7759c31b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
<spirit:displayName>VHDL Simulation</spirit:displayName>
@@ -326,6 +337,46 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_master_simmodel</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7759c31b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_crc_sim_1_axis_master_simmodel_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:36 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7759c31b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
@@ -335,6 +386,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -347,6 +399,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -359,6 +412,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -371,6 +425,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -387,6 +442,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -399,6 +455,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -411,6 +468,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -427,6 +485,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -443,6 +502,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -591,6 +651,25 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/d44d/bmp_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/d44d/axis_master_simmodel.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axis_crc_sim_1_axis_master_simmodel_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_master_simmodel</spirit:description>
<spirit:parameters>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_master_simmodel_0_0/synth/axis_crc_sim_1_axis_master_simmodel_0_0.vhd
+156
View File
@@ -0,0 +1,156 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: Gehrke:user:axis_master_simmodel:1.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_crc_sim_1_axis_master_simmodel_0_0 IS
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
FINISHED : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END axis_crc_sim_1_axis_master_simmodel_0_0;
ARCHITECTURE axis_crc_sim_1_axis_master_simmodel_0_0_arch OF axis_crc_sim_1_axis_master_simmodel_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_master_simmodel IS
GENERIC (
DATA_WIDTH : INTEGER;
HAS_FIFO_INTERFACE : BOOLEAN;
FIFO_AWIDTH : INTEGER;
FIFO_REQUEST_TRESHOLD : INTEGER;
TUSERWIDTH : INTEGER;
FILE_NAME : STRING;
FILE_EXTENSION : STRING;
FILE_AUTONUMBERING : BOOLEAN;
NUM_PIX_PER_LINE : INTEGER;
NUM_LINES : INTEGER;
NUM_FRAMES_PER_FILE : INTEGER;
RANDOM_TVALID : BOOLEAN;
PIXEL_FORMAT : INTEGER;
ALPHA_VALUE : INTEGER;
FRAMING_PIXELS : INTEGER;
FRAMING_LINES : INTEGER;
FRAMING_VAL_R_V : INTEGER;
FRAMING_VAL_G_Y : INTEGER;
FRAMING_VAL_B_U : INTEGER
);
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
FINISHED : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT axis_master_simmodel;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "axis_master_simmodel,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_master_simmodel_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_master_simmodel_0_0,axis_master_simmodel,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
BEGIN
U0 : axis_master_simmodel
GENERIC MAP (
DATA_WIDTH => 32,
HAS_FIFO_INTERFACE => false,
FIFO_AWIDTH => 11,
FIFO_REQUEST_TRESHOLD => 32,
TUSERWIDTH => 1,
FILE_NAME => "../../../../tst",
FILE_EXTENSION => "raw",
FILE_AUTONUMBERING => false,
NUM_PIX_PER_LINE => 3,
NUM_LINES => 1,
NUM_FRAMES_PER_FILE => 1,
RANDOM_TVALID => true,
PIXEL_FORMAT => 1,
ALPHA_VALUE => 255,
FRAMING_PIXELS => 0,
FRAMING_LINES => 0,
FRAMING_VAL_R_V => 128,
FRAMING_VAL_G_Y => 128,
FRAMING_VAL_B_U => 128
)
PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
FINISHED => FINISHED,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TUSER => M_AXIS_TUSER,
M_AXIS_NUM_FREE => STD_LOGIC_VECTOR(TO_UNSIGNED(1, 11))
);
END axis_crc_sim_1_axis_master_simmodel_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/axis_crc_sim_1_axis_slave_simmodel_0_0.xml
+78
View File
@@ -281,6 +281,17 @@
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:69398033</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
<spirit:displayName>VHDL Simulation</spirit:displayName>
@@ -321,6 +332,46 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_slave_simmodel</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:69398033</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_crc_sim_1_axis_slave_simmodel_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:36 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:69398033</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
@@ -330,6 +381,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -342,6 +394,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -354,6 +407,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -366,6 +420,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -382,6 +437,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -394,6 +450,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -406,6 +463,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -422,6 +480,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -525,6 +584,25 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/c453/bmp_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/c453/axis_slave_simmodel.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_slave_simmodel_v1_0</spirit:description>
<spirit:parameters>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_axis_slave_simmodel_0_0/synth/axis_crc_sim_1_axis_slave_simmodel_0_0.vhd
+140
View File
@@ -0,0 +1,140 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: Gehrke:user:axis_slave_simmodel:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_crc_sim_1_axis_slave_simmodel_0_0 IS
PORT (
FINISHED : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END axis_crc_sim_1_axis_slave_simmodel_0_0;
ARCHITECTURE axis_crc_sim_1_axis_slave_simmodel_0_0_arch OF axis_crc_sim_1_axis_slave_simmodel_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_slave_simmodel IS
GENERIC (
TUSERWIDTH : INTEGER;
FILE_NAME : STRING;
FILE_EXTENSION : STRING;
FILE_AUTONUMBERING : BOOLEAN;
PIXEL_FORMAT : INTEGER;
NUM_PIX_PER_LINE : INTEGER;
NUM_LINES : INTEGER;
NUM_FRAMES_PER_FILE : INTEGER;
NUM_FILES : INTEGER;
FRAMING_PIXELS : INTEGER;
FRAMING_LINES : INTEGER;
RANDOM_TREADY : BOOLEAN
);
PORT (
FINISHED : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axis_slave_simmodel;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "axis_slave_simmodel,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_axis_slave_simmodel_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_axis_slave_simmodel_0_0,axis_slave_simmodel,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_slave_simmodel
GENERIC MAP (
TUSERWIDTH => 1,
FILE_NAME => "../../../../tst_out",
FILE_EXTENSION => "raw",
FILE_AUTONUMBERING => false,
PIXEL_FORMAT => 1,
NUM_PIX_PER_LINE => 3,
NUM_LINES => 1,
NUM_FRAMES_PER_FILE => 1,
NUM_FILES => 1,
FRAMING_PIXELS => 0,
FRAMING_LINES => 0,
RANDOM_TREADY => true
)
PORT MAP (
FINISHED => FINISHED,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TUSER => S_AXIS_TUSER
);
END axis_crc_sim_1_axis_slave_simmodel_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/axis_crc_sim_1_clk_rst_generator_0_0.xml
+82
View File
@@ -25,6 +25,36 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>clk_rst_generator</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bbae1481</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bbae1481</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
@@ -45,6 +75,26 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>axis_crc_sim_1_clk_rst_generator_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:36 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bbae1481</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
@@ -54,6 +104,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -76,6 +127,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -98,6 +150,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -110,6 +163,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -122,6 +176,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -169,6 +224,25 @@
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constrs_1/new/clk_rst_generator.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/clk_rst_generator_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/clk_rst_generator_clocks.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
@@ -177,6 +251,14 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axis_crc_sim_1_clk_rst_generator_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>clk_rst_generator</spirit:description>
<spirit:parameters>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator.xdc
View File
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_clocks.xdc
View File
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_ooc.xdc
+1
View File
@@ -0,0 +1 @@
create_clock -period 10.000 -name clk_in -waveform {0.000 5.000} [get_ports clk_in]
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_clk_rst_generator_0_0/synth/axis_crc_sim_1_clk_rst_generator_0_0.vhd
+105
View File
@@ -0,0 +1,105 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:clk_rst_generator:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_crc_sim_1_clk_rst_generator_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END axis_crc_sim_1_clk_rst_generator_0_0;
ARCHITECTURE axis_crc_sim_1_clk_rst_generator_0_0_arch OF axis_crc_sim_1_clk_rst_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clk_rst_generator IS
GENERIC (
CLOCK_PERIOD : INTEGER;
HAS_CLK_INPUT : BOOLEAN;
HAS_RESET_INPUT : BOOLEAN;
HAS_STOP_INPUT : BOOLEAN
);
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END COMPONENT clk_rst_generator;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "clk_rst_generator,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axis_crc_sim_1_clk_rst_generator_0_0_arch : ARCHITECTURE IS "axis_crc_sim_1_clk_rst_generator_0_0,clk_rst_generator,{}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF axis_crc_sim_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "package_project";
BEGIN
U0 : clk_rst_generator
GENERIC MAP (
CLOCK_PERIOD => 10000,
HAS_CLK_INPUT => true,
HAS_RESET_INPUT => true,
HAS_STOP_INPUT => true
)
PORT MAP (
clk_in => clk_in,
rst_in => rst_in,
clk => clk,
rst_n => rst_n,
stop_simulation => stop_simulation
);
END axis_crc_sim_1_clk_rst_generator_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/axis_crc_sim_1_xlconstant_0_0.xml
+69 -1
View File
@@ -6,6 +6,17 @@
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e2c6de17</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_systemcsimulation</spirit:name>
<spirit:displayName>SystemC Simulation</spirit:displayName>
@@ -94,6 +105,46 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e2c6de17</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>axis_crc_sim_1_xlconstant_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:36 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e2c6de17</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
@@ -107,7 +158,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -168,6 +220,22 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axis_crc_sim_1_xlconstant_0_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Gives a constant signed value.</spirit:description>
<spirit:parameters>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.v → Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_0_0/synth/axis_crc_sim_1_xlconstant_0_0.v
+5 -4
View File
@@ -50,10 +50,11 @@
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 7
`timescale 1ns/1ps
(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *)
(* CHECK_LICENSE_TYPE = "axis_crc_sim_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{}" *)
(* CORE_GENERATION_INFO = "axis_crc_sim_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=32,CONST_VAL=0x00000001}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module test_1_xlconstant_1_0 (
module axis_crc_sim_1_xlconstant_0_0 (
dout
);
@@ -61,7 +62,7 @@ output wire [31 : 0] dout;
xlconstant_v1_1_7_xlconstant #(
.CONST_WIDTH(32),
.CONST_VAL(32'H00000000)
.CONST_VAL(32'H00000001)
) inst (
.dout(dout)
);
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/axis_crc_sim_1_xlconstant_1_0.xml
+69 -1
View File
@@ -6,6 +6,17 @@
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fe058b70</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_systemcsimulation</spirit:name>
<spirit:displayName>SystemC Simulation</spirit:displayName>
@@ -94,6 +105,46 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jan 31 17:33:27 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fe058b70</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>axis_crc_sim_1_xlconstant_1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 23:59:36 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fe058b70</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
@@ -107,7 +158,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -168,6 +220,22 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/axis_crc_sim_1_xlconstant_1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Gives a constant signed value.</spirit:description>
<spirit:parameters>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.v → Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/ip/axis_crc_sim_1_xlconstant_1_0/synth/axis_crc_sim_1_xlconstant_1_0.v
+5 -4
View File
@@ -50,10 +50,11 @@
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 7
`timescale 1ns/1ps
(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *)
(* CHECK_LICENSE_TYPE = "axis_crc_sim_1_xlconstant_1_0,xlconstant_v1_1_7_xlconstant,{}" *)
(* CORE_GENERATION_INFO = "axis_crc_sim_1_xlconstant_1_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=32,CONST_VAL=0x00000001}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module test_1_xlconstant_0_0 (
module axis_crc_sim_1_xlconstant_1_0 (
dout
);
@@ -61,7 +62,7 @@ output wire [31 : 0] dout;
xlconstant_v1_1_7_xlconstant #(
.CONST_WIDTH(32),
.CONST_VAL(32'H00000000)
.CONST_VAL(32'H00000001)
) inst (
.dout(dout)
);
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/sim/axis_crc_sim_1.vhd
+151
View File
@@ -0,0 +1,151 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Feb 2 00:16:45 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axis_crc_sim_1.bd
--Design : axis_crc_sim_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axis_crc_sim_1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef";
end axis_crc_sim_1;
architecture STRUCTURE of axis_crc_sim_1 is
component axis_crc_sim_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end component axis_crc_sim_1_clk_rst_generator_0_0;
component axis_crc_sim_1_axis_slave_simmodel_0_0 is
port (
FINISHED : out STD_LOGIC;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component axis_crc_sim_1_axis_slave_simmodel_0_0;
component axis_crc_sim_1_axis_master_simmodel_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
FINISHED : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component axis_crc_sim_1_axis_master_simmodel_0_0;
component axis_crc_sim_1_xlconstant_1_0 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component axis_crc_sim_1_xlconstant_1_0;
component axis_crc_sim_1_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component axis_crc_sim_1_xlconstant_0_0;
component axis_crc_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axis_crc_sim_1_axis_crc_0_0;
signal AXIS_ARESETN_1 : STD_LOGIC;
signal axis_master_simmodel_0_FINISHED : STD_LOGIC;
signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal crc_M_AXIS_TLAST : STD_LOGIC;
signal crc_M_AXIS_TREADY : STD_LOGIC;
signal crc_M_AXIS_TVALID : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
begin
axis_crc_0: component axis_crc_sim_1_axis_crc_0_0
port map (
CLK => clk_rst_generator_0_clk,
M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => crc_M_AXIS_TLAST,
M_AXIS_TREADY => crc_M_AXIS_TREADY,
M_AXIS_TVALID => crc_M_AXIS_TVALID,
RESETN => AXIS_ARESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID,
initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0),
polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0)
);
axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0
port map (
ACLK => clk_rst_generator_0_clk,
ARESETN => AXIS_ARESETN_1,
FINISHED => axis_master_simmodel_0_FINISHED,
M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
);
axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0
port map (
FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED,
S_AXIS_ACLK => clk_rst_generator_0_clk,
S_AXIS_ARESETN => AXIS_ARESETN_1,
S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => crc_M_AXIS_TLAST,
S_AXIS_TREADY => crc_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => crc_M_AXIS_TVALID
);
clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0
port map (
clk => clk_rst_generator_0_clk,
clk_in => '1',
rst_in => '0',
rst_n => AXIS_ARESETN_1,
stop_simulation => axis_master_simmodel_0_FINISHED
);
xlconstant_0: component axis_crc_sim_1_xlconstant_0_0
port map (
dout(31 downto 0) => xlconstant_0_dout(31 downto 0)
);
xlconstant_1: component axis_crc_sim_1_xlconstant_1_0
port map (
dout(31 downto 0) => xlconstant_1_dout(31 downto 0)
);
end STRUCTURE;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_crc_sim_1/synth/axis_crc_sim_1.vhd
+151
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--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Feb 2 00:16:45 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target axis_crc_sim_1.bd
--Design : axis_crc_sim_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity axis_crc_sim_1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of axis_crc_sim_1 : entity is "axis_crc_sim_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=axis_crc_sim_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of axis_crc_sim_1 : entity is "axis_crc_sim_1.hwdef";
end axis_crc_sim_1;
architecture STRUCTURE of axis_crc_sim_1 is
component axis_crc_sim_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end component axis_crc_sim_1_clk_rst_generator_0_0;
component axis_crc_sim_1_axis_slave_simmodel_0_0 is
port (
FINISHED : out STD_LOGIC;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
S_AXIS_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component axis_crc_sim_1_axis_slave_simmodel_0_0;
component axis_crc_sim_1_axis_master_simmodel_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
FINISHED : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component axis_crc_sim_1_axis_master_simmodel_0_0;
component axis_crc_sim_1_xlconstant_1_0 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component axis_crc_sim_1_xlconstant_1_0;
component axis_crc_sim_1_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component axis_crc_sim_1_xlconstant_0_0;
component axis_crc_sim_1_axis_crc_0_0 is
port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
initial_value : in STD_LOGIC_VECTOR ( 31 downto 0 );
polynomial : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component axis_crc_sim_1_axis_crc_0_0;
signal AXIS_ARESETN_1 : STD_LOGIC;
signal axis_master_simmodel_0_FINISHED : STD_LOGIC;
signal axis_master_simmodel_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_master_simmodel_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_master_simmodel_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_master_simmodel_0_M_AXIS_TVALID : STD_LOGIC;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal crc_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal crc_M_AXIS_TLAST : STD_LOGIC;
signal crc_M_AXIS_TREADY : STD_LOGIC;
signal crc_M_AXIS_TVALID : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED : STD_LOGIC;
begin
axis_crc_0: component axis_crc_sim_1_axis_crc_0_0
port map (
CLK => clk_rst_generator_0_clk,
M_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => crc_M_AXIS_TLAST,
M_AXIS_TREADY => crc_M_AXIS_TREADY,
M_AXIS_TVALID => crc_M_AXIS_TVALID,
RESETN => AXIS_ARESETN_1,
S_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
S_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID,
initial_value(31 downto 0) => xlconstant_1_dout(31 downto 0),
polynomial(31 downto 0) => xlconstant_0_dout(31 downto 0)
);
axis_master_simmodel_0: component axis_crc_sim_1_axis_master_simmodel_0_0
port map (
ACLK => clk_rst_generator_0_clk,
ARESETN => AXIS_ARESETN_1,
FINISHED => axis_master_simmodel_0_FINISHED,
M_AXIS_TDATA(31 downto 0) => axis_master_simmodel_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => axis_master_simmodel_0_M_AXIS_TLAST,
M_AXIS_TREADY => axis_master_simmodel_0_M_AXIS_TREADY,
M_AXIS_TUSER(0) => NLW_axis_master_simmodel_0_M_AXIS_TUSER_UNCONNECTED(0),
M_AXIS_TVALID => axis_master_simmodel_0_M_AXIS_TVALID
);
axis_slave_simmodel_0: component axis_crc_sim_1_axis_slave_simmodel_0_0
port map (
FINISHED => NLW_axis_slave_simmodel_0_FINISHED_UNCONNECTED,
S_AXIS_ACLK => clk_rst_generator_0_clk,
S_AXIS_ARESETN => AXIS_ARESETN_1,
S_AXIS_TDATA(31 downto 0) => crc_M_AXIS_TDATA(31 downto 0),
S_AXIS_TLAST => crc_M_AXIS_TLAST,
S_AXIS_TREADY => crc_M_AXIS_TREADY,
S_AXIS_TUSER(0) => '0',
S_AXIS_TVALID => crc_M_AXIS_TVALID
);
clk_rst_generator_0: component axis_crc_sim_1_clk_rst_generator_0_0
port map (
clk => clk_rst_generator_0_clk,
clk_in => '1',
rst_in => '0',
rst_n => AXIS_ARESETN_1,
stop_simulation => axis_master_simmodel_0_FINISHED
);
xlconstant_0: component axis_crc_sim_1_xlconstant_0_0
port map (
dout(31 downto 0) => xlconstant_0_dout(31 downto 0)
);
xlconstant_1: component axis_crc_sim_1_xlconstant_1_0
port map (
dout(31 downto 0) => xlconstant_1_dout(31 downto 0)
);
end STRUCTURE;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/axis_master_test.bxml
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<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="axis_master_test" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738431513"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1738431513"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738431513"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738431513"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xml
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/sim/axis_master_test_axis_mixer_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_mixer:1.0
-- IP Revision: 14
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_master_test_axis_mixer_0_0 IS
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
S_AXIS_1_TVALID : IN STD_LOGIC;
S_AXIS_1_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_1_TREADY : OUT STD_LOGIC;
S_AXIS_2_TVALID : IN STD_LOGIC;
S_AXIS_2_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_2_TREADY : OUT STD_LOGIC
);
END axis_master_test_axis_mixer_0_0;
ARCHITECTURE axis_master_test_axis_mixer_0_0_arch OF axis_master_test_axis_mixer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_master_test_axis_mixer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_mixer IS
GENERIC (
WEIGHT_1 : INTEGER;
DATA_WIDTH : INTEGER;
HAS_AXI_LITE_IF : BOOLEAN;
WEIGHT_2 : INTEGER;
FORCE_01_INPUT : BOOLEAN;
SHIFT_DEF : INTEGER
);
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
S_AXIS_1_TVALID : IN STD_LOGIC;
S_AXIS_1_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_1_TREADY : OUT STD_LOGIC;
S_AXIS_2_TVALID : IN STD_LOGIC;
S_AXIS_2_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_2_TREADY : OUT STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axis_mixer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_RESET ARESETN, ASSOCIATED_BUSIF S_AXIL:S_AXIS_2:S_AXIS_1:M_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_1_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS_1, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_1_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_1 TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_2_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS_2, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_2_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_2 TVALID";
BEGIN
U0 : axis_mixer
GENERIC MAP (
WEIGHT_1 => 1,
DATA_WIDTH => 32,
HAS_AXI_LITE_IF => false,
WEIGHT_2 => 1,
FORCE_01_INPUT => false,
SHIFT_DEF => 0
)
PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY,
S_AXIS_1_TVALID => S_AXIS_1_TVALID,
S_AXIS_1_TDATA => S_AXIS_1_TDATA,
S_AXIS_1_TREADY => S_AXIS_1_TREADY,
S_AXIS_2_TVALID => S_AXIS_2_TVALID,
S_AXIS_2_TDATA => S_AXIS_2_TDATA,
S_AXIS_2_TREADY => S_AXIS_2_TREADY,
S_AXIL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
S_AXIL_AWVALID => '0',
S_AXIL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXIL_WVALID => '0',
S_AXIL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXIL_BREADY => '1',
S_AXIL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
S_AXIL_ARVALID => '0',
S_AXIL_RREADY => '1'
);
END axis_master_test_axis_mixer_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/axis_master_test_axis_numeric_master_0_0.xml
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/sim/axis_master_test_axis_numeric_master_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_numeric_master_slave_simmodel:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY axis_master_test_axis_numeric_master_0_0 IS
PORT (
CLK : OUT STD_LOGIC;
RESETN : OUT STD_LOGIC;
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END axis_master_test_axis_numeric_master_0_0;
ARCHITECTURE axis_master_test_axis_numeric_master_0_0_arch OF axis_master_test_axis_numeric_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_master_test_axis_numeric_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_numeric_master_slave_simmodel IS
GENERIC (
HAS_CLOCK_GENERATOR : BOOLEAN;
CLOCK_PERIOD_NS : INTEGER;
HAS_RESET_GENERATOR : BOOLEAN;
RESET_ACTIVE_CYCLES : INTEGER;
HAS_MASTER1 : BOOLEAN;
MASTER1_DATA_WIDTH : INTEGER;
MASTER1_RANDOM_VALID : BOOLEAN;
MASTER1_HAS_LAST : BOOLEAN;
MASTER1_LAST_PERIOD : INTEGER;
MASTER1_HAS_USER : BOOLEAN;
MASTER1_USER_PERIOD : INTEGER;
HAS_MASTER2 : BOOLEAN;
MASTER2_DATA_WIDTH : INTEGER;
MASTER2_RANDOM_VALID : BOOLEAN;
MASTER2_HAS_LAST : BOOLEAN;
MASTER2_LAST_PERIOD : INTEGER;
MASTER2_HAS_USER : BOOLEAN;
MASTER2_USER_PERIOD : INTEGER;
HAS_SLAVE : BOOLEAN;
SLAVE_DATA_WIDTH : INTEGER;
SLAVE_RANDOM_READY : BOOLEAN;
SLAVE_HAS_LAST : BOOLEAN;
SLAVE_HAS_USER : BOOLEAN;
SLAVE_WAIT_FOR_SOF : BOOLEAN;
FILE_NAME_M1 : STRING;
FILE_NAME_M2 : STRING;
FILE_NAME_S : STRING;
HAS_RESETN_INPUT : BOOLEAN
);
PORT (
CLK : OUT STD_LOGIC;
RESETN : OUT STD_LOGIC;
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axis_numeric_master_slave_simmodel;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RESETN, ASSOCIATED_BUSIF S_AXIS:M2_AXIS:M1_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF M1_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M1_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF M2_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M2_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M2_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M2_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axis_master_test_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_numeric_master_slave_simmodel
GENERIC MAP (
HAS_CLOCK_GENERATOR => true,
CLOCK_PERIOD_NS => 10,
HAS_RESET_GENERATOR => true,
RESET_ACTIVE_CYCLES => 100,
HAS_MASTER1 => true,
MASTER1_DATA_WIDTH => 32,
MASTER1_RANDOM_VALID => true,
MASTER1_HAS_LAST => false,
MASTER1_LAST_PERIOD => 100,
MASTER1_HAS_USER => false,
MASTER1_USER_PERIOD => 1000,
HAS_MASTER2 => true,
MASTER2_DATA_WIDTH => 32,
MASTER2_RANDOM_VALID => true,
MASTER2_HAS_LAST => false,
MASTER2_LAST_PERIOD => 100,
MASTER2_HAS_USER => false,
MASTER2_USER_PERIOD => 1000,
HAS_SLAVE => true,
SLAVE_DATA_WIDTH => 32,
SLAVE_RANDOM_READY => true,
SLAVE_HAS_LAST => false,
SLAVE_HAS_USER => false,
SLAVE_WAIT_FOR_SOF => false,
FILE_NAME_M1 => "../../../../mstr1.txt",
FILE_NAME_M2 => "../../../../mstr2.txt",
FILE_NAME_S => "../../../../slv.txt",
HAS_RESETN_INPUT => false
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
ACLK => '0',
ARESETN => '1',
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TREADY => M1_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TUSER => M1_AXIS_TUSER,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TREADY => M2_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TUSER => M2_AXIS_TUSER,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TUSER => S_AXIS_TUSER
);
END axis_master_test_axis_numeric_master_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c104/sources_1/new/axis_mixer.vhd
-240
View File
@@ -1,240 +0,0 @@
------------------------------------------------------------------------------
-- axis_mixer.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2020, update 2022
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axis_mixer is
generic
(
HAS_AXI_LITE_IF : boolean := false;
FORCE_01_INPUT : boolean := false;
WEIGHT_1 : positive := 1;
WEIGHT_2 : positive := 1;
SHIFT_DEF : integer := 0;
DATA_WIDTH : integer := 16
);
port
(
ACLK : in std_logic;
ARESETN : in std_logic;
-- AXIS Master
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic := '1';
-- AXIS Slave 1
S_AXIS_1_TVALID : in std_logic := '1';
S_AXIS_1_TDATA : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
S_AXIS_1_TREADY : out std_logic;
-- AXIS Slave 2
S_AXIS_2_TVALID : in std_logic := '1';
S_AXIS_2_TDATA : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
S_AXIS_2_TREADY : out std_logic;
-- AXIL Interface
S_AXIL_AWADDR : in std_logic_vector(15 downto 0) := (others=>'0');
S_AXIL_AWVALID : in std_logic := '0';
S_AXIL_AWREADY : out std_logic;
S_AXIL_WDATA : in std_logic_vector(31 downto 0) := (others=>'0');
S_AXIL_WVALID : in std_logic := '0';
S_AXIL_WREADY : out std_logic;
S_AXIL_WSTRB : in std_logic_vector( 3 downto 0) := (others=>'0');
S_AXIL_BVALID : out std_logic;
S_AXIL_BREADY : in std_logic := '1';
S_AXIL_BRESP : out std_logic_vector( 1 downto 0);
S_AXIL_ARADDR : in std_logic_vector(15 downto 0) := (others=>'0');
S_AXIL_ARVALID : in std_logic := '0';
S_AXIL_ARREADY : out std_logic;
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
S_AXIL_RVALID : out std_logic;
S_AXIL_RREADY : in std_logic := '1';
S_AXIL_RRESP : out std_logic_vector( 1 downto 0)
);
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of axis_mixer is
signal weight1 : signed(8 downto 0) := to_signed(WEIGHT_1,9);
signal weight2 : signed(8 downto 0) := to_signed(WEIGHT_2,9);
signal shift : unsigned(3 downto 0) := to_unsigned(SHIFT_DEF,4);
begin
process
variable datain1 : signed(DATA_WIDTH-1 downto 0);
variable datain2 : signed(DATA_WIDTH-1 downto 0);
variable tmp2 : signed(DATA_WIDTH-1+9 downto 0);
variable tmp1 : signed(DATA_WIDTH-1+9 downto 0);
variable res : signed(DATA_WIDTH-1+10 downto 0);
variable shift_i : integer;
variable tmp1_valid : boolean := false;
variable tmp2_valid : boolean := false;
variable out_valid : boolean := false;
begin
wait until rising_edge(ACLK);
if ARESETN = '0' then
M_AXIS_TVALID <= '0';
S_AXIS_1_TREADY <= '0';
S_AXIS_2_TREADY <= '0';
tmp1 := to_signed(0,DATA_WIDTH+9);
tmp2 := to_signed(0,DATA_WIDTH+9);
tmp1_valid := false;
tmp2_valid := false;
out_valid := false;
else
-- nur für Simulation: Falls U,X etc am Eingang, 0 weitergeben
-- synthesis translate_off
if FORCE_01_INPUT then
for i in DATA_WIDTH-1 downto 0 loop
if S_AXIS_1_TDATA(i) = '1' then
datain1(i) := '1';
else
datain1(i) := '0';
end if;
if S_AXIS_2_TDATA(i) = '1' then
datain2(i) := '1';
else
datain2(i) := '0';
end if;
end loop;
end if;
-- synthesis translate_on
-- Datenpuffer tmp1 frei? Dann: ready = 1 und ggf. Daten übernehmen
if not tmp1_valid then
S_AXIS_1_TREADY <= '1';
if S_AXIS_1_TVALID = '1' then
tmp1 := signed(S_AXIS_1_TDATA)*weight1;
tmp1_valid := true;
-- Datenpuffer gefüllt, weitere Daten können nicht übernommen werden
-- Falls die Daten konsumiert werden, wird ready unten wieder auf 1 gesetzt
S_AXIS_1_TREADY <= '0';
end if;
end if;
-- Datenpuffer tmp2 frei? Dann: ready = 1 und ggf. Daten übernehmen
if not tmp2_valid then
S_AXIS_2_TREADY <= '1';
if S_AXIS_2_TVALID = '1' then
tmp2 := signed(S_AXIS_2_TDATA)*weight2;
tmp2_valid := true;
-- Datenpuffer gefüllt, weitere Daten können nicht übernommen werden
-- Falls die Daten konsumiert werden, wird ready unten wieder auf 1 gesetzt
S_AXIS_2_TREADY <= '0';
end if;
end if;
-- Ausgangsdaten übernommen? Dann: keine neuen Daten verfügbar (valid=0)
-- Falls in diesem Taktzyklus neue Ausgangsdaten produziert werden,
-- wird valid unten wieder auf 1 gesetzt
if M_AXIS_TREADY = '1' then
M_AXIS_TVALID <= '0';
out_valid := false;
end if;
-- Datenpuffer tmp1 UND tmp2 haben gültige Daten UND Ausgangspuffer ist frei?
-- Dann: neue Ausgangsdaten produzieren
if tmp1_valid and tmp2_valid and (not out_valid) then
-- Daten aus Eingangspuffer sind konsumiert
-- Daher: Pufferinhalt als ungültig markieren UND Epmfangsbereitschaft signalisieren
tmp1_valid := false;
tmp2_valid := false;
S_AXIS_1_TREADY <= '1';
S_AXIS_2_TREADY <= '1';
-- Neue Ausgangsdaten bereitstellen und als gültig markieren
res := (tmp1(DATA_WIDTH-1+9)&tmp1)+(tmp2(DATA_WIDTH-1+9)&tmp2);
shift_i := to_integer(shift);
if shift_i > 10 then shift_i := 10; end if;
M_AXIS_TDATA <= std_logic_vector(res(DATA_WIDTH-1+shift_i downto shift_i));
M_AXIS_TVALID <= '1';
out_valid := true;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- AXIL
--------------------------------------------------------------------------------------------------
S_AXIL_BRESP <= (others=>'0'); -- No write errors
S_AXIL_RRESP <= (others=>'0'); -- No read errors
S_AXIL_ARREADY <= '1'; -- IP is always ready
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
axilgen: if HAS_AXI_LITE_IF generate
process begin
wait until rising_edge (ACLK);
if ARESETN = '0' then
S_AXIL_BVALID <= '0';
S_AXIL_RVALID <= '0';
weight1 <= to_signed(WEIGHT_1,9);
weight2 <= to_signed(WEIGHT_2,9);
shift <= to_unsigned(8,4);
else
if S_AXIL_RREADY = '1' then
S_AXIL_RVALID <= '0';
end if;
if S_AXIL_ARVALID = '1' then
S_AXIL_RDATA <= (others=>'0');
case S_AXIL_ARADDR(3 downto 2) is
when "00" => S_AXIL_RDATA(7 downto 0) <= std_logic_vector(weight1(7 downto 0));
when "01" => S_AXIL_RDATA(7 downto 0) <= std_logic_vector(weight2(7 downto 0));
when "10" => S_AXIL_RDATA(3 downto 0) <= std_logic_vector(shift);
when others => null;
end case;
S_AXIL_RVALID <= '1';
end if;
if S_AXIL_BREADY = '1' then
S_AXIL_BVALID <= '0';
end if;
if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
S_AXIL_BVALID <= '1';
case S_AXIL_ARADDR(3 downto 2) is
when "00" =>
if S_AXIL_WSTRB(0) = '1' then
weight1(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0));
end if;
when "01" =>
if S_AXIL_WSTRB(0) = '1' then
weight2(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0));
end if;
when "11" =>
if S_AXIL_WSTRB(0) = '1' then
shift(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0));
end if;
when others => null;
end case;
end if;
end if;
end process;
end generate;
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd
-362
View File
@@ -1,362 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_c_pkg_tb.all;
entity axis_numeric_master_slave_simmodel is
generic
(
HAS_CLOCK_GENERATOR : boolean := true;
CLOCK_PERIOD_NS : integer := 10;
HAS_RESET_GENERATOR : boolean := true;
HAS_RESETN_INPUT : boolean := false;
RESET_ACTIVE_CYCLES : integer := 100;
HAS_MASTER1 : boolean := true;
FILE_NAME_M1 : string := string'("../../../../m1.txt");
MASTER1_DATA_WIDTH : integer := 32;
MASTER1_RANDOM_VALID : boolean := true;
MASTER1_HAS_LAST : boolean := true;
MASTER1_LAST_PERIOD : integer := 100;
MASTER1_HAS_USER : boolean := true;
MASTER1_USER_PERIOD : integer := 1000;
HAS_MASTER2 : boolean := true;
FILE_NAME_M2 : string := string'("../../../../m1.txt");
MASTER2_DATA_WIDTH : integer := 32;
MASTER2_RANDOM_VALID : boolean := true;
MASTER2_HAS_LAST : boolean := true;
MASTER2_LAST_PERIOD : integer := 100;
MASTER2_HAS_USER : boolean := true;
MASTER2_USER_PERIOD : integer := 1000;
HAS_SLAVE : boolean := true;
FILE_NAME_S : string := string'("../../../../m1.txt");
SLAVE_DATA_WIDTH : integer := 32;
SLAVE_RANDOM_READY : boolean := true;
SLAVE_HAS_LAST : boolean := true;
SLAVE_HAS_USER : boolean := true;
SLAVE_WAIT_FOR_SOF : boolean := true
);
port
(
CLK : out std_logic := '0';
RESETN : out std_logic := '1';
ACLK : in std_logic := '0';
ARESETN : in std_logic := '1';
M1_AXIS_TVALID : out std_logic := '0';
M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0');
M1_AXIS_TREADY : in std_logic := '1';
M1_AXIS_TLAST : out std_logic := '0';
M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
M2_AXIS_TVALID : out std_logic := '0';
M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0');
M2_AXIS_TREADY : in std_logic := '1';
M2_AXIS_TLAST : out std_logic := '0';
M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
S_AXIS_TVALID : in std_logic := '0';
S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0);
S_AXIS_TREADY : out std_logic;
S_AXIS_TLAST : in std_logic := '0';
S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0')
);
end;
architecture sim of axis_numeric_master_slave_simmodel is
signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA";
signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF";
signal rnd_s : unsigned (31 downto 0) := x"12345678";
signal lclk : std_logic := '0';
signal local_clk : std_logic := ACLK;
signal local_resetn : std_logic := '1';
signal DBG_M1_FILERELOAD : std_logic := '0';
signal DBG_M2_FILERELOAD : std_logic := '0';
signal DBG_S_FILERELOAD : std_logic := '0';
begin
-- synthesis translate_off
-- translate off
----------------------------------------
-- Clock Generator
----------------------------------------
genclk: if HAS_CLOCK_GENERATOR generate
lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns;
CLK <= lclk;
local_clk <= lclk;
end generate;
no_genclk: if not HAS_CLOCK_GENERATOR generate
local_clk <= ACLK;
end generate;
----------------------------------------
-- Reset Generator
----------------------------------------
genreset: if HAS_RESET_GENERATOR generate
process begin
RESETN <= '0';
local_resetn <= '0';
for i in 1 to RESET_ACTIVE_CYCLES loop
wait until rising_edge(local_clk);
end loop;
RESETN <= '1';
local_resetn <= '1';
wait;
end process;
end generate;
no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate
local_resetn <= ARESETN;
end generate;
----------------------------------------
-- Random Number Generator
----------------------------------------
-- uint32_t xorshift32() {
-- static uint32_t x = 314159265;
-- x ^= x << 13;
-- x ^= x >> 17;
-- x ^= x << 5;
-- return x;
-- }
rnd: process
variable r : unsigned (31 downto 0);
begin
wait until rising_edge(local_clk);
r := rnd_m1;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd_m1 <= r;
r := rnd_m2;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd_m2 <= r;
r := rnd_s;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd_s <= r;
end process;
----------------------------------------
-- Master 1
----------------------------------------
genmaster1: if HAS_MASTER1 generate
m1: process
variable fp : CFILE := 0;
variable data : std_logic_vector(31 downto 0);
variable rnd : integer;
variable data_cnt_last : integer := 1;
variable data_cnt_user : integer := 1;
variable valid_out : std_logic := '0';
begin
wait until rising_edge (local_clk);
DBG_M1_FILERELOAD <= '0';
if (local_resetn = '0') then
valid_out := '0';
M1_AXIS_TVALID <= '0';
M1_AXIS_TDATA <= (others=>'0');
if fp > 0 then
fclose(fp);
end if;
else
if fp > 0 then
fclose(fp);
fp := 0;
end if;
fp := fopen(FILE_NAME_M1, "r");
if fp = 0 then
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1);
wait;
end if;
while not feof(fp) loop
valid_out := '1';
fscanf(fp, string'("%x"), data);
M1_AXIS_TVALID <= '1';
M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0);
M1_AXIS_TLAST <= '0';
M1_AXIS_TUSER(0) <= '0';
if data_cnt_last >= MASTER1_LAST_PERIOD then
M1_AXIS_TLAST <= '1';
data_cnt_last := 0;
end if;
if data_cnt_user >= MASTER1_USER_PERIOD then
M1_AXIS_TUSER(0) <= '1';
data_cnt_user := 0;
end if;
data_cnt_last := data_cnt_last + 1;
data_cnt_user := data_cnt_user + 1;
wait until rising_edge (local_clk);
while M1_AXIS_TREADY /= '1' loop
wait until rising_edge (local_clk);
end loop;
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
if (rnd>0 and MASTER1_RANDOM_VALID) then
M1_AXIS_TVALID <= '0';
for i in 0 to rnd loop
wait until rising_edge (local_clk);
end loop;
end if;
end loop;
M1_AXIS_TVALID <= '0';
DBG_M1_FILERELOAD <= '1';
end if;
end process;
end generate;
----------------------------------------
-- Master 2
----------------------------------------
genmaster2: if HAS_MASTER2 generate
m2: process
variable fp : CFILE := 0;
variable data : std_logic_vector(31 downto 0);
variable rnd : integer;
variable data_cnt_last : integer := 1;
variable data_cnt_user : integer := 1;
variable valid_out : std_logic := '0';
begin
wait until rising_edge (local_clk);
DBG_M1_FILERELOAD <= '0';
if (local_resetn = '0') then
valid_out := '0';
M2_AXIS_TVALID <= '0';
M2_AXIS_TDATA <= (others=>'0');
if fp > 0 then
fclose(fp);
end if;
else
if fp > 0 then
fclose(fp);
fp := 0;
end if;
fp := fopen(FILE_NAME_M2, "r");
if fp = 0 then
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2);
wait;
end if;
while not feof(fp) loop
valid_out := '1';
fscanf(fp, string'("%x"), data);
M2_AXIS_TVALID <= '1';
M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0);
M2_AXIS_TLAST <= '0';
M2_AXIS_TUSER(0) <= '0';
if data_cnt_last >= MASTER2_LAST_PERIOD then
M2_AXIS_TLAST <= '1';
data_cnt_last := 0;
end if;
if data_cnt_user >= MASTER1_USER_PERIOD then
M2_AXIS_TUSER(0) <= '1';
data_cnt_user := 0;
end if;
data_cnt_last := data_cnt_last + 1;
data_cnt_user := data_cnt_user + 1;
wait until rising_edge (local_clk);
while M2_AXIS_TREADY /= '1' loop
wait until rising_edge (local_clk);
end loop;
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
if (rnd>0 and MASTER2_RANDOM_VALID) then
M2_AXIS_TVALID <= '0';
for i in 0 to rnd loop
wait until rising_edge (local_clk);
end loop;
end if;
end loop;
M2_AXIS_TVALID <= '0';
DBG_M2_FILERELOAD <= '1';
end if;
end process;
end generate;
----------------------------------------
-- SLAVE
----------------------------------------
genslave: if HAS_SLAVE generate
s: process
variable fp : CFILE := 0;
variable data : std_logic_vector(31 downto 0) := (others=>'0');
variable rnd : integer;
variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
begin
wait until rising_edge (local_clk);
DBG_S_FILERELOAD <= '0';
if (local_resetn = '0') then
S_AXIS_TREADY <= '0';
if fp > 0 then
fclose(fp);
end if;
wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
elsif wait_sof then
if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then
wait_sof := false;
end if;
else
if fp > 0 then
fclose(fp);
fp := 0;
end if;
fp := fopen(FILE_NAME_S, "r");
if fp = 0 then
printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S);
end if;
while not feof(fp) and fp /= 0 loop
S_AXIS_TREADY <= '1';
wait until rising_edge (local_clk);
while S_AXIS_TVALID /= '1' loop
wait until rising_edge (local_clk);
end loop;
if fp > 0 then
fscanf(fp, string'("%x"), data);
if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then
printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA);
end if;
end if;
rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length));
if (rnd>0 and SLAVE_RANDOM_READY) then
S_AXIS_TREADY <= '0';
for i in 0 to rnd loop
wait until rising_edge (local_clk);
end loop;
end if;
end loop;
S_AXIS_TREADY <= '0';
DBG_S_FILERELOAD <= '1';
end if;
end process;
end generate;
-- synthesis translate_on
-- translate on
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axis_master_test/ipshared/c6f6/vhdl_c_pkg_tb.vhd
-2604
View File
File diff suppressed because it is too large Load Diff
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/component.xml
+915
View File
@@ -0,0 +1,915 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>module_ref</spirit:library>
<spirit:name>axi3_slave_verif</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>S_AXI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWLEN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWSIZE</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWBURST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WSTRB</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_BRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_BVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_BREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARLEN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARSIZE</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARBURST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>RESETN</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>RESETN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>CLK</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>CLK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">RESETN</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>S_AXI</spirit:name>
<spirit:displayName>S_AXI</spirit:displayName>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:displayName>reg0</spirit:displayName>
<spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
<spirit:range spirit:format="bitString" spirit:bitStringLength="33" spirit:minimum="4096" spirit:rangeType="long">0x100000000</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DWIDTH&apos;)) - 1) - 0 + 1">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>VHDL</spirit:language>
<spirit:modelName>axi3_slave_verif</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>6d6387c1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>VHDL</spirit:language>
<spirit:modelName>axi3_slave_verif</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>6d6387c1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>CLK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>RESETN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IDWIDTH&apos;)) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARLEN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARSIZE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARBURST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RDATA</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DWIDTH&apos;)) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.IDWIDTH&apos;)) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RLAST</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWLEN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWSIZE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWBURST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WDATA</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.DWIDTH&apos;)) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WSTRB</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.DWIDTH&apos;)) / 8) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WLAST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_BVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_BREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_BRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>DWIDTH</spirit:name>
<spirit:displayName>Dwidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DWIDTH" spirit:minimum="0">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>IDWIDTH</spirit:name>
<spirit:displayName>Idwidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.IDWIDTH" spirit:minimum="0">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>MAX_BURSTLEN</spirit:name>
<spirit:displayName>Max Burstlen</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0">16</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_74b5137e</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/axi3_slave_verif_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_dc83b24a</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axi3_slave_verif:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>DWIDTH</spirit:name>
<spirit:displayName>Dwidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DWIDTH" spirit:minimum="0" spirit:rangeType="long">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>IDWIDTH</spirit:name>
<spirit:displayName>Idwidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IDWIDTH" spirit:minimum="0" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MAX_BURSTLEN</spirit:name>
<spirit:displayName>Max Burstlen</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi3_slave_verif_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>axi3_slave_verif_v1_0</xilinx:displayName>
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
<xilinx:designToolContexts>
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-01T20:40:20Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axi3_slave_verif/xgui/axi3_slave_verif_v1_0.tcl
+55
View File
@@ -0,0 +1,55 @@
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0}
}
proc update_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
# Procedure called to update DWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
# Procedure called to validate DWIDTH
return true
}
proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to validate IDWIDTH
return true
}
proc update_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to update MAX_BURSTLEN when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to validate MAX_BURSTLEN
return true
}
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DWIDTH}] ${MODELPARAM_VALUE.DWIDTH}
}
proc update_MODELPARAM_VALUE.IDWIDTH { MODELPARAM_VALUE.IDWIDTH PARAM_VALUE.IDWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IDWIDTH}] ${MODELPARAM_VALUE.IDWIDTH}
}
proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_VALUE.MAX_BURSTLEN } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN}
}
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_crc/component.xml
+3 -3
View File
@@ -145,7 +145,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>14047e48</spirit:value>
<spirit:value>b45c4280</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -158,7 +158,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>14047e48</spirit:value>
<spirit:value>b45c4280</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -395,7 +395,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-02-01T18:35:25Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-02-01T19:31:07Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/component.xml
+68 -4
View File
@@ -595,7 +595,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f22c6690</spirit:value>
<spirit:value>ba1cd223</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -608,7 +608,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f22c6690</spirit:value>
<spirit:value>ba1cd223</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -682,6 +682,40 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>FIFO_NUM_FREE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>FIFO_NUM_AVAIL</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXIL_AWADDR</spirit:name>
<spirit:wire>
@@ -1668,6 +1702,21 @@
<spirit:displayName>Max Burstlen</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0">16</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH" spirit:minimum="0">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>polynomial_default</spirit:name>
<spirit:displayName>Polynomial Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.polynomial_default" spirit:bitStringLength="32">0x04C11DB7</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>initial_value_default</spirit:name>
<spirit:displayName>Initial Value Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.initial_value_default" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
@@ -1683,7 +1732,7 @@
<spirit:file>
<spirit:name>xgui/axis_dma_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_dc83b24a</spirit:userFileType>
<spirit:userFileType>CHECKSUM_47a147b5</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
@@ -1705,6 +1754,21 @@
<spirit:displayName>Max Burstlen</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BURSTLEN" spirit:minimum="0" spirit:rangeType="long">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FIFO_AWIDTH</spirit:name>
<spirit:displayName>Fifo Awidth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:minimum="0" spirit:rangeType="long">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>polynomial_default</spirit:name>
<spirit:displayName>Polynomial Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.polynomial_default" spirit:bitStringLength="32">0x04C11DB7</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>initial_value_default</spirit:name>
<spirit:displayName>Initial Value Default</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.initial_value_default" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_dma_v1_0</spirit:value>
@@ -1725,7 +1789,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2025-01-31T17:03:28Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2025-02-01T23:59:34Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/mref/axis_dma/xgui/axis_dma_v1_0.tcl
+45
View File
@@ -4,8 +4,11 @@ proc init_gui { IPINST } {
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "FIFO_AWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "IDWIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "MAX_BURSTLEN" -parent ${Page_0}
ipgui::add_param $IPINST -name "initial_value_default" -parent ${Page_0}
ipgui::add_param $IPINST -name "polynomial_default" -parent ${Page_0}
}
@@ -19,6 +22,15 @@ proc validate_PARAM_VALUE.DWIDTH { PARAM_VALUE.DWIDTH } {
return true
}
proc update_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to update FIFO_AWIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FIFO_AWIDTH { PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to validate FIFO_AWIDTH
return true
}
proc update_PARAM_VALUE.IDWIDTH { PARAM_VALUE.IDWIDTH } {
# Procedure called to update IDWIDTH when any of the dependent parameters in the arguments change
}
@@ -37,6 +49,24 @@ proc validate_PARAM_VALUE.MAX_BURSTLEN { PARAM_VALUE.MAX_BURSTLEN } {
return true
}
proc update_PARAM_VALUE.initial_value_default { PARAM_VALUE.initial_value_default } {
# Procedure called to update initial_value_default when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.initial_value_default { PARAM_VALUE.initial_value_default } {
# Procedure called to validate initial_value_default
return true
}
proc update_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } {
# Procedure called to update polynomial_default when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.polynomial_default { PARAM_VALUE.polynomial_default } {
# Procedure called to validate polynomial_default
return true
}
proc update_MODELPARAM_VALUE.DWIDTH { MODELPARAM_VALUE.DWIDTH PARAM_VALUE.DWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
@@ -53,3 +83,18 @@ proc update_MODELPARAM_VALUE.MAX_BURSTLEN { MODELPARAM_VALUE.MAX_BURSTLEN PARAM_
set_property value [get_property value ${PARAM_VALUE.MAX_BURSTLEN}] ${MODELPARAM_VALUE.MAX_BURSTLEN}
}
proc update_MODELPARAM_VALUE.FIFO_AWIDTH { MODELPARAM_VALUE.FIFO_AWIDTH PARAM_VALUE.FIFO_AWIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FIFO_AWIDTH}] ${MODELPARAM_VALUE.FIFO_AWIDTH}
}
proc update_MODELPARAM_VALUE.polynomial_default { MODELPARAM_VALUE.polynomial_default PARAM_VALUE.polynomial_default } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.polynomial_default}] ${MODELPARAM_VALUE.polynomial_default}
}
proc update_MODELPARAM_VALUE.initial_value_default { MODELPARAM_VALUE.initial_value_default PARAM_VALUE.initial_value_default } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.initial_value_default}] ${MODELPARAM_VALUE.initial_value_default}
}
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/hdl/test_1_wrapper.vhd
-24
View File
@@ -1,24 +0,0 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sat Feb 1 18:39:19 2025
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target test_1_wrapper.bd
--Design : test_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity test_1_wrapper is
end test_1_wrapper;
architecture STRUCTURE of test_1_wrapper is
component test_1 is
end component test_1;
begin
test_1_i: component test_1
;
end STRUCTURE;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/test_1_axis_crc_0_0.xml
-669
View File
@@ -1,669 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>test_1_axis_crc_0_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>M_AXIS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>M_AXIS_TREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>TDATA_NUM_BYTES</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TDEST_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TREADY</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TKEEP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TLAST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S_AXIS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXIS_TREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>TDATA_NUM_BYTES</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TDEST_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>TUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TREADY</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TKEEP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_TLAST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>LAYERED_METADATA</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>RESETN</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>RESETN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>CLK</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>CLK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">RESETN</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>CLK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>RESETN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>initial_value</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>polynomial</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:name>S_AXIS_TDATA</spirit:name>
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<spirit:left spirit:format="long">31</spirit:left>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TLAST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXIS_TREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:port>
<spirit:name>M_AXIS_TVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>M_AXIS_TDATA</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
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<spirit:port>
<spirit:name>M_AXIS_TLAST</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
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</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>M_AXIS_TREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">test_1_axis_crc_0_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>axis_crc_v1_0</xilinx:displayName>
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/sim/test_1_axis_numeric_master_0_0.vhd
-196
View File
@@ -1,196 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_numeric_master_slave_simmodel:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test_1_axis_numeric_master_0_0 IS
PORT (
CLK : OUT STD_LOGIC;
RESETN : OUT STD_LOGIC;
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END test_1_axis_numeric_master_0_0;
ARCHITECTURE test_1_axis_numeric_master_0_0_arch OF test_1_axis_numeric_master_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF test_1_axis_numeric_master_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_numeric_master_slave_simmodel IS
GENERIC (
HAS_CLOCK_GENERATOR : BOOLEAN;
CLOCK_PERIOD_NS : INTEGER;
HAS_RESET_GENERATOR : BOOLEAN;
RESET_ACTIVE_CYCLES : INTEGER;
HAS_MASTER1 : BOOLEAN;
MASTER1_DATA_WIDTH : INTEGER;
MASTER1_RANDOM_VALID : BOOLEAN;
MASTER1_HAS_LAST : BOOLEAN;
MASTER1_LAST_PERIOD : INTEGER;
MASTER1_HAS_USER : BOOLEAN;
MASTER1_USER_PERIOD : INTEGER;
HAS_MASTER2 : BOOLEAN;
MASTER2_DATA_WIDTH : INTEGER;
MASTER2_RANDOM_VALID : BOOLEAN;
MASTER2_HAS_LAST : BOOLEAN;
MASTER2_LAST_PERIOD : INTEGER;
MASTER2_HAS_USER : BOOLEAN;
MASTER2_USER_PERIOD : INTEGER;
HAS_SLAVE : BOOLEAN;
SLAVE_DATA_WIDTH : INTEGER;
SLAVE_RANDOM_READY : BOOLEAN;
SLAVE_HAS_LAST : BOOLEAN;
SLAVE_HAS_USER : BOOLEAN;
SLAVE_WAIT_FOR_SOF : BOOLEAN;
FILE_NAME_M1 : STRING;
FILE_NAME_M2 : STRING;
FILE_NAME_S : STRING;
HAS_RESETN_INPUT : BOOLEAN
);
PORT (
CLK : OUT STD_LOGIC;
RESETN : OUT STD_LOGIC;
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axis_numeric_master_slave_simmodel;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RESETN, ASSOCIATED_BUSIF S_AXIS:M2_AXIS:M1_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF M1_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M1_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M1_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M1_AXIS TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN test_1_axis_numeric_master_0_0_CLK, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_numeric_master_slave_simmodel
GENERIC MAP (
HAS_CLOCK_GENERATOR => true,
CLOCK_PERIOD_NS => 10,
HAS_RESET_GENERATOR => true,
RESET_ACTIVE_CYCLES => 100,
HAS_MASTER1 => true,
MASTER1_DATA_WIDTH => 32,
MASTER1_RANDOM_VALID => true,
MASTER1_HAS_LAST => true,
MASTER1_LAST_PERIOD => 100,
MASTER1_HAS_USER => false,
MASTER1_USER_PERIOD => 1000,
HAS_MASTER2 => false,
MASTER2_DATA_WIDTH => 32,
MASTER2_RANDOM_VALID => true,
MASTER2_HAS_LAST => false,
MASTER2_LAST_PERIOD => 100,
MASTER2_HAS_USER => false,
MASTER2_USER_PERIOD => 1000,
HAS_SLAVE => true,
SLAVE_DATA_WIDTH => 32,
SLAVE_RANDOM_READY => true,
SLAVE_HAS_LAST => true,
SLAVE_HAS_USER => false,
SLAVE_WAIT_FOR_SOF => false,
FILE_NAME_M1 => "../../../../m1.txt",
FILE_NAME_M2 => "../../../../m1.txt",
FILE_NAME_S => "../../../../m1.txt",
HAS_RESETN_INPUT => false
)
PORT MAP (
CLK => CLK,
RESETN => RESETN,
ACLK => '0',
ARESETN => '1',
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TREADY => M1_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TUSER => M1_AXIS_TUSER,
M2_AXIS_TREADY => '1',
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TUSER => S_AXIS_TUSER
);
END test_1_axis_numeric_master_0_0_arch;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/test_1_axis_numeric_master_0_0.xml
-1838
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0.h
-65
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@@ -1,65 +0,0 @@
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _test_1_xlconstant_0_0_H_
#define _test_1_xlconstant_0_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class test_1_xlconstant_0_0 : public sc_module {
public:
xlconstant_v1_1_7<32,0> mod;
sc_out< sc_bv<32> > dout;
test_1_xlconstant_0_0 (sc_core::sc_module_name name);
};
#endif
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/test_1_xlconstant_0_0_stub.sv
-79
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@@ -1,79 +0,0 @@
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
//------------------------------------------------------------------------------------
// Filename: xl_Constant_stub.sv
// Description: This HDL file is intended to be used with following simulators only:
//
// Vivado Simulator (XSim)
// Cadence Xcelium Simulator
//
//------------------------------------------------------------------------------------
`ifdef XILINX_SIMULATOR
`ifndef XILINX_SIMULATOR_BITASBOOL
`define XILINX_SIMULATOR_BITASBOOL
typedef bit bit_as_bool;
`endif
(* SC_MODULE_EXPORT *)
module test_1_xlconstant_0_0 (
output bit [31 : 0 ] dout
);
endmodule
`endif
`ifdef XCELIUM
(* XMSC_MODULE_EXPORT *)
module test_1_xlconstant_0_0 (dout)
(* integer foreign = "SystemC";
*);
output wire [31 : 0 ] dout;
endmodule
`endif
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/sim/xlconstant_v1_1_7.h
-69
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@@ -1,69 +0,0 @@
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _xlconstant_v1_1_7_H_
#define _xlconstant_v1_1_7_H_
#include "systemc.h"
template<int CONST_WIDTH,long int CONST_VAL>
SC_MODULE(xlconstant_v1_1_7) {
public:
sc_out< sc_bv<CONST_WIDTH> > dout;
void init() {
dout.write(CONST_VAL);
}
SC_CTOR(xlconstant_v1_1_7) {
SC_METHOD(init);
}
};
#endif
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xml
-206
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@@ -1,206 +0,0 @@
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Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0.h
-65
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@@ -1,65 +0,0 @@
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _test_1_xlconstant_1_0_H_
#define _test_1_xlconstant_1_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class test_1_xlconstant_1_0 : public sc_module {
public:
xlconstant_v1_1_7<32,0> mod;
sc_out< sc_bv<32> > dout;
test_1_xlconstant_1_0 (sc_core::sc_module_name name);
};
#endif
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/test_1_xlconstant_1_0_stub.sv
-79
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@@ -1,79 +0,0 @@
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
//------------------------------------------------------------------------------------
// Filename: xl_Constant_stub.sv
// Description: This HDL file is intended to be used with following simulators only:
//
// Vivado Simulator (XSim)
// Cadence Xcelium Simulator
//
//------------------------------------------------------------------------------------
`ifdef XILINX_SIMULATOR
`ifndef XILINX_SIMULATOR_BITASBOOL
`define XILINX_SIMULATOR_BITASBOOL
typedef bit bit_as_bool;
`endif
(* SC_MODULE_EXPORT *)
module test_1_xlconstant_1_0 (
output bit [31 : 0 ] dout
);
endmodule
`endif
`ifdef XCELIUM
(* XMSC_MODULE_EXPORT *)
module test_1_xlconstant_1_0 (dout)
(* integer foreign = "SystemC";
*);
output wire [31 : 0 ] dout;
endmodule
`endif
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/sim/xlconstant_v1_1_7.h
-69
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@@ -1,69 +0,0 @@
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _xlconstant_v1_1_7_H_
#define _xlconstant_v1_1_7_H_
#include "systemc.h"
template<int CONST_WIDTH,long int CONST_VAL>
SC_MODULE(xlconstant_v1_1_7) {
public:
sc_out< sc_bv<CONST_WIDTH> > dout;
void init() {
dout.write(CONST_VAL);
}
SC_CTOR(xlconstant_v1_1_7) {
SC_METHOD(init);
}
};
#endif
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xml
-206
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@@ -1,206 +0,0 @@
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</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 17:07:49 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:8609d079</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>tlm</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 16:15:06 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:8609d079</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>test_1_xlconstant_1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sat Feb 01 17:07:49 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:8609d079</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>dout</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
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<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>CONST_WIDTH</spirit:name>
<spirit:displayName>Const Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>CONST_VAL</spirit:name>
<spirit:displayName>Const Val</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/xlconstant_v1_1_7.h</spirit:name>
<spirit:fileType>systemCSource</spirit:fileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/test_1_xlconstant_1_0.h</spirit:name>
<spirit:fileType>systemCSource</spirit:fileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>sim/test_1_xlconstant_1_0.cpp</spirit:name>
<spirit:fileType>systemCSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>sim/test_1_xlconstant_1_0_stub.sv</spirit:name>
<spirit:fileType>systemVerilogSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xlconstant_v1_1_7</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/test_1_xlconstant_1_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Gives a constant signed value.</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">test_1_xlconstant_1_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CONST_WIDTH</spirit:name>
<spirit:displayName>Const Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CONST_VAL</spirit:name>
<spirit:displayName>Const Val</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>Constant</xilinx:displayName>
<xilinx:coreRevision>7</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="412efde3"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/b0f2/hdl/xlconstant_v1_1_vl_rfs.v
-31
View File
@@ -1,31 +0,0 @@
//------------------------------------------------------------------------
//--
//-- Filename : xlconstant.v
//--
//-- Date : 06/05/12
//--
//-- Description : VERILOG description of a constant block. This
//-- block does not use a core.
//--
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//--
//-- Module : xlconstant
//--
//-- Architecture : behavior
//--
//-- Description : Top level VERILOG description of constant block
//--
//------------------------------------------------------------------------
`timescale 1ps/1ps
module xlconstant_v1_1_7_xlconstant (dout);
parameter CONST_VAL = 1;
parameter CONST_WIDTH = 1;
output [CONST_WIDTH-1:0] dout;
assign dout = CONST_VAL;
endmodule
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/axis_numeric_master_slave_simmodel.vhd
-362
View File
@@ -1,362 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_c_pkg_tb.all;
entity axis_numeric_master_slave_simmodel is
generic
(
HAS_CLOCK_GENERATOR : boolean := true;
CLOCK_PERIOD_NS : integer := 10;
HAS_RESET_GENERATOR : boolean := true;
HAS_RESETN_INPUT : boolean := false;
RESET_ACTIVE_CYCLES : integer := 100;
HAS_MASTER1 : boolean := true;
FILE_NAME_M1 : string := string'("../../../../m1.txt");
MASTER1_DATA_WIDTH : integer := 32;
MASTER1_RANDOM_VALID : boolean := true;
MASTER1_HAS_LAST : boolean := true;
MASTER1_LAST_PERIOD : integer := 100;
MASTER1_HAS_USER : boolean := true;
MASTER1_USER_PERIOD : integer := 1000;
HAS_MASTER2 : boolean := true;
FILE_NAME_M2 : string := string'("../../../../m1.txt");
MASTER2_DATA_WIDTH : integer := 32;
MASTER2_RANDOM_VALID : boolean := true;
MASTER2_HAS_LAST : boolean := true;
MASTER2_LAST_PERIOD : integer := 100;
MASTER2_HAS_USER : boolean := true;
MASTER2_USER_PERIOD : integer := 1000;
HAS_SLAVE : boolean := true;
FILE_NAME_S : string := string'("../../../../m1.txt");
SLAVE_DATA_WIDTH : integer := 32;
SLAVE_RANDOM_READY : boolean := true;
SLAVE_HAS_LAST : boolean := true;
SLAVE_HAS_USER : boolean := true;
SLAVE_WAIT_FOR_SOF : boolean := true
);
port
(
CLK : out std_logic := '0';
RESETN : out std_logic := '1';
ACLK : in std_logic := '0';
ARESETN : in std_logic := '1';
M1_AXIS_TVALID : out std_logic := '0';
M1_AXIS_TDATA : out std_logic_vector(MASTER1_DATA_WIDTH-1 downto 0):= (others=>'0');
M1_AXIS_TREADY : in std_logic := '1';
M1_AXIS_TLAST : out std_logic := '0';
M1_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
M2_AXIS_TVALID : out std_logic := '0';
M2_AXIS_TDATA : out std_logic_vector(MASTER2_DATA_WIDTH-1 downto 0) := (others=>'0');
M2_AXIS_TREADY : in std_logic := '1';
M2_AXIS_TLAST : out std_logic := '0';
M2_AXIS_TUSER : out std_logic_vector(0 downto 0):= (others=>'0');
S_AXIS_TVALID : in std_logic := '0';
S_AXIS_TDATA : in std_logic_vector(SLAVE_DATA_WIDTH-1 downto 0);
S_AXIS_TREADY : out std_logic;
S_AXIS_TLAST : in std_logic := '0';
S_AXIS_TUSER : in std_logic_vector(0 downto 0):= (others=>'0')
);
end;
architecture sim of axis_numeric_master_slave_simmodel is
signal rnd_m1 : unsigned (31 downto 0) := x"ABBAABBA";
signal rnd_m2 : unsigned (31 downto 0) := x"DEADBEEF";
signal rnd_s : unsigned (31 downto 0) := x"12345678";
signal lclk : std_logic := '0';
signal local_clk : std_logic := ACLK;
signal local_resetn : std_logic := '1';
signal DBG_M1_FILERELOAD : std_logic := '0';
signal DBG_M2_FILERELOAD : std_logic := '0';
signal DBG_S_FILERELOAD : std_logic := '0';
begin
-- synthesis translate_off
-- translate off
----------------------------------------
-- Clock Generator
----------------------------------------
genclk: if HAS_CLOCK_GENERATOR generate
lclk <= not lclk after CLOCK_PERIOD_NS * 0.5 ns;
CLK <= lclk;
local_clk <= lclk;
end generate;
no_genclk: if not HAS_CLOCK_GENERATOR generate
local_clk <= ACLK;
end generate;
----------------------------------------
-- Reset Generator
----------------------------------------
genreset: if HAS_RESET_GENERATOR generate
process begin
RESETN <= '0';
local_resetn <= '0';
for i in 1 to RESET_ACTIVE_CYCLES loop
wait until rising_edge(local_clk);
end loop;
RESETN <= '1';
local_resetn <= '1';
wait;
end process;
end generate;
no_genreset: if HAS_RESETN_INPUT and (not HAS_RESET_GENERATOR) generate
local_resetn <= ARESETN;
end generate;
----------------------------------------
-- Random Number Generator
----------------------------------------
-- uint32_t xorshift32() {
-- static uint32_t x = 314159265;
-- x ^= x << 13;
-- x ^= x >> 17;
-- x ^= x << 5;
-- return x;
-- }
rnd: process
variable r : unsigned (31 downto 0);
begin
wait until rising_edge(local_clk);
r := rnd_m1;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd_m1 <= r;
r := rnd_m2;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd_m2 <= r;
r := rnd_s;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd_s <= r;
end process;
----------------------------------------
-- Master 1
----------------------------------------
genmaster1: if HAS_MASTER1 generate
m1: process
variable fp : CFILE := 0;
variable data : std_logic_vector(31 downto 0);
variable rnd : integer;
variable data_cnt_last : integer := 1;
variable data_cnt_user : integer := 1;
variable valid_out : std_logic := '0';
begin
wait until rising_edge (local_clk);
DBG_M1_FILERELOAD <= '0';
if (local_resetn = '0') then
valid_out := '0';
M1_AXIS_TVALID <= '0';
M1_AXIS_TDATA <= (others=>'0');
if fp > 0 then
fclose(fp);
end if;
else
if fp > 0 then
fclose(fp);
fp := 0;
end if;
fp := fopen(FILE_NAME_M1, "r");
if fp = 0 then
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master1 (%s).\n",FILE_NAME_M1);
wait;
end if;
while not feof(fp) loop
valid_out := '1';
fscanf(fp, string'("%x"), data);
M1_AXIS_TVALID <= '1';
M1_AXIS_TDATA <= data(MASTER1_DATA_WIDTH-1 downto 0);
M1_AXIS_TLAST <= '0';
M1_AXIS_TUSER(0) <= '0';
if data_cnt_last >= MASTER1_LAST_PERIOD then
M1_AXIS_TLAST <= '1';
data_cnt_last := 0;
end if;
if data_cnt_user >= MASTER1_USER_PERIOD then
M1_AXIS_TUSER(0) <= '1';
data_cnt_user := 0;
end if;
data_cnt_last := data_cnt_last + 1;
data_cnt_user := data_cnt_user + 1;
wait until rising_edge (local_clk);
while M1_AXIS_TREADY /= '1' loop
wait until rising_edge (local_clk);
end loop;
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
if (rnd>0 and MASTER1_RANDOM_VALID) then
M1_AXIS_TVALID <= '0';
for i in 0 to rnd loop
wait until rising_edge (local_clk);
end loop;
end if;
end loop;
M1_AXIS_TVALID <= '0';
DBG_M1_FILERELOAD <= '1';
end if;
end process;
end generate;
----------------------------------------
-- Master 2
----------------------------------------
genmaster2: if HAS_MASTER2 generate
m2: process
variable fp : CFILE := 0;
variable data : std_logic_vector(31 downto 0);
variable rnd : integer;
variable data_cnt_last : integer := 1;
variable data_cnt_user : integer := 1;
variable valid_out : std_logic := '0';
begin
wait until rising_edge (local_clk);
DBG_M1_FILERELOAD <= '0';
if (local_resetn = '0') then
valid_out := '0';
M2_AXIS_TVALID <= '0';
M2_AXIS_TDATA <= (others=>'0');
if fp > 0 then
fclose(fp);
end if;
else
if fp > 0 then
fclose(fp);
fp := 0;
end if;
fp := fopen(FILE_NAME_M2, "r");
if fp = 0 then
printf("*** Simulation Error *** => Cannot open stimuli file for AXIS-Master2 (%s).\n",FILE_NAME_M2);
wait;
end if;
while not feof(fp) loop
valid_out := '1';
fscanf(fp, string'("%x"), data);
M2_AXIS_TVALID <= '1';
M2_AXIS_TDATA <= data(MASTER2_DATA_WIDTH-1 downto 0);
M2_AXIS_TLAST <= '0';
M2_AXIS_TUSER(0) <= '0';
if data_cnt_last >= MASTER2_LAST_PERIOD then
M2_AXIS_TLAST <= '1';
data_cnt_last := 0;
end if;
if data_cnt_user >= MASTER1_USER_PERIOD then
M2_AXIS_TUSER(0) <= '1';
data_cnt_user := 0;
end if;
data_cnt_last := data_cnt_last + 1;
data_cnt_user := data_cnt_user + 1;
wait until rising_edge (local_clk);
while M2_AXIS_TREADY /= '1' loop
wait until rising_edge (local_clk);
end loop;
rnd := to_integer(rnd_m1 and to_unsigned(3,rnd_m1'length));
if (rnd>0 and MASTER2_RANDOM_VALID) then
M2_AXIS_TVALID <= '0';
for i in 0 to rnd loop
wait until rising_edge (local_clk);
end loop;
end if;
end loop;
M2_AXIS_TVALID <= '0';
DBG_M2_FILERELOAD <= '1';
end if;
end process;
end generate;
----------------------------------------
-- SLAVE
----------------------------------------
genslave: if HAS_SLAVE generate
s: process
variable fp : CFILE := 0;
variable data : std_logic_vector(31 downto 0) := (others=>'0');
variable rnd : integer;
variable wait_sof : boolean := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
begin
wait until rising_edge (local_clk);
DBG_S_FILERELOAD <= '0';
if (local_resetn = '0') then
S_AXIS_TREADY <= '0';
if fp > 0 then
fclose(fp);
end if;
wait_sof := SLAVE_WAIT_FOR_SOF and SLAVE_HAS_USER;
elsif wait_sof then
if S_AXIS_TVALID = '1' and S_AXIS_TUSER(0) = '1' then
wait_sof := false;
end if;
else
if fp > 0 then
fclose(fp);
fp := 0;
end if;
fp := fopen(FILE_NAME_S, "r");
if fp = 0 then
printf("*** Simulation Info *** => Cannot open stimuli file for AXIS-Slave (%s).\n",FILE_NAME_S);
end if;
while not feof(fp) and fp /= 0 loop
S_AXIS_TREADY <= '1';
wait until rising_edge (local_clk);
while S_AXIS_TVALID /= '1' loop
wait until rising_edge (local_clk);
end loop;
if fp > 0 then
fscanf(fp, string'("%x"), data);
if data(SLAVE_DATA_WIDTH-1 downto 0) /= S_AXIS_TDATA then
printf("*** Verification Error *** => expected %x - received %x\n",data(SLAVE_DATA_WIDTH-1 downto 0),S_AXIS_TDATA);
end if;
end if;
rnd := to_integer(rnd_s and to_unsigned(3,rnd_s'length));
if (rnd>0 and SLAVE_RANDOM_READY) then
S_AXIS_TREADY <= '0';
for i in 0 to rnd loop
wait until rising_edge (local_clk);
end loop;
end if;
end loop;
S_AXIS_TREADY <= '0';
DBG_S_FILERELOAD <= '1';
end if;
end process;
end generate;
-- synthesis translate_on
-- translate on
end;
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/ipshared/c6f6/vhdl_c_pkg_tb.vhd
-2604
View File
File diff suppressed because it is too large Load Diff
Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/test_1/test_1.bxml
-11
View File
@@ -1,11 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="test_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738434926"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1738434926"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738434926"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738434926"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/axi_crc_dma_sim_1.bd
+531 -311
View File
@@ -7,21 +7,19 @@
"name": "axi_crc_dma_sim_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2023.1"
"tool_version": "2023.1",
"validated": "true"
},
"design_tree": {
"axi_crc_dma": {
"axis_dma_0": "",
"axis_fifo_0": "",
"axis_fifo_1": "",
"crc": {
"axis_downsizer_0": "",
"axis_upsizer_0": "",
"axis_crc_0": ""
}
"axis_crc_0": "",
"axis_dma_0": ""
},
"axil_master_with_rom_0": "",
"clk_rst_generator_0": ""
"clk_rst_generator_0": "",
"axi3_slave_verif_0": ""
},
"components": {
"axi_crc_dma": {
@@ -30,6 +28,11 @@
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"M_AXI": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
}
},
"ports": {
@@ -43,6 +46,195 @@
}
},
"components": {
"axis_fifo_0": {
"vlnv": "Gehrke:user:axis_fifo:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_fifo_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_0_0\\axi_crc_dma_sim_1_axis_fifo_0_0.xci",
"inst_hier_path": "axi_crc_dma/axis_fifo_0",
"parameters": {
"FIFO_AWIDTH": {
"value": "8"
}
}
},
"axis_fifo_1": {
"vlnv": "Gehrke:user:axis_fifo:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_fifo_1_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_1_0\\axi_crc_dma_sim_1_axis_fifo_1_0.xci",
"inst_hier_path": "axi_crc_dma/axis_fifo_1",
"parameters": {
"FIFO_AWIDTH": {
"value": "8"
}
}
},
"axis_crc_0": {
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_crc_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_crc_0_0\\axi_crc_dma_sim_1_axis_crc_0_0.xci",
"inst_hier_path": "axi_crc_dma/axis_crc_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "axis_crc",
"boundary_crc": "0x0"
},
"interface_ports": {
"M_AXIS": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "4",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "M_AXIS_TDATA",
"direction": "O",
"left": "31",
"right": "0"
},
"TLAST": {
"physical_name": "M_AXIS_TLAST",
"direction": "O"
},
"TVALID": {
"physical_name": "M_AXIS_TVALID",
"direction": "O"
},
"TREADY": {
"physical_name": "M_AXIS_TREADY",
"direction": "I"
}
}
},
"S_AXIS": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "4",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "S_AXIS_TDATA",
"direction": "I",
"left": "31",
"right": "0"
},
"TLAST": {
"physical_name": "S_AXIS_TLAST",
"direction": "I"
},
"TVALID": {
"physical_name": "S_AXIS_TVALID",
"direction": "I"
},
"TREADY": {
"physical_name": "S_AXIS_TREADY",
"direction": "O"
}
}
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXIS:S_AXIS",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
}
}
},
"RESETN": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"initial_value": {
"direction": "I",
"left": "31",
"right": "0"
},
"polynomial": {
"direction": "I",
"left": "31",
"right": "0"
}
}
},
"axis_dma_0": {
"vlnv": "xilinx.com:module_ref:axis_dma:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_dma_0_0",
@@ -678,6 +870,16 @@
"direction": "O",
"left": "31",
"right": "0"
},
"FIFO_NUM_FREE": {
"direction": "I",
"left": "7",
"right": "0"
},
"FIFO_NUM_AVAIL": {
"direction": "I",
"left": "7",
"right": "0"
}
},
"addressing": {
@@ -688,299 +890,6 @@
}
}
}
},
"axis_fifo_0": {
"vlnv": "Gehrke:user:axis_fifo:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_fifo_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_0_0\\axi_crc_dma_sim_1_axis_fifo_0_0.xci",
"inst_hier_path": "axi_crc_dma/axis_fifo_0"
},
"axis_fifo_1": {
"vlnv": "Gehrke:user:axis_fifo:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_fifo_1_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_fifo_1_0\\axi_crc_dma_sim_1_axis_fifo_1_0.xci",
"inst_hier_path": "axi_crc_dma/axis_fifo_1"
},
"crc": {
"interface_ports": {
"S_AXIS": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"M_AXIS": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I"
},
"RESETN": {
"type": "rst",
"direction": "I"
},
"initial_value": {
"direction": "I",
"left": "31",
"right": "0"
},
"polynomial": {
"direction": "I",
"left": "31",
"right": "0"
}
},
"components": {
"axis_downsizer_0": {
"vlnv": "xilinx.com:user:axis_downsizer:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_downsizer_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_downsizer_0_0\\axi_crc_dma_sim_1_axis_downsizer_0_0.xci",
"inst_hier_path": "axi_crc_dma/crc/axis_downsizer_0",
"parameters": {
"WIDTH_OUT": {
"value": "16"
}
}
},
"axis_upsizer_0": {
"vlnv": "xilinx.com:user:axis_upsizer:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_upsizer_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_upsizer_0_0\\axi_crc_dma_sim_1_axis_upsizer_0_0.xci",
"inst_hier_path": "axi_crc_dma/crc/axis_upsizer_0",
"parameters": {
"WIDTH_IN": {
"value": "16"
}
}
},
"axis_crc_0": {
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
"xci_name": "axi_crc_dma_sim_1_axis_crc_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axis_crc_0_0\\axi_crc_dma_sim_1_axis_crc_0_0.xci",
"inst_hier_path": "axi_crc_dma/crc/axis_crc_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "axis_crc",
"boundary_crc": "0x0"
},
"interface_ports": {
"M_AXIS": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "4",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "M_AXIS_TDATA",
"direction": "O",
"left": "31",
"right": "0"
},
"TLAST": {
"physical_name": "M_AXIS_TLAST",
"direction": "O"
},
"TVALID": {
"physical_name": "M_AXIS_TVALID",
"direction": "O"
},
"TREADY": {
"physical_name": "M_AXIS_TREADY",
"direction": "I"
}
}
},
"S_AXIS": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "4",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "S_AXIS_TDATA",
"direction": "I",
"left": "31",
"right": "0"
},
"TLAST": {
"physical_name": "S_AXIS_TLAST",
"direction": "I"
},
"TVALID": {
"physical_name": "S_AXIS_TVALID",
"direction": "I"
},
"TREADY": {
"physical_name": "S_AXIS_TREADY",
"direction": "O"
}
}
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXIS:S_AXIS",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
}
}
},
"RESETN": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"initial_value": {
"direction": "I",
"left": "31",
"right": "0"
},
"polynomial": {
"direction": "I",
"left": "31",
"right": "0"
}
}
}
},
"interface_nets": {
"axis_crc_0_M_AXIS": {
"interface_ports": [
"axis_crc_0/M_AXIS",
"axis_upsizer_0/S_AXIS"
]
},
"axis_downsizer_0_M_AXIS": {
"interface_ports": [
"axis_downsizer_0/M_AXIS",
"axis_crc_0/S_AXIS"
]
},
"axis_fifo_0_M_AXIS": {
"interface_ports": [
"S_AXIS",
"axis_downsizer_0/S_AXIS"
]
},
"axis_upsizer_0_M_AXIS": {
"interface_ports": [
"M_AXIS",
"axis_upsizer_0/M_AXIS"
]
}
},
"nets": {
"CLK_1": {
"ports": [
"CLK",
"axis_upsizer_0/AXIS_ACLK",
"axis_downsizer_0/AXIS_ACLK",
"axis_crc_0/CLK"
]
},
"RESETN_1": {
"ports": [
"RESETN",
"axis_upsizer_0/AXIS_ARESETN",
"axis_downsizer_0/AXIS_ARESETN",
"axis_crc_0/RESETN"
]
},
"axis_dma_0_initial_value": {
"ports": [
"initial_value",
"axis_crc_0/initial_value"
]
},
"axis_dma_0_polynomial": {
"ports": [
"polynomial",
"axis_crc_0/polynomial"
]
}
}
}
},
"interface_nets": {
@@ -990,6 +899,12 @@
"S_AXIL"
]
},
"Conn2": {
"interface_ports": [
"axis_dma_0/M_AXI",
"M_AXI"
]
},
"axis_dma_0_M_AXIS": {
"interface_ports": [
"axis_dma_0/M_AXIS",
@@ -999,7 +914,7 @@
"axis_fifo_0_M_AXIS": {
"interface_ports": [
"axis_fifo_0/M_AXIS",
"crc/S_AXIS"
"axis_crc_0/S_AXIS"
]
},
"axis_fifo_1_M_AXIS": {
@@ -1010,7 +925,7 @@
},
"axis_upsizer_0_M_AXIS": {
"interface_ports": [
"crc/M_AXIS",
"axis_crc_0/M_AXIS",
"axis_fifo_1/S_AXIS"
]
}
@@ -1019,34 +934,47 @@
"CLK_1": {
"ports": [
"CLK",
"axis_dma_0/CLK",
"axis_fifo_0/M_AXIS_ACLK",
"axis_fifo_0/S_AXIS_ACLK",
"axis_fifo_1/S_AXIS_ACLK",
"axis_fifo_1/M_AXIS_ACLK",
"crc/CLK"
"axis_crc_0/CLK",
"axis_dma_0/CLK"
]
},
"RESETN_1": {
"ports": [
"RESETN",
"axis_dma_0/RESETN",
"axis_fifo_0/M_AXIS_ARESETN",
"axis_fifo_1/S_AXIS_ARESETN",
"axis_fifo_1/M_AXIS_ARESETN",
"crc/RESETN"
"axis_crc_0/RESETN",
"axis_fifo_0/S_AXIS_ARESETN",
"axis_dma_0/RESETN"
]
},
"axis_dma_0_initial_value": {
"ports": [
"axis_dma_0/initial_value",
"crc/initial_value"
"axis_crc_0/initial_value"
]
},
"axis_dma_0_polynomial": {
"ports": [
"axis_dma_0/polynomial",
"crc/polynomial"
"axis_crc_0/polynomial"
]
},
"axis_fifo_0_S_NUM_FREE": {
"ports": [
"axis_fifo_0/S_NUM_FREE",
"axis_dma_0/FIFO_NUM_FREE"
]
},
"axis_fifo_1_M_NUM_AVAIL": {
"ports": [
"axis_fifo_1/M_NUM_AVAIL",
"axis_dma_0/FIFO_NUM_AVAIL"
]
}
}
@@ -1056,6 +984,11 @@
"xci_name": "axi_crc_dma_sim_1_axil_master_with_rom_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axil_master_with_rom_0_0\\axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci",
"inst_hier_path": "axil_master_with_rom_0",
"parameters": {
"STIM_FILENAME": {
"value": "../../axi_crc_dma_sim.mem"
}
},
"interface_ports": {
"M_AXIL": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
@@ -1082,9 +1015,294 @@
"xci_name": "axi_crc_dma_sim_1_clk_rst_generator_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_clk_rst_generator_0_0\\axi_crc_dma_sim_1_clk_rst_generator_0_0.xci",
"inst_hier_path": "clk_rst_generator_0"
},
"axi3_slave_verif_0": {
"vlnv": "xilinx.com:module_ref:axi3_slave_verif:1.0",
"xci_name": "axi_crc_dma_sim_1_axi3_slave_verif_0_0",
"xci_path": "ip\\axi_crc_dma_sim_1_axi3_slave_verif_0_0\\axi_crc_dma_sim_1_axi3_slave_verif_0_0.xci",
"inst_hier_path": "axi3_slave_verif_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "axi3_slave_verif",
"boundary_crc": "0x0"
},
"interface_ports": {
"S_AXI": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"parameters": {
"DATA_WIDTH": {
"value": "32",
"value_src": "auto"
},
"PROTOCOL": {
"value": "AXI3",
"value_src": "constant"
},
"ID_WIDTH": {
"value": "1",
"value_src": "auto"
},
"ADDR_WIDTH": {
"value": "32",
"value_src": "constant"
},
"AWUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"ARUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"WUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"RUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"BUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"READ_WRITE_MODE": {
"value": "READ_WRITE",
"value_src": "constant"
},
"HAS_BURST": {
"value": "1",
"value_src": "constant"
},
"HAS_LOCK": {
"value": "0",
"value_src": "constant"
},
"HAS_PROT": {
"value": "0",
"value_src": "constant"
},
"HAS_CACHE": {
"value": "0",
"value_src": "constant"
},
"HAS_QOS": {
"value": "0",
"value_src": "constant"
},
"HAS_REGION": {
"value": "0",
"value_src": "constant"
},
"HAS_WSTRB": {
"value": "1",
"value_src": "constant"
},
"HAS_BRESP": {
"value": "1",
"value_src": "constant"
},
"HAS_RRESP": {
"value": "1",
"value_src": "constant"
},
"SUPPORTS_NARROW_BURST": {
"value": "1",
"value_src": "auto"
},
"NUM_READ_OUTSTANDING": {
"value": "2",
"value_src": "auto"
},
"NUM_WRITE_OUTSTANDING": {
"value": "2",
"value_src": "auto"
},
"MAX_BURST_LENGTH": {
"value": "16",
"value_src": "auto"
}
},
"memory_map_ref": "S_AXI",
"port_maps": {
"AWADDR": {
"physical_name": "S_AXI_AWADDR",
"direction": "I",
"left": "31",
"right": "0"
},
"AWLEN": {
"physical_name": "S_AXI_AWLEN",
"direction": "I",
"left": "3",
"right": "0"
},
"AWSIZE": {
"physical_name": "S_AXI_AWSIZE",
"direction": "I",
"left": "2",
"right": "0"
},
"AWBURST": {
"physical_name": "S_AXI_AWBURST",
"direction": "I",
"left": "1",
"right": "0"
},
"AWVALID": {
"physical_name": "S_AXI_AWVALID",
"direction": "I"
},
"AWREADY": {
"physical_name": "S_AXI_AWREADY",
"direction": "O"
},
"WDATA": {
"physical_name": "S_AXI_WDATA",
"direction": "I",
"left": "31",
"right": "0"
},
"WSTRB": {
"physical_name": "S_AXI_WSTRB",
"direction": "I",
"left": "3",
"right": "0"
},
"WLAST": {
"physical_name": "S_AXI_WLAST",
"direction": "I"
},
"WVALID": {
"physical_name": "S_AXI_WVALID",
"direction": "I"
},
"WREADY": {
"physical_name": "S_AXI_WREADY",
"direction": "O"
},
"BRESP": {
"physical_name": "S_AXI_BRESP",
"direction": "O",
"left": "1",
"right": "0"
},
"BVALID": {
"physical_name": "S_AXI_BVALID",
"direction": "O"
},
"BREADY": {
"physical_name": "S_AXI_BREADY",
"direction": "I"
},
"ARID": {
"physical_name": "S_AXI_ARID",
"direction": "I",
"left": "0",
"right": "0"
},
"ARADDR": {
"physical_name": "S_AXI_ARADDR",
"direction": "I",
"left": "31",
"right": "0"
},
"ARLEN": {
"physical_name": "S_AXI_ARLEN",
"direction": "I",
"left": "3",
"right": "0"
},
"ARSIZE": {
"physical_name": "S_AXI_ARSIZE",
"direction": "I",
"left": "2",
"right": "0"
},
"ARBURST": {
"physical_name": "S_AXI_ARBURST",
"direction": "I",
"left": "1",
"right": "0"
},
"ARVALID": {
"physical_name": "S_AXI_ARVALID",
"direction": "I"
},
"ARREADY": {
"physical_name": "S_AXI_ARREADY",
"direction": "O"
},
"RID": {
"physical_name": "S_AXI_RID",
"direction": "O",
"left": "0",
"right": "0"
},
"RDATA": {
"physical_name": "S_AXI_RDATA",
"direction": "O",
"left": "31",
"right": "0"
},
"RRESP": {
"physical_name": "S_AXI_RRESP",
"direction": "O",
"left": "1",
"right": "0"
},
"RLAST": {
"physical_name": "S_AXI_RLAST",
"direction": "O"
},
"RVALID": {
"physical_name": "S_AXI_RVALID",
"direction": "O"
},
"RREADY": {
"physical_name": "S_AXI_RREADY",
"direction": "I"
}
}
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "S_AXI",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
}
}
},
"RESETN": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
}
},
"interface_nets": {
"axi_crc_dma_M_AXI": {
"interface_ports": [
"axi3_slave_verif_0/S_AXI",
"axi_crc_dma/M_AXI"
]
},
"axil_master_with_rom_0_M_AXIL": {
"interface_ports": [
"axil_master_with_rom_0/M_AXIL",
@@ -1097,14 +1315,16 @@
"ports": [
"clk_rst_generator_0/clk",
"axil_master_with_rom_0/M_AXIL_ACLK",
"axi_crc_dma/CLK"
"axi_crc_dma/CLK",
"axi3_slave_verif_0/CLK"
]
},
"clk_rst_generator_0_rst_n": {
"ports": [
"clk_rst_generator_0/rst_n",
"axil_master_with_rom_0/M_AXIL_ARESETN",
"axi_crc_dma/RESETN"
"axi_crc_dma/RESETN",
"axi3_slave_verif_0/RESETN"
]
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0/axi_crc_dma_sim_1_axi3_slave_verif_0_0.xci
+192
View File
@@ -0,0 +1,192 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axi_crc_dma_sim_1_axi3_slave_verif_0_0",
"cell_name": "axi3_slave_verif_0",
"component_reference": "xilinx.com:module_ref:axi3_slave_verif:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0",
"parameters": {
"component_parameters": {
"DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IDWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MAX_BURSTLEN": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axi3_slave_verif_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IDWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"MAX_BURSTLEN": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "1" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axi3_slave_verif_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
}
},
"boundary": {
"ports": {
"CLK": [ { "direction": "in" } ],
"RESETN": [ { "direction": "in" } ],
"S_AXI_ARVALID": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_ARREADY": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_ARADDR": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXI_ARID": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"S_AXI_ARLEN": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"S_AXI_ARSIZE": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
"S_AXI_ARBURST": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
"S_AXI_RVALID": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_RREADY": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"S_AXI_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"S_AXI_RID": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
"S_AXI_RLAST": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_AWVALID": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_AWREADY": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_AWADDR": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXI_AWLEN": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"S_AXI_AWSIZE": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
"S_AXI_AWBURST": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "1" } ],
"S_AXI_WVALID": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_WREADY": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXI_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
"S_AXI_WLAST": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_BVALID": [ { "direction": "out", "driver_value": "0x0" } ],
"S_AXI_BREADY": [ { "direction": "in", "driver_value": "0" } ],
"S_AXI_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
},
"interfaces": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"memory_map_ref": "S_AXI",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"AWADDR": [ { "physical_name": "S_AXI_AWADDR" } ],
"AWLEN": [ { "physical_name": "S_AXI_AWLEN" } ],
"AWSIZE": [ { "physical_name": "S_AXI_AWSIZE" } ],
"AWBURST": [ { "physical_name": "S_AXI_AWBURST" } ],
"AWVALID": [ { "physical_name": "S_AXI_AWVALID" } ],
"AWREADY": [ { "physical_name": "S_AXI_AWREADY" } ],
"WDATA": [ { "physical_name": "S_AXI_WDATA" } ],
"WSTRB": [ { "physical_name": "S_AXI_WSTRB" } ],
"WLAST": [ { "physical_name": "S_AXI_WLAST" } ],
"WVALID": [ { "physical_name": "S_AXI_WVALID" } ],
"WREADY": [ { "physical_name": "S_AXI_WREADY" } ],
"BRESP": [ { "physical_name": "S_AXI_BRESP" } ],
"BVALID": [ { "physical_name": "S_AXI_BVALID" } ],
"BREADY": [ { "physical_name": "S_AXI_BREADY" } ],
"ARID": [ { "physical_name": "S_AXI_ARID" } ],
"ARADDR": [ { "physical_name": "S_AXI_ARADDR" } ],
"ARLEN": [ { "physical_name": "S_AXI_ARLEN" } ],
"ARSIZE": [ { "physical_name": "S_AXI_ARSIZE" } ],
"ARBURST": [ { "physical_name": "S_AXI_ARBURST" } ],
"ARVALID": [ { "physical_name": "S_AXI_ARVALID" } ],
"ARREADY": [ { "physical_name": "S_AXI_ARREADY" } ],
"RID": [ { "physical_name": "S_AXI_RID" } ],
"RDATA": [ { "physical_name": "S_AXI_RDATA" } ],
"RRESP": [ { "physical_name": "S_AXI_RRESP" } ],
"RLAST": [ { "physical_name": "S_AXI_RLAST" } ],
"RVALID": [ { "physical_name": "S_AXI_RVALID" } ],
"RREADY": [ { "physical_name": "S_AXI_RREADY" } ]
}
},
"RESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "RESETN" } ]
}
},
"CLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "CLK" } ]
}
}
},
"memory_maps": {
"S_AXI": {
"display_name": "S_AXI",
"address_blocks": {
"reg0": {
"base_address": "0x0",
"range": "0x100000000",
"display_name": "reg0",
"usage": "register"
}
}
}
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0/axi_crc_dma_sim_1_axil_master_with_rom_0_0.xci
+3 -3
View File
@@ -8,14 +8,14 @@
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axil_master_with_rom_0_0",
"parameters": {
"component_parameters": {
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "user", "usage": "all" } ],
"STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"REVISION_NO": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "generated", "usage": "all" } ],
"STIM_FILENAME": [ { "value": "../../axi_crc_dma_sim.mem", "resolve_type": "generated", "usage": "all" } ],
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"REVISION_NO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
@@ -78,7 +78,7 @@
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0/axi_crc_dma_sim_1_axis_crc_0_0.xci
+1 -1
View File
@@ -2,7 +2,7 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axi_crc_dma_sim_1_axis_crc_0_0",
"cell_name": "axis_crc_0",
"cell_name": "axi_crc_dma/axis_crc_0",
"component_reference": "xilinx.com:module_ref:axis_crc:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_crc_0_0",
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0/axi_crc_dma_sim_1_axis_dma_0_0.xci
+46 -38
View File
@@ -2,7 +2,7 @@
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axi_crc_dma_sim_1_axis_dma_0_0",
"cell_name": "axi_crc_dma/axis_dma_0",
"cell_name": "axis_dma_0",
"component_reference": "xilinx.com:module_ref:axis_dma:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_dma_0_0",
@@ -11,12 +11,18 @@
"DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"IDWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MAX_BURSTLEN": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_AWIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"polynomial_default": [ { "value": "0x04C11DB7", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"initial_value_default": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"Component_Name": [ { "value": "axi_crc_dma_sim_1_axis_dma_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"IDWIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"polynomial_default": [ { "value": "0x04C11DB7", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
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},
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@@ -48,6 +54,8 @@
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"S_AXIL_AWREADY": [ { "direction": "out" } ],
@@ -168,25 +176,25 @@
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@@ -242,26 +250,26 @@
"mode": "slave",
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Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_downsizer_0_0/axi_crc_dma_sim_1_axis_downsizer_0_0.xci
-148
View File
@@ -1,148 +0,0 @@
{
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},
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},
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},
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}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_0_0/axi_crc_dma_sim_1_axis_fifo_0_0.xci
+4 -4
View File
@@ -10,7 +10,7 @@
"component_parameters": {
"FIFO_TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FIFO_DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Component_Name": [ { "value": "axi_crc_dma_sim_1_axis_fifo_0_0", "resolve_type": "user", "usage": "all" } ]
@@ -18,7 +18,7 @@
"model_parameters": {
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},
@@ -55,7 +55,7 @@
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@@ -63,7 +63,7 @@
"M_AXIS_TLAST": [ { "direction": "out" } ],
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Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_fifo_1_0/axi_crc_dma_sim_1_axis_fifo_1_0.xci
+4 -4
View File
@@ -10,7 +10,7 @@
"component_parameters": {
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"FIFO_DWIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"Component_Name": [ { "value": "axi_crc_dma_sim_1_axis_fifo_1_0", "resolve_type": "user", "usage": "all" } ]
@@ -18,7 +18,7 @@
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@@ -55,7 +55,7 @@
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@@ -63,7 +63,7 @@
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Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ip/axi_crc_dma_sim_1_axis_upsizer_0_0/axi_crc_dma_sim_1_axis_upsizer_0_0.xci
-148
View File
@@ -1,148 +0,0 @@
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"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
}
},
"AXIS_ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "AXIS_ARESETN" } ]
}
},
"AXIS_ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
}
}
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axi_crc_dma_sim_1/ui/bd_e4a1ea.ui
+12 -10
View File
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"2.0",
"Default View_TopLeft":"1191,-40",
"Default View_ScaleFactor":"1.25",
"Default View_TopLeft":"-146,-50",
"Display-PortTypeOthers":"true",
"ExpandedHierarchyInLayout":"",
"Interfaces View_ExpandedHierarchyInLayout":"",
@@ -19,14 +19,16 @@ pagesize -pg 1 -db -bbox -sgen 0 0 1990 480
"Interfaces View_TopLeft":"-199,-369",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 600 -y 78 -defaultsOSRD
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 110 -defaultsOSRD
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 120 -defaultsOSRD
preplace netloc clk_rst_generator_0_clk 1 1 2 220 20 490J
preplace netloc clk_rst_generator_0_rst_n 1 1 2 230 30 470J
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 480 58n
levelinfo -pg 1 0 110 350 600 680
pagesize -pg 1 -db -bbox -sgen 0 -10 2700 420
preplace inst axi_crc_dma -pg 1 -lvl 3 -x 620 -y 240 -defaultsOSRD
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 350 -y 210 -defaultsOSRD
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 110 -y 130 -defaultsOSRD
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 850 -y 260 -defaultsOSRD
preplace netloc clk_rst_generator_0_clk 1 1 3 230 290 510 310 720J
preplace netloc clk_rst_generator_0_rst_n 1 1 3 220 300 520 320 730J
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 1 470 210n
preplace netloc axi_crc_dma_M_AXI 1 3 1 N 240
levelinfo -pg 1 0 110 350 620 850 940
pagesize -pg 1 -db -bbox -sgen 0 0 940 340
"
}
{
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/axis_crc_sim_1.bd
+2 -1
View File
@@ -7,7 +7,8 @@
"name": "axis_crc_sim_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2023.1"
"tool_version": "2023.1",
"validated": "true"
},
"design_tree": {
"clk_rst_generator_0": "",
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_crc_sim_1/ui/bd_9f9006c0.ui
+1 -1
View File
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"2.0",
"Default View_TopLeft":"-180,-69",
"Default View_TopLeft":"187,103",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/axis_master_test.bd
-117
View File
@@ -1,117 +0,0 @@
{
"design": {
"design_info": {
"boundary_crc": "0x0",
"device": "xc7z020clg400-1",
"gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test",
"name": "axis_master_test",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2023.1"
},
"design_tree": {
"axis_mixer_0": "",
"axis_numeric_master_0": ""
},
"components": {
"axis_mixer_0": {
"vlnv": "xilinx.com:user:axis_mixer:1.0",
"xci_name": "axis_master_test_axis_mixer_0_0",
"xci_path": "ip\\axis_master_test_axis_mixer_0_0\\axis_master_test_axis_mixer_0_0.xci",
"inst_hier_path": "axis_mixer_0",
"parameters": {
"DATA_WIDTH": {
"value": "32"
},
"WEIGHT_1": {
"value": "1"
},
"WEIGHT_2": {
"value": "1"
}
}
},
"axis_numeric_master_0": {
"vlnv": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
"xci_name": "axis_master_test_axis_numeric_master_0_0",
"xci_path": "ip\\axis_master_test_axis_numeric_master_0_0\\axis_master_test_axis_numeric_master_0_0.xci",
"inst_hier_path": "axis_numeric_master_0",
"parameters": {
"FILE_NAME_M1": {
"value": "../../../../mstr1.txt"
},
"FILE_NAME_M2": {
"value": "../../../../mstr2.txt"
},
"FILE_NAME_S": {
"value": "../../../../slv.txt"
},
"MASTER1_HAS_LAST": {
"value": "false"
},
"MASTER1_HAS_USER": {
"value": "false"
},
"MASTER1_RANDOM_VALID": {
"value": "true"
},
"MASTER2_HAS_LAST": {
"value": "false"
},
"MASTER2_HAS_USER": {
"value": "false"
},
"MASTER2_RANDOM_VALID": {
"value": "true"
},
"SLAVE_HAS_LAST": {
"value": "false"
},
"SLAVE_HAS_USER": {
"value": "false"
},
"SLAVE_RANDOM_READY": {
"value": "true"
},
"SLAVE_WAIT_FOR_SOF": {
"value": "false"
}
}
}
},
"interface_nets": {
"axis_mixer_0_M_AXIS": {
"interface_ports": [
"axis_mixer_0/M_AXIS",
"axis_numeric_master_0/S_AXIS"
]
},
"axis_numeric_master_0_M1_AXIS": {
"interface_ports": [
"axis_mixer_0/S_AXIS_1",
"axis_numeric_master_0/M1_AXIS"
]
},
"axis_numeric_master_0_M2_AXIS": {
"interface_ports": [
"axis_mixer_0/S_AXIS_2",
"axis_numeric_master_0/M2_AXIS"
]
}
},
"nets": {
"axis_numeric_master_0_CLK": {
"ports": [
"axis_numeric_master_0/CLK",
"axis_mixer_0/ACLK"
]
},
"axis_numeric_master_0_RESETN": {
"ports": [
"axis_numeric_master_0/RESETN",
"axis_mixer_0/ARESETN"
]
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0/axis_master_test_axis_mixer_0_0.xci
-185
View File
@@ -1,185 +0,0 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "axis_master_test_axis_mixer_0_0",
"cell_name": "axis_mixer_0",
"component_reference": "xilinx.com:user:axis_mixer:1.0",
"ip_revision": "14",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0",
"parameters": {
"component_parameters": {
"WEIGHT_1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "axis_master_test_axis_mixer_0_0", "resolve_type": "user", "usage": "all" } ],
"HAS_AXI_LITE_IF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"WEIGHT_2": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FORCE_01_INPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SHIFT_DEF": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
},
"model_parameters": {
"WEIGHT_1": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"HAS_AXI_LITE_IF": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"WEIGHT_2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"FORCE_01_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SHIFT_DEF": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "14" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/axis_master_test/ip/axis_master_test_axis_mixer_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"ACLK": [ { "direction": "in" } ],
"ARESETN": [ { "direction": "in" } ],
"M_AXIS_TVALID": [ { "direction": "out" } ],
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "0x1" } ],
"S_AXIS_1_TVALID": [ { "direction": "in", "driver_value": "0x1" } ],
"S_AXIS_1_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXIS_1_TREADY": [ { "direction": "out" } ],
"S_AXIS_2_TVALID": [ { "direction": "in", "driver_value": "0x1" } ],
"S_AXIS_2_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXIS_2_TREADY": [ { "direction": "out" } ]
},
"interfaces": {
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
}
},
"S_AXIS_1": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "S_AXIS_1_TDATA" } ],
"TVALID": [ { "physical_name": "S_AXIS_1_TVALID" } ],
"TREADY": [ { "physical_name": "S_AXIS_1_TREADY" } ]
}
},
"S_AXIS_2": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "S_AXIS_2_TDATA" } ],
"TVALID": [ { "physical_name": "S_AXIS_2_TVALID" } ],
"TREADY": [ { "physical_name": "S_AXIS_2_TREADY" } ]
}
},
"ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
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Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/ip/axis_master_test_axis_numeric_master_0_0/axis_master_test_axis_numeric_master_0_0.xci
-230
View File
@@ -1,230 +0,0 @@
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"mode": "master",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M2_AXIS:M1_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "axis_master_test_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "CLK" } ]
}
}
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/axis_master_test/ui/bd_d41d9491.ui
-19
View File
@@ -1,19 +0,0 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.25",
"Default View_TopLeft":"-450,-164",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
preplace inst axis_mixer_0 -pg 1 -lvl 2 -x 350 -y 90 -defaultsOSRD
preplace inst axis_numeric_master_0 -pg 1 -lvl 1 -x 130 -y 90 -defaultsOSRD
preplace netloc axis_numeric_master_0_CLK 1 1 1 N 100
preplace netloc axis_numeric_master_0_RESETN 1 1 1 N 120
preplace netloc axis_mixer_0_M_AXIS 1 0 3 20 180 NJ 180 460
preplace netloc axis_numeric_master_0_M1_AXIS 1 1 1 N 60
preplace netloc axis_numeric_master_0_M2_AXIS 1 1 1 N 80
levelinfo -pg 1 0 130 350 480
pagesize -pg 1 -db -bbox -sgen 0 0 480 190
"
}
0
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_axis_crc_0_0/test_1_axis_crc_0_0.xci
-138
View File
@@ -1,138 +0,0 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "test_1_axis_crc_0_0",
"cell_name": "axis_crc_0",
"component_reference": "xilinx.com:module_ref:axis_crc:1.0",
"ip_revision": "1",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "test_1_axis_crc_0_0", "resolve_type": "user", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "1" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_crc_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
}
},
"boundary": {
"ports": {
"CLK": [ { "direction": "in" } ],
"RESETN": [ { "direction": "in" } ],
"initial_value": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"polynomial": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
"S_AXIS_TVALID": [ { "direction": "in" } ],
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
"S_AXIS_TREADY": [ { "direction": "out" } ],
"M_AXIS_TVALID": [ { "direction": "out" } ],
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"M_AXIS_TLAST": [ { "direction": "out" } ],
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
},
"interfaces": {
"M_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
}
},
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
}
},
"RESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "RESETN" } ]
}
},
"CLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "CLK" } ]
}
}
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0/test_1_axis_numeric_master_0_0.xci
-198
View File
@@ -1,198 +0,0 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "test_1_axis_numeric_master_0_0",
"cell_name": "axis_numeric_master_0",
"component_reference": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
"ip_revision": "18",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0",
"parameters": {
"component_parameters": {
"HAS_CLOCK_GENERATOR": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLOCK_PERIOD_NS": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_RESET_GENERATOR": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RESET_ACTIVE_CYCLES": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_MASTER1": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER1_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MASTER1_RANDOM_VALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER1_HAS_LAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER1_LAST_PERIOD": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MASTER1_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER1_USER_PERIOD": [ { "value": "1000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_MASTER2": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER2_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MASTER2_RANDOM_VALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER2_HAS_LAST": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER2_LAST_PERIOD": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MASTER2_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MASTER2_USER_PERIOD": [ { "value": "1000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HAS_SLAVE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SLAVE_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SLAVE_RANDOM_READY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SLAVE_HAS_LAST": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SLAVE_HAS_USER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SLAVE_WAIT_FOR_SOF": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"FILE_NAME_M1": [ { "value": "../../../../m1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"FILE_NAME_M2": [ { "value": "../../../../m1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"FILE_NAME_S": [ { "value": "../../../../m1.txt", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "test_1_axis_numeric_master_0_0", "resolve_type": "user", "usage": "all" } ],
"HAS_RESETN_INPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
"HAS_CLOCK_GENERATOR": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"CLOCK_PERIOD_NS": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"HAS_RESET_GENERATOR": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"RESET_ACTIVE_CYCLES": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"HAS_MASTER1": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER1_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"MASTER1_RANDOM_VALID": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER1_HAS_LAST": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER1_LAST_PERIOD": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"MASTER1_HAS_USER": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER1_USER_PERIOD": [ { "value": "1000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"HAS_MASTER2": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER2_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"MASTER2_RANDOM_VALID": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER2_HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER2_LAST_PERIOD": [ { "value": "100", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"MASTER2_HAS_USER": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"MASTER2_USER_PERIOD": [ { "value": "1000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"HAS_SLAVE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SLAVE_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SLAVE_RANDOM_READY": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SLAVE_HAS_LAST": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SLAVE_HAS_USER": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SLAVE_WAIT_FOR_SOF": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"FILE_NAME_M1": [ { "value": "../../../../m1.txt", "resolve_type": "generated", "usage": "all" } ],
"FILE_NAME_M2": [ { "value": "../../../../m1.txt", "resolve_type": "generated", "usage": "all" } ],
"FILE_NAME_S": [ { "value": "../../../../m1.txt", "resolve_type": "generated", "usage": "all" } ],
"HAS_RESETN_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "18" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_axis_numeric_master_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"CLK": [ { "direction": "out", "driver_value": "0x0" } ],
"RESETN": [ { "direction": "out", "driver_value": "0x1" } ],
"M1_AXIS_TVALID": [ { "direction": "out", "driver_value": "0x0" } ],
"M1_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"M1_AXIS_TREADY": [ { "direction": "in", "driver_value": "0x1" } ],
"M1_AXIS_TLAST": [ { "direction": "out", "driver_value": "0x0" } ],
"M1_AXIS_TUSER": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
"S_AXIS_TVALID": [ { "direction": "in", "driver_value": "0x0" } ],
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"S_AXIS_TREADY": [ { "direction": "out" } ],
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
"S_AXIS_TUSER": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
},
"interfaces": {
"M1_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "master",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "M1_AXIS_TDATA" } ],
"TLAST": [ { "physical_name": "M1_AXIS_TLAST" } ],
"TUSER": [ { "physical_name": "M1_AXIS_TUSER" } ],
"TVALID": [ { "physical_name": "M1_AXIS_TVALID" } ],
"TREADY": [ { "physical_name": "M1_AXIS_TREADY" } ]
}
},
"S_AXIS": {
"vlnv": "xilinx.com:interface:axis:1.0",
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "slave",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
}
},
"RESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "RESETN" } ]
}
},
"CLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "master",
"parameters": {
"ASSOCIATED_RESET": [ { "value": "RESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS:M2_AXIS:M1_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "test_1_axis_numeric_master_0_0_CLK", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "CLK" } ]
}
}
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_0_0/test_1_xlconstant_0_0.xci
-49
View File
@@ -1,49 +0,0 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "test_1_xlconstant_0_0",
"cell_name": "xlconstant_0",
"component_reference": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "7",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "test_1_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
"CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CONST_VAL": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "7" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/ip/test_1_xlconstant_1_0/test_1_xlconstant_1_0.xci
-49
View File
@@ -1,49 +0,0 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "test_1_xlconstant_1_0",
"cell_name": "xlconstant_1",
"component_reference": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "7",
"gen_directory": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "test_1_xlconstant_1_0", "resolve_type": "user", "usage": "all" } ],
"CONST_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"CONST_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"CONST_VAL": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VHDL" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "7" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../aci_crc_dma.gen/sources_1/bd/test_1/ip/test_1_xlconstant_1_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2023.1" } ],
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
}
},
"boundary": {
"ports": {
"dout": [ { "direction": "out", "size_left": "31", "size_right": "0" } ]
}
}
}
}
Hardware/aci_crc_dma/aci_crc_dma.srcs/sources_1/bd/test_1/test_1.bd
-300
View File
@@ -1,300 +0,0 @@
{
"design": {
"design_info": {
"boundary_crc": "0x0",
"device": "xc7z020clg400-1",
"gen_directory": "../../../../aci_crc_dma.gen/sources_1/bd/test_1",
"name": "test_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2023.1"
},
"design_tree": {
"xlconstant_0": "",
"xlconstant_1": "",
"axis_numeric_master_0": "",
"axis_crc_0": ""
},
"components": {
"xlconstant_0": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"xci_name": "test_1_xlconstant_0_0",
"xci_path": "ip\\test_1_xlconstant_0_0\\test_1_xlconstant_0_0.xci",
"inst_hier_path": "xlconstant_0",
"parameters": {
"CONST_VAL": {
"value": "0"
},
"CONST_WIDTH": {
"value": "32"
}
}
},
"xlconstant_1": {
"vlnv": "xilinx.com:ip:xlconstant:1.1",
"xci_name": "test_1_xlconstant_1_0",
"xci_path": "ip\\test_1_xlconstant_1_0\\test_1_xlconstant_1_0.xci",
"inst_hier_path": "xlconstant_1",
"parameters": {
"CONST_VAL": {
"value": "0"
},
"CONST_WIDTH": {
"value": "32"
}
}
},
"axis_numeric_master_0": {
"vlnv": "xilinx.com:user:axis_numeric_master_slave_simmodel:1.0",
"xci_name": "test_1_axis_numeric_master_0_0",
"xci_path": "ip\\test_1_axis_numeric_master_0_0\\test_1_axis_numeric_master_0_0.xci",
"inst_hier_path": "axis_numeric_master_0",
"parameters": {
"CLOCK_PERIOD_NS": {
"value": "10"
},
"FILE_NAME_M1": {
"value": "../../../../m1.txt"
},
"FILE_NAME_M2": {
"value": "../../../../m1.txt"
},
"FILE_NAME_S": {
"value": "../../../../m1.txt"
},
"HAS_MASTER2": {
"value": "false"
},
"MASTER1_HAS_LAST": {
"value": "true"
},
"MASTER1_HAS_USER": {
"value": "false"
},
"MASTER2_HAS_LAST": {
"value": "false"
},
"MASTER2_HAS_USER": {
"value": "false"
},
"SLAVE_HAS_LAST": {
"value": "true"
},
"SLAVE_HAS_USER": {
"value": "false"
},
"SLAVE_WAIT_FOR_SOF": {
"value": "false"
}
}
},
"axis_crc_0": {
"vlnv": "xilinx.com:module_ref:axis_crc:1.0",
"xci_name": "test_1_axis_crc_0_0",
"xci_path": "ip\\test_1_axis_crc_0_0\\test_1_axis_crc_0_0.xci",
"inst_hier_path": "axis_crc_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "axis_crc",
"boundary_crc": "0x0"
},
"interface_ports": {
"M_AXIS": {
"mode": "Master",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "4",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "M_AXIS_TDATA",
"direction": "O",
"left": "31",
"right": "0"
},
"TLAST": {
"physical_name": "M_AXIS_TLAST",
"direction": "O"
},
"TVALID": {
"physical_name": "M_AXIS_TVALID",
"direction": "O"
},
"TREADY": {
"physical_name": "M_AXIS_TREADY",
"direction": "I"
}
}
},
"S_AXIS": {
"mode": "Slave",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "4",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
}
},
"port_maps": {
"TDATA": {
"physical_name": "S_AXIS_TDATA",
"direction": "I",
"left": "31",
"right": "0"
},
"TLAST": {
"physical_name": "S_AXIS_TLAST",
"direction": "I"
},
"TVALID": {
"physical_name": "S_AXIS_TVALID",
"direction": "I"
},
"TREADY": {
"physical_name": "S_AXIS_TREADY",
"direction": "O"
}
}
}
},
"ports": {
"CLK": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "M_AXIS:S_AXIS",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "RESETN",
"value_src": "constant"
}
}
},
"RESETN": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"initial_value": {
"direction": "I",
"left": "31",
"right": "0"
},
"polynomial": {
"direction": "I",
"left": "31",
"right": "0"
}
}
}
},
"interface_nets": {
"axis_crc_0_M_AXIS": {
"interface_ports": [
"axis_crc_0/M_AXIS",
"axis_numeric_master_0/S_AXIS"
]
},
"axis_numeric_master_0_M1_AXIS": {
"interface_ports": [
"axis_numeric_master_0/M1_AXIS",
"axis_crc_0/S_AXIS"
]
}
},
"nets": {
"axis_numeric_master_0_CLK": {
"ports": [
"axis_numeric_master_0/CLK",
"axis_crc_0/CLK"
]
},
"axis_numeric_master_0_RESETN": {
"ports": [
"axis_numeric_master_0/RESETN",
"axis_crc_0/RESETN"
]
},
"xlconstant_0_dout": {
"ports": [
"xlconstant_0/dout",
"axis_crc_0/initial_value"
]
},
"xlconstant_1_dout": {
"ports": [
"xlconstant_1/dout",
"axis_crc_0/polynomial"
]
}
}
}
}

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