Testbench für Bitcrusher für einen Durchlauf erstellt

Milestone2/axis_audio_bitcrusher.vhd

@@ -42,9 +42,7 @@ begin
     type state_t is (S_INPUT, S_CALCULATE, S_OUTPUT, S_ERROR);
     signal state      : state_t := S_INPUT;
     signal state_next : state_t;
-
 begin
-
     -- Register fuer die Inputdaten
     RegInput: process
     begin
@@ -126,7 +124,7 @@ begin
             when S_INPUT =>
                 S_AXIS_TREADY  <= '1';
                 RegOutputEn    <= '0';
-                RegInputEn     <= '0';
+                RegInputEn     <= '1';
                 M_AXIS_TVALID  <= '0';
             when S_CALCULATE =>
                 S_AXIS_TREADY  <= '0';
@@ -136,7 +134,7 @@ begin
             when S_OUTPUT =>
                 S_AXIS_TREADY  <= '0';
                 RegOutputEn    <= '0';
-                RegInputEn     <= '1';
+                RegInputEn     <= '0';
                 M_AXIS_TVALID  <= '1';
             when S_ERROR =>
                 S_AXIS_TREADY  <= 'X';
@@ -145,4 +143,4 @@ begin
                 M_AXIS_TVALID  <= 'X';
         end case;
     end process;
-end rtl;
+end rtl;

Milestone2/axis_audio_bitcrusher_tb.vhd

@@ -0,0 +1,80 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_audio_bitcrusher_tb is
+end;
+
+architecture rtl of axis_audio_bitcrusher_tb is
+
+    constant EXT_CLOCK_FREQ : integer := 125000000;
+    constant SCK_FREQ       : integer := 1000000;
+    constant has_last       : boolean := true;
+    constant bit_reduction  : integer := 14;
+    
+    constant clk_half_period : time :=  1 sec / EXT_CLOCK_FREQ / 2;
+
+    signal axis_clk     : std_logic := '0';
+    signal axis_reset   : std_logic := '1';
+
+    signal s_axis_data  : std_logic_vector(15 downto 0) := (others=>'0') ;
+    signal s_axis_valid : std_logic := '0';
+    signal s_axis_tlast : std_logic := '0';
+    signal s_axis_ready : std_logic;
+
+    signal m_axis_data  : std_logic_vector(15 downto 0) := (others=>'0') ;
+    signal m_axis_valid : std_logic;
+    signal m_axis_tlast : std_logic;
+    signal m_axis_ready : std_logic := '0';
+
+
+begin
+
+    clk_proc: process (clk)
+    begin
+        clk <= not clk after clk_half_period;
+    end process;
+
+    stim: process
+    begin
+        axis_reset <= '0' after 100 * clk_half_period;
+
+        wait until axis_reset = '0';
+        wait until rising_edge(clk);
+        s_axis_data <= x"1234";
+        s_axis_valid <= '1';
+        s_axis_tlast <= '1';
+
+        loop
+            wait until rising_edge(clk);
+            if s_axis_ready = '1' then
+                s_axis_valid <= '0';
+                s_axis_tlast <= '0';
+                s_data <= (others=>'0');
+            if m_axis_valid and m_axis_tlast then 
+                exit;
+            end if;
+        end loop;
+
+        wait;
+
+    end process;
+
+    dut: entity work.axis_audio_bitcrusher
+    generic map (
+        BIT_REDUCTION  => bit_reduction;  
+        HAS_LAST       => has_last;
+    );
+    port map (
+        -- AXI Streaming Target Port
+        S_AXIS_TVALID  => s_axis_data ;      
+        S_AXIS_TDATA   => s_axis_valid;      
+        S_AXIS_TLAST   => s_axis_tlast;      
+        S_AXIS_TREADY  => s_axis_ready;
+        -- AXI Streaming Initiator Port
+        M_AXIS_TVALID  => m_axis_data ;
+        M_AXIS_TDATA   => m_axis_valid;      
+        M_AXIS_TLAST   => m_axis_tlast;
+        M_AXIS_TREADY  => m_axis_ready;     
+    );  
+end architecture;