Merge branch 'milestone3' into 'main'
Milestone 3 See merge request NdotPaul/es-praktikum!2
This commit is contained in:
+13
-13
@@ -5,17 +5,17 @@
|
||||
work/
|
||||
*.wlf
|
||||
|
||||
# Vidado project directories which are not needed
|
||||
.Xil/
|
||||
*.cache/
|
||||
*.hw/
|
||||
*.ip_user_files/
|
||||
*.runs/
|
||||
*.sim/
|
||||
# design checkpoint file
|
||||
*.dcp
|
||||
# # Vidado project directories which are not needed
|
||||
# .Xil/
|
||||
# *.cache/
|
||||
# *.hw/
|
||||
# *.ip_user_files/
|
||||
# *.runs/
|
||||
# *.sim/
|
||||
# # design checkpoint file
|
||||
# *.dcp
|
||||
|
||||
# ignore Vivado log files
|
||||
*.log
|
||||
*.jou
|
||||
vivado_pid*.str
|
||||
# # ignore Vivado log files
|
||||
# *.log
|
||||
# *.jou
|
||||
# vivado_pid*.str
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
# Ignore everything
|
||||
*
|
||||
# Allow whitelisting subdirectories
|
||||
!*/
|
||||
# Don\'t ignore the block design and block design hdl wrapper files
|
||||
!/bd/*/*.bd
|
||||
!/bd/*/hdl/*.sv
|
||||
!/bd/*/hdl/*.v
|
||||
!/bd/*/hdl/*.vhd
|
||||
!/bd/*/hdl/*.vhdl
|
||||
# Don\'t ignore the constraint files
|
||||
!/constraints/**/*.xdc
|
||||
# Don\'t ignore the synthesis files
|
||||
!/hdl/**/*.sv
|
||||
!/hdl/**/*.v
|
||||
!/hdl/**/*.vh
|
||||
!/hdl/**/*.vhd
|
||||
!/hdl/**/*.vhdl
|
||||
# Don\'t ignore the HLS source and testbench files
|
||||
!/hsl/*/sources/*.cpp
|
||||
!/hsl/*/sources/*.hpp
|
||||
!/hsl/*/testbench/*.cpp
|
||||
# Don\'t ignore the IP defintion files
|
||||
!/ip/*/*.xci
|
||||
# Don\'t ignore the HLS IP defintion files
|
||||
!/ip/hls_ip/**
|
||||
# Don\'t ignore the output files
|
||||
!/output/**/*.bit
|
||||
!/output/**/*.xsa
|
||||
!/output/**/*.dcp
|
||||
# Don\'t ignore the project files
|
||||
!/project/*.xpr
|
||||
# Don\'t ignore the simulation files
|
||||
!/sim/**/*.sv
|
||||
!/sim/**/*.v
|
||||
!/sim/**/*.vh
|
||||
!/sim/**/*.vhd
|
||||
!/sim/**/*.vhdl
|
||||
!/sim/**/*.wav
|
||||
# Don\'t ignore this file
|
||||
!.gitignore
|
||||
@@ -0,0 +1,41 @@
|
||||
# Ignore everything
|
||||
*
|
||||
# Allow whitelisting subdirectories
|
||||
!*/
|
||||
# Don\'t ignore the block design and block design hdl wrapper files
|
||||
!/bd/*/*.bd
|
||||
!/bd/*/hdl/*.sv
|
||||
!/bd/*/hdl/*.v
|
||||
!/bd/*/hdl/*.vhd
|
||||
!/bd/*/hdl/*.vhdl
|
||||
# Don\'t ignore the constraint files
|
||||
!/constraints/**/*.xdc
|
||||
# Don\'t ignore the synthesis files
|
||||
!/hdl/**/*.sv
|
||||
!/hdl/**/*.v
|
||||
!/hdl/**/*.vh
|
||||
!/hdl/**/*.vhd
|
||||
!/hdl/**/*.vhdl
|
||||
# Don\'t ignore the HLS source and testbench files
|
||||
!/hsl/*/sources/*.cpp
|
||||
!/hsl/*/sources/*.hpp
|
||||
!/hsl/*/testbench/*.cpp
|
||||
# Don\'t ignore the IP defintion files
|
||||
!/ip/*/*.xci
|
||||
# Don\'t ignore the HLS IP defintion files
|
||||
!/ip/hls_ip/**
|
||||
# Don\'t ignore the output files
|
||||
!/output/**/*.bit
|
||||
!/output/**/*.xsa
|
||||
!/output/**/*.dcp
|
||||
# Don\'t ignore the project files
|
||||
!/project/*.xpr
|
||||
# Don\'t ignore the simulation files
|
||||
!/sim/**/*.sv
|
||||
!/sim/**/*.v
|
||||
!/sim/**/*.vh
|
||||
!/sim/**/*.vhd
|
||||
!/sim/**/*.vhdl
|
||||
!/sim/**/*.wav
|
||||
# Don\'t ignore this file
|
||||
!.gitignore
|
||||
Binary file not shown.
Binary file not shown.
|
After Width: | Height: | Size: 106 KiB |
@@ -0,0 +1,3 @@
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||||
@echo off
|
||||
echo:
|
||||
for %%i in (*.stm) do stm2mem %%i & echo: & echo: & echo:
|
||||
@@ -0,0 +1,41 @@
|
||||
# Ignore everything
|
||||
*
|
||||
# Allow whitelisting subdirectories
|
||||
!*/
|
||||
# Don\'t ignore the block design and block design hdl wrapper files
|
||||
!/bd/*/*.bd
|
||||
!/bd/*/hdl/*.sv
|
||||
!/bd/*/hdl/*.v
|
||||
!/bd/*/hdl/*.vhd
|
||||
!/bd/*/hdl/*.vhdl
|
||||
# Don\'t ignore the constraint files
|
||||
!/constraints/**/*.xdc
|
||||
# Don\'t ignore the synthesis files
|
||||
!/hdl/**/*.sv
|
||||
!/hdl/**/*.v
|
||||
!/hdl/**/*.vh
|
||||
!/hdl/**/*.vhd
|
||||
!/hdl/**/*.vhdl
|
||||
# Don\'t ignore the HLS source and testbench files
|
||||
!/hsl/*/sources/*.cpp
|
||||
!/hsl/*/sources/*.hpp
|
||||
!/hsl/*/testbench/*.cpp
|
||||
# Don\'t ignore the IP defintion files
|
||||
!/ip/*/*.xci
|
||||
# Don\'t ignore the HLS IP defintion files
|
||||
!/ip/hls_ip/**
|
||||
# Don\'t ignore the output files
|
||||
!/output/**/*.bit
|
||||
!/output/**/*.xsa
|
||||
!/output/**/*.dcp
|
||||
# Don\'t ignore the project files
|
||||
!/project/*.xpr
|
||||
# Don\'t ignore the simulation files
|
||||
!/sim/**/*.sv
|
||||
!/sim/**/*.v
|
||||
!/sim/**/*.vh
|
||||
!/sim/**/*.vhd
|
||||
!/sim/**/*.vhdl
|
||||
!/sim/**/*.wav
|
||||
# Don\'t ignore this file
|
||||
!.gitignore
|
||||
Binary file not shown.
@@ -0,0 +1,40 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="af_sim_wrapper_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="af_sim_wrapper" />
|
||||
<top_module name="glbl" />
|
||||
<top_module name="wav_pkg" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="124,607,295.370 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="124,610,292.315 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,863,983,476.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="256"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="116"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="4" />
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_stereo2mo_0/AXIS_ACLK" type="logic">
|
||||
<obj_property name="ElementShortName">AXIS_ACLK</obj_property>
|
||||
<obj_property name="ObjectShortName">AXIS_ACLK</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_stereo2mo_0/M_AXIS" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_mono2ster_0/S_AXIS" type="protoinst">
|
||||
<obj_property name="ElementShortName">S_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_slave_sim_0/FINISHED" type="logic">
|
||||
<obj_property name="ElementShortName">FINISHED</obj_property>
|
||||
<obj_property name="ObjectShortName">FINISHED</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "af_sim",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "af_sim",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="af_sim" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1732630962"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732630962"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732630962"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732630962"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\af_sim.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\af_sim.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="af_sim_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\af_sim.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="af_sim.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\af_sim.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\af_sim.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
@@ -0,0 +1,24 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 15:22:42 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target af_sim_wrapper.bd
|
||||
--Design : af_sim_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity af_sim_wrapper is
|
||||
end af_sim_wrapper;
|
||||
|
||||
architecture STRUCTURE of af_sim_wrapper is
|
||||
component af_sim is
|
||||
end component af_sim;
|
||||
begin
|
||||
af_sim_i: component af_sim
|
||||
;
|
||||
end STRUCTURE;
|
||||
+506
@@ -0,0 +1,506 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_axis_audio_master_si_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">M_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_master_simmodel</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:9805a313</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>af_sim_axis_audio_master_si_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:9805a313</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>WAV_HEADER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">351</spirit:left>
|
||||
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|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2720fb8a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>af_sim_axis_audio_mono2ster_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2720fb8a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
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<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a5608c2f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>af_sim_axis_audio_stereo2mo_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a5608c2f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1a2f7743"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="71e811ad"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="b17a0555"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+1482
File diff suppressed because it is too large
Load Diff
+228
@@ -0,0 +1,228 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
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|
||||
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|
||||
</spirit:fileSetRef>
|
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<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
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</spirit:parameter>
|
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<spirit:parameter>
|
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</spirit:fileSetRef>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
|
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>outputProductCRC</spirit:name>
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</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">false</xilinx:isEnabled>
|
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</xilinx:enablement>
|
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</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">false</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>clk</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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||||
<spirit:name>rst_n</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
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<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
|
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</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
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<spirit:fileSet>
|
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
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<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/af_sim_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">af_sim_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLOCK_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_CLK_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_RESET_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_STOP_INPUT" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,205 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 15:22:42 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target af_sim.bd
|
||||
--Design : af_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity af_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef";
|
||||
end af_sim;
|
||||
|
||||
architecture STRUCTURE of af_sim is
|
||||
component af_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_clk_rst_generator_0_0;
|
||||
component af_sim_axis_audio_master_si_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_master_si_0_0;
|
||||
component af_sim_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_mono2ster_0_0;
|
||||
component af_sim_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_stereo2mo_0_0;
|
||||
component af_sim_axis_audio_slave_sim_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_slave_sim_0_0;
|
||||
component af_sim_axis_prog_audio_filt_0_0 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_prog_audio_filt_0_0;
|
||||
signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
begin
|
||||
axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
FINISHED => axis_audio_slave_sim_0_FINISHED,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED,
|
||||
S_AXIL_ARVALID => '0',
|
||||
S_AXIL_AWADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED,
|
||||
S_AXIL_AWVALID => '0',
|
||||
S_AXIL_BREADY => '0',
|
||||
S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED,
|
||||
S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0),
|
||||
S_AXIL_RREADY => '0',
|
||||
S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED,
|
||||
S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED,
|
||||
S_AXIL_WSTRB(3 downto 0) => B"1111",
|
||||
S_AXIL_WVALID => '0',
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component af_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => axis_audio_slave_sim_0_FINISHED
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,205 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 15:22:42 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target af_sim.bd
|
||||
--Design : af_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity af_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef";
|
||||
end af_sim;
|
||||
|
||||
architecture STRUCTURE of af_sim is
|
||||
component af_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_clk_rst_generator_0_0;
|
||||
component af_sim_axis_audio_master_si_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_master_si_0_0;
|
||||
component af_sim_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_mono2ster_0_0;
|
||||
component af_sim_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_stereo2mo_0_0;
|
||||
component af_sim_axis_audio_slave_sim_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_slave_sim_0_0;
|
||||
component af_sim_axis_prog_audio_filt_0_0 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_prog_audio_filt_0_0;
|
||||
signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
begin
|
||||
axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
FINISHED => axis_audio_slave_sim_0_FINISHED,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED,
|
||||
S_AXIL_ARVALID => '0',
|
||||
S_AXIL_AWADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED,
|
||||
S_AXIL_AWVALID => '0',
|
||||
S_AXIL_BREADY => '0',
|
||||
S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED,
|
||||
S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0),
|
||||
S_AXIL_RREADY => '0',
|
||||
S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED,
|
||||
S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED,
|
||||
S_AXIL_WSTRB(3 downto 0) => B"1111",
|
||||
S_AXIL_WVALID => '0',
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component af_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => axis_audio_slave_sim_0_FINISHED
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "design_1",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "design_1",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732630534"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732630534"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732630534"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732630534"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 15:15:29 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1_wrapper.bd
|
||||
--Design : design_1_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_wrapper is
|
||||
port (
|
||||
bclk : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
i2c_scl_io : inout STD_LOGIC;
|
||||
i2c_sda_io : inout STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
reset : in STD_LOGIC
|
||||
);
|
||||
end design_1_wrapper;
|
||||
|
||||
architecture STRUCTURE of design_1_wrapper is
|
||||
component design_1 is
|
||||
port (
|
||||
i2c_scl_t : out STD_LOGIC;
|
||||
i2c_sda_o : out STD_LOGIC;
|
||||
i2c_sda_i : in STD_LOGIC;
|
||||
i2c_scl_o : out STD_LOGIC;
|
||||
i2c_scl_i : in STD_LOGIC;
|
||||
i2c_sda_t : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
reset : in STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC
|
||||
);
|
||||
end component design_1;
|
||||
component IOBUF is
|
||||
port (
|
||||
I : in STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
T : in STD_LOGIC;
|
||||
IO : inout STD_LOGIC
|
||||
);
|
||||
end component IOBUF;
|
||||
signal i2c_scl_i : STD_LOGIC;
|
||||
signal i2c_scl_o : STD_LOGIC;
|
||||
signal i2c_scl_t : STD_LOGIC;
|
||||
signal i2c_sda_i : STD_LOGIC;
|
||||
signal i2c_sda_o : STD_LOGIC;
|
||||
signal i2c_sda_t : STD_LOGIC;
|
||||
begin
|
||||
design_1_i: component design_1
|
||||
port map (
|
||||
bclk => bclk,
|
||||
clk => clk,
|
||||
i2c_scl_i => i2c_scl_i,
|
||||
i2c_scl_o => i2c_scl_o,
|
||||
i2c_scl_t => i2c_scl_t,
|
||||
i2c_sda_i => i2c_sda_i,
|
||||
i2c_sda_o => i2c_sda_o,
|
||||
i2c_sda_t => i2c_sda_t,
|
||||
mclk => mclk,
|
||||
mute => mute,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc,
|
||||
reset => reset
|
||||
);
|
||||
i2c_scl_iobuf: component IOBUF
|
||||
port map (
|
||||
I => i2c_scl_o,
|
||||
IO => i2c_scl_io,
|
||||
O => i2c_scl_i,
|
||||
T => i2c_scl_t
|
||||
);
|
||||
i2c_sda_iobuf: component IOBUF
|
||||
port map (
|
||||
I => i2c_sda_o,
|
||||
IO => i2c_sda_io,
|
||||
O => i2c_sda_i,
|
||||
T => i2c_sda_t
|
||||
);
|
||||
end STRUCTURE;
|
||||
+1250
File diff suppressed because it is too large
Load Diff
+836
@@ -0,0 +1,836 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:27d6e957</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
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<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e1ff5562</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:25:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_audio_stereo2mo_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e1ff5562</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_audio_stereo2mo_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
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|
||||
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|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
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|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
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|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
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+974
@@ -0,0 +1,974 @@
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_READ_THREADS": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_WRITE_THREADS": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "default"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "default"
|
||||
},
|
||||
"RUSER_BITS_PER_BYTE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"WUSER_BITS_PER_BYTE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_2_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "resetn"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"ila_lib": {
|
||||
"vlnv": "xilinx.com:ip:ila:6.2",
|
||||
"xci_name": "bd_f60c_ila_lib_0",
|
||||
"xci_path": "ip\\ip_0\\bd_f60c_ila_lib_0.xci",
|
||||
"inst_hier_path": "ila_lib",
|
||||
"parameters": {
|
||||
"ALL_PROBE_SAME_MU": {
|
||||
"value": "TRUE"
|
||||
},
|
||||
"ALL_PROBE_SAME_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_ADV_TRIGGER": {
|
||||
"value": "FALSE"
|
||||
},
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "16384"
|
||||
},
|
||||
"C_EN_STRG_QUAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_ILA_CLK_FREQ": {
|
||||
"value": "100000000"
|
||||
},
|
||||
"C_INPUT_PIPE_STAGES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_MONITOR_TYPE": {
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "26"
|
||||
},
|
||||
"C_PROBE0_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE0_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE10_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE10_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE11_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE11_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE12_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE12_WIDTH": {
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE13_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE13_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE14_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE14_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE15_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE15_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE16_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE16_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE17_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE17_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE18_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE18_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE19_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE19_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE20_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE20_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE21_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE21_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE22_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE22_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE23_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE23_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE24_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE24_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE25_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE25_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE2_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE2_WIDTH": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE3_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE3_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE4_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE4_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE5_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE5_WIDTH": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE6_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE6_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE7_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE7_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE8_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE8_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE9_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE9_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_TRIGIN_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_TRIGOUT_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_XLNX_HW_PROBE_INFO": {
|
||||
"value": "DEFAULT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"g_inst": {
|
||||
"vlnv": "xilinx.com:ip:gigantic_mux:1.0",
|
||||
"xci_name": "bd_f60c_g_inst_0",
|
||||
"xci_path": "ip\\ip_1\\bd_f60c_g_inst_0.xci",
|
||||
"inst_hier_path": "g_inst",
|
||||
"parameters": {
|
||||
"C_EN_GIGAMUX": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_ADDR_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_SLOT_0_AXI_ARUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_AR_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_AWUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_AW_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_AXLEN_WIDTH": {
|
||||
"value": "8"
|
||||
},
|
||||
"C_SLOT_0_AXI_AXLOCK_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_BUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_B_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_DATA_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_SLOT_0_AXI_ID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_PROTOCOL": {
|
||||
"value": "AXI4LITE"
|
||||
},
|
||||
"C_SLOT_0_AXI_RUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_R_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_WUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_W_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_BRESP": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_BURST": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_CACHE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_LOCK": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_PROT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_QOS": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_REGION": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_RRESP": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_WSTRB": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_MAX_RD_BURSTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_MAX_WR_BURSTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_0_TXN_CNTR_EN": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_1_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_2_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_2_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_MON_MODE": {
|
||||
"value": "FT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"slot_0_aw": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_aw_0",
|
||||
"xci_path": "ip\\ip_2\\bd_f60c_slot_0_aw_0.xci",
|
||||
"inst_hier_path": "slot_0_aw"
|
||||
},
|
||||
"slot_0_w": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_w_0",
|
||||
"xci_path": "ip\\ip_3\\bd_f60c_slot_0_w_0.xci",
|
||||
"inst_hier_path": "slot_0_w",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
},
|
||||
"slot_0_b": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_b_0",
|
||||
"xci_path": "ip\\ip_4\\bd_f60c_slot_0_b_0.xci",
|
||||
"inst_hier_path": "slot_0_b"
|
||||
},
|
||||
"slot_0_ar": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_ar_0",
|
||||
"xci_path": "ip\\ip_5\\bd_f60c_slot_0_ar_0.xci",
|
||||
"inst_hier_path": "slot_0_ar"
|
||||
},
|
||||
"slot_0_r": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_r_0",
|
||||
"xci_path": "ip\\ip_6\\bd_f60c_slot_0_r_0.xci",
|
||||
"inst_hier_path": "slot_0_r",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"SLOT_0_AXI",
|
||||
"g_inst/slot_0_axi"
|
||||
]
|
||||
},
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"SLOT_1_AXIS",
|
||||
"g_inst/slot_1_axis"
|
||||
]
|
||||
},
|
||||
"Conn2": {
|
||||
"interface_ports": [
|
||||
"SLOT_2_AXIS",
|
||||
"g_inst/slot_2_axis"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"ila_lib/clk",
|
||||
"g_inst/aclk"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_ar_cnt",
|
||||
"ila_lib/probe0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_ar/dout",
|
||||
"ila_lib/probe16"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_araddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_araddr",
|
||||
"ila_lib/probe1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arprot": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_arprot",
|
||||
"ila_lib/probe2"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_arready",
|
||||
"slot_0_ar/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_arvalid",
|
||||
"slot_0_ar/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_aw_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_aw_cnt",
|
||||
"ila_lib/probe3"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_aw_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_aw/dout",
|
||||
"ila_lib/probe13"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awaddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awaddr",
|
||||
"ila_lib/probe4"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awprot": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awprot",
|
||||
"ila_lib/probe5"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awready",
|
||||
"slot_0_aw/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awvalid",
|
||||
"slot_0_aw/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_b_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_b_cnt",
|
||||
"ila_lib/probe6"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_b_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_b/dout",
|
||||
"ila_lib/probe15"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bready",
|
||||
"slot_0_b/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bresp",
|
||||
"ila_lib/probe7"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bvalid",
|
||||
"slot_0_b/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_r_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_r_cnt",
|
||||
"ila_lib/probe8"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_r_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_r/dout",
|
||||
"ila_lib/probe17"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rdata",
|
||||
"ila_lib/probe9"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rready",
|
||||
"slot_0_r/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rresp",
|
||||
"ila_lib/probe10"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rvalid",
|
||||
"slot_0_r/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_w_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_w/dout",
|
||||
"ila_lib/probe14"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wdata",
|
||||
"ila_lib/probe11"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wready",
|
||||
"slot_0_w/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wstrb": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wstrb",
|
||||
"ila_lib/probe12"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wvalid",
|
||||
"slot_0_w/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tdata",
|
||||
"ila_lib/probe18"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tlast",
|
||||
"ila_lib/probe21"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tready",
|
||||
"ila_lib/probe20"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tvalid",
|
||||
"ila_lib/probe19"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tdata",
|
||||
"ila_lib/probe22"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tlast",
|
||||
"ila_lib/probe25"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tready",
|
||||
"ila_lib/probe24"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tvalid",
|
||||
"ila_lib/probe23"
|
||||
]
|
||||
},
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
"g_inst/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732630534"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732630534"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732630534"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732630534"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_f60c.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_f60c.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_f60c_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_system_ila_0_0.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_system_ila_0_0.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_f60c.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+6324
File diff suppressed because it is too large
Load Diff
+74986
File diff suppressed because it is too large
Load Diff
+3042
File diff suppressed because it is too large
Load Diff
+113981
File diff suppressed because it is too large
Load Diff
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_f60c_slot_0_aw_0",
|
||||
"cell_name": "slot_0_aw",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_f60c_slot_0_aw_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||
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+5065
File diff suppressed because it is too large
Load Diff
+307
@@ -0,0 +1,307 @@
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+5066
File diff suppressed because it is too large
Load Diff
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@@ -0,0 +1,307 @@
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+5065
File diff suppressed because it is too large
Load Diff
+307
@@ -0,0 +1,307 @@
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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+5065
File diff suppressed because it is too large
Load Diff
+307
@@ -0,0 +1,307 @@
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||||
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|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+5066
File diff suppressed because it is too large
Load Diff
+37244
File diff suppressed because it is too large
Load Diff
+1437
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,476 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 15:15:29 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1 is
|
||||
port (
|
||||
bclk : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
i2c_scl_i : in STD_LOGIC;
|
||||
i2c_scl_o : out STD_LOGIC;
|
||||
i2c_scl_t : out STD_LOGIC;
|
||||
i2c_sda_i : in STD_LOGIC;
|
||||
i2c_sda_o : out STD_LOGIC;
|
||||
i2c_sda_t : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
reset : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
|
||||
end design_1;
|
||||
|
||||
architecture STRUCTURE of design_1 is
|
||||
component design_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component design_1_clk_rst_generator_0_0;
|
||||
component design_1_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_stereo2mo_0_0;
|
||||
component design_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
interrupt_in : in STD_LOGIC;
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axil_master_with_rom_0_0;
|
||||
component design_1_system_ila_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end component design_1_system_ila_0_0;
|
||||
component design_1_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_mono2ster_0_0;
|
||||
component design_1_zybo_audio_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
axis_pb_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_pb_valid : in STD_LOGIC;
|
||||
axis_pb_ready : out STD_LOGIC;
|
||||
axis_rec_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_rec_valid : out STD_LOGIC;
|
||||
axis_rec_ready : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
scl_i : in STD_LOGIC;
|
||||
scl_o : out STD_LOGIC;
|
||||
scl_t : out STD_LOGIC;
|
||||
sda_i : in STD_LOGIC;
|
||||
sda_o : out STD_LOGIC;
|
||||
sda_t : out STD_LOGIC
|
||||
);
|
||||
end component design_1_zybo_audio_0_0;
|
||||
component design_1_axis_prog_audio_filt_0_1 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_prog_audio_filt_0_1;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DEBUG : string;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWADDR";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWPROT";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BRESP";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RDATA";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RRESP";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WDATA";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WSTRB";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TLAST";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal rec_dat_1 : STD_LOGIC;
|
||||
signal resez_1 : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal zybo_audio_0_axis_rec_TREADY : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TVALID : STD_LOGIC;
|
||||
signal zybo_audio_0_bclk : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_T : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_T : STD_LOGIC;
|
||||
signal zybo_audio_0_mclk : STD_LOGIC;
|
||||
signal zybo_audio_0_mute : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_dat : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_lrc : STD_LOGIC;
|
||||
signal zybo_audio_0_rec_lrc : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
begin
|
||||
bclk <= zybo_audio_0_bclk;
|
||||
clk_1 <= clk;
|
||||
i2c_scl_o <= zybo_audio_0_i2c_SCL_O;
|
||||
i2c_scl_t <= zybo_audio_0_i2c_SCL_T;
|
||||
i2c_sda_o <= zybo_audio_0_i2c_SDA_O;
|
||||
i2c_sda_t <= zybo_audio_0_i2c_SDA_T;
|
||||
mclk <= zybo_audio_0_mclk;
|
||||
mute <= zybo_audio_0_mute;
|
||||
pb_dat <= zybo_audio_0_pb_dat;
|
||||
pb_lrc <= zybo_audio_0_pb_lrc;
|
||||
rec_dat_1 <= rec_dat;
|
||||
rec_lrc <= zybo_audio_0_rec_lrc;
|
||||
resez_1 <= reset;
|
||||
zybo_audio_0_i2c_SCL_I <= i2c_scl_i;
|
||||
zybo_audio_0_i2c_SDA_I <= i2c_sda_i;
|
||||
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => '0'
|
||||
);
|
||||
axis_audio_mono2ster_0: component design_1_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_stereo2mo_0: component design_1_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => zybo_audio_0_axis_rec_TREADY,
|
||||
S_AXIS_TVALID => zybo_audio_0_axis_rec_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component design_1_axis_prog_audio_filt_0_1
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(7 downto 0),
|
||||
S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_AWADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(7 downto 0),
|
||||
S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component design_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => clk_1,
|
||||
rst_in => resez_1,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
system_ila_0: component design_1_system_ila_0_0
|
||||
port map (
|
||||
SLOT_0_AXI_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
SLOT_0_AXI_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
SLOT_0_AXI_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
SLOT_0_AXI_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
SLOT_0_AXI_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
SLOT_0_AXI_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
SLOT_0_AXI_bready => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
SLOT_0_AXI_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
SLOT_0_AXI_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
SLOT_0_AXI_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
SLOT_0_AXI_rready => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
SLOT_0_AXI_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
SLOT_0_AXI_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
SLOT_0_AXI_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
SLOT_0_AXI_wready => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
SLOT_0_AXI_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
SLOT_0_AXI_wvalid => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
SLOT_1_AXIS_tdata(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_1_AXIS_tlast => '0',
|
||||
SLOT_1_AXIS_tready => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
SLOT_1_AXIS_tvalid => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
SLOT_2_AXIS_tdata(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_2_AXIS_tlast => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
SLOT_2_AXIS_tready => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
SLOT_2_AXIS_tvalid => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n
|
||||
);
|
||||
zybo_audio_0: component design_1_zybo_audio_0_0
|
||||
port map (
|
||||
axis_pb_data(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
axis_pb_ready => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
axis_pb_valid => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
axis_rec_data(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
axis_rec_ready => zybo_audio_0_axis_rec_TREADY,
|
||||
axis_rec_valid => zybo_audio_0_axis_rec_TVALID,
|
||||
bclk => zybo_audio_0_bclk,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
mclk => zybo_audio_0_mclk,
|
||||
mute => zybo_audio_0_mute,
|
||||
pb_dat => zybo_audio_0_pb_dat,
|
||||
pb_lrc => zybo_audio_0_pb_lrc,
|
||||
rec_dat => rec_dat_1,
|
||||
rec_lrc => zybo_audio_0_rec_lrc,
|
||||
scl_i => zybo_audio_0_i2c_SCL_I,
|
||||
scl_o => zybo_audio_0_i2c_SCL_O,
|
||||
scl_t => zybo_audio_0_i2c_SCL_T,
|
||||
sda_i => zybo_audio_0_i2c_SDA_I,
|
||||
sda_o => zybo_audio_0_i2c_SDA_O,
|
||||
sda_t => zybo_audio_0_i2c_SDA_T
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -0,0 +1,476 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 15:15:29 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1 is
|
||||
port (
|
||||
bclk : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
i2c_scl_i : in STD_LOGIC;
|
||||
i2c_scl_o : out STD_LOGIC;
|
||||
i2c_scl_t : out STD_LOGIC;
|
||||
i2c_sda_i : in STD_LOGIC;
|
||||
i2c_sda_o : out STD_LOGIC;
|
||||
i2c_sda_t : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
reset : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
|
||||
end design_1;
|
||||
|
||||
architecture STRUCTURE of design_1 is
|
||||
component design_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component design_1_clk_rst_generator_0_0;
|
||||
component design_1_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_stereo2mo_0_0;
|
||||
component design_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
interrupt_in : in STD_LOGIC;
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axil_master_with_rom_0_0;
|
||||
component design_1_system_ila_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end component design_1_system_ila_0_0;
|
||||
component design_1_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_mono2ster_0_0;
|
||||
component design_1_zybo_audio_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
axis_pb_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_pb_valid : in STD_LOGIC;
|
||||
axis_pb_ready : out STD_LOGIC;
|
||||
axis_rec_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_rec_valid : out STD_LOGIC;
|
||||
axis_rec_ready : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
scl_i : in STD_LOGIC;
|
||||
scl_o : out STD_LOGIC;
|
||||
scl_t : out STD_LOGIC;
|
||||
sda_i : in STD_LOGIC;
|
||||
sda_o : out STD_LOGIC;
|
||||
sda_t : out STD_LOGIC
|
||||
);
|
||||
end component design_1_zybo_audio_0_0;
|
||||
component design_1_axis_prog_audio_filt_0_1 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_prog_audio_filt_0_1;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DEBUG : string;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWADDR";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWPROT";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BRESP";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RDATA";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RRESP";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WDATA";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WREADY";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WSTRB";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WVALID";
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TLAST";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal rec_dat_1 : STD_LOGIC;
|
||||
signal resez_1 : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal zybo_audio_0_axis_rec_TREADY : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TVALID : STD_LOGIC;
|
||||
signal zybo_audio_0_bclk : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_T : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_T : STD_LOGIC;
|
||||
signal zybo_audio_0_mclk : STD_LOGIC;
|
||||
signal zybo_audio_0_mute : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_dat : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_lrc : STD_LOGIC;
|
||||
signal zybo_audio_0_rec_lrc : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
begin
|
||||
bclk <= zybo_audio_0_bclk;
|
||||
clk_1 <= clk;
|
||||
i2c_scl_o <= zybo_audio_0_i2c_SCL_O;
|
||||
i2c_scl_t <= zybo_audio_0_i2c_SCL_T;
|
||||
i2c_sda_o <= zybo_audio_0_i2c_SDA_O;
|
||||
i2c_sda_t <= zybo_audio_0_i2c_SDA_T;
|
||||
mclk <= zybo_audio_0_mclk;
|
||||
mute <= zybo_audio_0_mute;
|
||||
pb_dat <= zybo_audio_0_pb_dat;
|
||||
pb_lrc <= zybo_audio_0_pb_lrc;
|
||||
rec_dat_1 <= rec_dat;
|
||||
rec_lrc <= zybo_audio_0_rec_lrc;
|
||||
resez_1 <= reset;
|
||||
zybo_audio_0_i2c_SCL_I <= i2c_scl_i;
|
||||
zybo_audio_0_i2c_SDA_I <= i2c_sda_i;
|
||||
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => '0'
|
||||
);
|
||||
axis_audio_mono2ster_0: component design_1_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_stereo2mo_0: component design_1_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => zybo_audio_0_axis_rec_TREADY,
|
||||
S_AXIS_TVALID => zybo_audio_0_axis_rec_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component design_1_axis_prog_audio_filt_0_1
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(7 downto 0),
|
||||
S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_AWADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(7 downto 0),
|
||||
S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component design_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => clk_1,
|
||||
rst_in => resez_1,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
system_ila_0: component design_1_system_ila_0_0
|
||||
port map (
|
||||
SLOT_0_AXI_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
SLOT_0_AXI_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
SLOT_0_AXI_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
SLOT_0_AXI_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
SLOT_0_AXI_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
SLOT_0_AXI_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
SLOT_0_AXI_bready => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
SLOT_0_AXI_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
SLOT_0_AXI_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
SLOT_0_AXI_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
SLOT_0_AXI_rready => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
SLOT_0_AXI_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
SLOT_0_AXI_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
SLOT_0_AXI_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
SLOT_0_AXI_wready => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
SLOT_0_AXI_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
SLOT_0_AXI_wvalid => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
SLOT_1_AXIS_tdata(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_1_AXIS_tlast => '0',
|
||||
SLOT_1_AXIS_tready => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
SLOT_1_AXIS_tvalid => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
SLOT_2_AXIS_tdata(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_2_AXIS_tlast => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
SLOT_2_AXIS_tready => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
SLOT_2_AXIS_tvalid => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n
|
||||
);
|
||||
zybo_audio_0: component design_1_zybo_audio_0_0
|
||||
port map (
|
||||
axis_pb_data(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
axis_pb_ready => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
axis_pb_valid => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
axis_rec_data(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
axis_rec_ready => zybo_audio_0_axis_rec_TREADY,
|
||||
axis_rec_valid => zybo_audio_0_axis_rec_TVALID,
|
||||
bclk => zybo_audio_0_bclk,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
mclk => zybo_audio_0_mclk,
|
||||
mute => zybo_audio_0_mute,
|
||||
pb_dat => zybo_audio_0_pb_dat,
|
||||
pb_lrc => zybo_audio_0_pb_lrc,
|
||||
rec_dat => rec_dat_1,
|
||||
rec_lrc => zybo_audio_0_rec_lrc,
|
||||
scl_i => zybo_audio_0_i2c_SCL_I,
|
||||
scl_o => zybo_audio_0_i2c_SCL_O,
|
||||
scl_t => zybo_audio_0_i2c_SCL_T,
|
||||
sda_i => zybo_audio_0_i2c_SDA_I,
|
||||
sda_o => zybo_audio_0_i2c_SDA_O,
|
||||
sda_t => zybo_audio_0_i2c_SDA_T
|
||||
);
|
||||
end STRUCTURE;
|
||||
+864
@@ -0,0 +1,864 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>axis_prog_audio_filter3</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIL</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave>
|
||||
<spirit:memoryMapRef spirit:memoryMapRef="S_AXIL"/>
|
||||
</spirit:slave>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWADDR</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WSTRB</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BRESP</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BREADY</spirit:name>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIL_RREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIL_RRESP</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>COEFF_0</spirit:name>
|
||||
<spirit:displayName>Coeff 0</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_0">42</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>COEFF_1</spirit:name>
|
||||
<spirit:displayName>Coeff 1</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_1">42</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>COEFF_2</spirit:name>
|
||||
<spirit:displayName>Coeff 2</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_2">42</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SHIFT</spirit:name>
|
||||
<spirit:displayName>Shift</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHIFT">7</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>RUN_AFTER_RESET</spirit:name>
|
||||
<spirit:displayName>Run After Reset</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RUN_AFTER_RESET">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axis_prog_audio_filter3_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_5efbb7ff</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_prog_audio_filter3:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_0</spirit:name>
|
||||
<spirit:displayName>Coeff 0</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_0">42</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_1</spirit:name>
|
||||
<spirit:displayName>Coeff 1</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_1">42</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_2</spirit:name>
|
||||
<spirit:displayName>Coeff 2</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_2">42</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SHIFT</spirit:name>
|
||||
<spirit:displayName>Shift</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SHIFT">7</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RUN_AFTER_RESET</spirit:name>
|
||||
<spirit:displayName>Run After Reset</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RUN_AFTER_RESET">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_prog_audio_filter3_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axis_prog_audio_filter3_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-11-26T14:02:40Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+100
@@ -0,0 +1,100 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "COEFF_0" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "COEFF_1" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "COEFF_2" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "HAS_LAST" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "RUN_AFTER_RESET" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SHIFT" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_0 { PARAM_VALUE.COEFF_0 } {
|
||||
# Procedure called to update COEFF_0 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_0 { PARAM_VALUE.COEFF_0 } {
|
||||
# Procedure called to validate COEFF_0
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_1 { PARAM_VALUE.COEFF_1 } {
|
||||
# Procedure called to update COEFF_1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_1 { PARAM_VALUE.COEFF_1 } {
|
||||
# Procedure called to validate COEFF_1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_2 { PARAM_VALUE.COEFF_2 } {
|
||||
# Procedure called to update COEFF_2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_2 { PARAM_VALUE.COEFF_2 } {
|
||||
# Procedure called to validate COEFF_2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.HAS_LAST { PARAM_VALUE.HAS_LAST } {
|
||||
# Procedure called to update HAS_LAST when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.HAS_LAST { PARAM_VALUE.HAS_LAST } {
|
||||
# Procedure called to validate HAS_LAST
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.RUN_AFTER_RESET { PARAM_VALUE.RUN_AFTER_RESET } {
|
||||
# Procedure called to update RUN_AFTER_RESET when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.RUN_AFTER_RESET { PARAM_VALUE.RUN_AFTER_RESET } {
|
||||
# Procedure called to validate RUN_AFTER_RESET
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SHIFT { PARAM_VALUE.SHIFT } {
|
||||
# Procedure called to update SHIFT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SHIFT { PARAM_VALUE.SHIFT } {
|
||||
# Procedure called to validate SHIFT
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_0 { MODELPARAM_VALUE.COEFF_0 PARAM_VALUE.COEFF_0 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_0}] ${MODELPARAM_VALUE.COEFF_0}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_1 { MODELPARAM_VALUE.COEFF_1 PARAM_VALUE.COEFF_1 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_1}] ${MODELPARAM_VALUE.COEFF_1}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_2 { MODELPARAM_VALUE.COEFF_2 PARAM_VALUE.COEFF_2 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_2}] ${MODELPARAM_VALUE.COEFF_2}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SHIFT { MODELPARAM_VALUE.SHIFT PARAM_VALUE.SHIFT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SHIFT}] ${MODELPARAM_VALUE.SHIFT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.RUN_AFTER_RESET { MODELPARAM_VALUE.RUN_AFTER_RESET PARAM_VALUE.RUN_AFTER_RESET } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.RUN_AFTER_RESET}] ${MODELPARAM_VALUE.RUN_AFTER_RESET}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.HAS_LAST { MODELPARAM_VALUE.HAS_LAST PARAM_VALUE.HAS_LAST } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.HAS_LAST}] ${MODELPARAM_VALUE.HAS_LAST}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,490 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../es-milestone3.gen/sources_1/bd/af_sim",
|
||||
"name": "af_sim",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
"axis_audio_master_si_0": "",
|
||||
"axis_audio_mono2ster_0": "",
|
||||
"axis_audio_stereo2mo_0": "",
|
||||
"axis_audio_slave_sim_0": "",
|
||||
"axis_prog_audio_filt_0": ""
|
||||
},
|
||||
"components": {
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "af_sim_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\af_sim_clk_rst_generator_0_0\\af_sim_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0",
|
||||
"parameters": {
|
||||
"CLOCK_PERIOD": {
|
||||
"value": "8000"
|
||||
},
|
||||
"HAS_CLK_INPUT": {
|
||||
"value": "false"
|
||||
},
|
||||
"HAS_RESET_INPUT": {
|
||||
"value": "false"
|
||||
},
|
||||
"HAS_STOP_INPUT": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_master_si_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_master_simmodel:1.0",
|
||||
"xci_name": "af_sim_axis_audio_master_si_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_master_si_0_0\\af_sim_axis_audio_master_si_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_master_si_0",
|
||||
"parameters": {
|
||||
"CLOCK_CYCLES_PER_SAMPLE": {
|
||||
"value": "5"
|
||||
},
|
||||
"FILE_NAME": {
|
||||
"value": "../../../../HaveANiceDay"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_mono2ster_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"xci_name": "af_sim_axis_audio_mono2ster_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_mono2ster_0_0\\af_sim_axis_audio_mono2ster_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_mono2ster_0"
|
||||
},
|
||||
"axis_audio_stereo2mo_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"xci_name": "af_sim_axis_audio_stereo2mo_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_stereo2mo_0_0\\af_sim_axis_audio_stereo2mo_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_stereo2mo_0"
|
||||
},
|
||||
"axis_audio_slave_sim_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_slave_simmodel:1.0",
|
||||
"xci_name": "af_sim_axis_audio_slave_sim_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_slave_sim_0_0\\af_sim_axis_audio_slave_sim_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_slave_sim_0",
|
||||
"parameters": {
|
||||
"FILE_NAME": {
|
||||
"value": "../../../../sim_out"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_prog_audio_filt_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"xci_name": "af_sim_axis_prog_audio_filt_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_prog_audio_filt_0_0\\af_sim_axis_prog_audio_filt_0_0.xci",
|
||||
"inst_hier_path": "axis_prog_audio_filt_0",
|
||||
"parameters": {
|
||||
"COEFF_0": {
|
||||
"value": "16"
|
||||
},
|
||||
"COEFF_1": {
|
||||
"value": "32"
|
||||
},
|
||||
"COEFF_2": {
|
||||
"value": "16"
|
||||
},
|
||||
"SHIFT": {
|
||||
"value": "6"
|
||||
}
|
||||
},
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_prog_audio_filter3",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ADDR_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
}
|
||||
},
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"port_maps": {
|
||||
"AWADDR": {
|
||||
"physical_name": "S_AXIL_AWADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "S_AXIL_AWVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "S_AXIL_AWREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "S_AXIL_WDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "S_AXIL_WSTRB",
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "S_AXIL_WVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "S_AXIL_WREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "S_AXIL_BRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "S_AXIL_BVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "S_AXIL_BREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "S_AXIL_ARADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "S_AXIL_ARVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "S_AXIL_ARREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "S_AXIL_RDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "S_AXIL_RRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "S_AXIL_RVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "S_AXIL_RREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"AXI_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "AXI_ARESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axis_audio_master_si_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_master_si_0/M_AXIS",
|
||||
"axis_audio_stereo2mo_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_audio_mono2ster_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_mono2ster_0/M_AXIS",
|
||||
"axis_audio_slave_sim_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_audio_stereo2mo_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_stereo2mo_0/M_AXIS",
|
||||
"axis_prog_audio_filt_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_prog_audio_filt_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_prog_audio_filt_0/M_AXIS",
|
||||
"axis_audio_mono2ster_0/S_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"axis_audio_master_si_0_WAV_HEADER": {
|
||||
"ports": [
|
||||
"axis_audio_master_si_0/WAV_HEADER",
|
||||
"axis_audio_slave_sim_0/WAV_HEADER"
|
||||
]
|
||||
},
|
||||
"axis_audio_slave_sim_0_FINISHED": {
|
||||
"ports": [
|
||||
"axis_audio_slave_sim_0/FINISHED",
|
||||
"clk_rst_generator_0/stop_simulation"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_audio_master_si_0/ACLK",
|
||||
"axis_audio_stereo2mo_0/AXIS_ACLK",
|
||||
"axis_audio_mono2ster_0/AXIS_ACLK",
|
||||
"axis_audio_slave_sim_0/ACLK",
|
||||
"axis_prog_audio_filt_0/AXI_ACLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axis_audio_master_si_0/ARESETN",
|
||||
"axis_audio_slave_sim_0/ARESETN",
|
||||
"axis_prog_audio_filt_0/AXI_ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "af_sim",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "af_sim",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+111
@@ -0,0 +1,111 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_master_si_0_0",
|
||||
"cell_name": "axis_audio_master_si_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_master_simmodel:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_CYCLES_PER_SAMPLE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FILE_NAME": [ { "value": "../../../../HaveANiceDay", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_master_si_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_CYCLES_PER_SAMPLE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FILE_NAME": [ { "value": "../../../../HaveANiceDay", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"ACLK": [ { "direction": "in" } ],
|
||||
"ARESETN": [ { "direction": "in" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"WAV_HEADER": [ { "direction": "out", "size_left": "351", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_mono2ster_0_0",
|
||||
"cell_name": "axis_audio_mono2ster_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_mono2ster_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+112
@@ -0,0 +1,112 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_slave_sim_0_0",
|
||||
"cell_name": "axis_audio_slave_sim_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_slave_simmodel:1.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FILE_NAME": [ { "value": "../../../../sim_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"RANDOM_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_slave_sim_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"FILE_NAME": [ { "value": "../../../../sim_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"RANDOM_TREADY": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"ACLK": [ { "direction": "in" } ],
|
||||
"ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"FINISHED": [ { "direction": "out" } ],
|
||||
"WAV_HEADER": [ { "direction": "in", "size_left": "351", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_stereo2mo_0_0",
|
||||
"cell_name": "axis_audio_stereo2mo_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_stereo2mo_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_stereo2mo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_stereo2mo_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+238
@@ -0,0 +1,238 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_prog_audio_filt_0_0",
|
||||
"cell_name": "axis_prog_audio_filt_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"COEFF_0": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"COEFF_1": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"COEFF_2": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SHIFT": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_prog_audio_filt_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"COEFF_0": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"COEFF_1": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"COEFF_2": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SHIFT": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXI_ACLK": [ { "direction": "in" } ],
|
||||
"AXI_ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_AWREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_WREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"S_AXIL_BVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIL_ARADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_ARREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIL_RVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
|
||||
"AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
|
||||
"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXI_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "AXI_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXI_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"display_name": "S_AXIL",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x1000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+55
@@ -0,0 +1,55 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "8000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "8000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Interfaces View",
|
||||
"Default View_ScaleFactor":"1.43494",
|
||||
"Default View_TopLeft":"-250,-605",
|
||||
"Display-PortTypeOthers":"false",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_Layout":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axis_audio_master_si_0 -pg 1 -lvl 2 -x 140 -y 60 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 780 -y 70 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 340 -y 60 -defaultsOSRD
|
||||
preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 980 -y 70 -defaultsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 560 -y 70 -defaultsOSRD
|
||||
preplace netloc axis_audio_master_si_0_WAV_HEADER 1 2 4 250J -40n NJ -40n NJ -40n 1080
|
||||
preplace netloc axis_audio_slave_sim_0_FINISHED 1 0 7 -240 -30n NJ -30n NJ -30n NJ -30n NJ -30n NJ -30n 1360
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 5 -10 -80n 260 -80n 540 -70n 830 -60n 1060
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 5 -20 -70n N -70n 530 -50n N -50n 1070
|
||||
preplace netloc axis_audio_master_si_0_M_AXIS 1 2 1 N 60
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 5 1 N 70
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 3 1 N 60
|
||||
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 4 1 N 70
|
||||
levelinfo -pg 1 0 20 140 340 560 780 980 1080
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1080 140
|
||||
",
|
||||
"Interfaces View_ScaleFactor":"1.39512",
|
||||
"Interfaces View_TopLeft":"32,-191",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 670 -y -160 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -130 -y -150 -defaultsOSRD
|
||||
preplace inst axis_audio_master_si_0 -pg 1 -lvl 2 -x 120 -y -150 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 940 -y -130 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 370 -y -150 -defaultsOSRD
|
||||
preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 1230 -y -140 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 5 -10 -80 260 -80 540 -70 830 -60 1050
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 5 -20 -70 N -70 530 -50 N -50 1060
|
||||
preplace netloc axis_audio_master_si_0_WAV_HEADER 1 2 4 250J -40 NJ -40 NJ -40 1070
|
||||
preplace netloc axis_audio_slave_sim_0_FINISHED 1 0 7 -240 -30 NJ -30 NJ -30 NJ -30 NJ -30 NJ -30 1360
|
||||
levelinfo -pg 1 -260 -130 120 370 670 940 1230 1380
|
||||
pagesize -pg 1 -db -bbox -sgen -260 -380 1380 350
|
||||
"
|
||||
}
|
||||
0
|
||||
@@ -0,0 +1,654 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x20E2EFC194C17796",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../es-milestone3.gen/sources_1/bd/design_1",
|
||||
"name": "design_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
"axis_audio_stereo2mo_0": "",
|
||||
"axil_master_with_rom_0": "",
|
||||
"system_ila_0": "",
|
||||
"axis_audio_mono2ster_0": "",
|
||||
"zybo_audio_0": "",
|
||||
"axis_prog_audio_filt_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"i2c": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:iic:1.0",
|
||||
"vlnv": "xilinx.com:interface:iic_rtl:1.0",
|
||||
"port_maps": {
|
||||
"SCL_T": {
|
||||
"physical_name": "i2c_scl_t",
|
||||
"direction": "O"
|
||||
},
|
||||
"SDA_O": {
|
||||
"physical_name": "i2c_sda_o",
|
||||
"direction": "O"
|
||||
},
|
||||
"SDA_I": {
|
||||
"physical_name": "i2c_sda_i",
|
||||
"direction": "I"
|
||||
},
|
||||
"SCL_O": {
|
||||
"physical_name": "i2c_scl_o",
|
||||
"direction": "O"
|
||||
},
|
||||
"SCL_I": {
|
||||
"physical_name": "i2c_scl_i",
|
||||
"direction": "I"
|
||||
},
|
||||
"SDA_T": {
|
||||
"physical_name": "i2c_sda_t",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"direction": "I"
|
||||
},
|
||||
"reset": {
|
||||
"direction": "I"
|
||||
},
|
||||
"rec_dat": {
|
||||
"direction": "I"
|
||||
},
|
||||
"mute": {
|
||||
"direction": "O"
|
||||
},
|
||||
"mclk": {
|
||||
"direction": "O"
|
||||
},
|
||||
"bclk": {
|
||||
"direction": "O"
|
||||
},
|
||||
"pb_dat": {
|
||||
"direction": "O"
|
||||
},
|
||||
"pb_lrc": {
|
||||
"direction": "O"
|
||||
},
|
||||
"rec_lrc": {
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0"
|
||||
},
|
||||
"axis_audio_stereo2mo_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"xci_name": "design_1_axis_audio_stereo2mo_0_0",
|
||||
"xci_path": "ip\\design_1_axis_audio_stereo2mo_0_0\\design_1_axis_audio_stereo2mo_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_stereo2mo_0"
|
||||
},
|
||||
"axil_master_with_rom_0": {
|
||||
"vlnv": "wg:user:axil_master_with_rom:1.0",
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
|
||||
"inst_hier_path": "axil_master_with_rom_0",
|
||||
"interface_ports": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"base_address": {
|
||||
"minimum": "0x00000000",
|
||||
"maximum": "0xFFFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"system_ila_0": {
|
||||
"vlnv": "xilinx.com:ip:system_ila:1.1",
|
||||
"xci_name": "design_1_system_ila_0_0",
|
||||
"xci_path": "ip\\design_1_system_ila_0_0\\design_1_system_ila_0_0.xci",
|
||||
"inst_hier_path": "system_ila_0",
|
||||
"parameters": {
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "16384"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_SLOT": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_SLOT_1_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"C_SLOT_2_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXI": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"SLOT_2_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_mono2ster_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"xci_name": "design_1_axis_audio_mono2ster_0_0",
|
||||
"xci_path": "ip\\design_1_axis_audio_mono2ster_0_0\\design_1_axis_audio_mono2ster_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_mono2ster_0"
|
||||
},
|
||||
"zybo_audio_0": {
|
||||
"vlnv": "xilinx.com:user:zybo_audio:1.0",
|
||||
"xci_name": "design_1_zybo_audio_0_0",
|
||||
"xci_path": "ip\\design_1_zybo_audio_0_0\\design_1_zybo_audio_0_0.xci",
|
||||
"inst_hier_path": "zybo_audio_0"
|
||||
},
|
||||
"axis_prog_audio_filt_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"xci_name": "design_1_axis_prog_audio_filt_0_1",
|
||||
"xci_path": "ip\\design_1_axis_prog_audio_filt_0_1\\design_1_axis_prog_audio_filt_0_1.xci",
|
||||
"inst_hier_path": "axis_prog_audio_filt_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_prog_audio_filter3",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ADDR_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
}
|
||||
},
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"port_maps": {
|
||||
"AWADDR": {
|
||||
"physical_name": "S_AXIL_AWADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "S_AXIL_AWVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "S_AXIL_AWREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "S_AXIL_WDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "S_AXIL_WSTRB",
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "S_AXIL_WVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "S_AXIL_WREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "S_AXIL_BRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "S_AXIL_BVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "S_AXIL_BREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "S_AXIL_ARADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "S_AXIL_ARVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "S_AXIL_ARREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "S_AXIL_RDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "S_AXIL_RRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "S_AXIL_RVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "S_AXIL_RREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"AXI_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "AXI_ARESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axil_master_with_rom_0_M_AXIL": {
|
||||
"interface_ports": [
|
||||
"axil_master_with_rom_0/M_AXIL",
|
||||
"axis_prog_audio_filt_0/S_AXIL",
|
||||
"system_ila_0/SLOT_0_AXI"
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_mono2ster_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_mono2ster_0/M_AXIS",
|
||||
"zybo_audio_0/axis_pb"
|
||||
]
|
||||
},
|
||||
"axis_audio_stereo2mo_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_stereo2mo_0/M_AXIS",
|
||||
"axis_prog_audio_filt_0/S_AXIS",
|
||||
"system_ila_0/SLOT_1_AXIS"
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_prog_audio_filt_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_prog_audio_filt_0/M_AXIS",
|
||||
"axis_audio_mono2ster_0/S_AXIS",
|
||||
"system_ila_0/SLOT_2_AXIS"
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"zybo_audio_0_axis_rec": {
|
||||
"interface_ports": [
|
||||
"zybo_audio_0/axis_rec",
|
||||
"axis_audio_stereo2mo_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_i2c": {
|
||||
"interface_ports": [
|
||||
"i2c",
|
||||
"zybo_audio_0/i2c"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"clk_rst_generator_0/clk_in"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_audio_stereo2mo_0/AXIS_ACLK",
|
||||
"axil_master_with_rom_0/M_AXIL_ACLK",
|
||||
"axis_audio_mono2ster_0/AXIS_ACLK",
|
||||
"zybo_audio_0/clk",
|
||||
"system_ila_0/clk",
|
||||
"axis_prog_audio_filt_0/AXI_ACLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axil_master_with_rom_0/M_AXIL_ARESETN",
|
||||
"system_ila_0/resetn",
|
||||
"axis_prog_audio_filt_0/AXI_ARESETN"
|
||||
]
|
||||
},
|
||||
"rec_dat_1": {
|
||||
"ports": [
|
||||
"rec_dat",
|
||||
"zybo_audio_0/rec_dat"
|
||||
]
|
||||
},
|
||||
"resez_1": {
|
||||
"ports": [
|
||||
"reset",
|
||||
"clk_rst_generator_0/rst_in"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_bclk": {
|
||||
"ports": [
|
||||
"zybo_audio_0/bclk",
|
||||
"bclk"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_mclk": {
|
||||
"ports": [
|
||||
"zybo_audio_0/mclk",
|
||||
"mclk"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_mute": {
|
||||
"ports": [
|
||||
"zybo_audio_0/mute",
|
||||
"mute"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_pb_dat": {
|
||||
"ports": [
|
||||
"zybo_audio_0/pb_dat",
|
||||
"pb_dat"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_pb_lrc": {
|
||||
"ports": [
|
||||
"zybo_audio_0/pb_lrc",
|
||||
"pb_lrc"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_rec_lrc": {
|
||||
"ports": [
|
||||
"zybo_audio_0/rec_lrc",
|
||||
"rec_lrc"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
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|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
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|
||||
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|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "design_1",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "design_1",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+171
@@ -0,0 +1,171 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"cell_name": "axil_master_with_rom_0",
|
||||
"component_reference": "wg:user:axil_master_with_rom:1.0",
|
||||
"ip_revision": "17",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
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|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "17" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"interrupt_in": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXIL_ACLK": [ { "direction": "in" } ],
|
||||
"M_AXIL_ARESETN": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIL_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
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|
||||
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|
||||
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|
||||
"M_AXIL_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"M_AXIL_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
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|
||||
"M_AXIL_BVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M_AXIL_AWADDR" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXIL_AWPROT" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXIL_ARADDR" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXIL_ARPROT" } ],
|
||||
"ARVALID": [ { "physical_name": "M_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "M_AXIL_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "M_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "M_AXIL_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "0x100000000",
|
||||
"display_name": "M_AXIL",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_audio_mono2ster_0_0",
|
||||
"cell_name": "axis_audio_mono2ster_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_audio_mono2ster_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_audio_stereo2mo_0_0",
|
||||
"cell_name": "axis_audio_stereo2mo_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_audio_stereo2mo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+238
@@ -0,0 +1,238 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_prog_audio_filt_0_1",
|
||||
"cell_name": "axis_prog_audio_filt_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"COEFF_0": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"COEFF_1": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"COEFF_2": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SHIFT": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_prog_audio_filt_0_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"COEFF_0": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"COEFF_1": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"COEFF_2": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SHIFT": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXI_ACLK": [ { "direction": "in" } ],
|
||||
"AXI_ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_AWREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_WREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"S_AXIL_BVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIL_ARADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_ARREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIL_RVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
|
||||
"AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
|
||||
"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXI_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "AXI_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXI_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"display_name": "S_AXIL",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x1000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"rst_in": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4042
File diff suppressed because it is too large
Load Diff
+159
@@ -0,0 +1,159 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_zybo_audio_0_0",
|
||||
"cell_name": "zybo_audio_0",
|
||||
"component_reference": "xilinx.com:user:zybo_audio:1.0",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"MIC_IN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"I2C_CLKDIV": [ { "value": "9999", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"I2S_CLKDIV": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_zybo_audio_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_RESET_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SRR_70": [ { "value": "\"00000000\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"MIC_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"I2C_CLKDIV": [ { "value": "9999", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"I2S_CLKDIV": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_RESET_PIN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SRR_70": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "22" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"axis_pb_data": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"axis_pb_valid": [ { "direction": "in" } ],
|
||||
"axis_pb_ready": [ { "direction": "out" } ],
|
||||
"axis_rec_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"axis_rec_valid": [ { "direction": "out" } ],
|
||||
"axis_rec_ready": [ { "direction": "in" } ],
|
||||
"mute": [ { "direction": "out" } ],
|
||||
"mclk": [ { "direction": "out" } ],
|
||||
"bclk": [ { "direction": "out" } ],
|
||||
"pb_dat": [ { "direction": "out" } ],
|
||||
"pb_lrc": [ { "direction": "out" } ],
|
||||
"rec_dat": [ { "direction": "in" } ],
|
||||
"rec_lrc": [ { "direction": "out" } ],
|
||||
"scl_i": [ { "direction": "in" } ],
|
||||
"scl_o": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"scl_t": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"sda_i": [ { "direction": "in" } ],
|
||||
"sda_o": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"sda_t": [ { "direction": "out", "driver_value": "0x1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis_rec:axis_pb", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"axis_pb": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_pb_data" } ],
|
||||
"TVALID": [ { "physical_name": "axis_pb_valid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_pb_ready" } ]
|
||||
}
|
||||
},
|
||||
"axis_rec": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_rec_data" } ],
|
||||
"TVALID": [ { "physical_name": "axis_rec_valid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_rec_ready" } ]
|
||||
}
|
||||
},
|
||||
"i2c": {
|
||||
"vlnv": "xilinx.com:interface:iic:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:iic_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"SCL_T": [ { "physical_name": "scl_t" } ],
|
||||
"SDA_O": [ { "physical_name": "sda_o" } ],
|
||||
"SDA_I": [ { "physical_name": "sda_i" } ],
|
||||
"SCL_O": [ { "physical_name": "scl_o" } ],
|
||||
"SCL_I": [ { "physical_name": "scl_i" } ],
|
||||
"SDA_T": [ { "physical_name": "sda_t" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.42004",
|
||||
"Default View_TopLeft":"20,-332",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port i2c -pg 1 -lvl 6 -x 1340 -y 80 -defaultsOSRD
|
||||
preplace port port-id_clk -pg 1 -lvl 0 -x -240 -y -40 -defaultsOSRD
|
||||
preplace port port-id_reset -pg 1 -lvl 0 -x -240 -y 0 -defaultsOSRD
|
||||
preplace port port-id_rec_dat -pg 1 -lvl 0 -x -240 -y 200 -defaultsOSRD
|
||||
preplace port port-id_mute -pg 1 -lvl 6 -x 1340 -y 10 -defaultsOSRD
|
||||
preplace port port-id_mclk -pg 1 -lvl 6 -x 1340 -y 230 -defaultsOSRD
|
||||
preplace port port-id_bclk -pg 1 -lvl 6 -x 1340 -y 260 -defaultsOSRD
|
||||
preplace port port-id_pb_dat -pg 1 -lvl 6 -x 1340 -y 40 -defaultsOSRD
|
||||
preplace port port-id_pb_lrc -pg 1 -lvl 6 -x 1340 -y 300 -defaultsOSRD
|
||||
preplace port port-id_rec_lrc -pg 1 -lvl 6 -x 1340 -y 190 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -20 -y 0 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 2 -x 320 -y -90 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 320 -y 110 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 4 -x 940 -y -170 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 940 -y 110 -defaultsOSRD
|
||||
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1170 -y 130 -defaultsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 640 -y -110 -defaultsOSRD
|
||||
preplace netloc clk_1 1 0 1 -220 -40n
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 500 0 820 180 1050
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 510 -20 830
|
||||
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 1060
|
||||
preplace netloc resez_1 1 0 1 N 0
|
||||
preplace netloc zybo_audio_0_bclk 1 5 1 1290 140n
|
||||
preplace netloc zybo_audio_0_mclk 1 5 1 1310 120n
|
||||
preplace netloc zybo_audio_0_mute 1 5 1 1290 10n
|
||||
preplace netloc zybo_audio_0_pb_dat 1 5 1 1300 40n
|
||||
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1280 180n
|
||||
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1320 190n
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 480 -210 NJ
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 N 110
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 490 -200 770J
|
||||
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 810 -170n
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1280
|
||||
preplace netloc zybo_audio_0_i2c 1 5 1 N 80
|
||||
levelinfo -pg 1 -240 -20 320 640 940 1170 1340
|
||||
pagesize -pg 1 -db -bbox -sgen -340 -420 1450 560
|
||||
"
|
||||
}
|
||||
0
|
||||
@@ -0,0 +1,513 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2023.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="ac364057cd1843739edfb55c505ac94b"/>
|
||||
<Option Name="Part" Val="xc7z020clg400-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2023.1"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2022.3"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2022.3"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../IP"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="21"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="9"/>
|
||||
<Option Name="WTModelSimExportSim" Val="9"/>
|
||||
<Option Name="WTQuestaExportSim" Val="9"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="9"/>
|
||||
<Option Name="WTRivieraExportSim" Val="9"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="9"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../sources/axis_audio_filter3.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
|
||||
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci">
|
||||
<Proxy FileSetName="design_1_system_ila_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xci">
|
||||
<Proxy FileSetName="design_1_zybo_audio_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/af_sim/af_sim.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/af_sim/hdl/af_sim_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../milestone3.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/af_sim_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="af_sim_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/design_1_wrapper_behav.wcfg"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/af_sim_wrapper_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_axis_audio_stereo2mo_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axis_audio_stereo2mo_0_0" RelGenDir="$PGENDIR/design_1_axis_audio_stereo2mo_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_axis_audio_stereo2mo_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_axil_master_with_rom_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axil_master_with_rom_0_0" RelGenDir="$PGENDIR/design_1_axil_master_with_rom_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_axil_master_with_rom_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_clk_rst_generator_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clk_rst_generator_0_0" RelGenDir="$PGENDIR/design_1_clk_rst_generator_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_clk_rst_generator_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_axis_audio_mono2ster_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axis_audio_mono2ster_0_0" RelGenDir="$PGENDIR/design_1_axis_audio_mono2ster_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_axis_audio_mono2ster_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_axis_prog_audio_filt_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axis_prog_audio_filt_0_1" RelGenDir="$PGENDIR/design_1_axis_prog_audio_filt_0_1">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_axis_prog_audio_filt_0_1"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_system_ila_0_0" RelGenDir="$PGENDIR/design_1_system_ila_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_system_ila_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="design_1_zybo_audio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_zybo_audio_0_0" RelGenDir="$PGENDIR/design_1_zybo_audio_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="design_1_zybo_audio_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="20">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axis_audio_stereo2mo_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_audio_stereo2mo_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_stereo2mo_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_audio_stereo2mo_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axil_master_with_rom_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axil_master_with_rom_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axil_master_with_rom_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axil_master_with_rom_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_clk_rst_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_rst_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_rst_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_rst_generator_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axis_audio_mono2ster_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_audio_mono2ster_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_mono2ster_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axis_prog_audio_filt_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_prog_audio_filt_0_1" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_zybo_audio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_zybo_audio_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_zybo_audio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axis_audio_stereo2mo_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_stereo2mo_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_audio_stereo2mo_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axil_master_with_rom_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axil_master_with_rom_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axil_master_with_rom_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_clk_rst_generator_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_rst_generator_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_rst_generator_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axis_audio_mono2ster_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_mono2ster_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_axis_prog_audio_filt_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="design_1_zybo_audio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_zybo_audio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Binary file not shown.
@@ -0,0 +1,18 @@
|
||||
0000000000000000000000000000000000000001
|
||||
0000000000000000000000000000000100001111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000010000001000000001000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011011110000001000001111000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000010000000010001110000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000100000000010000010000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000000000010000000000000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000000000000000
|
||||
@@ -0,0 +1,14 @@
|
||||
create_clock -add -name clk_pin -period 8.00 [get_ports clk ];
|
||||
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports clk]; # Board Clock (125 MHZ)
|
||||
|
||||
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports reset];
|
||||
|
||||
set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 PULLUP true} [get_ports i2c_scl_io];
|
||||
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 PULLUP true} [get_ports i2c_sda_io];
|
||||
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports bclk];
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports pb_dat];
|
||||
set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports pb_lrc];
|
||||
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports rec_dat];
|
||||
set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports rec_lrc];
|
||||
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports mute];
|
||||
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports mclk];
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
|
||||
architecture rtl of axis_prog_audio_filter3 is
|
||||
signal m_valid_sig : std_logic := '0';
|
||||
signal run : std_logic := '0';
|
||||
begin
|
||||
|
||||
process
|
||||
variable c0 : signed( 7 downto 0) := to_signed(COEFF_0,8);
|
||||
variable c1 : signed( 7 downto 0) := to_signed(COEFF_1,8);
|
||||
variable c2 : signed( 7 downto 0) := to_signed(COEFF_2,8);
|
||||
variable s0 : signed(15 downto 0) := (others=>'0');
|
||||
variable s1 : signed(15 downto 0) := (others=>'0');
|
||||
variable s2 : signed(15 downto 0) := (others=>'0');
|
||||
variable p0 : signed(23 downto 0);
|
||||
variable p1 : signed(23 downto 0);
|
||||
variable p2 : signed(23 downto 0);
|
||||
variable res : signed(25 downto 0);
|
||||
variable lshift : unsigned(2 downto 0) := to_unsigned(SHIFT, 3);
|
||||
begin
|
||||
wait until rising_edge(AXI_ACLK);
|
||||
|
||||
-- AXIL Slave Lesezugriff
|
||||
-- das koennen Sie selbst !!
|
||||
|
||||
-- AXI Slave Schreibzugriff
|
||||
-- das koennen Sie selbst !!
|
||||
|
||||
|
||||
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
|
||||
|
||||
if HAS_LAST then
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
end if;
|
||||
|
||||
m_valid_sig <= S_AXIS_TVALID;
|
||||
|
||||
if S_AXIS_TVALID = '1' then
|
||||
s2 := s1;
|
||||
s1 := s0;
|
||||
s0 := signed(S_AXIS_TDATA);
|
||||
|
||||
p0 := s0*c0;
|
||||
p1 := s1*c1;
|
||||
p2 := s2*c2;
|
||||
|
||||
res := (p0(23)&p0(23)&p0);
|
||||
res := res + (p1(23)&p1(23)&p1);
|
||||
res := res + (p2(23)&p2(23)&p2);
|
||||
|
||||
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Reset
|
||||
if AXI_ARESETN = '0' then
|
||||
S_AXIL_RVALID <= '0';
|
||||
S_AXIL_BVALID <= '0';
|
||||
|
||||
if RUN_AFTER_RESET = true then
|
||||
run <= '1';
|
||||
else
|
||||
run <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end;
|
||||
@@ -0,0 +1,181 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axis_prog_audio_filter3 is
|
||||
generic
|
||||
(
|
||||
COEFF_0 : integer := 42;
|
||||
COEFF_1 : integer := 42;
|
||||
COEFF_2 : integer := 42;
|
||||
SHIFT : integer := 7;
|
||||
RUN_AFTER_RESET : boolean := true;
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXI_ACLK : in std_logic;
|
||||
AXI_ARESETN : in std_logic;
|
||||
|
||||
--- Write address channel
|
||||
S_AXIL_AWADDR : in std_logic_vector(7 downto 0);
|
||||
S_AXIL_AWVALID : in std_logic;
|
||||
S_AXIL_AWREADY : out std_logic;
|
||||
--- Write data channel
|
||||
S_AXIL_WDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIL_WVALID : in std_logic;
|
||||
S_AXIL_WREADY : out std_logic;
|
||||
S_AXIL_WSTRB : in std_logic_vector((32/8)-1 downto 0);
|
||||
--- Write response channel
|
||||
S_AXIL_BVALID : out std_logic;
|
||||
S_AXIL_BREADY : in std_logic;
|
||||
S_AXIL_BRESP : out std_logic_vector(1 downto 0);
|
||||
--- Read address channel
|
||||
S_AXIL_ARADDR : in std_logic_vector(7 downto 0);
|
||||
S_AXIL_ARVALID : in std_logic;
|
||||
S_AXIL_ARREADY : out std_logic;
|
||||
--- Read data channel
|
||||
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
|
||||
S_AXIL_RVALID : out std_logic;
|
||||
S_AXIL_RREADY : in std_logic;
|
||||
S_AXIL_RRESP : out std_logic_vector(1 downto 0);
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(15 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(15 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axis_prog_audio_filter3 is
|
||||
|
||||
-- Signale fuer AXI-Lite Register
|
||||
signal ip_active : std_logic := '0';
|
||||
signal c0 : signed( 7 downto 0) := to_signed(COEFF_0,8);
|
||||
signal c1 : signed( 7 downto 0) := to_signed(COEFF_1,8);
|
||||
signal c2 : signed( 7 downto 0) := to_signed(COEFF_2,8);
|
||||
signal shift_sig : unsigned( 2 downto 0) := to_unsigned(SHIFT,3);
|
||||
|
||||
type T_STATE is (IDLE, CALC);
|
||||
signal state : T_STATE := IDLE;
|
||||
|
||||
begin
|
||||
|
||||
S_AXIL_BRESP <= (others=>'0'); -- No write errors
|
||||
S_AXIL_RRESP <= (others=>'0'); -- No read errors
|
||||
S_AXIL_ARREADY <= '1'; -- IP is always ready
|
||||
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
|
||||
|
||||
process
|
||||
variable s0 : signed(15 downto 0) := (others=>'0');
|
||||
variable s1 : signed(15 downto 0) := (others=>'0');
|
||||
variable s2 : signed(15 downto 0) := (others=>'0');
|
||||
variable p0 : signed(23 downto 0);
|
||||
variable p1 : signed(23 downto 0);
|
||||
variable p2 : signed(23 downto 0);
|
||||
variable res : signed(25 downto 0);
|
||||
|
||||
begin
|
||||
wait until rising_edge(AXI_ACLK);
|
||||
|
||||
-- AXI-Stream Schnittstelle
|
||||
if AXI_ARESETN = '0' then
|
||||
state <= IDLE;
|
||||
else
|
||||
if M_AXIS_TREADY = '1' then
|
||||
M_AXIS_TVALID <= '0';
|
||||
end if;
|
||||
|
||||
case state is
|
||||
when IDLE =>
|
||||
S_AXIS_TREADY <= '1';
|
||||
if S_AXIS_TVALID = '1' then
|
||||
s2 := s1;
|
||||
s1 := s0;
|
||||
s0 := signed(S_AXIS_TDATA);
|
||||
|
||||
p0 := s0*c0;
|
||||
p1 := s1*c1;
|
||||
p2 := s2*c2;
|
||||
|
||||
res := (p0(23)&p0(23)&p0);
|
||||
res := res + (p1(23)&p1(23)&p1);
|
||||
res := res + (p2(23)&p2(23)&p2);
|
||||
|
||||
state <= CALC;
|
||||
end if;
|
||||
when CALC =>
|
||||
M_AXIS_TVALID <= '1';
|
||||
S_AXIS_TREADY <= '1';
|
||||
M_AXIS_TDATA <= std_logic_vector(res(to_integer(shift_sig)+15 downto to_integer(shift_sig)));
|
||||
state <= IDLE;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- AXI-Lite Schnittstelle
|
||||
if AXI_ARESETN = '0' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
S_AXIL_RVALID <= '0';
|
||||
c0 <= to_signed(COEFF_0,8);
|
||||
c1 <= to_signed(COEFF_1,8);
|
||||
c2 <= to_signed(COEFF_2,8);
|
||||
shift_sig <= to_unsigned(SHIFT,3);
|
||||
ip_active <= '1';
|
||||
else
|
||||
-- Lesezugriff
|
||||
if S_AXIL_RREADY = '1' then
|
||||
S_AXIL_RVALID <= '0';
|
||||
end if;
|
||||
|
||||
if S_AXIL_ARVALID = '1' then
|
||||
S_AXIL_RDATA <= (others=>'0');
|
||||
if S_AXIL_ARADDR(7 downto 0) = x"00" then
|
||||
S_AXIL_RDATA(26 downto 0) <= std_logic_vector(shift_sig) & std_logic_vector(c2) & std_logic_vector(c1) & std_logic_vector(c0);
|
||||
elsif S_AXIL_ARADDR(7 downto 0) = x"04" then
|
||||
S_AXIL_RDATA(0) <= ip_active;
|
||||
end if;
|
||||
S_AXIL_RVALID <= '1';
|
||||
end if;
|
||||
|
||||
-- Schreibzugriff
|
||||
if S_AXIL_BREADY = '1' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
end if;
|
||||
|
||||
if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
|
||||
S_AXIL_BVALID <= '1';
|
||||
|
||||
-- Register schreiben
|
||||
if S_AXIL_AWADDR = x"00" then
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
ip_active <= S_AXIL_WDATA(0);
|
||||
end if;
|
||||
elsif S_AXIL_AWADDR = x"04" then
|
||||
if S_AXIL_WSTRB(0) = '1' then
|
||||
c0 <= signed(S_AXIL_WDATA(7 downto 0));
|
||||
end if;
|
||||
if S_AXIL_WSTRB(1) = '1' then
|
||||
c1 <= signed(S_AXIL_WDATA(15 downto 8));
|
||||
end if;
|
||||
if S_AXIL_WSTRB(2) = '1' then
|
||||
c2 <= signed(S_AXIL_WDATA(23 downto 16));
|
||||
end if;
|
||||
if S_AXIL_WSTRB(3) = '1' then
|
||||
shift_sig <= unsigned(S_AXIL_WDATA(26 downto 24));
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end;
|
||||
@@ -0,0 +1,18 @@
|
||||
0000000000000000000000000000000000000001
|
||||
0000000000000000000000000000000100001111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000010000001000000001000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011011110000001000001111000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000010000000010001110000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000100000000010000010000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000000000010000000000000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000000000000000
|
||||
@@ -0,0 +1,11 @@
|
||||
wal 0 1 # RUN auf 1
|
||||
wal 4 0x06102010 # LOW PASS
|
||||
slp 375000000 # sleep 3 sec
|
||||
wal 4 0x06F020F0 # HIGH PASS
|
||||
slp 375000000 # sleep 3 sec
|
||||
wal 4 0x061008E0 # BAND PASS
|
||||
slp 375000000 # sleep 3 sec
|
||||
wal 4 0x06200820 # BAND STOP
|
||||
slp 375000000 # sleep 3 sec
|
||||
wal 4 0x06004000 # PASS THRU
|
||||
slp 375000000 # sleep 3 sec
|
||||
Binary file not shown.
Reference in New Issue
Block a user