Hardware beschrieben und Blockschaltbild aufgebaut. => Filter macht bislang nichts
This commit is contained in:
Sebastian Meyer
@@ -2,10 +2,10 @@
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1733753232"/>
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||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1733753232"/>
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||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733753232"/>
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||||
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1733753232"/>
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||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1733781618"/>
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||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1733781618"/>
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||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733781618"/>
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||||
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1733781618"/>
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||||
<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\design_1.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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Binary file not shown.
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Before Width: | Height: | Size: 108 KiB |
@@ -61,19 +61,92 @@ architecture rtl of axis_video_filter is
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constant wRowProd : integer := wPixelSigned + wCoeff + 2;
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constant wFilterRes : integer := wRowProd+1 + 2;
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signal m_valid_sig1 : std_logic;
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signal m_valid_sig2 : std_logic;
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signal m_last_sig1 : std_logic;
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signal m_user_sig1 : std_logic;
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signal row1Result : signed(wRowProd-1 downto 0);
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signal row2Result : signed(wRowProd-1 downto 0);
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signal row3Result : signed(wRowProd-1 downto 0);
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signal coeff_11 : signed(wCoeff-1 downto 0);
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signal coeff_12 : signed(wCoeff-1 downto 0);
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signal coeff_13 : signed(wCoeff-1 downto 0);
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signal coeff_21 : signed(wCoeff-1 downto 0);
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signal coeff_22 : signed(wCoeff-1 downto 0);
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signal coeff_23 : signed(wCoeff-1 downto 0);
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signal coeff_31 : signed(wCoeff-1 downto 0);
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signal coeff_32 : signed(wCoeff-1 downto 0);
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signal coeff_33 : signed(wCoeff-1 downto 0);
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signal shiftAmount : unsigned(wShift-1 downto 0);
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begin
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S_AXIS_TREADY <= M_AXIS_TREADY;
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S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig1) or (not m_valid_sig2);
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-----------------------
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-- Filter Kernel
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-----------------------
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process
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-----------------------
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-- Filter Kernel
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-----------------------
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process
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variable data_11 : signed (wPixelSigned-1 downto 0);
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variable data_12 : signed (wPixelSigned-1 downto 0);
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variable data_13 : signed (wPixelSigned-1 downto 0);
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variable data_21 : signed (wPixelSigned-1 downto 0);
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variable data_22 : signed (wPixelSigned-1 downto 0);
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variable data_23 : signed (wPixelSigned-1 downto 0);
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variable data_31 : signed (wPixelSigned-1 downto 0);
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variable data_32 : signed (wPixelSigned-1 downto 0);
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variable data_33 : signed (wPixelSigned-1 downto 0);
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variable filterResult : signed (wFilterRes-1 downto 0);
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begin
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begin
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wait until rising_edge (ACLK);
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if ARESETN = '0' then
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m_valid_sig1 <= '0';
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m_valid_sig2 <= '0';
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else
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if M_AXIS_TREADY = '1' or m_valid_sig1='0' then
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data_11 := data_12;
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data_12 := data_13;
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data_13 := signed("0"&S_AXIS_TDATA(wPixel*3-1 downto wPixel*2));
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data_21 := data_22;
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data_22 := data_23;
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data_23 := signed("0"&S_AXIS_TDATA(wPixel*2-1 downto wPixel*1));
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data_31 := data_32;
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data_32 := data_33;
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data_33 := signed("0"&S_AXIS_TDATA(wPixel*1-1 downto wPixel*0));
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end process;
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row1Result <= resize(data_11*coeff_11,wRowProd) + resize(data_12*coeff_12,wRowProd) + resize(data_13*coeff_13,wRowProd);
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row2Result <= resize(data_21*coeff_21,wRowProd) + resize(data_22*coeff_22,wRowProd) + resize(data_23*coeff_23,wRowProd);
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row3Result <= resize(data_31*coeff_31,wRowProd) + resize(data_32*coeff_32,wRowProd) + resize(data_33*coeff_33,wRowProd);
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m_last_sig1 <= S_AXIS_TLAST;
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m_user_sig1 <= S_AXIS_TUSER(1);
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m_valid_sig1 <= S_AXIS_TVALID;
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end if;
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if M_AXIS_TREADY = '1' or m_valid_sig2='0' then
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filterResult := resize(row1Result,wFilterRes)+resize(row2Result,wFilterRes)+resize(row3Result,wFilterRes);
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filterResult := shift_right(filterResult, to_integer(shiftAmount));
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if (filterResult < 0) then
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filterResult := to_signed(0,wFilterRes);
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elsif (filterResult > 255) then
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filterResult := to_signed(255,wFilterRes);
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end if;
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M_AXIS_TDATA <= std_logic_vector(filterResult(7 downto 0));
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M_AXIS_TVALID <= m_valid_sig1;
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M_AXIS_TLAST <= m_last_sig1;
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M_AXIS_TUSER <= m_user_sig1;
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m_valid_sig2 <= m_valid_sig1;
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end if;
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end if;
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end process;
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@@ -94,24 +167,66 @@ process begin
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if ARESETN = '0' then
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S_AXIL_BVALID <= '0';
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S_AXIL_RVALID <= '0';
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coeff_11 <= (others=>'0');
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coeff_12 <= (others=>'0');
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coeff_13 <= (others=>'0');
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coeff_21 <= (others=>'0');
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coeff_22 <= (0=>'1',others=>'0');
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coeff_23 <= (others=>'0');
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coeff_31 <= (others=>'0');
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coeff_32 <= (others=>'0');
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coeff_33 <= (others=>'0');
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shiftAmount <= to_unsigned(0,wShift);
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else
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if S_AXIL_RREADY = '1' then
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S_AXIL_RVALID <= '0';
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end if;
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--Leselogik
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if S_AXIL_ARVALID = '1' then
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S_AXIL_RDATA <= (others=>'0');
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case (to_integer(unsigned(S_AXIL_ARADDR(5 downto 0)))) is
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when 0 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_11);
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when 4 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_12);
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when 8 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_13);
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when 12 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_21);
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when 16 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_22);
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when 20 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_23);
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when 24 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_31);
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when 28 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_32);
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when 32 => S_AXIL_RDATA <= (31 downto 8 => '0') & std_logic_vector(coeff_33);
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when 36 => S_AXIL_RDATA <= (31 downto 4 => '0') & std_logic_vector(shiftAmount);
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when others => null;
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end case;
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S_AXIL_RVALID <= '1';
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end if;
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if S_AXIL_BREADY = '1' then
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S_AXIL_BVALID <= '0';
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end if;
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if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
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S_AXIL_BVALID <= '1';
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end if;
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--schreiblogik
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if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
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S_AXIL_BVALID <= '0';
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S_AXIL_RDATA <= (others=>'0');
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if S_AXIL_WSTRB(0) = '1' then
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case (to_integer(unsigned(S_AXIL_AWADDR(5 downto 0)))) is
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when 0 => if S_AXIL_WSTRB(0) = '1' then coeff_11(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 4 => if S_AXIL_WSTRB(0) = '1' then coeff_12(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 8 => if S_AXIL_WSTRB(0) = '1' then coeff_13(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 12 => if S_AXIL_WSTRB(0) = '1' then coeff_21(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 16 => if S_AXIL_WSTRB(0) = '1' then coeff_22(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 20 => if S_AXIL_WSTRB(0) = '1' then coeff_23(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 24 => if S_AXIL_WSTRB(0) = '1' then coeff_31(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 28 => if S_AXIL_WSTRB(0) = '1' then coeff_32(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 32 => if S_AXIL_WSTRB(0) = '1' then coeff_33(7 downto 0) <= signed(S_AXIL_WDATA(7 downto 0)); end if;
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when 36 => if S_AXIL_WSTRB(0) = '1' then shiftAmount(3 downto 0) <= unsigned(S_AXIL_WDATA(3 downto 0)); end if;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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end;
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@@ -0,0 +1,57 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<Root MajorVersion="0" MinorVersion="40">
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||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1733787924"/>
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||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1733787924"/>
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||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1733787924"/>
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||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1733787924"/>
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||||
<FileCollection Name="SOURCES" Type="SOURCES">
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||||
<File Name="synth\design_1.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
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<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_ooc.xdc" Type="XDC">
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||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
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<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
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<UsedIn Val="SIMULATION"/>
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||||
<ProcessingOrder Val="NORMAL"/>
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</File>
|
||||
</FileCollection>
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||||
</CompositeFile>
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</Root>
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||||
@@ -0,0 +1,10 @@
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################################################################################
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# This XDC is used only for OOC mode of synthesis, implementation
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# This constraints file contains default clock frequencies to be used during
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# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
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# This constraints file is not used in normal top-down synthesis (default flow
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# of Vivado)
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################################################################################
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################################################################################
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@@ -0,0 +1,93 @@
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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//Date : Tue Dec 10 00:45:24 2024
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//Host : Bastistablet running 64-bit major release (build 9200)
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//Command : generate_target design_1_wrapper.bd
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//Design : design_1_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module design_1_wrapper
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(m_axi_lite_araddr,
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m_axi_lite_arprot,
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m_axi_lite_arready,
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m_axi_lite_arvalid,
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m_axi_lite_awaddr,
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m_axi_lite_awprot,
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m_axi_lite_awready,
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m_axi_lite_awvalid,
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m_axi_lite_bready,
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m_axi_lite_bresp,
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m_axi_lite_bvalid,
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||||
m_axi_lite_rdata,
|
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m_axi_lite_rready,
|
||||
m_axi_lite_rresp,
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m_axi_lite_rvalid,
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||||
m_axi_lite_wdata,
|
||||
m_axi_lite_wready,
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||||
m_axi_lite_wstrb,
|
||||
m_axi_lite_wvalid);
|
||||
output [31:0]m_axi_lite_araddr;
|
||||
output [2:0]m_axi_lite_arprot;
|
||||
input m_axi_lite_arready;
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||||
output m_axi_lite_arvalid;
|
||||
output [31:0]m_axi_lite_awaddr;
|
||||
output [2:0]m_axi_lite_awprot;
|
||||
input m_axi_lite_awready;
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||||
output m_axi_lite_awvalid;
|
||||
output m_axi_lite_bready;
|
||||
input [1:0]m_axi_lite_bresp;
|
||||
input m_axi_lite_bvalid;
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||||
input [31:0]m_axi_lite_rdata;
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||||
output m_axi_lite_rready;
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||||
input [1:0]m_axi_lite_rresp;
|
||||
input m_axi_lite_rvalid;
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||||
output [31:0]m_axi_lite_wdata;
|
||||
input m_axi_lite_wready;
|
||||
output [3:0]m_axi_lite_wstrb;
|
||||
output m_axi_lite_wvalid;
|
||||
|
||||
wire [31:0]m_axi_lite_araddr;
|
||||
wire [2:0]m_axi_lite_arprot;
|
||||
wire m_axi_lite_arready;
|
||||
wire m_axi_lite_arvalid;
|
||||
wire [31:0]m_axi_lite_awaddr;
|
||||
wire [2:0]m_axi_lite_awprot;
|
||||
wire m_axi_lite_awready;
|
||||
wire m_axi_lite_awvalid;
|
||||
wire m_axi_lite_bready;
|
||||
wire [1:0]m_axi_lite_bresp;
|
||||
wire m_axi_lite_bvalid;
|
||||
wire [31:0]m_axi_lite_rdata;
|
||||
wire m_axi_lite_rready;
|
||||
wire [1:0]m_axi_lite_rresp;
|
||||
wire m_axi_lite_rvalid;
|
||||
wire [31:0]m_axi_lite_wdata;
|
||||
wire m_axi_lite_wready;
|
||||
wire [3:0]m_axi_lite_wstrb;
|
||||
wire m_axi_lite_wvalid;
|
||||
|
||||
design_1 design_1_i
|
||||
(.m_axi_lite_araddr(m_axi_lite_araddr),
|
||||
.m_axi_lite_arprot(m_axi_lite_arprot),
|
||||
.m_axi_lite_arready(m_axi_lite_arready),
|
||||
.m_axi_lite_arvalid(m_axi_lite_arvalid),
|
||||
.m_axi_lite_awaddr(m_axi_lite_awaddr),
|
||||
.m_axi_lite_awprot(m_axi_lite_awprot),
|
||||
.m_axi_lite_awready(m_axi_lite_awready),
|
||||
.m_axi_lite_awvalid(m_axi_lite_awvalid),
|
||||
.m_axi_lite_bready(m_axi_lite_bready),
|
||||
.m_axi_lite_bresp(m_axi_lite_bresp),
|
||||
.m_axi_lite_bvalid(m_axi_lite_bvalid),
|
||||
.m_axi_lite_rdata(m_axi_lite_rdata),
|
||||
.m_axi_lite_rready(m_axi_lite_rready),
|
||||
.m_axi_lite_rresp(m_axi_lite_rresp),
|
||||
.m_axi_lite_rvalid(m_axi_lite_rvalid),
|
||||
.m_axi_lite_wdata(m_axi_lite_wdata),
|
||||
.m_axi_lite_wready(m_axi_lite_wready),
|
||||
.m_axi_lite_wstrb(m_axi_lite_wstrb),
|
||||
.m_axi_lite_wvalid(m_axi_lite_wvalid));
|
||||
endmodule
|
||||
+1102
File diff suppressed because it is too large
Load Diff
+177
@@ -0,0 +1,177 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:axil_master_with_rom:1.0
|
||||
-- IP Revision: 19
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axil_master_with_rom_0_0 IS
|
||||
PORT (
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axil_master_with_rom IS
|
||||
GENERIC (
|
||||
STIM_FILENAME : STRING;
|
||||
HAS_FINISHED_OUT : BOOLEAN;
|
||||
HAS_INTERRUPT_IN : BOOLEAN;
|
||||
REVISION_NO : INTEGER
|
||||
);
|
||||
PORT (
|
||||
interrupt_in : IN STD_LOGIC;
|
||||
finished_o : OUT STD_LOGIC;
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axil_master_with_rom;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
|
||||
"SERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axil_master_with_rom
|
||||
GENERIC MAP (
|
||||
STIM_FILENAME => "../../stimuli.mem",
|
||||
HAS_FINISHED_OUT => false,
|
||||
HAS_INTERRUPT_IN => false,
|
||||
REVISION_NO => 1
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt_in => '0',
|
||||
M_AXIL_ACLK => M_AXIL_ACLK,
|
||||
M_AXIL_ARESETN => M_AXIL_ARESETN,
|
||||
M_AXIL_ARREADY => M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => M_AXIL_ARVALID,
|
||||
M_AXIL_ARADDR => M_AXIL_ARADDR,
|
||||
M_AXIL_ARPROT => M_AXIL_ARPROT,
|
||||
M_AXIL_RREADY => M_AXIL_RREADY,
|
||||
M_AXIL_RVALID => M_AXIL_RVALID,
|
||||
M_AXIL_RDATA => M_AXIL_RDATA,
|
||||
M_AXIL_RRESP => M_AXIL_RRESP,
|
||||
M_AXIL_AWREADY => M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => M_AXIL_AWVALID,
|
||||
M_AXIL_AWADDR => M_AXIL_AWADDR,
|
||||
M_AXIL_AWPROT => M_AXIL_AWPROT,
|
||||
M_AXIL_WREADY => M_AXIL_WREADY,
|
||||
M_AXIL_WVALID => M_AXIL_WVALID,
|
||||
M_AXIL_WDATA => M_AXIL_WDATA,
|
||||
M_AXIL_WSTRB => M_AXIL_WSTRB,
|
||||
M_AXIL_BREADY => M_AXIL_BREADY,
|
||||
M_AXIL_BVALID => M_AXIL_BVALID,
|
||||
M_AXIL_BRESP => M_AXIL_BRESP
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0_arch;
|
||||
+779
@@ -0,0 +1,779 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_downsizer_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_downsizer</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b4dbaa33</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_downsizer_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b4dbaa33</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.WIDTH_OUT')) * spirit:decode(id('MODELPARAM_VALUE.SIZE_FACTOR'))) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH_OUT')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>WIDTH_OUT</spirit:name>
|
||||
<spirit:displayName>Width Out</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH_OUT">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SIZE_FACTOR">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9185/sources_1/new/axis_downsizer.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_axis_downsizer_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_downsizer_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>WIDTH_OUT</spirit:name>
|
||||
<spirit:displayName>Width Out</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH_OUT">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIZE_FACTOR">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_axis_downsizer_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_downsizer_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:user:axis_downsizer:1.0_ARCHIVE_LOCATION">d:/projekte/edvs/vivado/vivado/ip_projects/axis_downsizer/axis_downsizer.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SIZE_FACTOR" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="4ed6aff9"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0d56d993"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="745602f7"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c0a09c04"/>
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||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="bb0d91f4"/>
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</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_downsizer:1.0
|
||||
-- IP Revision: 2
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_downsizer_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
);
|
||||
END design_1_axis_downsizer_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_downsizer_0_0_arch OF design_1_axis_downsizer_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_downsizer_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_downsizer IS
|
||||
GENERIC (
|
||||
WIDTH_OUT : INTEGER;
|
||||
SIZE_FACTOR : INTEGER;
|
||||
BIG_ENDIAN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_downsizer;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_downsizer
|
||||
GENERIC MAP (
|
||||
WIDTH_OUT => 8,
|
||||
SIZE_FACTOR => 4,
|
||||
BIG_ENDIAN => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
AXIS_ARESETN => AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER
|
||||
);
|
||||
END design_1_axis_downsizer_0_0_arch;
|
||||
+896
@@ -0,0 +1,896 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_linemem_single_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>m_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tuser</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>m_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">3</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tuser</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:name>POLARITY</spirit:name>
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">m_axis:s_axis</spirit:value>
|
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|
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|
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|
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<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
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|
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|
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<spirit:name>FREQ_HZ</spirit:name>
|
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">100000000</spirit:value>
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|
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|
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|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
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|
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|
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<spirit:name>PHASE</spirit:name>
|
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<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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|
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|
||||
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|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN"/>
|
||||
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|
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|
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|
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|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT"/>
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|
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|
||||
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|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_linemem_single_master</spirit:modelName>
|
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<spirit:fileSetRef>
|
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
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|
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|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:c744c730</spirit:value>
|
||||
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<spirit:view>
|
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<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
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<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
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<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:language>vhdl</spirit:language>
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<spirit:modelName>design_1_axis_linemem_single_0_0</spirit:modelName>
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<spirit:fileSetRef>
|
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<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
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|
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<spirit:parameter>
|
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<spirit:name>GENtimestamp</spirit:name>
|
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<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
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|
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<spirit:parameter>
|
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<spirit:name>outputProductCRC</spirit:name>
|
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<spirit:value>9:c744c730</spirit:value>
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|
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|
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|
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|
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|
||||
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|
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<spirit:name>aclk</spirit:name>
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<spirit:wire>
|
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:port>
|
||||
<spirit:name>aresetn</spirit:name>
|
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<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
||||
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|
||||
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|
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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|
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|
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<spirit:driver>
|
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
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</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
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<spirit:port>
|
||||
<spirit:name>s_axis_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
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|
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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|
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axis_tuser</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.TUSER_WIDTH')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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<spirit:name>m_axis_tvalid</spirit:name>
|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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<spirit:port>
|
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<spirit:name>m_axis_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_LINES')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">23</spirit:left>
|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:port>
|
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<spirit:name>m_axis_tlast</spirit:name>
|
||||
<spirit:wire>
|
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<spirit:direction>out</spirit:direction>
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|
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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<spirit:port>
|
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<spirit:name>m_axis_tready</spirit:name>
|
||||
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|
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|
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|
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<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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<spirit:port>
|
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<spirit:name>m_axis_tuser</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_LINES')) * spirit:decode(id('MODELPARAM_VALUE.TUSER_WIDTH'))) - 1)">2</spirit:left>
|
||||
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|
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|
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|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>MAX_LINELEN</spirit:name>
|
||||
<spirit:displayName>Max Linelen</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_LINELEN">2048</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINES">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
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|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:displayName>Tuser Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TUSER_WIDTH">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
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|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9ba2/sources_1/new/bmem_dp.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
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|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9ba2/sources_1/new/axis_linemem_single_master.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
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|
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<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
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<spirit:file>
|
||||
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<spirit:name>MAX_LINELEN</spirit:name>
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<spirit:displayName>Max Linelen</spirit:displayName>
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<spirit:name>NUM_LINES</spirit:name>
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<spirit:displayName>Num Lines</spirit:displayName>
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<spirit:name>DATA_WIDTH</spirit:name>
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<spirit:displayName>Data Width</spirit:displayName>
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<spirit:name>TUSER_WIDTH</spirit:name>
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<spirit:displayName>Tuser Width</spirit:displayName>
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<spirit:name>Component_Name</spirit:name>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@4afed1de_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@60c75b5d_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4fdbb7bc_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@14715325_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@113fdba8_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@78f3a756_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2495bf64_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2b0b0a41_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@a7b102f_ARCHIVE_LOCATION">d:/ES-IP/IP/axis_linemem_single_master/axis_linemem_single_master.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3e7581fb"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="560625a6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="5f547e23"/>
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||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="16f58197"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="87330cb1"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+138
@@ -0,0 +1,138 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_linemem_single_master:1.0
|
||||
-- IP Revision: 17
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_linemem_single_0_0 IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_tlast : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
m_axis_tlast : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC;
|
||||
m_axis_tuser : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
|
||||
);
|
||||
END design_1_axis_linemem_single_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_linemem_single_0_0_arch OF design_1_axis_linemem_single_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_linemem_single_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_linemem_single_master IS
|
||||
GENERIC (
|
||||
MAX_LINELEN : INTEGER;
|
||||
NUM_LINES : INTEGER;
|
||||
DATA_WIDTH : INTEGER;
|
||||
TUSER_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_tvalid : IN STD_LOGIC;
|
||||
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_tlast : IN STD_LOGIC;
|
||||
s_axis_tready : OUT STD_LOGIC;
|
||||
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_tvalid : OUT STD_LOGIC;
|
||||
m_axis_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
m_axis_tlast : OUT STD_LOGIC;
|
||||
m_axis_tready : IN STD_LOGIC;
|
||||
m_axis_tuser : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_linemem_single_master;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF m_axis:s_axis, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_tvalid: SIGNAL IS "XIL_INTERFACENAME m_axis, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 m_axis TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_tvalid: SIGNAL IS "XIL_INTERFACENAME s_axis, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 s_axis TVALID";
|
||||
BEGIN
|
||||
U0 : axis_linemem_single_master
|
||||
GENERIC MAP (
|
||||
MAX_LINELEN => 2048,
|
||||
NUM_LINES => 3,
|
||||
DATA_WIDTH => 8,
|
||||
TUSER_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aresetn => aresetn,
|
||||
s_axis_tvalid => s_axis_tvalid,
|
||||
s_axis_tdata => s_axis_tdata,
|
||||
s_axis_tlast => s_axis_tlast,
|
||||
s_axis_tready => s_axis_tready,
|
||||
s_axis_tuser => s_axis_tuser,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tdata => m_axis_tdata,
|
||||
m_axis_tlast => m_axis_tlast,
|
||||
m_axis_tready => m_axis_tready,
|
||||
m_axis_tuser => m_axis_tuser
|
||||
);
|
||||
END design_1_axis_linemem_single_0_0_arch;
|
||||
+738
@@ -0,0 +1,738 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>Gehrke</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_master_simmodel_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>signal_reset</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>signal_clock</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_BUSIF">M_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_RESET">ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SIGNAL_CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axis_master_simmodel</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:82169cab</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_master_simmodel_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:82169cab</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>FINISHED</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.TUSERWIDTH')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_NUM_FREE</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.FIFO_AWIDTH')) - 1)">10</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXIS_NUM_FREE" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_FIFO_INTERFACE'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">32</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_FIFO_INTERFACE</spirit:name>
|
||||
<spirit:displayName>Has Fifo Interface</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_FIFO_INTERFACE">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FIFO_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Fifo Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_AWIDTH">11</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FIFO_REQUEST_TRESHOLD</spirit:name>
|
||||
<spirit:displayName>Fifo Request Treshold</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FIFO_REQUEST_TRESHOLD">32</spirit:value>
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</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="integer">
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||||
<spirit:name>TUSERWIDTH</spirit:name>
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||||
<spirit:displayName>Tuserwidth</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TUSERWIDTH">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="string">
|
||||
<spirit:name>FILE_NAME</spirit:name>
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||||
<spirit:displayName>File Name</spirit:displayName>
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||||
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FILE_NAME">../../../../Moewe-192x192</spirit:value>
|
||||
</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="string">
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||||
<spirit:name>FILE_EXTENSION</spirit:name>
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||||
<spirit:displayName>File Extension</spirit:displayName>
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<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FILE_EXTENSION">bmp</spirit:value>
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||||
</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="boolean">
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||||
<spirit:name>FILE_AUTONUMBERING</spirit:name>
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<spirit:displayName>File Autonumbering</spirit:displayName>
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<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FILE_AUTONUMBERING">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_PIX_PER_LINE">192</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
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||||
<spirit:name>NUM_LINES</spirit:name>
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||||
<spirit:displayName>Num Lines</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINES">192</spirit:value>
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||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_FRAMES_PER_FILE</spirit:name>
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||||
<spirit:displayName>Num Frames Per File</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_FRAMES_PER_FILE">1</spirit:value>
|
||||
</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="boolean">
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||||
<spirit:name>RANDOM_TVALID</spirit:name>
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||||
<spirit:displayName>Random Tvalid</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RANDOM_TVALID">true</spirit:value>
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||||
</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="integer">
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||||
<spirit:name>PIXEL_FORMAT</spirit:name>
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||||
<spirit:displayName>Pixel Format</spirit:displayName>
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||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PIXEL_FORMAT">13</spirit:value>
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||||
</spirit:modelParameter>
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||||
<spirit:modelParameter spirit:dataType="integer">
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||||
<spirit:name>ALPHA_VALUE</spirit:name>
|
||||
<spirit:displayName>Alpha Value</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ALPHA_VALUE">255</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FRAMING_PIXELS</spirit:name>
|
||||
<spirit:displayName>Framing Pixels</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FRAMING_PIXELS">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FRAMING_LINES</spirit:name>
|
||||
<spirit:displayName>Framing Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FRAMING_LINES">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FRAMING_VAL_R_V</spirit:name>
|
||||
<spirit:displayName>Framing Val R V</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FRAMING_VAL_R_V">128</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FRAMING_VAL_G_Y</spirit:name>
|
||||
<spirit:displayName>Framing Val G Y</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FRAMING_VAL_G_Y">128</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>FRAMING_VAL_B_U</spirit:name>
|
||||
<spirit:displayName>Framing Val B U</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FRAMING_VAL_B_U">128</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_91f15632</spirit:name>
|
||||
<spirit:enumeration>bmp</spirit:enumeration>
|
||||
<spirit:enumeration>yuv</spirit:enumeration>
|
||||
<spirit:enumeration>bin</spirit:enumeration>
|
||||
<spirit:enumeration>raw</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/d44d/bmp_pkg.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/d44d/axis_master_simmodel.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_axis_master_simmodel_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_master_simmodel</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FRAMING_VAL_B_U</spirit:name>
|
||||
<spirit:displayName>Framing Val B U</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FRAMING_VAL_B_U" spirit:order="1100">128</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FRAMING_VAL_G_Y</spirit:name>
|
||||
<spirit:displayName>Framing Val G Y</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FRAMING_VAL_G_Y" spirit:order="1200">128</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FRAMING_VAL_R_V</spirit:name>
|
||||
<spirit:displayName>Framing Val R V</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FRAMING_VAL_R_V" spirit:order="1300">128</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FRAMING_LINES</spirit:name>
|
||||
<spirit:displayName>Framing Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FRAMING_LINES" spirit:order="1400">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FRAMING_PIXELS</spirit:name>
|
||||
<spirit:displayName>Framing Pixels</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FRAMING_PIXELS" spirit:order="1500">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ALPHA_VALUE</spirit:name>
|
||||
<spirit:displayName>Alpha Value</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ALPHA_VALUE" spirit:order="1600">255</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PIXEL_FORMAT</spirit:name>
|
||||
<spirit:displayName>Pixel Format</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIXEL_FORMAT" spirit:order="1700">13</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RANDOM_TVALID</spirit:name>
|
||||
<spirit:displayName>Random Tvalid</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RANDOM_TVALID" spirit:order="1800">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_FRAMES_PER_FILE</spirit:name>
|
||||
<spirit:displayName>Num Frames Per File</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_FRAMES_PER_FILE" spirit:order="1900">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINES" spirit:order="2000" spirit:configGroups="0 UnGrouped textEdit">192</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PIX_PER_LINE" spirit:order="2100" spirit:configGroups="0 UnGrouped textEdit">192</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FILE_AUTONUMBERING</spirit:name>
|
||||
<spirit:displayName>File Autonumbering</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.FILE_AUTONUMBERING" spirit:order="2200">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FILE_EXTENSION</spirit:name>
|
||||
<spirit:displayName>File Extension</spirit:displayName>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FILE_EXTENSION" spirit:choiceRef="choice_list_91f15632" spirit:order="2300" spirit:configGroups="0 UnGrouped radioGroup">bmp</spirit:value>
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</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FILE_NAME</spirit:name>
|
||||
<spirit:displayName>File Name</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FILE_NAME" spirit:order="2400" spirit:configGroups="0 UnGrouped textEdit">../../../../Moewe-192x192</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
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<spirit:name>TUSERWIDTH</spirit:name>
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||||
<spirit:displayName>Tuserwidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TUSERWIDTH" spirit:order="2500">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FIFO_REQUEST_TRESHOLD</spirit:name>
|
||||
<spirit:displayName>Fifo Request Treshold</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_REQUEST_TRESHOLD" spirit:order="2600">32</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FIFO_AWIDTH</spirit:name>
|
||||
<spirit:displayName>Fifo Awidth</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_AWIDTH" spirit:order="2700">11</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_FIFO_INTERFACE</spirit:name>
|
||||
<spirit:displayName>Has Fifo Interface</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_FIFO_INTERFACE" spirit:order="2800">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:displayName>Component Name</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_axis_master_simmodel_0_0</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_master_simmodel</xilinx:displayName>
|
||||
<xilinx:coreRevision>10</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:ip:axis_master_simmodel:1.0_ARCHIVE_LOCATION">D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new</xilinx:tag>
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||||
<xilinx:tag xilinx:name="Gehrke:ip:axis_master_simmodel:1.0_ARCHIVE_LOCATION">D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new</xilinx:tag>
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||||
<xilinx:tag xilinx:name="Gehrke:user:axis_master_simmodel:1.0_ARCHIVE_LOCATION">D:/Projekte/edvs/vivado/ip_projects/axis_master_simmodel/axis_master_simmodel.srcs/sources_1/new</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
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||||
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||||
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_NAME" xilinx:valueSource="user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_LINES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_PIX_PER_LINE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PIXEL_FORMAT" xilinx:valueSource="user"/>
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||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
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||||
<xilinx:packagingInfo>
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||||
<xilinx:xilinxVersion>2015.2</xilinx:xilinxVersion>
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</xilinx:packagingInfo>
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||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axis_master_simmodel:1.0
|
||||
-- IP Revision: 10
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_master_simmodel_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_1_axis_master_simmodel_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_master_simmodel_0_0_arch OF design_1_axis_master_simmodel_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_master_simmodel_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_master_simmodel IS
|
||||
GENERIC (
|
||||
DATA_WIDTH : INTEGER;
|
||||
HAS_FIFO_INTERFACE : BOOLEAN;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
FIFO_REQUEST_TRESHOLD : INTEGER;
|
||||
TUSERWIDTH : INTEGER;
|
||||
FILE_NAME : STRING;
|
||||
FILE_EXTENSION : STRING;
|
||||
FILE_AUTONUMBERING : BOOLEAN;
|
||||
NUM_PIX_PER_LINE : INTEGER;
|
||||
NUM_LINES : INTEGER;
|
||||
NUM_FRAMES_PER_FILE : INTEGER;
|
||||
RANDOM_TVALID : BOOLEAN;
|
||||
PIXEL_FORMAT : INTEGER;
|
||||
ALPHA_VALUE : INTEGER;
|
||||
FRAMING_PIXELS : INTEGER;
|
||||
FRAMING_LINES : INTEGER;
|
||||
FRAMING_VAL_R_V : INTEGER;
|
||||
FRAMING_VAL_G_Y : INTEGER;
|
||||
FRAMING_VAL_B_U : INTEGER
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXIS_NUM_FREE : IN STD_LOGIC_VECTOR(10 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_master_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_master_simmodel
|
||||
GENERIC MAP (
|
||||
DATA_WIDTH => 32,
|
||||
HAS_FIFO_INTERFACE => false,
|
||||
FIFO_AWIDTH => 11,
|
||||
FIFO_REQUEST_TRESHOLD => 32,
|
||||
TUSERWIDTH => 1,
|
||||
FILE_NAME => "../../../../Moewe-192x192",
|
||||
FILE_EXTENSION => "bmp",
|
||||
FILE_AUTONUMBERING => false,
|
||||
NUM_PIX_PER_LINE => 192,
|
||||
NUM_LINES => 192,
|
||||
NUM_FRAMES_PER_FILE => 1,
|
||||
RANDOM_TVALID => true,
|
||||
PIXEL_FORMAT => 13,
|
||||
ALPHA_VALUE => 255,
|
||||
FRAMING_PIXELS => 0,
|
||||
FRAMING_LINES => 0,
|
||||
FRAMING_VAL_R_V => 128,
|
||||
FRAMING_VAL_G_Y => 128,
|
||||
FRAMING_VAL_B_U => 128
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
FINISHED => FINISHED,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
M_AXIS_NUM_FREE => STD_LOGIC_VECTOR(TO_UNSIGNED(1, 11))
|
||||
);
|
||||
END design_1_axis_master_simmodel_0_0_arch;
|
||||
+642
@@ -0,0 +1,642 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>Gehrke</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_slave_simmodel_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS_signal_reset</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS_signal_clock</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">S_AXIS_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_HZ"/>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
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|
||||
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|
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
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<spirit:name>FILE_NAME</spirit:name>
|
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<spirit:displayName>File Name</spirit:displayName>
|
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|
||||
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|
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|
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<spirit:name>FILE_EXTENSION</spirit:name>
|
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<spirit:displayName>File Extension</spirit:displayName>
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
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|
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|
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|
||||
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|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
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|
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|
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|
||||
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|
||||
<spirit:displayName>Num Frames Per File</spirit:displayName>
|
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|
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|
||||
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|
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|
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<spirit:displayName>Num Files</spirit:displayName>
|
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
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|
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>FRAMING_LINES</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>FRAMING_PIXELS</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>NUM_FILES</spirit:name>
|
||||
<spirit:displayName>Num Files</spirit:displayName>
|
||||
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||||
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|
||||
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|
||||
<spirit:name>NUM_FRAMES_PER_FILE</spirit:name>
|
||||
<spirit:displayName>Num Frames Per File</spirit:displayName>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_LINES</spirit:name>
|
||||
<spirit:displayName>Num Lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINES" spirit:order="1600">192</spirit:value>
|
||||
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|
||||
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|
||||
<spirit:name>NUM_PIX_PER_LINE</spirit:name>
|
||||
<spirit:displayName>Num Pix Per Line</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_PIX_PER_LINE" spirit:order="1700">192</spirit:value>
|
||||
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|
||||
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|
||||
<spirit:name>PIXEL_FORMAT</spirit:name>
|
||||
<spirit:displayName>Pixel Format</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PIXEL_FORMAT" spirit:order="1800">13</spirit:value>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>FILE_EXTENSION</spirit:name>
|
||||
<spirit:displayName>File Extension</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FILE_EXTENSION" spirit:choiceRef="choice_list_91f15632" spirit:order="2000" spirit:configGroups="0 UnGrouped radioGroup">bmp</spirit:value>
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||||
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|
||||
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|
||||
<spirit:name>FILE_NAME</spirit:name>
|
||||
<spirit:displayName>File Name</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FILE_NAME" spirit:order="2100" spirit:configGroups="0 UnGrouped textEdit">../../../../tst_out</spirit:value>
|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSERWIDTH</spirit:name>
|
||||
<spirit:displayName>Tuserwidth</spirit:displayName>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:displayName>Component Name</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_axis_slave_simmodel_0_0</spirit:value>
|
||||
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||||
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||||
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|
||||
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|
||||
<xilinx:displayName>axis_slave_simmodel_v1_0</xilinx:displayName>
|
||||
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|
||||
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|
||||
<xilinx:tag xilinx:name="xilinx.com:ip:axis_slave_simmodel:1.0_ARCHIVE_LOCATION">D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="Gehrke:ip:axis_slave_simmodel:1.0_ARCHIVE_LOCATION">D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="Gehrke:user:axis_slave_simmodel:1.0_ARCHIVE_LOCATION">D:/Projekte/edvs/vivado/ip_projects/axis_slave_simmodel/axis_slave_simmodel.srcs/sources_1/new</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_SIGNAL_RESET.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_NAME" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_LINES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_PIX_PER_LINE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PIXEL_FORMAT" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="059f8320"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9aebe377"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="fa7123cf"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8e12d972"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="a6f2b82f"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axis_slave_simmodel:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_slave_simmodel_0_0 IS
|
||||
PORT (
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_1_axis_slave_simmodel_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_slave_simmodel_0_0_arch OF design_1_axis_slave_simmodel_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_slave_simmodel_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_slave_simmodel IS
|
||||
GENERIC (
|
||||
TUSERWIDTH : INTEGER;
|
||||
FILE_NAME : STRING;
|
||||
FILE_EXTENSION : STRING;
|
||||
FILE_AUTONUMBERING : BOOLEAN;
|
||||
PIXEL_FORMAT : INTEGER;
|
||||
NUM_PIX_PER_LINE : INTEGER;
|
||||
NUM_LINES : INTEGER;
|
||||
NUM_FRAMES_PER_FILE : INTEGER;
|
||||
NUM_FILES : INTEGER;
|
||||
FRAMING_PIXELS : INTEGER;
|
||||
FRAMING_LINES : INTEGER;
|
||||
RANDOM_TREADY : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_slave_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_slave_simmodel
|
||||
GENERIC MAP (
|
||||
TUSERWIDTH => 1,
|
||||
FILE_NAME => "../../../../tst_out",
|
||||
FILE_EXTENSION => "bmp",
|
||||
FILE_AUTONUMBERING => false,
|
||||
PIXEL_FORMAT => 13,
|
||||
NUM_PIX_PER_LINE => 192,
|
||||
NUM_LINES => 192,
|
||||
NUM_FRAMES_PER_FILE => 1,
|
||||
NUM_FILES => 1,
|
||||
FRAMING_PIXELS => 0,
|
||||
FRAMING_LINES => 0,
|
||||
RANDOM_TREADY => true
|
||||
)
|
||||
PORT MAP (
|
||||
FINISHED => FINISHED,
|
||||
S_AXIS_ACLK => S_AXIS_ACLK,
|
||||
S_AXIS_ARESETN => S_AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER
|
||||
);
|
||||
END design_1_axis_slave_simmodel_0_0_arch;
|
||||
+795
@@ -0,0 +1,795 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_upsizer_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_upsizer</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8a86da2c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_upsizer_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:8a86da2c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.WIDTH_IN')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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|
||||
</spirit:wire>
|
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
|
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<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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|
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.WIDTH_IN')) * spirit:decode(id('MODELPARAM_VALUE.SIZE_FACTOR'))) - 1)">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
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|
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</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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|
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|
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|
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
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|
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<spirit:direction>in</spirit:direction>
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</spirit:wireTypeDefs>
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|
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<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
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</spirit:driver>
|
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</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
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|
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<spirit:typeName>std_logic</spirit:typeName>
|
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|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>WIDTH_IN</spirit:name>
|
||||
<spirit:displayName>Width In</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.WIDTH_IN">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SIZE_FACTOR</spirit:name>
|
||||
<spirit:displayName>Size Factor</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SIZE_FACTOR">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>BIG_ENDIAN</spirit:name>
|
||||
<spirit:displayName>Big Endian</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIG_ENDIAN">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
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|
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<spirit:name>choice_list_552a89ba</spirit:name>
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<spirit:enumeration>16</spirit:enumeration>
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</spirit:choice>
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<spirit:choice>
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<spirit:name>choice_list_5f2cf65b</spirit:name>
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<spirit:enumeration>1</spirit:enumeration>
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<spirit:enumeration>8</spirit:enumeration>
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<spirit:enumeration>16</spirit:enumeration>
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<spirit:enumeration>32</spirit:enumeration>
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<spirit:enumeration>64</spirit:enumeration>
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<spirit:enumeration>128</spirit:enumeration>
|
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</spirit:choice>
|
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<spirit:choice>
|
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<spirit:name>choice_list_9d8b0d81</spirit:name>
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>../../ipshared/dfd1/sources_1/new/axis_upsizer.vhd</spirit:name>
|
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<spirit:fileType>vhdlSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>sim/design_1_axis_upsizer_0_0.vhd</spirit:name>
|
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
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<spirit:description>axis_upsizer_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIDTH_IN</spirit:name>
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<spirit:displayName>Width In</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.WIDTH_IN" spirit:choiceRef="choice_list_5f2cf65b">8</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
|
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<spirit:name>SIZE_FACTOR</spirit:name>
|
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<spirit:displayName>Size Factor</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SIZE_FACTOR" spirit:choiceRef="choice_list_552a89ba">4</spirit:value>
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>BIG_ENDIAN</spirit:name>
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<spirit:displayName>Big Endian</spirit:displayName>
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<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.BIG_ENDIAN">false</spirit:value>
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</spirit:parameter>
|
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<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_axis_upsizer_0_0</spirit:value>
|
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</spirit:parameter>
|
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:displayName>axis_upsizer_v1_0</xilinx:displayName>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:coreRevision>3</xilinx:coreRevision>
|
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<xilinx:tags>
|
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<xilinx:tag xilinx:name="xilinx.com:user:axis_upsizer:1.0_ARCHIVE_LOCATION">d:/Projekte/edvs/vivado/vivado/ip_projects/axis_upsizer/axis_upsizer.srcs</xilinx:tag>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SIZE_FACTOR" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3243ed51"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="b1ca67f8"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b7579622"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="0d5be49c"/>
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</spirit:vendorExtensions>
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||||
</spirit:component>
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_upsizer:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_upsizer_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
);
|
||||
END design_1_axis_upsizer_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_upsizer_0_0_arch OF design_1_axis_upsizer_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_upsizer_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_upsizer IS
|
||||
GENERIC (
|
||||
WIDTH_IN : INTEGER;
|
||||
SIZE_FACTOR : INTEGER;
|
||||
BIG_ENDIAN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_upsizer;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_upsizer
|
||||
GENERIC MAP (
|
||||
WIDTH_IN => 8,
|
||||
SIZE_FACTOR => 4,
|
||||
BIG_ENDIAN => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
AXIS_ARESETN => AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER
|
||||
);
|
||||
END design_1_axis_upsizer_0_0_arch;
|
||||
+1473
File diff suppressed because it is too large
Load Diff
+187
@@ -0,0 +1,187 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:axis_video_filter:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_axis_video_filter_0_0 (
|
||||
ACLK,
|
||||
ARESETN,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
S_AXIS_TUSER,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY,
|
||||
M_AXIS_TUSER,
|
||||
S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA,
|
||||
S_AXIL_WVALID,
|
||||
S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID,
|
||||
S_AXIL_BREADY,
|
||||
S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA,
|
||||
S_AXIL_RVALID,
|
||||
S_AXIL_RREADY,
|
||||
S_AXIL_RRESP
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:S_AXIL, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ACLK CLK" *)
|
||||
input wire ACLK;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ARESETN RST" *)
|
||||
input wire ARESETN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire S_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [23 : 0] S_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
|
||||
input wire S_AXIS_TLAST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire S_AXIS_TREADY;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *)
|
||||
input wire [2 : 0] S_AXIS_TUSER;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire M_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [7 : 0] M_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
|
||||
output wire M_AXIS_TLAST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire M_AXIS_TREADY;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *)
|
||||
output wire M_AXIS_TUSER;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR" *)
|
||||
input wire [14 : 0] S_AXIL_AWADDR;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID" *)
|
||||
input wire S_AXIL_AWVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY" *)
|
||||
output wire S_AXIL_AWREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WDATA" *)
|
||||
input wire [31 : 0] S_AXIL_WDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WVALID" *)
|
||||
input wire S_AXIL_WVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WREADY" *)
|
||||
output wire S_AXIL_WREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB" *)
|
||||
input wire [3 : 0] S_AXIL_WSTRB;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BVALID" *)
|
||||
output wire S_AXIL_BVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BREADY" *)
|
||||
input wire S_AXIL_BREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL BRESP" *)
|
||||
output wire [1 : 0] S_AXIL_BRESP;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR" *)
|
||||
input wire [14 : 0] S_AXIL_ARADDR;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID" *)
|
||||
input wire S_AXIL_ARVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY" *)
|
||||
output wire S_AXIL_ARREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RDATA" *)
|
||||
output wire [31 : 0] S_AXIL_RDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RVALID" *)
|
||||
output wire S_AXIL_RVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RREADY" *)
|
||||
input wire S_AXIL_RREADY;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 15, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_\
|
||||
BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXIL RRESP" *)
|
||||
output wire [1 : 0] S_AXIL_RRESP;
|
||||
|
||||
axis_video_filter #(
|
||||
.COEFF_WIDTH(8)
|
||||
) inst (
|
||||
.ACLK(ACLK),
|
||||
.ARESETN(ARESETN),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(S_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(S_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(S_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(M_AXIS_TUSER),
|
||||
.S_AXIL_AWADDR(S_AXIL_AWADDR),
|
||||
.S_AXIL_AWVALID(S_AXIL_AWVALID),
|
||||
.S_AXIL_AWREADY(S_AXIL_AWREADY),
|
||||
.S_AXIL_WDATA(S_AXIL_WDATA),
|
||||
.S_AXIL_WVALID(S_AXIL_WVALID),
|
||||
.S_AXIL_WREADY(S_AXIL_WREADY),
|
||||
.S_AXIL_WSTRB(S_AXIL_WSTRB),
|
||||
.S_AXIL_BVALID(S_AXIL_BVALID),
|
||||
.S_AXIL_BREADY(S_AXIL_BREADY),
|
||||
.S_AXIL_BRESP(S_AXIL_BRESP),
|
||||
.S_AXIL_ARADDR(S_AXIL_ARADDR),
|
||||
.S_AXIL_ARVALID(S_AXIL_ARVALID),
|
||||
.S_AXIL_ARREADY(S_AXIL_ARREADY),
|
||||
.S_AXIL_RDATA(S_AXIL_RDATA),
|
||||
.S_AXIL_RVALID(S_AXIL_RVALID),
|
||||
.S_AXIL_RREADY(S_AXIL_RREADY),
|
||||
.S_AXIL_RRESP(S_AXIL_RRESP)
|
||||
);
|
||||
endmodule
|
||||
+226
@@ -0,0 +1,226 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:deff16df</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Dec 09 23:02:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:deff16df</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_CLK_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_RESET_INPUT" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 10000,
|
||||
HAS_CLK_INPUT => false,
|
||||
HAS_RESET_INPUT => false,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0_arch;
|
||||
+285
@@ -0,0 +1,285 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axil_master_with_rom.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
-- AXIL-Master
|
||||
--
|
||||
-- Transactions des Masters werden durch ein ladbares ROM definiert
|
||||
-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet
|
||||
-- Das ROM besitzt eine Wortbreite von 40 bit
|
||||
-- Für einen Befehl werden 1 bis 2 Worte verwendet
|
||||
-- Nur 'wal' verwendet 2 40 - Bit - Worte
|
||||
--
|
||||
-- Die Codierung ist nachfolgend dargestellt :
|
||||
-- command wal : <39 : 8> Adresse <3 : 0> Befehl(wal = 1)
|
||||
-- <39 : 8> Daten <3 : 0> Befehl WStrobe
|
||||
-- command ral : <39 : 8> Adresse <3 : 0> Befehl(ral = 2)
|
||||
-- command wfi : Befehl(wfi = 6)
|
||||
-- command ral : <15 : 8> Wartezyklen <3 : 0> Befehl(slp = 7)
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axil_master_with_rom is
|
||||
generic
|
||||
(
|
||||
HAS_INTERRUPT_IN : boolean := true;
|
||||
HAS_FINISHED_OUT : boolean := false;
|
||||
REVISION_NO : integer := 1;
|
||||
STIM_FILENAME : string := "../../stimuli.mem"
|
||||
);
|
||||
port
|
||||
(
|
||||
interrupt_in : in std_logic:='0';
|
||||
finished_o : out std_logic;
|
||||
|
||||
M_AXIL_ACLK : in std_logic;
|
||||
M_AXIL_ARESETN : in std_logic;
|
||||
|
||||
M_AXIL_ARREADY : in std_logic;
|
||||
M_AXIL_ARVALID : out std_logic;
|
||||
M_AXIL_ARADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_ARPROT : out std_logic_vector(2 downto 0);
|
||||
M_AXIL_RREADY : out std_logic;
|
||||
M_AXIL_RVALID : in std_logic;
|
||||
M_AXIL_RDATA : in std_logic_vector(31 downto 0);
|
||||
M_AXIL_RRESP : in std_logic_vector(1 downto 0);
|
||||
M_AXIL_AWREADY : in std_logic;
|
||||
M_AXIL_AWVALID : out std_logic;
|
||||
M_AXIL_AWADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_AWPROT : out std_logic_vector(2 downto 0);
|
||||
M_AXIL_WREADY : in std_logic;
|
||||
M_AXIL_WVALID : out std_logic;
|
||||
M_AXIL_WDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_WSTRB : out std_logic_vector(3 downto 0);
|
||||
M_AXIL_BREADY : out std_logic;
|
||||
M_AXIL_BVALID : in std_logic;
|
||||
M_AXIL_BRESP : in std_logic_vector(1 downto 0)
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axil_master_with_rom is
|
||||
|
||||
|
||||
type TSTATE is (INIT,INIT_WAIT,
|
||||
GET_COMMAND,
|
||||
WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP,
|
||||
RD_ADDR,RD_DATA,
|
||||
WAIT_FOR_INT,
|
||||
SLEEP,SLEEP_WAIT,
|
||||
FINISHED
|
||||
);
|
||||
|
||||
signal state : TSTATE := INIT;
|
||||
|
||||
constant ADDR_WIDTH_CMD_ROM : integer := 12;
|
||||
|
||||
signal mdata : std_logic_vector(39 downto 0);
|
||||
signal maddr : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
cmdrom : entity work.axilm_rom
|
||||
generic map (
|
||||
FILENAME => STIM_FILENAME,
|
||||
DW => 40,
|
||||
AW => ADDR_WIDTH_CMD_ROM
|
||||
)
|
||||
port map (
|
||||
clk => M_AXIL_ACLK,
|
||||
a => maddr,
|
||||
q => mdata
|
||||
);
|
||||
|
||||
|
||||
process
|
||||
variable cnt8 : unsigned( 7 downto 0);
|
||||
variable cnt32 : unsigned(31 downto 0);
|
||||
variable addr_accepted : boolean;
|
||||
variable data_accepted : boolean;
|
||||
|
||||
begin
|
||||
wait until rising_edge(M_AXIL_ACLK);
|
||||
|
||||
if M_AXIL_ARESETN = '0' then
|
||||
state <= INIT;
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others=>'X');
|
||||
M_AXIL_ARPROT <= (others=>'0');
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_AWADDR <= (others=>'X');
|
||||
M_AXIL_AWPROT <= (others=>'0');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_BREADY <= '0';
|
||||
finished_o <= '0';
|
||||
else
|
||||
case state is
|
||||
|
||||
----
|
||||
-- Init
|
||||
----
|
||||
when INIT =>
|
||||
finished_o <= '0';
|
||||
cnt8 := x"10";
|
||||
maddr <= (others=>'0');
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others=>'X');
|
||||
M_AXIL_ARPROT <= (others=>'0');
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_AWADDR <= (others=>'X');
|
||||
M_AXIL_AWPROT <= (others=>'0');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_BREADY <= '0';
|
||||
state <= INIT_WAIT;
|
||||
|
||||
when INIT_WAIT =>
|
||||
cnt8 := cnt8 - 1;
|
||||
if cnt8 = 0 then
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when GET_COMMAND =>
|
||||
case (mdata(3 downto 0)) is
|
||||
when x"0" => state <= FINISHED;
|
||||
when x"1" => state <= WR_ADDR;
|
||||
when x"2" => state <= RD_ADDR;
|
||||
when x"6" => state <= WAIT_FOR_INT;
|
||||
when x"7" => state <= SLEEP;
|
||||
when others => maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
end case;
|
||||
|
||||
|
||||
----
|
||||
-- Write
|
||||
----
|
||||
when WR_ADDR =>
|
||||
M_AXIL_AWVALID <= '1';
|
||||
M_AXIL_AWADDR <= mdata(39 downto 8);
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others => 'X');
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
addr_accepted := false;
|
||||
data_accepted := false;
|
||||
state <= WR_ADDR_WAIT1;
|
||||
when WR_ADDR_WAIT1 =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
state <= WR_ADDR_WAIT2;
|
||||
when WR_ADDR_WAIT2 =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
state <= WR_DATA;
|
||||
when WR_DATA =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
M_AXIL_WSTRB <= mdata( 3 downto 0);
|
||||
M_AXIL_WDATA <= mdata(39 downto 8);
|
||||
M_AXIL_WVALID <= '1';
|
||||
state <= WR_DATA_WAIT;
|
||||
when WR_DATA_WAIT =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
if (M_AXIL_WREADY = '1') then
|
||||
M_AXIL_WVALID <= '0';
|
||||
data_accepted := true;
|
||||
end if;
|
||||
|
||||
if (addr_accepted and data_accepted) then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_BREADY <= '1';
|
||||
state <= WR_RESP;
|
||||
end if;
|
||||
when WR_RESP =>
|
||||
if M_AXIL_BVALID = '1' then
|
||||
M_AXIL_BREADY <= '0';
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
|
||||
----
|
||||
-- Read
|
||||
----
|
||||
when RD_ADDR =>
|
||||
M_AXIL_ARVALID <= '1';
|
||||
M_AXIL_ARADDR <= mdata(39 downto 8);
|
||||
M_AXIL_AWVALID <= 'X';
|
||||
M_AXIL_AWADDR <= (others => 'X');
|
||||
M_AXIL_RREADY <= '1';
|
||||
addr_accepted := false;
|
||||
state <= RD_DATA;
|
||||
when RD_DATA =>
|
||||
if (M_AXIL_ARREADY = '1') then
|
||||
M_AXIL_ARVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
if (M_AXIL_RVALID = '1') then
|
||||
M_AXIL_RREADY <= '0';
|
||||
data_accepted := true;
|
||||
end if;
|
||||
if (addr_accepted and data_accepted) then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_ARADDR <= (others => 'X');
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when WAIT_FOR_INT =>
|
||||
if (interrupt_in = '1') then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when SLEEP =>
|
||||
cnt32 := unsigned(mdata(39 downto 8));
|
||||
-- synthesis translate_off
|
||||
cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern
|
||||
-- synthesis translate_on
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
state <= SLEEP_WAIT;
|
||||
|
||||
when SLEEP_WAIT =>
|
||||
if (cnt32 /= 0) then
|
||||
cnt32 := cnt32 - 1;
|
||||
else
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when FINISHED =>
|
||||
finished_o <= '1';
|
||||
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end;
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axilm_rom.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
entity axilm_rom is
|
||||
|
||||
generic (
|
||||
FILENAME : string;
|
||||
DW : integer; -- Data Width
|
||||
AW : integer -- Address Width
|
||||
);
|
||||
port (
|
||||
clk : in std_logic; -- Clock
|
||||
a : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
q : out std_logic_vector(DW-1 downto 0) -- Data out port
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axilm_rom is
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
|
||||
|
||||
impure function InitMemFromFile(MemFileName : in string) return tmem is
|
||||
FILE MemFile : text is in MemFileName;
|
||||
variable MemFileLine : line;
|
||||
variable mem : tmem;
|
||||
begin
|
||||
for i in tmem'range loop
|
||||
readline(MemFile, MemFileLine);
|
||||
read(MemFileLine, mem(i));
|
||||
end loop;
|
||||
return mem;
|
||||
end function;
|
||||
|
||||
constant mem : tmem := InitMemFromFile(
|
||||
-- synthesis translate_off
|
||||
"../../" &
|
||||
-- synthesis translate_on
|
||||
FILENAME);
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
q <= mem(to_integer(unsigned(a)));
|
||||
end process;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_downsizer is
|
||||
generic
|
||||
(
|
||||
WIDTH_OUT : integer := 8;
|
||||
SIZE_FACTOR : integer := 2;
|
||||
BIG_ENDIAN : boolean := false
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
AXIS_ARESETN : in std_logic;
|
||||
|
||||
-- AXIS SLAVE
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic;
|
||||
|
||||
-- AXIS Master
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(WIDTH_OUT-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
M_AXIS_TUSER : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axis_downsizer is
|
||||
type T_STATE is (BYTE0,BYTE1);
|
||||
signal state : T_STATE := BYTE0;
|
||||
signal last : std_logic;
|
||||
signal data : std_logic_vector(WIDTH_OUT*SIZE_FACTOR-1 downto 0);
|
||||
signal ui : unsigned(5 downto 0);
|
||||
begin
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTE0 else '0';
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTE0 else '1';
|
||||
M_AXIS_TLAST <= last when ui = to_unsigned(SIZE_FACTOR-1,6) else '0';
|
||||
M_AXIS_TUSER <= S_AXIS_TUSER when state = BYTE0 else '0';
|
||||
|
||||
|
||||
process (S_AXIS_TDATA, ui)
|
||||
variable i: integer;
|
||||
begin
|
||||
i := to_integer(ui);
|
||||
if BIG_ENDIAN then
|
||||
if ui = 0 then
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT*SIZE_FACTOR-1 downto WIDTH_OUT*(SIZE_FACTOR-1));
|
||||
else
|
||||
M_AXIS_TDATA <= data(WIDTH_OUT*(SIZE_FACTOR-i)-1 downto WIDTH_OUT*(SIZE_FACTOR-i-1));
|
||||
end if;
|
||||
else
|
||||
if ui = 0 then
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA(WIDTH_OUT-1 downto 0);
|
||||
else
|
||||
M_AXIS_TDATA <= data(WIDTH_OUT*(i+1)-1 downto WIDTH_OUT*i);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
begin
|
||||
wait until rising_edge (AXIS_ACLK);
|
||||
if AXIS_ARESETN = '0' then
|
||||
state <= BYTE0;
|
||||
else
|
||||
case state is
|
||||
when BYTE0 =>
|
||||
if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then
|
||||
last <= S_AXIS_TLAST;
|
||||
data <= S_AXIS_TDATA;
|
||||
ui <= to_unsigned(1,6);
|
||||
state <= BYTE1;
|
||||
end if;
|
||||
when BYTE1 =>
|
||||
if M_AXIS_TREADY='1' then
|
||||
if ui >= SIZE_FACTOR-1 then
|
||||
state <= BYTE0;
|
||||
ui <= to_unsigned(0,6);
|
||||
else
|
||||
ui <= ui+1;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- clk_rst_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_rst_generator is
|
||||
generic
|
||||
(
|
||||
CLOCK_PERIOD : integer := 10000;
|
||||
HAS_CLK_INPUT : boolean := true;
|
||||
HAS_RESET_INPUT : boolean := true;
|
||||
HAS_STOP_INPUT : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
clk_in : in std_logic := '1';
|
||||
rst_in : in std_logic := '0';
|
||||
|
||||
clk : out std_logic;
|
||||
rst_n : out std_logic;
|
||||
|
||||
stop_simulation : in std_logic := '0'
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of clk_rst_generator is
|
||||
|
||||
signal clk_sim : std_logic := '1';
|
||||
signal clk_in_sig : std_logic := '1';
|
||||
signal clk_sig : std_logic := '1';
|
||||
signal rst_sig : std_logic := '0';
|
||||
signal rst_in_sync : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk <= clk_sig;
|
||||
rst_n <= not rst_sig;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
clk_sig <= clk_in_sig and clk_sim;
|
||||
-- Dies ist kein gated Clock!
|
||||
-- Fuer die Synthese ist clk_sim konstant '1'
|
||||
-- somit wird die UND-Verknuepfung 'wegoptimiert'
|
||||
-- und was übrig bleibt, ist ein 'Draht'
|
||||
|
||||
-- synthesis translate_off
|
||||
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
-- synthesis translate_on
|
||||
|
||||
process (clk_in) begin
|
||||
clk_in_sig <= clk_in;
|
||||
-- synthesis translate_off
|
||||
clk_in_sig <= '1';
|
||||
-- synthesis translate_on
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- RESET GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
process
|
||||
variable rescnt : unsigned (6 downto 0) := (others=>'1');
|
||||
begin
|
||||
wait until rising_edge(clk_sig);
|
||||
|
||||
rst_in_sync <= rst_in;
|
||||
if rst_in_sync = '1' then
|
||||
rescnt := (others=>'1');
|
||||
end if;
|
||||
|
||||
if rescnt = 0 then
|
||||
rst_sig <= '0';
|
||||
else
|
||||
rescnt := rescnt - 1;
|
||||
rst_sig <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- STOP SIMULATION INPUT (simulation only)
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- synthesis translate_off
|
||||
process (stop_simulation) begin
|
||||
if stop_simulation = '1' then
|
||||
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
|
||||
end if;
|
||||
end process;
|
||||
-- synthesis translate_on
|
||||
|
||||
end rtl;
|
||||
+150
@@ -0,0 +1,150 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_linemem_single_master.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2014/2015/2016
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all; -- required for log2()
|
||||
|
||||
entity axis_linemem_single_master is
|
||||
generic
|
||||
(
|
||||
MAX_LINELEN : integer := 2048;
|
||||
NUM_LINES : integer := 3;
|
||||
DATA_WIDTH : integer := 32;
|
||||
TUSER_WIDTH : integer := 1
|
||||
);
|
||||
port
|
||||
(
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
s_axis_tvalid : in std_logic := '0';
|
||||
s_axis_tdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
s_axis_tlast : in std_logic := '0';
|
||||
s_axis_tready : out std_logic;
|
||||
s_axis_tuser : in std_logic_vector(TUSER_WIDTH-1 downto 0);
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
|
||||
m_axis_tvalid : out std_logic;
|
||||
m_axis_tdata : out std_logic_vector(NUM_LINES*DATA_WIDTH-1 downto 0);
|
||||
m_axis_tlast : out std_logic;
|
||||
m_axis_tready : in std_logic := '1';
|
||||
m_axis_tuser : out std_logic_vector(NUM_LINES*TUSER_WIDTH-1 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_linemem_single_master is
|
||||
|
||||
constant TUSER_OFFS : integer := (NUM_LINES-1)*DATA_WIDTH;
|
||||
constant LOG2_MAX_LINELEN : integer := integer(ceil(log2(real(MAX_LINELEN))));
|
||||
|
||||
signal enable : std_logic;
|
||||
signal zero : std_logic_vector((NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH)-1 downto 0) := (others=>'0');
|
||||
signal rdaddr : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0);
|
||||
signal rdaddrReg : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0);
|
||||
signal rdaddrInc : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0);
|
||||
signal rddata : std_logic_vector((NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH)-1 downto 0);
|
||||
signal wraddr : std_logic_vector(LOG2_MAX_LINELEN-1 downto 0);
|
||||
signal wren : std_logic;
|
||||
signal wrdata : std_logic_vector((NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH)-1 downto 0);
|
||||
|
||||
signal tuser_reg : std_logic_vector(TUSER_WIDTH-1 downto 0);
|
||||
signal tdata_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
signal tlast_reg : std_logic;
|
||||
signal tvalid_reg : std_logic;
|
||||
signal m_valid_sig : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
enable <= s_axis_tvalid and (m_axis_tready or (not m_valid_sig));
|
||||
|
||||
s_axis_tready <= enable;
|
||||
|
||||
rdaddr <= (others=>'0') when s_axis_tlast = '1' and s_axis_tvalid = '1'
|
||||
else rdaddrInc when enable='1'
|
||||
else rdaddrReg;
|
||||
|
||||
-- asynchronous feedback of data read from and written to memory
|
||||
wrdata((NUM_LINES-1)*DATA_WIDTH-1 downto 0) <= rddata((NUM_LINES-2)*DATA_WIDTH-1 downto 0) & tdata_reg;
|
||||
wrdata((NUM_LINES-1)*TUSER_WIDTH-1+TUSER_OFFS downto TUSER_OFFS) <= rddata((NUM_LINES-2)*TUSER_WIDTH-1+TUSER_OFFS downto TUSER_OFFS) & tuser_reg;
|
||||
|
||||
|
||||
process begin
|
||||
wait until rising_edge(aclk);
|
||||
if aresetn = '0' then
|
||||
m_valid_sig <= '0';
|
||||
m_axis_tvalid <= '0';
|
||||
m_axis_tlast <= '0';
|
||||
m_axis_tdata <= (others=>'0');
|
||||
m_axis_tuser <= (others=>'0');
|
||||
tlast_reg <= '0';
|
||||
tuser_reg <= (others=>'0');
|
||||
tdata_reg <= (others=>'0');
|
||||
tvalid_reg <= '0';
|
||||
rdaddrReg <= (others=>'1'); -- entspricht -1
|
||||
rdaddrInc <= (others=>'0');
|
||||
wraddr <= (others=>'0');
|
||||
wren <= '0';
|
||||
else
|
||||
wren <= enable;
|
||||
wraddr <= rdaddr;
|
||||
rdaddrReg <= rdaddr;
|
||||
rdaddrInc <= std_logic_vector(unsigned(rdaddr)+1);
|
||||
|
||||
if m_axis_tready = '1' then -- falls Daten übernommen wurden, valid auf 0 setzen
|
||||
m_valid_sig <= '0';
|
||||
m_axis_tvalid <= '0';
|
||||
end if;
|
||||
|
||||
if enable = '1' then
|
||||
tvalid_reg <= s_axis_tvalid;
|
||||
tdata_reg <= s_axis_tdata;
|
||||
tuser_reg <= s_axis_tuser;
|
||||
tlast_reg <= s_axis_tlast;
|
||||
|
||||
m_valid_sig <= tvalid_reg;
|
||||
m_axis_tvalid <= tvalid_reg;
|
||||
m_axis_tlast <= tlast_reg;
|
||||
m_axis_tdata <= rddata((NUM_LINES-1)*DATA_WIDTH-1 downto 0) & tdata_reg;
|
||||
m_axis_tuser <= rddata((NUM_LINES-1)*TUSER_WIDTH-1+TUSER_OFFS downto TUSER_OFFS) & tuser_reg;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
dpmem : entity work.bmem_dp
|
||||
generic map(
|
||||
DW => (NUM_LINES-1)*(DATA_WIDTH+TUSER_WIDTH), -- Data Width
|
||||
AW => LOG2_MAX_LINELEN -- Address Width
|
||||
)
|
||||
port map(
|
||||
-- Port 1
|
||||
clk1 => aclk, -- Clock
|
||||
en1 => enable, -- Enable
|
||||
a1 => rdaddr, -- Address
|
||||
d1 => zero, -- Data in
|
||||
we1 => '0', -- Write enable
|
||||
q1 => rddata, -- Data out port
|
||||
-- Port 2
|
||||
clk2 => aclk, -- Clock
|
||||
en2 => '1', -- Enable
|
||||
a2 => wraddr, -- Address
|
||||
d2 => wrdata, -- Data in
|
||||
we2 => wren, -- Write enable
|
||||
q2 => open -- Data out port (not used)
|
||||
);
|
||||
|
||||
end rtl;
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- Dual-ported Synchronous Memory (Block Memory)
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2011
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity bmem_dp is
|
||||
|
||||
generic (
|
||||
DW : integer := 16; -- Data Width
|
||||
AW : integer := 10 -- Address Width
|
||||
);
|
||||
port (
|
||||
-- Port 1
|
||||
clk1 : in std_logic; -- Clock
|
||||
en1 : in std_logic; -- Enable
|
||||
a1 : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
d1 : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
we1 : in std_logic; -- Write enable
|
||||
q1 : out std_logic_vector(DW-1 downto 0); -- Data out port
|
||||
|
||||
-- Port 2
|
||||
clk2 : in std_logic; -- Clock
|
||||
en2 : in std_logic; -- Enable
|
||||
a2 : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
d2 : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
we2 : in std_logic; -- Write enable
|
||||
q2 : out std_logic_vector(DW-1 downto 0) -- Data out port
|
||||
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of bmem_dp is
|
||||
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
|
||||
shared variable mem : tmem := ((others=> (others=>'0')));
|
||||
|
||||
signal q1_sig : std_logic_vector(DW-1 downto 0) := (others=>'0');
|
||||
signal q2_sig : std_logic_vector(DW-1 downto 0) := (others=>'0');
|
||||
|
||||
begin
|
||||
q1 <= q1_sig;
|
||||
q2 <= q2_sig;
|
||||
|
||||
-- Port 1
|
||||
process (clk1)
|
||||
begin
|
||||
if (clk1'event and clk1 = '1') then
|
||||
if (en1 = '1') then
|
||||
if (we1 = '1') then
|
||||
mem(to_integer(unsigned(a1))) := d1;
|
||||
end if;
|
||||
q1_sig <= mem(to_integer(unsigned(a1)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Port 2
|
||||
process (clk2)
|
||||
begin
|
||||
if (clk2'event and clk2 = '1') then
|
||||
if (en2 = '1') then
|
||||
if (we2 = '1') then
|
||||
mem(to_integer(unsigned(a2))) := d2;
|
||||
end if;
|
||||
q2_sig <= mem(to_integer(unsigned(a2)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
+317
@@ -0,0 +1,317 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_slave_simmodel.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013
|
||||
----------------------------------------------------------
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.bmp_pkg.all;
|
||||
|
||||
|
||||
entity axis_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
TUSERWIDTH : integer := 1;
|
||||
FILE_NAME : string := string'("tst_out");
|
||||
FILE_EXTENSION : string := string'("bmp");
|
||||
FILE_AUTONUMBERING : boolean := false;
|
||||
PIXEL_FORMAT : integer := 1;
|
||||
NUM_PIX_PER_LINE : integer := 128;
|
||||
NUM_LINES : integer := 128;
|
||||
NUM_FRAMES_PER_FILE : integer := 1;
|
||||
NUM_FILES : integer := 1;
|
||||
FRAMING_PIXELS : integer := 0;
|
||||
FRAMING_LINES : integer := 0;
|
||||
RANDOM_TREADY : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
FINISHED : out std_logic;
|
||||
S_AXIS_ACLK : in std_logic;
|
||||
S_AXIS_ARESETN : in std_logic;
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic_vector(TUSERWIDTH-1 downto 0)
|
||||
);
|
||||
|
||||
end entity axis_slave_simmodel;
|
||||
|
||||
|
||||
architecture sim of axis_slave_simmodel is
|
||||
|
||||
signal rnd : unsigned (31 downto 0) := x"DEADBEEF";
|
||||
signal local_clk : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
local_clk <= S_AXIS_ACLK after 10 ps;
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd <= r;
|
||||
end process;
|
||||
|
||||
process
|
||||
|
||||
variable file_num : integer := 0;
|
||||
variable is_bmp_file: boolean;
|
||||
variable is_yuv_file: boolean;
|
||||
|
||||
variable r : integer;
|
||||
variable g : integer;
|
||||
variable b : integer;
|
||||
|
||||
variable y1 : integer;
|
||||
variable u1 : integer;
|
||||
variable v1 : integer;
|
||||
variable y2 : integer;
|
||||
variable u2 : integer;
|
||||
variable v2 : integer;
|
||||
|
||||
variable delay_cnt : integer;
|
||||
variable tready_cnt : integer := 31415;
|
||||
|
||||
file f : BMP_FILE_TYPE;
|
||||
|
||||
variable file_status : file_open_status;
|
||||
|
||||
variable x : integer;
|
||||
variable pixels_per_beat : integer;
|
||||
|
||||
|
||||
type rgbyuv is record
|
||||
r : integer;
|
||||
g : integer;
|
||||
b : integer;
|
||||
y : integer;
|
||||
u : integer;
|
||||
v : integer;
|
||||
end record;
|
||||
type tarr1 is array(0 to NUM_PIX_PER_LINE-1) of rgbyuv;
|
||||
type tarr2 is array(0 to NUM_LINES-1) of tarr1;
|
||||
variable pix : tarr2;
|
||||
|
||||
type t_pixel_data is array(0 to 3) of rgbyuv;
|
||||
variable p : t_pixel_data;
|
||||
|
||||
type t_raw_data is array(0 to 3) of integer;
|
||||
variable raw_data : t_raw_data;
|
||||
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
if (S_AXIS_ARESETN = '0') then
|
||||
S_AXIS_TREADY <= '0';
|
||||
FINISHED <= '0';
|
||||
tready_cnt := to_integer(rnd and x"0000001F");
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
|
||||
-- Check if output file is in BMP format
|
||||
is_bmp_file := false;
|
||||
is_yuv_file := false;
|
||||
if (FILE_EXTENSION = "BMP") or (FILE_EXTENSION = "bmp") then
|
||||
is_bmp_file := true;
|
||||
elsif (FILE_EXTENSION = "YUV") or (FILE_EXTENSION = "yuv") then
|
||||
is_yuv_file := true;
|
||||
end if;
|
||||
|
||||
case PIXEL_FORMAT is
|
||||
when 0 => pixels_per_beat := 2;
|
||||
when 1|5 => pixels_per_beat := 1;
|
||||
when 2|6 => pixels_per_beat := 1;
|
||||
when 12 => pixels_per_beat := 1;
|
||||
when 13 => pixels_per_beat := 4;
|
||||
when others => pixels_per_beat := 4;
|
||||
end case;
|
||||
|
||||
|
||||
for files in 0 to NUM_FILES-1 loop -- file loop
|
||||
|
||||
-- Create filename and try to open the file
|
||||
if FILE_AUTONUMBERING then
|
||||
file_open ( file_status, f, FILE_NAME & "_" & integer'image(file_num) & "." & FILE_EXTENSION, write_mode);
|
||||
else
|
||||
file_open ( file_status, f, FILE_NAME & "." & FILE_EXTENSION, write_mode);
|
||||
end if;
|
||||
|
||||
file_num := file_num + 1; -- increase filenum idx
|
||||
if is_bmp_file then
|
||||
write_bmp_header(NUM_PIX_PER_LINE,NUM_LINES,f);
|
||||
end if;
|
||||
|
||||
for fr in 0 to NUM_FRAMES_PER_FILE-1 loop -- frame loop
|
||||
|
||||
-- wait for start of frame
|
||||
while S_AXIS_TVALID /= '1' or S_AXIS_TUSER(0) /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
for y in 0 to NUM_LINES+2*FRAMING_LINES-1 loop
|
||||
x := 0;
|
||||
while x < NUM_PIX_PER_LINE+2*FRAMING_PIXELS loop
|
||||
|
||||
-- wait for valid data
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
-- "active" pixel area ?
|
||||
if (y >= FRAMING_LINES) and (y < FRAMING_LINES+NUM_LINES) and
|
||||
(x >= FRAMING_PIXELS) and (x < FRAMING_PIXELS+NUM_PIX_PER_LINE) then
|
||||
|
||||
if is_bmp_file or is_yuv_file then -- bmp format or yuv format ?
|
||||
case PIXEL_FORMAT is
|
||||
when 0 =>
|
||||
p(1).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24)));
|
||||
p(1).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
p(0).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
p(0).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8)));
|
||||
p(1).u := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
p(0).u := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b);
|
||||
yuv2rgb(p(1).y,p(1).u,p(1).v,p(1).r,p(1).g,p(1).b);
|
||||
when 1|5 =>
|
||||
p(0).v := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
p(0).u := to_integer(unsigned(S_AXIS_TDATA(15 downto 8)));
|
||||
p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b);
|
||||
when 2|6 =>
|
||||
p(0).r := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
p(0).b := to_integer(unsigned(S_AXIS_TDATA(15 downto 8)));
|
||||
p(0).g := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
rgb2yuv(p(0).r,p(0).g,p(0).b,p(0).y,p(0).u,p(0).v);
|
||||
when 12 =>
|
||||
p(0).v := 128;
|
||||
p(0).u := 128;
|
||||
p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b);
|
||||
when 13 =>
|
||||
p(3).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24)));
|
||||
p(3).v := 128;
|
||||
p(3).u := 128;
|
||||
p(2).y := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
p(2).v := 128;
|
||||
p(2).u := 128;
|
||||
p(1).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8)));
|
||||
p(1).v := 128;
|
||||
p(1).u := 128;
|
||||
p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
p(0).v := 128;
|
||||
p(0).u := 128;
|
||||
yuv2rgb(p(0).y,p(0).u,p(0).v,p(0).r,p(0).g,p(0).b);
|
||||
yuv2rgb(p(1).y,p(1).u,p(1).v,p(1).r,p(1).g,p(1).b);
|
||||
yuv2rgb(p(2).y,p(2).u,p(2).v,p(2).r,p(2).g,p(2).b);
|
||||
yuv2rgb(p(3).y,p(3).u,p(3).v,p(3).r,p(3).g,p(3).b);
|
||||
when others =>
|
||||
p(3).y := to_integer(unsigned(S_AXIS_TDATA(31 downto 24)));
|
||||
p(3).v := 128;
|
||||
p(3).u := 128;
|
||||
p(2).y := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
p(2).v := 128;
|
||||
p(2).u := 128;
|
||||
p(1).y := to_integer(unsigned(S_AXIS_TDATA(15 downto 8)));
|
||||
p(1).v := 128;
|
||||
p(1).u := 128;
|
||||
p(0).y := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
p(0).v := 128;
|
||||
p(0).u := 128;
|
||||
end case;
|
||||
else -- raw format
|
||||
raw_data(3) := to_integer(unsigned(S_AXIS_TDATA(31 downto 24)));
|
||||
raw_data(2) := to_integer(unsigned(S_AXIS_TDATA(23 downto 16)));
|
||||
raw_data(1) := to_integer(unsigned(S_AXIS_TDATA(15 downto 8)));
|
||||
raw_data(0) := to_integer(unsigned(S_AXIS_TDATA( 7 downto 0)));
|
||||
end if;
|
||||
|
||||
if is_bmp_file or is_yuv_file then -- bmp format or yuv format ?
|
||||
for xi in 0 to pixels_per_beat-1 loop
|
||||
pix(y-FRAMING_LINES)(x+xi-FRAMING_PIXELS) := p(xi);
|
||||
end loop;
|
||||
x := x+pixels_per_beat;
|
||||
else
|
||||
bmpput8(raw_data(0),f);
|
||||
bmpput8(raw_data(1),f);
|
||||
bmpput8(raw_data(2),f);
|
||||
bmpput8(raw_data(3),f);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
tready_cnt := tready_cnt - 1;
|
||||
if RANDOM_TREADY and tready_cnt <= 0 then
|
||||
-- random TREADY delay
|
||||
delay_cnt := to_integer(rnd and x"00000007");
|
||||
while delay_cnt > 0 loop
|
||||
S_AXIS_TREADY <= '0';
|
||||
delay_cnt := delay_cnt - 1;
|
||||
wait until rising_edge (local_clk);
|
||||
tready_cnt := to_integer(rnd and x"0000001F");
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge (local_clk);
|
||||
|
||||
end loop; -- hor loop (x)
|
||||
end loop; -- ver loop (y)
|
||||
if is_bmp_file then -- bmp format ?
|
||||
for y in NUM_LINES-1 downto 0 loop
|
||||
for x in 0 to NUM_PIX_PER_LINE-1 loop
|
||||
write_bmp_pixel(pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,f);
|
||||
end loop;
|
||||
end loop;
|
||||
end if;
|
||||
if is_bmp_file then -- yuv format ?
|
||||
for y in NUM_LINES-1 downto 0 loop
|
||||
for x in 0 to NUM_PIX_PER_LINE/2-1 loop
|
||||
bmpput8(pix(y)(2*x).u,f);
|
||||
bmpput8(pix(y)(2*x).y,f);
|
||||
bmpput8(pix(y)(2*x).v,f);
|
||||
bmpput8(pix(y)(2*x+1).y,f);
|
||||
end loop;
|
||||
end loop;
|
||||
end if;
|
||||
end loop; -- frame loop (fr)
|
||||
file_close(f);
|
||||
end loop; -- files loop (files)
|
||||
|
||||
|
||||
FINISHED <= '1';
|
||||
S_AXIS_TREADY <= '0';
|
||||
|
||||
-- wait until reset is activated
|
||||
while S_AXIS_ARESETN = '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
|
||||
end sim;
|
||||
@@ -0,0 +1,207 @@
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
package bmp_pkg is
|
||||
|
||||
type BMP_FILE_TYPE is file of character;
|
||||
|
||||
procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE );
|
||||
|
||||
function bmpget8 (file f : BMP_FILE_TYPE ) return integer;
|
||||
function bmpget16 (file f : BMP_FILE_TYPE ) return integer;
|
||||
function bmpget32 (file f : BMP_FILE_TYPE ) return integer;
|
||||
procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE );
|
||||
procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE );
|
||||
procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE );
|
||||
procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer );
|
||||
procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer );
|
||||
|
||||
end;
|
||||
|
||||
package body bmp_pkg is
|
||||
|
||||
procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
write(f, character'val(value));
|
||||
end bmpput8;
|
||||
|
||||
procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
bmpput8((value) mod 256,f);
|
||||
bmpput8((value/256) mod 256,f);
|
||||
end bmpput16;
|
||||
|
||||
procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
bmpput8((value) mod 256,f);
|
||||
bmpput8((value/256) mod 256,f);
|
||||
bmpput8((value/256/256) mod 256,f);
|
||||
bmpput8((value/256/256/256) mod 256,f);
|
||||
end bmpput32;
|
||||
|
||||
|
||||
procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
write(f,'B');
|
||||
write(f,'M');
|
||||
bmpput32(54+sizex*sizey*3,f); -- bfSize : size of file (unsave)
|
||||
bmpput32( 0, f); -- bfReserved : always 0
|
||||
bmpput32(54, f); -- bfOffBits : image data offset (=54)
|
||||
bmpput32(40, f); -- biSize : header size (=40)
|
||||
bmpput32(sizex,f); -- biWidth : num horizontal pixel
|
||||
bmpput32(sizey,f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap)
|
||||
bmpput16( 1, f); -- biPlanes : num bitplanes, always 1
|
||||
bmpput16(24, f); -- biBitCount : bpp
|
||||
bmpput32( 0, f); -- biCompression : compression (0: uncompressed)
|
||||
bmpput32(3*sizex*sizey,f); -- biSizeImage : if uncompressed: image size or 0
|
||||
bmpput32( 0, f); -- biXPelsPerMeter : hor resolution
|
||||
bmpput32( 0, f); -- biYPelsPerMeter : ver resolution
|
||||
bmpput32( 0, f); -- biClrUsed : for supported format always 0
|
||||
bmpput32( 0, f); -- biClrImportant : no color table => 0
|
||||
|
||||
end write_bmp_header;
|
||||
|
||||
procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
bmpput8(b,f);
|
||||
bmpput8(g,f);
|
||||
bmpput8(r,f);
|
||||
end write_bmp_pixel;
|
||||
|
||||
|
||||
function bmpget8 (file f : BMP_FILE_TYPE ) return integer is
|
||||
variable chr : character;
|
||||
begin
|
||||
read (f,chr);
|
||||
return character'pos(chr);
|
||||
end bmpget8;
|
||||
|
||||
function bmpget16 (file f : BMP_FILE_TYPE ) return integer is
|
||||
variable value : integer;
|
||||
begin
|
||||
value := bmpget8(f);
|
||||
value := value + bmpget8(f)*256;
|
||||
return value;
|
||||
end bmpget16;
|
||||
|
||||
function bmpget32 (file f : BMP_FILE_TYPE ) return integer is
|
||||
variable value : integer;
|
||||
begin
|
||||
value := bmpget8(f);
|
||||
value := value + bmpget8(f)*256;
|
||||
value := value + bmpget8(f)*256*256;
|
||||
value := value + bmpget8(f)*256*256*256;
|
||||
return value;
|
||||
end bmpget32;
|
||||
|
||||
procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ) is
|
||||
variable chr : character;
|
||||
variable val : integer;
|
||||
begin
|
||||
success := true;
|
||||
read (f,chr);
|
||||
if chr /= 'B' then success := false; end if;
|
||||
read (f,chr);
|
||||
if chr /= 'M' then success := false; end if;
|
||||
val := bmpget32(f); -- bfSize : size of file (unsave)
|
||||
val := bmpget32(f); -- bfReserved : always 0
|
||||
if val /= 0 then success := false; end if;
|
||||
val := bmpget32(f); -- bfOffBits : image data offset
|
||||
val := bmpget32(f); -- biSize : header size (=40)
|
||||
if val /= 40 then success := false; end if;
|
||||
sizex := bmpget32(f); -- biWidth : num horizontal pixel
|
||||
sizey := bmpget32(f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap)
|
||||
val := bmpget16(f); -- biPlanes : num bitplanes, always 1
|
||||
if val /= 1 then success := false; end if;
|
||||
val := bmpget16(f); -- biBitCount : bpp
|
||||
if val /= 24 then success := false; end if;
|
||||
val := bmpget32(f); -- biCompression : compression (0: uncompressed)
|
||||
if val /= 0 then success := false; end if;
|
||||
val := bmpget32(f); -- biSizeImage : if uncompressed: image size or 0
|
||||
val := bmpget32(f); -- biXPelsPerMeter : hor resolution
|
||||
val := bmpget32(f); -- biYPelsPerMeter : ver resolution
|
||||
val := bmpget32(f); -- biClrUsed : for supported format always 0
|
||||
if val /= 0 then success := false; end if;
|
||||
val := bmpget32(f); -- biClrImportant : no color table => 0
|
||||
if val /= 0 then success := false; end if;
|
||||
end read_bmp_header;
|
||||
|
||||
|
||||
procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
if endfile(f) then
|
||||
success := false;
|
||||
else
|
||||
b := bmpget8(f);
|
||||
g := bmpget8(f);
|
||||
r := bmpget8(f);
|
||||
success := true;
|
||||
end if;
|
||||
end read_bmp_pixel;
|
||||
|
||||
procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
if endfile(f) then
|
||||
success := false;
|
||||
else
|
||||
u := bmpget8(f);
|
||||
y1 := bmpget8(f);
|
||||
v := bmpget8(f);
|
||||
y2 := bmpget8(f);
|
||||
success := true;
|
||||
end if;
|
||||
end read_yuv422_pixels;
|
||||
|
||||
procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ) is
|
||||
begin
|
||||
y := INTEGER( (0.299 * REAL(r)) + (0.587 * REAL(g)) + (0.114 * REAL(b)) + 0.0 );
|
||||
u := INTEGER(-(0.169 * REAL(r)) - (0.331 * REAL(g)) + (0.500 * REAL(b)) + 128.0 );
|
||||
v := INTEGER( (0.500 * REAL(r)) - (0.419 * REAL(g)) - (0.081 * REAL(b)) + 128.0 );
|
||||
if (y>255) then
|
||||
y := 255;
|
||||
elsif (y<0) then
|
||||
y := 0;
|
||||
end if;
|
||||
if (u>255) then
|
||||
u := 255;
|
||||
elsif (u<0) then
|
||||
u := 0;
|
||||
end if;
|
||||
if (v>255) then
|
||||
v := 255;
|
||||
elsif (v<0) then
|
||||
v := 0;
|
||||
end if;
|
||||
end rgb2yuv;
|
||||
|
||||
procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ) is
|
||||
begin
|
||||
r := INTEGER( (1.000 * REAL(y)) + (0.000 * REAL(u-128)) + (1.400 * REAL(v-128)));
|
||||
g := INTEGER( (1.000 * REAL(y)) - (0.343 * REAL(u-128)) - (0.711 * REAL(v-128)));
|
||||
b := INTEGER( (1.000 * REAL(y)) + (1.765 * REAL(u-128)) - (0.000 * REAL(v-128)));
|
||||
if (r>255) then
|
||||
r := 255;
|
||||
elsif (r<0) then
|
||||
r := 0;
|
||||
end if;
|
||||
if (g>255) then
|
||||
g := 255;
|
||||
elsif (g<0) then
|
||||
g := 0;
|
||||
end if;
|
||||
if (b>255) then
|
||||
b := 255;
|
||||
elsif (b<0) then
|
||||
b := 0;
|
||||
end if;
|
||||
end yuv2rgb;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end package body;
|
||||
+375
@@ -0,0 +1,375 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_master_simmodel.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2015
|
||||
----------------------------------------------------------
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.bmp_pkg.all;
|
||||
|
||||
entity axis_master_simmodel is
|
||||
generic
|
||||
(
|
||||
DATA_WIDTH : integer := 32;
|
||||
HAS_FIFO_INTERFACE : boolean := false;
|
||||
FIFO_AWIDTH : integer := 11;
|
||||
FIFO_REQUEST_TRESHOLD : integer := 32;
|
||||
TUSERWIDTH : integer := 1;
|
||||
FILE_NAME : string := string'("tst");
|
||||
FILE_EXTENSION : string := string'("bmp");
|
||||
FILE_AUTONUMBERING : boolean := false;
|
||||
NUM_PIX_PER_LINE : integer := 32;
|
||||
NUM_LINES : integer := 32;
|
||||
NUM_FRAMES_PER_FILE : integer := 1;
|
||||
RANDOM_TVALID : boolean := true;
|
||||
PIXEL_FORMAT : integer := 1;
|
||||
ALPHA_VALUE : integer := 255;
|
||||
FRAMING_PIXELS : integer := 0;
|
||||
FRAMING_LINES : integer := 0;
|
||||
FRAMING_VAL_R_V : integer := 128;
|
||||
FRAMING_VAL_G_Y : integer := 128;
|
||||
FRAMING_VAL_B_U : integer := 128
|
||||
);
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic;
|
||||
FINISHED : out std_logic;
|
||||
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
M_AXIS_TUSER : out std_logic_vector(TUSERWIDTH-1 downto 0);
|
||||
M_AXIS_NUM_FREE : in std_logic_vector(FIFO_AWIDTH-1 downto 0) := (others=>'1') -- Number of free entries in target
|
||||
);
|
||||
|
||||
|
||||
end entity axis_master_simmodel;
|
||||
|
||||
|
||||
architecture sim of axis_master_simmodel is
|
||||
|
||||
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal local_clk : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
|
||||
local_clk <= ACLK;
|
||||
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd <= r;
|
||||
end process;
|
||||
|
||||
|
||||
process
|
||||
|
||||
variable file_num : integer := 0;
|
||||
variable is_bmp_file: boolean;
|
||||
variable is_yuv_file: boolean;
|
||||
|
||||
variable r : integer;
|
||||
variable g : integer;
|
||||
variable b : integer;
|
||||
|
||||
variable y1 : integer;
|
||||
variable u1 : integer;
|
||||
variable v1 : integer;
|
||||
variable y2 : integer;
|
||||
variable u2 : integer;
|
||||
variable v2 : integer;
|
||||
|
||||
variable sizex : integer;
|
||||
variable sizey : integer;
|
||||
|
||||
variable delay_cnt : integer;
|
||||
variable tvalid_cnt : integer := 31415;
|
||||
|
||||
variable ok : boolean;
|
||||
|
||||
file f : BMP_FILE_TYPE;
|
||||
|
||||
variable file_status : file_open_status;
|
||||
|
||||
|
||||
variable x : integer;
|
||||
variable pixels_per_beat : integer;
|
||||
|
||||
|
||||
type rgbyuv is record
|
||||
r : integer;
|
||||
g : integer;
|
||||
b : integer;
|
||||
y : integer;
|
||||
u : integer;
|
||||
v : integer;
|
||||
end record;
|
||||
type tarr1 is array(0 to NUM_PIX_PER_LINE-1) of rgbyuv;
|
||||
type tarr2 is array(0 to NUM_LINES-1) of tarr1;
|
||||
variable pix : tarr2;
|
||||
|
||||
type t_pixel_data is array(0 to 3) of rgbyuv;
|
||||
variable p : t_pixel_data;
|
||||
|
||||
type t_raw_data is array(0 to 3) of integer;
|
||||
variable raw_data : t_raw_data;
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
if (ARESETN = '0') then
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TDATA <= (others=>'0');
|
||||
M_AXIS_TLAST <= '0';
|
||||
M_AXIS_TUSER <= (others=>'0');
|
||||
FINISHED <= '0';
|
||||
file_num := 0;
|
||||
tvalid_cnt := to_integer(rnd and x"0000001F");
|
||||
else
|
||||
M_AXIS_TLAST <= '0';
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TUSER <= (others=>'0');
|
||||
FINISHED <= '0';
|
||||
|
||||
-- Start-Up delay
|
||||
for i in 0 to 100 loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
-- Send dummy data in front of the frame to chen
|
||||
M_AXIS_TVALID <= '1';
|
||||
M_AXIS_TDATA <= (others=>'0');
|
||||
M_AXIS_TLAST <= '0';
|
||||
M_AXIS_TUSER <= (others=>'0');
|
||||
|
||||
for i in 0 to 5000 loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
|
||||
-- Check if input file is in BMP format
|
||||
is_bmp_file := false;
|
||||
is_yuv_file := false;
|
||||
if (FILE_EXTENSION = "BMP") or (FILE_EXTENSION = "bmp") then
|
||||
is_bmp_file := true;
|
||||
elsif (FILE_EXTENSION = "YUV") or (FILE_EXTENSION = "yuv") then
|
||||
is_yuv_file := true;
|
||||
end if;
|
||||
|
||||
file_status := open_ok;
|
||||
|
||||
while file_status = open_ok loop
|
||||
-- Create filename and try to open the file
|
||||
if FILE_AUTONUMBERING then
|
||||
file_open ( file_status, f, FILE_NAME & "_" & integer'image(file_num) & "." & FILE_EXTENSION, read_mode);
|
||||
else
|
||||
file_open ( file_status, f, FILE_NAME & "." & FILE_EXTENSION, read_mode);
|
||||
end if;
|
||||
|
||||
-- File open succeeded ?
|
||||
if file_status = open_ok then
|
||||
file_num := file_num + 1; -- increase filenum idx
|
||||
if is_bmp_file then
|
||||
read_bmp_header(ok,sizex,sizey,f);
|
||||
if sizey < 0 then
|
||||
sizey := -sizey;
|
||||
end if;
|
||||
else
|
||||
sizex := NUM_PIX_PER_LINE;
|
||||
sizey := NUM_LINES;
|
||||
ok := true;
|
||||
end if;
|
||||
|
||||
if ok then
|
||||
for fr in 0 to NUM_FRAMES_PER_FILE-1 loop -- frame loop
|
||||
M_AXIS_TUSER(0) <= '1'; -- start of frame
|
||||
|
||||
if is_bmp_file then -- bmp format ?
|
||||
for y in NUM_LINES-1 downto 0 loop
|
||||
for x in 0 to NUM_PIX_PER_LINE-1 loop
|
||||
read_bmp_pixel(ok,pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,f);
|
||||
rgb2yuv(pix(y)(x).r,pix(y)(x).g,pix(y)(x).b,pix(y)(x).y,pix(y)(x).u,pix(y)(x).v);
|
||||
end loop;
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
if is_yuv_file then -- yuv format (YUV422) ?
|
||||
for y in NUM_LINES-1 downto 0 loop
|
||||
for x in 0 to NUM_PIX_PER_LINE/2-1 loop
|
||||
read_yuv422_pixels(ok,pix(y)(x).y,pix(y)(x+1).y,pix(y)(x).u,pix(y)(x).v,f);
|
||||
pix(y)(x+1).u := pix(y)(x).u;
|
||||
pix(y)(x+1).v := pix(y)(x).v;
|
||||
yuv2rgb(pix(y)(x).y,pix(y)(x).u,pix(y)(x).v,pix(y)(x).r,pix(y)(x).g,pix(y)(x).b);
|
||||
yuv2rgb(pix(y)(x+1).y,pix(y)(x+1).u,pix(y)(x+1).v,pix(y)(x+1).r,pix(y)(x+1).g,pix(y)(x+1).b);
|
||||
end loop;
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
if DATA_WIDTH = 32 then
|
||||
case PIXEL_FORMAT is
|
||||
when 0 => pixels_per_beat := 2;
|
||||
when 1|5 => pixels_per_beat := 1;
|
||||
when 2|6 => pixels_per_beat := 1;
|
||||
when 12 => pixels_per_beat := 1;
|
||||
when 13 => pixels_per_beat := 4;
|
||||
when others => pixels_per_beat := 4;
|
||||
end case;
|
||||
else
|
||||
pixels_per_beat := 1;
|
||||
end if;
|
||||
|
||||
for y in 0 to (sizey+2*FRAMING_LINES)-1 loop -- line loop
|
||||
x := 0;
|
||||
while x<(sizex+2*FRAMING_PIXELS) loop
|
||||
if (y >= FRAMING_LINES) and (y < FRAMING_LINES+sizey) and
|
||||
(x >= FRAMING_PIXELS) and (x < FRAMING_PIXELS+sizex) then
|
||||
-- "active" pixel area
|
||||
if is_bmp_file or is_yuv_file then -- bmp_format or yuv format ?
|
||||
p(0) := pix(y-FRAMING_LINES)(x-FRAMING_PIXELS);
|
||||
if pixels_per_beat > 1 then
|
||||
p(1) := pix(y-FRAMING_LINES)(x+1-FRAMING_PIXELS);
|
||||
end if;
|
||||
if pixels_per_beat > 2 then
|
||||
p(2) := pix(y-FRAMING_LINES)(x+2-FRAMING_PIXELS);
|
||||
end if;
|
||||
if pixels_per_beat > 3 then
|
||||
p(3) := pix(y-FRAMING_LINES)(x+3-FRAMING_PIXELS);
|
||||
end if;
|
||||
else
|
||||
raw_data(0) := bmpget8(f);
|
||||
if DATA_WIDTH = 32 then
|
||||
raw_data(1) := bmpget8(f);
|
||||
raw_data(2) := bmpget8(f);
|
||||
raw_data(3) := bmpget8(f);
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
-- "framing" area
|
||||
p(0).r := FRAMING_VAL_R_V;
|
||||
p(0).g := FRAMING_VAL_G_Y;
|
||||
p(0).b := FRAMING_VAL_B_U;
|
||||
p(0).v := FRAMING_VAL_R_V;
|
||||
p(0).y := FRAMING_VAL_G_Y;
|
||||
p(0).u := FRAMING_VAL_B_U;
|
||||
p(1) := p(0);
|
||||
p(2) := p(0);
|
||||
p(3) := p(0);
|
||||
end if;
|
||||
|
||||
-- wait until receiving FIFO has sufficient space
|
||||
-- if FIFO_REQUEST_TRESHOLD equals 0, this function is disabled
|
||||
if HAS_FIFO_INTERFACE then
|
||||
while FIFO_REQUEST_TRESHOLD /= 0 and to_integer(unsigned(M_AXIS_NUM_FREE)) < FIFO_REQUEST_TRESHOLD loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
-- output data, valid and last
|
||||
|
||||
if is_bmp_file or is_yuv_file then -- bmp format or yuv format ?
|
||||
if DATA_WIDTH = 32 then
|
||||
case PIXEL_FORMAT is
|
||||
when 0 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(1).y,8)&to_unsigned((p(1).v+p(0).v)/2,8)&to_unsigned(p(0).y,8)&to_unsigned((p(1).u+p(0).u)/2,8));
|
||||
when 1|5 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(p(0).v,8)&to_unsigned(p(0).u,8)&to_unsigned(p(0).y,8));
|
||||
when 2|6 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(p(0).r,8)&to_unsigned(p(0).b,8)&to_unsigned(p(0).g,8));
|
||||
when 12 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(ALPHA_VALUE,8)&to_unsigned(128,8)&to_unsigned(128,8)&to_unsigned(p(0).y,8));
|
||||
when 13 => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(3).y,8)&to_unsigned(p(2).y,8)&to_unsigned(p(1).y,8)&to_unsigned(p(0).y,8));
|
||||
when others => M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(3).y,8)&to_unsigned(p(2).y,8)&to_unsigned(p(1).y,8)&to_unsigned(p(0).y,8));
|
||||
end case;
|
||||
else
|
||||
M_AXIS_TDATA <= std_logic_vector(to_unsigned(p(0).y,8));
|
||||
end if;
|
||||
else -- raw format
|
||||
if DATA_WIDTH = 32 then
|
||||
M_AXIS_TDATA <= std_logic_vector(to_unsigned(raw_data(3),8)&to_unsigned(raw_data(2),8)&to_unsigned(raw_data(1),8)&to_unsigned(raw_data(0),8));
|
||||
else
|
||||
M_AXIS_TDATA <= std_logic_vector(to_unsigned(raw_data(0),8));
|
||||
end if;
|
||||
end if;
|
||||
|
||||
M_AXIS_TVALID <= '1';
|
||||
if x = (sizex+2*FRAMING_PIXELS)-pixels_per_beat then
|
||||
M_AXIS_TLAST <= '1';
|
||||
else
|
||||
M_AXIS_TLAST <= '0';
|
||||
end if;
|
||||
|
||||
-- wait until data has been acknowledged
|
||||
wait until rising_edge (local_clk);
|
||||
while M_AXIS_TREADY = '0' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
M_AXIS_TUSER(0) <= '0';
|
||||
|
||||
tvalid_cnt := tvalid_cnt - 1;
|
||||
if RANDOM_TVALID and tvalid_cnt <= 0 then
|
||||
-- random TVALID delay
|
||||
delay_cnt := to_integer(rnd and x"00000007");
|
||||
while delay_cnt > 0 loop
|
||||
M_AXIS_TVALID <= '0';
|
||||
delay_cnt := delay_cnt - 1;
|
||||
wait until rising_edge (local_clk);
|
||||
tvalid_cnt := to_integer(rnd and x"0000001F");
|
||||
end loop;
|
||||
M_AXIS_TVALID <= '1';
|
||||
end if;
|
||||
|
||||
x := x + pixels_per_beat;
|
||||
|
||||
end loop; -- pixel loop
|
||||
end loop; -- line loop
|
||||
end loop; -- frame loop
|
||||
file_close(f);
|
||||
end if; -- if ok
|
||||
end if; -- if open_status ok
|
||||
end loop;
|
||||
|
||||
FINISHED <= '1';
|
||||
M_AXIS_TLAST <= '0';
|
||||
M_AXIS_TVALID <= '1';
|
||||
M_AXIS_TUSER <= (others=>'0');
|
||||
if DATA_WIDTH = 32 then
|
||||
M_AXIS_TDATA <= x"80808080";
|
||||
else
|
||||
M_AXIS_TDATA <= x"80";
|
||||
end if;
|
||||
|
||||
-- wait until reset is activated
|
||||
while ARESETN = '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
|
||||
end sim;
|
||||
@@ -0,0 +1,208 @@
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
package bmp_pkg is
|
||||
|
||||
type BMP_FILE_TYPE is file of character;
|
||||
|
||||
procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE );
|
||||
procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE );
|
||||
|
||||
function bmpget8 (file f : BMP_FILE_TYPE ) return integer;
|
||||
function bmpget16 (file f : BMP_FILE_TYPE ) return integer;
|
||||
function bmpget32 (file f : BMP_FILE_TYPE ) return integer;
|
||||
procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE );
|
||||
procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE );
|
||||
procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE );
|
||||
procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer );
|
||||
procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer );
|
||||
|
||||
end;
|
||||
|
||||
package body bmp_pkg is
|
||||
|
||||
procedure bmpput8 (value : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
write(f, character'val(value));
|
||||
end bmpput8;
|
||||
|
||||
procedure bmpput16 (value : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
bmpput8((value) mod 256,f);
|
||||
bmpput8((value/256) mod 256,f);
|
||||
end bmpput16;
|
||||
|
||||
procedure bmpput32 (value : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
bmpput8((value) mod 256,f);
|
||||
bmpput8((value/256) mod 256,f);
|
||||
bmpput8((value/256/256) mod 256,f);
|
||||
bmpput8((value/256/256/256) mod 256,f);
|
||||
end bmpput32;
|
||||
|
||||
|
||||
procedure write_bmp_header (sizex : in integer; sizey : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
write(f,'B');
|
||||
write(f,'M');
|
||||
bmpput32(54+sizex*sizey*3,f); -- bfSize : size of file (unsave)
|
||||
bmpput32( 0, f); -- bfReserved : always 0
|
||||
bmpput32(54, f); -- bfOffBits : image data offset (=54)
|
||||
bmpput32(40, f); -- biSize : header size (=40)
|
||||
bmpput32(sizex,f); -- biWidth : num horizontal pixel
|
||||
bmpput32(sizey,f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap)
|
||||
bmpput16( 1, f); -- biPlanes : num bitplanes, always 1
|
||||
bmpput16(24, f); -- biBitCount : bpp
|
||||
bmpput32( 0, f); -- biCompression : compression (0: uncompressed)
|
||||
bmpput32(3*sizex*sizey,f); -- biSizeImage : if uncompressed: image size or 0
|
||||
bmpput32( 0, f); -- biXPelsPerMeter : hor resolution
|
||||
bmpput32( 0, f); -- biYPelsPerMeter : ver resolution
|
||||
bmpput32( 0, f); -- biClrUsed : for supported format always 0
|
||||
bmpput32( 0, f); -- biClrImportant : no color table => 0
|
||||
|
||||
end write_bmp_header;
|
||||
|
||||
procedure write_bmp_pixel (r : in integer; g : in integer; b : in integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
bmpput8(b,f);
|
||||
bmpput8(g,f);
|
||||
bmpput8(r,f);
|
||||
end write_bmp_pixel;
|
||||
|
||||
|
||||
function bmpget8 (file f : BMP_FILE_TYPE ) return integer is
|
||||
variable chr : character;
|
||||
begin
|
||||
read (f,chr);
|
||||
return character'pos(chr);
|
||||
end bmpget8;
|
||||
|
||||
function bmpget16 (file f : BMP_FILE_TYPE ) return integer is
|
||||
variable value : integer;
|
||||
begin
|
||||
value := bmpget8(f);
|
||||
value := value + bmpget8(f)*256;
|
||||
return value;
|
||||
end bmpget16;
|
||||
|
||||
function bmpget32 (file f : BMP_FILE_TYPE ) return integer is
|
||||
variable value : integer;
|
||||
begin
|
||||
value := bmpget8(f);
|
||||
value := value + bmpget8(f)*256;
|
||||
value := value + bmpget8(f)*256*256;
|
||||
value := value + bmpget8(f)*256*256*256;
|
||||
return value;
|
||||
end bmpget32;
|
||||
|
||||
procedure read_bmp_header (success : inout boolean; sizex : inout integer; sizey : inout integer; file f : BMP_FILE_TYPE ) is
|
||||
variable chr : character;
|
||||
variable val : integer;
|
||||
begin
|
||||
success := true;
|
||||
read (f,chr);
|
||||
if chr /= 'B' then success := false; end if;
|
||||
read (f,chr);
|
||||
if chr /= 'M' then success := false; end if;
|
||||
val := bmpget32(f); -- bfSize : size of file (unsave)
|
||||
val := bmpget32(f); -- bfReserved : always 0
|
||||
if val /= 0 then success := false; end if;
|
||||
val := bmpget32(f); -- bfOffBits : image data offset
|
||||
val := bmpget32(f); -- biSize : header size (=40)
|
||||
if val /= 40 then success := false; end if;
|
||||
sizex := bmpget32(f); -- biWidth : num horizontal pixel
|
||||
sizey := bmpget32(f); -- biHeight : num vertical pixel (>0: bottom-up bitmap, <0: top-down bitmap)
|
||||
val := bmpget16(f); -- biPlanes : num bitplanes, always 1
|
||||
if val /= 1 then success := false; end if;
|
||||
val := bmpget16(f); -- biBitCount : bpp
|
||||
if val /= 24 then success := false; end if;
|
||||
val := bmpget32(f); -- biCompression : compression (0: uncompressed)
|
||||
if val /= 0 then success := false; end if;
|
||||
val := bmpget32(f); -- biSizeImage : if uncompressed: image size or 0
|
||||
val := bmpget32(f); -- biXPelsPerMeter : hor resolution
|
||||
val := bmpget32(f); -- biYPelsPerMeter : ver resolution
|
||||
val := bmpget32(f); -- biClrUsed : for supported format always 0
|
||||
if val /= 0 then success := false; end if;
|
||||
val := bmpget32(f); -- biClrImportant : no color table => 0
|
||||
if val /= 0 then success := false; end if;
|
||||
end read_bmp_header;
|
||||
|
||||
|
||||
procedure read_bmp_pixel (success : inout boolean; r : inout integer; g : inout integer; b : inout integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
if endfile(f) then
|
||||
success := false;
|
||||
else
|
||||
b := bmpget8(f);
|
||||
g := bmpget8(f);
|
||||
r := bmpget8(f);
|
||||
success := true;
|
||||
end if;
|
||||
end read_bmp_pixel;
|
||||
|
||||
procedure read_yuv422_pixels (success : inout boolean; y1 : inout integer; y2 : inout integer; u : inout integer; v : inout integer; file f : BMP_FILE_TYPE ) is
|
||||
begin
|
||||
if endfile(f) then
|
||||
success := false;
|
||||
else
|
||||
u := bmpget8(f);
|
||||
y1 := bmpget8(f);
|
||||
v := bmpget8(f);
|
||||
y2 := bmpget8(f);
|
||||
success := true;
|
||||
end if;
|
||||
end read_yuv422_pixels;
|
||||
|
||||
procedure rgb2yuv (r : in integer; g : in integer; b : in integer; y : inout integer; u : inout integer; v : inout integer ) is
|
||||
begin
|
||||
y := INTEGER( (0.299 * REAL(r)) + (0.587 * REAL(g)) + (0.114 * REAL(b)) + 0.0 );
|
||||
u := INTEGER(-(0.169 * REAL(r)) - (0.331 * REAL(g)) + (0.500 * REAL(b)) + 128.0 );
|
||||
v := INTEGER( (0.500 * REAL(r)) - (0.419 * REAL(g)) - (0.081 * REAL(b)) + 128.0 );
|
||||
if (y>255) then
|
||||
y := 255;
|
||||
elsif (y<0) then
|
||||
y := 0;
|
||||
end if;
|
||||
if (u>255) then
|
||||
u := 255;
|
||||
elsif (u<0) then
|
||||
u := 0;
|
||||
end if;
|
||||
if (v>255) then
|
||||
v := 255;
|
||||
elsif (v<0) then
|
||||
v := 0;
|
||||
end if;
|
||||
end rgb2yuv;
|
||||
|
||||
procedure yuv2rgb (y : in integer; u : in integer; v : in integer; r : inout integer; g : inout integer; b : inout integer ) is
|
||||
begin
|
||||
r := INTEGER( (1.000 * REAL(y)) + (0.000 * REAL(u-128)) + (1.400 * REAL(v-128)));
|
||||
g := INTEGER( (1.000 * REAL(y)) - (0.343 * REAL(u-128)) - (0.711 * REAL(v-128)));
|
||||
b := INTEGER( (1.000 * REAL(y)) + (1.765 * REAL(u-128)) - (0.000 * REAL(v-128)));
|
||||
if (r>255) then
|
||||
r := 255;
|
||||
elsif (r<0) then
|
||||
r := 0;
|
||||
end if;
|
||||
if (g>255) then
|
||||
g := 255;
|
||||
elsif (g<0) then
|
||||
g := 0;
|
||||
end if;
|
||||
if (b>255) then
|
||||
b := 255;
|
||||
elsif (b<0) then
|
||||
b := 0;
|
||||
end if;
|
||||
end yuv2rgb;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end package body;
|
||||
|
||||
+103
@@ -0,0 +1,103 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axis_upsizer is
|
||||
generic
|
||||
(
|
||||
WIDTH_IN : integer := 8;
|
||||
SIZE_FACTOR : integer := 2;
|
||||
BIG_ENDIAN : boolean := false
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
AXIS_ARESETN : in std_logic;
|
||||
|
||||
-- AXIS SLAVE
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(WIDTH_IN-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic;
|
||||
|
||||
-- AXIS Master
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
M_AXIS_TUSER : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axis_upsizer is
|
||||
type T_STATE is (BYTE0,BYTE1,BYTEF);
|
||||
signal state : T_STATE := BYTE0;
|
||||
signal user : std_logic;
|
||||
signal data : std_logic_vector(WIDTH_IN*SIZE_FACTOR-1 downto 0);
|
||||
begin
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY when state = BYTEF else '1';
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID when state = BYTEF else '0';
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST when state = BYTEF else '0';
|
||||
M_AXIS_TUSER <= user when state = BYTEF else '0';
|
||||
|
||||
process (S_AXIS_TDATA, data)
|
||||
begin
|
||||
if BIG_ENDIAN then
|
||||
for i in 0 to SIZE_FACTOR-1 loop
|
||||
M_AXIS_TDATA(WIDTH_IN*SIZE_FACTOR-1-WIDTH_IN*i downto (WIDTH_IN-1)*SIZE_FACTOR-WIDTH_IN*i) <= data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i);
|
||||
end loop;
|
||||
M_AXIS_TDATA(WIDTH_IN-1 downto 0) <= S_AXIS_TDATA;
|
||||
|
||||
else
|
||||
M_AXIS_TDATA <= S_AXIS_TDATA & data(WIDTH_IN*(SIZE_FACTOR-1)-1 downto 0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process
|
||||
variable i : integer;
|
||||
variable ui : unsigned(5 downto 0);
|
||||
begin
|
||||
wait until rising_edge (AXIS_ACLK);
|
||||
if AXIS_ARESETN = '0' then
|
||||
state <= BYTE0;
|
||||
else
|
||||
case state is
|
||||
when BYTE0 =>
|
||||
if S_AXIS_TVALID = '1' then
|
||||
ui := (others=>'0');
|
||||
i := to_integer(ui);
|
||||
data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA;
|
||||
user <= S_AXIS_TUSER;
|
||||
if S_AXIS_TLAST = '1' then
|
||||
state <= BYTE0;
|
||||
else
|
||||
if (i<SIZE_FACTOR-2) then
|
||||
state <= BYTE1;
|
||||
else
|
||||
state <= BYTEF;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when BYTE1 =>
|
||||
if S_AXIS_TVALID = '1' then
|
||||
ui := ui+1;
|
||||
i := to_integer(ui);
|
||||
data(WIDTH_IN*(i+1)-1 downto WIDTH_IN*i) <= S_AXIS_TDATA;
|
||||
if S_AXIS_TLAST = '1' then
|
||||
state <= BYTE0;
|
||||
elsif (i>=SIZE_FACTOR-2) then
|
||||
state <= BYTEF;
|
||||
end if;
|
||||
end if;
|
||||
when BYTEF =>
|
||||
if S_AXIS_TVALID = '1' and M_AXIS_TREADY='1' then
|
||||
state <= BYTE0;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,225 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Tue Dec 10 00:45:24 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1.bd
|
||||
//Design : design_1
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *)
|
||||
module design_1
|
||||
(m_axi_lite_araddr,
|
||||
m_axi_lite_arprot,
|
||||
m_axi_lite_arready,
|
||||
m_axi_lite_arvalid,
|
||||
m_axi_lite_awaddr,
|
||||
m_axi_lite_awprot,
|
||||
m_axi_lite_awready,
|
||||
m_axi_lite_awvalid,
|
||||
m_axi_lite_bready,
|
||||
m_axi_lite_bresp,
|
||||
m_axi_lite_bvalid,
|
||||
m_axi_lite_rdata,
|
||||
m_axi_lite_rready,
|
||||
m_axi_lite_rresp,
|
||||
m_axi_lite_rvalid,
|
||||
m_axi_lite_wdata,
|
||||
m_axi_lite_wready,
|
||||
m_axi_lite_wstrb,
|
||||
m_axi_lite_wvalid);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi_lite, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]m_axi_lite_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARPROT" *) output [2:0]m_axi_lite_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARREADY" *) input m_axi_lite_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARVALID" *) output m_axi_lite_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWADDR" *) output [31:0]m_axi_lite_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWPROT" *) output [2:0]m_axi_lite_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWREADY" *) input m_axi_lite_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWVALID" *) output m_axi_lite_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BREADY" *) output m_axi_lite_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BRESP" *) input [1:0]m_axi_lite_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BVALID" *) input m_axi_lite_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RDATA" *) input [31:0]m_axi_lite_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RREADY" *) output m_axi_lite_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RRESP" *) input [1:0]m_axi_lite_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RVALID" *) input m_axi_lite_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WDATA" *) output [31:0]m_axi_lite_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WREADY" *) input m_axi_lite_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WSTRB" *) output [3:0]m_axi_lite_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WVALID" *) output m_axi_lite_wvalid;
|
||||
|
||||
wire Net;
|
||||
wire Net1;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_ARADDR;
|
||||
wire [2:0]axil_master_with_rom_0_M_AXIL_ARPROT;
|
||||
wire axil_master_with_rom_0_M_AXIL_ARREADY;
|
||||
wire axil_master_with_rom_0_M_AXIL_ARVALID;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_AWADDR;
|
||||
wire [2:0]axil_master_with_rom_0_M_AXIL_AWPROT;
|
||||
wire axil_master_with_rom_0_M_AXIL_AWREADY;
|
||||
wire axil_master_with_rom_0_M_AXIL_AWVALID;
|
||||
wire axil_master_with_rom_0_M_AXIL_BREADY;
|
||||
wire [1:0]axil_master_with_rom_0_M_AXIL_BRESP;
|
||||
wire axil_master_with_rom_0_M_AXIL_BVALID;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_RDATA;
|
||||
wire axil_master_with_rom_0_M_AXIL_RREADY;
|
||||
wire [1:0]axil_master_with_rom_0_M_AXIL_RRESP;
|
||||
wire axil_master_with_rom_0_M_AXIL_RVALID;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_WDATA;
|
||||
wire axil_master_with_rom_0_M_AXIL_WREADY;
|
||||
wire [3:0]axil_master_with_rom_0_M_AXIL_WSTRB;
|
||||
wire axil_master_with_rom_0_M_AXIL_WVALID;
|
||||
wire [7:0]axis_downsizer_0_M_AXIS_TDATA;
|
||||
wire axis_downsizer_0_M_AXIS_TLAST;
|
||||
wire axis_downsizer_0_M_AXIS_TREADY;
|
||||
wire axis_downsizer_0_M_AXIS_TUSER;
|
||||
wire axis_downsizer_0_M_AXIS_TVALID;
|
||||
wire [23:0]axis_linemem_single_0_m_axis_TDATA;
|
||||
wire axis_linemem_single_0_m_axis_TLAST;
|
||||
wire axis_linemem_single_0_m_axis_TREADY;
|
||||
wire [2:0]axis_linemem_single_0_m_axis_TUSER;
|
||||
wire axis_linemem_single_0_m_axis_TVALID;
|
||||
wire [31:0]axis_master_simmodel_0_M_AXIS_TDATA;
|
||||
wire axis_master_simmodel_0_M_AXIS_TLAST;
|
||||
wire axis_master_simmodel_0_M_AXIS_TREADY;
|
||||
wire [0:0]axis_master_simmodel_0_M_AXIS_TUSER;
|
||||
wire axis_master_simmodel_0_M_AXIS_TVALID;
|
||||
wire axis_slave_simmodel_0_FINISHED;
|
||||
wire [31:0]axis_upsizer_0_M_AXIS_TDATA;
|
||||
wire axis_upsizer_0_M_AXIS_TLAST;
|
||||
wire axis_upsizer_0_M_AXIS_TREADY;
|
||||
wire axis_upsizer_0_M_AXIS_TUSER;
|
||||
wire axis_upsizer_0_M_AXIS_TVALID;
|
||||
wire [7:0]axis_video_filter_0_M_AXIS_TDATA;
|
||||
wire axis_video_filter_0_M_AXIS_TLAST;
|
||||
wire axis_video_filter_0_M_AXIS_TREADY;
|
||||
wire axis_video_filter_0_M_AXIS_TUSER;
|
||||
wire axis_video_filter_0_M_AXIS_TVALID;
|
||||
|
||||
assign axil_master_with_rom_0_M_AXIL_ARREADY = m_axi_lite_arready;
|
||||
assign axil_master_with_rom_0_M_AXIL_AWREADY = m_axi_lite_awready;
|
||||
assign axil_master_with_rom_0_M_AXIL_BRESP = m_axi_lite_bresp[1:0];
|
||||
assign axil_master_with_rom_0_M_AXIL_BVALID = m_axi_lite_bvalid;
|
||||
assign axil_master_with_rom_0_M_AXIL_RDATA = m_axi_lite_rdata[31:0];
|
||||
assign axil_master_with_rom_0_M_AXIL_RRESP = m_axi_lite_rresp[1:0];
|
||||
assign axil_master_with_rom_0_M_AXIL_RVALID = m_axi_lite_rvalid;
|
||||
assign axil_master_with_rom_0_M_AXIL_WREADY = m_axi_lite_wready;
|
||||
assign m_axi_lite_araddr[31:0] = axil_master_with_rom_0_M_AXIL_ARADDR;
|
||||
assign m_axi_lite_arprot[2:0] = axil_master_with_rom_0_M_AXIL_ARPROT;
|
||||
assign m_axi_lite_arvalid = axil_master_with_rom_0_M_AXIL_ARVALID;
|
||||
assign m_axi_lite_awaddr[31:0] = axil_master_with_rom_0_M_AXIL_AWADDR;
|
||||
assign m_axi_lite_awprot[2:0] = axil_master_with_rom_0_M_AXIL_AWPROT;
|
||||
assign m_axi_lite_awvalid = axil_master_with_rom_0_M_AXIL_AWVALID;
|
||||
assign m_axi_lite_bready = axil_master_with_rom_0_M_AXIL_BREADY;
|
||||
assign m_axi_lite_rready = axil_master_with_rom_0_M_AXIL_RREADY;
|
||||
assign m_axi_lite_wdata[31:0] = axil_master_with_rom_0_M_AXIL_WDATA;
|
||||
assign m_axi_lite_wstrb[3:0] = axil_master_with_rom_0_M_AXIL_WSTRB;
|
||||
assign m_axi_lite_wvalid = axil_master_with_rom_0_M_AXIL_WVALID;
|
||||
design_1_axil_master_with_rom_0_0 axil_master_with_rom_0
|
||||
(.M_AXIL_ACLK(Net),
|
||||
.M_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR),
|
||||
.M_AXIL_ARESETN(Net1),
|
||||
.M_AXIL_ARPROT(axil_master_with_rom_0_M_AXIL_ARPROT),
|
||||
.M_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY),
|
||||
.M_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID),
|
||||
.M_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR),
|
||||
.M_AXIL_AWPROT(axil_master_with_rom_0_M_AXIL_AWPROT),
|
||||
.M_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY),
|
||||
.M_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID),
|
||||
.M_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY),
|
||||
.M_AXIL_BRESP(axil_master_with_rom_0_M_AXIL_BRESP),
|
||||
.M_AXIL_BVALID(axil_master_with_rom_0_M_AXIL_BVALID),
|
||||
.M_AXIL_RDATA(axil_master_with_rom_0_M_AXIL_RDATA),
|
||||
.M_AXIL_RREADY(axil_master_with_rom_0_M_AXIL_RREADY),
|
||||
.M_AXIL_RRESP(axil_master_with_rom_0_M_AXIL_RRESP),
|
||||
.M_AXIL_RVALID(axil_master_with_rom_0_M_AXIL_RVALID),
|
||||
.M_AXIL_WDATA(axil_master_with_rom_0_M_AXIL_WDATA),
|
||||
.M_AXIL_WREADY(axil_master_with_rom_0_M_AXIL_WREADY),
|
||||
.M_AXIL_WSTRB(axil_master_with_rom_0_M_AXIL_WSTRB),
|
||||
.M_AXIL_WVALID(axil_master_with_rom_0_M_AXIL_WVALID));
|
||||
design_1_axis_downsizer_0_0 axis_downsizer_0
|
||||
(.AXIS_ACLK(Net),
|
||||
.AXIS_ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_downsizer_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_downsizer_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_downsizer_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_downsizer_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_downsizer_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER),
|
||||
.S_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID));
|
||||
design_1_axis_linemem_single_0_0 axis_linemem_single_0
|
||||
(.aclk(Net),
|
||||
.aresetn(Net1),
|
||||
.m_axis_tdata(axis_linemem_single_0_m_axis_TDATA),
|
||||
.m_axis_tlast(axis_linemem_single_0_m_axis_TLAST),
|
||||
.m_axis_tready(axis_linemem_single_0_m_axis_TREADY),
|
||||
.m_axis_tuser(axis_linemem_single_0_m_axis_TUSER),
|
||||
.m_axis_tvalid(axis_linemem_single_0_m_axis_TVALID),
|
||||
.s_axis_tdata(axis_downsizer_0_M_AXIS_TDATA),
|
||||
.s_axis_tlast(axis_downsizer_0_M_AXIS_TLAST),
|
||||
.s_axis_tready(axis_downsizer_0_M_AXIS_TREADY),
|
||||
.s_axis_tuser(axis_downsizer_0_M_AXIS_TUSER),
|
||||
.s_axis_tvalid(axis_downsizer_0_M_AXIS_TVALID));
|
||||
design_1_axis_master_simmodel_0_0 axis_master_simmodel_0
|
||||
(.ACLK(Net),
|
||||
.ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID));
|
||||
design_1_axis_slave_simmodel_0_0 axis_slave_simmodel_0
|
||||
(.FINISHED(axis_slave_simmodel_0_FINISHED),
|
||||
.S_AXIS_ACLK(Net),
|
||||
.S_AXIS_ARESETN(Net1),
|
||||
.S_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER),
|
||||
.S_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID));
|
||||
design_1_axis_upsizer_0_0 axis_upsizer_0
|
||||
(.AXIS_ACLK(Net),
|
||||
.AXIS_ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER),
|
||||
.S_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID));
|
||||
design_1_axis_video_filter_0_0 axis_video_filter_0
|
||||
(.ACLK(Net),
|
||||
.ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID),
|
||||
.S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXIL_ARVALID(1'b0),
|
||||
.S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXIL_AWVALID(1'b0),
|
||||
.S_AXIL_BREADY(1'b0),
|
||||
.S_AXIL_RREADY(1'b0),
|
||||
.S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXIL_WSTRB({1'b1,1'b1,1'b1,1'b1}),
|
||||
.S_AXIL_WVALID(1'b0),
|
||||
.S_AXIS_TDATA(axis_linemem_single_0_m_axis_TDATA),
|
||||
.S_AXIS_TLAST(axis_linemem_single_0_m_axis_TLAST),
|
||||
.S_AXIS_TREADY(axis_linemem_single_0_m_axis_TREADY),
|
||||
.S_AXIS_TUSER(axis_linemem_single_0_m_axis_TUSER),
|
||||
.S_AXIS_TVALID(axis_linemem_single_0_m_axis_TVALID));
|
||||
design_1_clk_rst_generator_0_0 clk_rst_generator_0
|
||||
(.clk(Net),
|
||||
.rst_n(Net1),
|
||||
.stop_simulation(axis_slave_simmodel_0_FINISHED));
|
||||
endmodule
|
||||
@@ -0,0 +1,225 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Tue Dec 10 00:45:24 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1.bd
|
||||
//Design : design_1
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=4,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *)
|
||||
module design_1
|
||||
(m_axi_lite_araddr,
|
||||
m_axi_lite_arprot,
|
||||
m_axi_lite_arready,
|
||||
m_axi_lite_arvalid,
|
||||
m_axi_lite_awaddr,
|
||||
m_axi_lite_awprot,
|
||||
m_axi_lite_awready,
|
||||
m_axi_lite_awvalid,
|
||||
m_axi_lite_bready,
|
||||
m_axi_lite_bresp,
|
||||
m_axi_lite_bvalid,
|
||||
m_axi_lite_rdata,
|
||||
m_axi_lite_rready,
|
||||
m_axi_lite_rresp,
|
||||
m_axi_lite_rvalid,
|
||||
m_axi_lite_wdata,
|
||||
m_axi_lite_wready,
|
||||
m_axi_lite_wstrb,
|
||||
m_axi_lite_wvalid);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi_lite, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) output [31:0]m_axi_lite_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARPROT" *) output [2:0]m_axi_lite_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARREADY" *) input m_axi_lite_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite ARVALID" *) output m_axi_lite_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWADDR" *) output [31:0]m_axi_lite_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWPROT" *) output [2:0]m_axi_lite_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWREADY" *) input m_axi_lite_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite AWVALID" *) output m_axi_lite_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BREADY" *) output m_axi_lite_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BRESP" *) input [1:0]m_axi_lite_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite BVALID" *) input m_axi_lite_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RDATA" *) input [31:0]m_axi_lite_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RREADY" *) output m_axi_lite_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RRESP" *) input [1:0]m_axi_lite_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite RVALID" *) input m_axi_lite_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WDATA" *) output [31:0]m_axi_lite_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WREADY" *) input m_axi_lite_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WSTRB" *) output [3:0]m_axi_lite_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_lite WVALID" *) output m_axi_lite_wvalid;
|
||||
|
||||
wire Net;
|
||||
wire Net1;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_ARADDR;
|
||||
wire [2:0]axil_master_with_rom_0_M_AXIL_ARPROT;
|
||||
wire axil_master_with_rom_0_M_AXIL_ARREADY;
|
||||
wire axil_master_with_rom_0_M_AXIL_ARVALID;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_AWADDR;
|
||||
wire [2:0]axil_master_with_rom_0_M_AXIL_AWPROT;
|
||||
wire axil_master_with_rom_0_M_AXIL_AWREADY;
|
||||
wire axil_master_with_rom_0_M_AXIL_AWVALID;
|
||||
wire axil_master_with_rom_0_M_AXIL_BREADY;
|
||||
wire [1:0]axil_master_with_rom_0_M_AXIL_BRESP;
|
||||
wire axil_master_with_rom_0_M_AXIL_BVALID;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_RDATA;
|
||||
wire axil_master_with_rom_0_M_AXIL_RREADY;
|
||||
wire [1:0]axil_master_with_rom_0_M_AXIL_RRESP;
|
||||
wire axil_master_with_rom_0_M_AXIL_RVALID;
|
||||
wire [31:0]axil_master_with_rom_0_M_AXIL_WDATA;
|
||||
wire axil_master_with_rom_0_M_AXIL_WREADY;
|
||||
wire [3:0]axil_master_with_rom_0_M_AXIL_WSTRB;
|
||||
wire axil_master_with_rom_0_M_AXIL_WVALID;
|
||||
wire [7:0]axis_downsizer_0_M_AXIS_TDATA;
|
||||
wire axis_downsizer_0_M_AXIS_TLAST;
|
||||
wire axis_downsizer_0_M_AXIS_TREADY;
|
||||
wire axis_downsizer_0_M_AXIS_TUSER;
|
||||
wire axis_downsizer_0_M_AXIS_TVALID;
|
||||
wire [23:0]axis_linemem_single_0_m_axis_TDATA;
|
||||
wire axis_linemem_single_0_m_axis_TLAST;
|
||||
wire axis_linemem_single_0_m_axis_TREADY;
|
||||
wire [2:0]axis_linemem_single_0_m_axis_TUSER;
|
||||
wire axis_linemem_single_0_m_axis_TVALID;
|
||||
wire [31:0]axis_master_simmodel_0_M_AXIS_TDATA;
|
||||
wire axis_master_simmodel_0_M_AXIS_TLAST;
|
||||
wire axis_master_simmodel_0_M_AXIS_TREADY;
|
||||
wire [0:0]axis_master_simmodel_0_M_AXIS_TUSER;
|
||||
wire axis_master_simmodel_0_M_AXIS_TVALID;
|
||||
wire axis_slave_simmodel_0_FINISHED;
|
||||
wire [31:0]axis_upsizer_0_M_AXIS_TDATA;
|
||||
wire axis_upsizer_0_M_AXIS_TLAST;
|
||||
wire axis_upsizer_0_M_AXIS_TREADY;
|
||||
wire axis_upsizer_0_M_AXIS_TUSER;
|
||||
wire axis_upsizer_0_M_AXIS_TVALID;
|
||||
wire [7:0]axis_video_filter_0_M_AXIS_TDATA;
|
||||
wire axis_video_filter_0_M_AXIS_TLAST;
|
||||
wire axis_video_filter_0_M_AXIS_TREADY;
|
||||
wire axis_video_filter_0_M_AXIS_TUSER;
|
||||
wire axis_video_filter_0_M_AXIS_TVALID;
|
||||
|
||||
assign axil_master_with_rom_0_M_AXIL_ARREADY = m_axi_lite_arready;
|
||||
assign axil_master_with_rom_0_M_AXIL_AWREADY = m_axi_lite_awready;
|
||||
assign axil_master_with_rom_0_M_AXIL_BRESP = m_axi_lite_bresp[1:0];
|
||||
assign axil_master_with_rom_0_M_AXIL_BVALID = m_axi_lite_bvalid;
|
||||
assign axil_master_with_rom_0_M_AXIL_RDATA = m_axi_lite_rdata[31:0];
|
||||
assign axil_master_with_rom_0_M_AXIL_RRESP = m_axi_lite_rresp[1:0];
|
||||
assign axil_master_with_rom_0_M_AXIL_RVALID = m_axi_lite_rvalid;
|
||||
assign axil_master_with_rom_0_M_AXIL_WREADY = m_axi_lite_wready;
|
||||
assign m_axi_lite_araddr[31:0] = axil_master_with_rom_0_M_AXIL_ARADDR;
|
||||
assign m_axi_lite_arprot[2:0] = axil_master_with_rom_0_M_AXIL_ARPROT;
|
||||
assign m_axi_lite_arvalid = axil_master_with_rom_0_M_AXIL_ARVALID;
|
||||
assign m_axi_lite_awaddr[31:0] = axil_master_with_rom_0_M_AXIL_AWADDR;
|
||||
assign m_axi_lite_awprot[2:0] = axil_master_with_rom_0_M_AXIL_AWPROT;
|
||||
assign m_axi_lite_awvalid = axil_master_with_rom_0_M_AXIL_AWVALID;
|
||||
assign m_axi_lite_bready = axil_master_with_rom_0_M_AXIL_BREADY;
|
||||
assign m_axi_lite_rready = axil_master_with_rom_0_M_AXIL_RREADY;
|
||||
assign m_axi_lite_wdata[31:0] = axil_master_with_rom_0_M_AXIL_WDATA;
|
||||
assign m_axi_lite_wstrb[3:0] = axil_master_with_rom_0_M_AXIL_WSTRB;
|
||||
assign m_axi_lite_wvalid = axil_master_with_rom_0_M_AXIL_WVALID;
|
||||
design_1_axil_master_with_rom_0_0 axil_master_with_rom_0
|
||||
(.M_AXIL_ACLK(Net),
|
||||
.M_AXIL_ARADDR(axil_master_with_rom_0_M_AXIL_ARADDR),
|
||||
.M_AXIL_ARESETN(Net1),
|
||||
.M_AXIL_ARPROT(axil_master_with_rom_0_M_AXIL_ARPROT),
|
||||
.M_AXIL_ARREADY(axil_master_with_rom_0_M_AXIL_ARREADY),
|
||||
.M_AXIL_ARVALID(axil_master_with_rom_0_M_AXIL_ARVALID),
|
||||
.M_AXIL_AWADDR(axil_master_with_rom_0_M_AXIL_AWADDR),
|
||||
.M_AXIL_AWPROT(axil_master_with_rom_0_M_AXIL_AWPROT),
|
||||
.M_AXIL_AWREADY(axil_master_with_rom_0_M_AXIL_AWREADY),
|
||||
.M_AXIL_AWVALID(axil_master_with_rom_0_M_AXIL_AWVALID),
|
||||
.M_AXIL_BREADY(axil_master_with_rom_0_M_AXIL_BREADY),
|
||||
.M_AXIL_BRESP(axil_master_with_rom_0_M_AXIL_BRESP),
|
||||
.M_AXIL_BVALID(axil_master_with_rom_0_M_AXIL_BVALID),
|
||||
.M_AXIL_RDATA(axil_master_with_rom_0_M_AXIL_RDATA),
|
||||
.M_AXIL_RREADY(axil_master_with_rom_0_M_AXIL_RREADY),
|
||||
.M_AXIL_RRESP(axil_master_with_rom_0_M_AXIL_RRESP),
|
||||
.M_AXIL_RVALID(axil_master_with_rom_0_M_AXIL_RVALID),
|
||||
.M_AXIL_WDATA(axil_master_with_rom_0_M_AXIL_WDATA),
|
||||
.M_AXIL_WREADY(axil_master_with_rom_0_M_AXIL_WREADY),
|
||||
.M_AXIL_WSTRB(axil_master_with_rom_0_M_AXIL_WSTRB),
|
||||
.M_AXIL_WVALID(axil_master_with_rom_0_M_AXIL_WVALID));
|
||||
design_1_axis_downsizer_0_0 axis_downsizer_0
|
||||
(.AXIS_ACLK(Net),
|
||||
.AXIS_ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_downsizer_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_downsizer_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_downsizer_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_downsizer_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_downsizer_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER),
|
||||
.S_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID));
|
||||
design_1_axis_linemem_single_0_0 axis_linemem_single_0
|
||||
(.aclk(Net),
|
||||
.aresetn(Net1),
|
||||
.m_axis_tdata(axis_linemem_single_0_m_axis_TDATA),
|
||||
.m_axis_tlast(axis_linemem_single_0_m_axis_TLAST),
|
||||
.m_axis_tready(axis_linemem_single_0_m_axis_TREADY),
|
||||
.m_axis_tuser(axis_linemem_single_0_m_axis_TUSER),
|
||||
.m_axis_tvalid(axis_linemem_single_0_m_axis_TVALID),
|
||||
.s_axis_tdata(axis_downsizer_0_M_AXIS_TDATA),
|
||||
.s_axis_tlast(axis_downsizer_0_M_AXIS_TLAST),
|
||||
.s_axis_tready(axis_downsizer_0_M_AXIS_TREADY),
|
||||
.s_axis_tuser(axis_downsizer_0_M_AXIS_TUSER),
|
||||
.s_axis_tvalid(axis_downsizer_0_M_AXIS_TVALID));
|
||||
design_1_axis_master_simmodel_0_0 axis_master_simmodel_0
|
||||
(.ACLK(Net),
|
||||
.ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_master_simmodel_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_master_simmodel_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_master_simmodel_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_master_simmodel_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_master_simmodel_0_M_AXIS_TVALID));
|
||||
design_1_axis_slave_simmodel_0_0 axis_slave_simmodel_0
|
||||
(.FINISHED(axis_slave_simmodel_0_FINISHED),
|
||||
.S_AXIS_ACLK(Net),
|
||||
.S_AXIS_ARESETN(Net1),
|
||||
.S_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER),
|
||||
.S_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID));
|
||||
design_1_axis_upsizer_0_0 axis_upsizer_0
|
||||
(.AXIS_ACLK(Net),
|
||||
.AXIS_ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_upsizer_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_upsizer_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_upsizer_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_upsizer_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_upsizer_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER),
|
||||
.S_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID));
|
||||
design_1_axis_video_filter_0_0 axis_video_filter_0
|
||||
(.ACLK(Net),
|
||||
.ARESETN(Net1),
|
||||
.M_AXIS_TDATA(axis_video_filter_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(axis_video_filter_0_M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(axis_video_filter_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TUSER(axis_video_filter_0_M_AXIS_TUSER),
|
||||
.M_AXIS_TVALID(axis_video_filter_0_M_AXIS_TVALID),
|
||||
.S_AXIL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXIL_ARVALID(1'b0),
|
||||
.S_AXIL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXIL_AWVALID(1'b0),
|
||||
.S_AXIL_BREADY(1'b0),
|
||||
.S_AXIL_RREADY(1'b0),
|
||||
.S_AXIL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.S_AXIL_WSTRB({1'b1,1'b1,1'b1,1'b1}),
|
||||
.S_AXIL_WVALID(1'b0),
|
||||
.S_AXIS_TDATA(axis_linemem_single_0_m_axis_TDATA),
|
||||
.S_AXIS_TLAST(axis_linemem_single_0_m_axis_TLAST),
|
||||
.S_AXIS_TREADY(axis_linemem_single_0_m_axis_TREADY),
|
||||
.S_AXIS_TUSER(axis_linemem_single_0_m_axis_TUSER),
|
||||
.S_AXIS_TVALID(axis_linemem_single_0_m_axis_TVALID));
|
||||
design_1_clk_rst_generator_0_0 clk_rst_generator_0
|
||||
(.clk(Net),
|
||||
.rst_n(Net1),
|
||||
.stop_simulation(axis_slave_simmodel_0_FINISHED));
|
||||
endmodule
|
||||
+870
@@ -0,0 +1,870 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>axis_video_filter</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TUSER</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIL</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave>
|
||||
<spirit:memoryMapRef spirit:memoryMapRef="S_AXIL"/>
|
||||
</spirit:slave>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWADDR</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WSTRB</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BRESP</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_ARADDR</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_ARVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_ARREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RRESP</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS:S_AXIL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:memoryMaps>
|
||||
<spirit:memoryMap>
|
||||
<spirit:name>S_AXIL</spirit:name>
|
||||
<spirit:displayName>S_AXIL</spirit:displayName>
|
||||
<spirit:addressBlock>
|
||||
<spirit:name>reg0</spirit:name>
|
||||
<spirit:displayName>reg0</spirit:displayName>
|
||||
<spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
|
||||
<spirit:range spirit:format="bitString" spirit:bitStringLength="16" spirit:minimum="4096" spirit:rangeType="long">0x8000</spirit:range>
|
||||
<spirit:width spirit:format="long">32</spirit:width>
|
||||
<spirit:usage>register</spirit:usage>
|
||||
</spirit:addressBlock>
|
||||
</spirit:memoryMap>
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_video_filter</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>9f5bf2d9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_video_filter</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>9f5bf2d9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">23</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
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|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_video_filter:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_WIDTH</spirit:name>
|
||||
<spirit:displayName>Coeff Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_WIDTH">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_video_filter_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axis_video_filter_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-12-09T23:45:17Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+25
@@ -0,0 +1,25 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "COEFF_WIDTH" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_WIDTH { PARAM_VALUE.COEFF_WIDTH } {
|
||||
# Procedure called to update COEFF_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_WIDTH { PARAM_VALUE.COEFF_WIDTH } {
|
||||
# Procedure called to validate COEFF_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_WIDTH { MODELPARAM_VALUE.COEFF_WIDTH PARAM_VALUE.COEFF_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_WIDTH}] ${MODELPARAM_VALUE.COEFF_WIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,799 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x29EA2656194EC7BE",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../milestone6.gen/sources_1/bd/design_1",
|
||||
"name": "design_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axis_slave_simmodel_0": "",
|
||||
"clk_rst_generator_0": "",
|
||||
"axil_master_with_rom_0": "",
|
||||
"axis_master_simmodel_0": "",
|
||||
"axis_downsizer_0": "",
|
||||
"axis_linemem_single_0": "",
|
||||
"axis_upsizer_0": "",
|
||||
"axis_video_filter_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"m_axi_lite": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"ADDR_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "1",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto_prop"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto_prop"
|
||||
},
|
||||
"NUM_READ_THREADS": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto_prop"
|
||||
},
|
||||
"NUM_WRITE_THREADS": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"RUSER_BITS_PER_BYTE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "const_prop"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "auto_prop"
|
||||
},
|
||||
"WUSER_BITS_PER_BYTE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "const_prop"
|
||||
}
|
||||
},
|
||||
"memory_map_ref": "m_axi_lite",
|
||||
"port_maps": {
|
||||
"AWADDR": {
|
||||
"physical_name": "m_axi_lite_awaddr",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"AWPROT": {
|
||||
"physical_name": "m_axi_lite_awprot",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "m_axi_lite_awvalid",
|
||||
"direction": "O"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "m_axi_lite_awready",
|
||||
"direction": "I"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "m_axi_lite_wdata",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "m_axi_lite_wstrb",
|
||||
"direction": "O",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "m_axi_lite_wvalid",
|
||||
"direction": "O"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "m_axi_lite_wready",
|
||||
"direction": "I"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "m_axi_lite_bresp",
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "m_axi_lite_bvalid",
|
||||
"direction": "I"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "m_axi_lite_bready",
|
||||
"direction": "O"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "m_axi_lite_araddr",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"ARPROT": {
|
||||
"physical_name": "m_axi_lite_arprot",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "m_axi_lite_arvalid",
|
||||
"direction": "O"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "m_axi_lite_arready",
|
||||
"direction": "I"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "m_axi_lite_rdata",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "m_axi_lite_rresp",
|
||||
"direction": "I",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "m_axi_lite_rvalid",
|
||||
"direction": "I"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "m_axi_lite_rready",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"axis_slave_simmodel_0": {
|
||||
"vlnv": "Gehrke:user:axis_slave_simmodel:1.0",
|
||||
"xci_name": "design_1_axis_slave_simmodel_0_0",
|
||||
"xci_path": "ip\\design_1_axis_slave_simmodel_0_0\\design_1_axis_slave_simmodel_0_0.xci",
|
||||
"inst_hier_path": "axis_slave_simmodel_0",
|
||||
"parameters": {
|
||||
"FILE_NAME": {
|
||||
"value": "../../../../tst_out"
|
||||
},
|
||||
"NUM_LINES": {
|
||||
"value": "192"
|
||||
},
|
||||
"NUM_PIX_PER_LINE": {
|
||||
"value": "192"
|
||||
},
|
||||
"PIXEL_FORMAT": {
|
||||
"value": "13"
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0",
|
||||
"parameters": {
|
||||
"HAS_CLK_INPUT": {
|
||||
"value": "false"
|
||||
},
|
||||
"HAS_RESET_INPUT": {
|
||||
"value": "false"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axil_master_with_rom_0": {
|
||||
"vlnv": "wg:user:axil_master_with_rom:1.0",
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
|
||||
"inst_hier_path": "axil_master_with_rom_0",
|
||||
"parameters": {
|
||||
"HAS_INTERRUPT_IN": {
|
||||
"value": "false"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"base_address": {
|
||||
"minimum": "0x00000000",
|
||||
"maximum": "0xFFFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_master_simmodel_0": {
|
||||
"vlnv": "Gehrke:user:axis_master_simmodel:1.0",
|
||||
"xci_name": "design_1_axis_master_simmodel_0_0",
|
||||
"xci_path": "ip\\design_1_axis_master_simmodel_0_0\\design_1_axis_master_simmodel_0_0.xci",
|
||||
"inst_hier_path": "axis_master_simmodel_0",
|
||||
"parameters": {
|
||||
"FILE_NAME": {
|
||||
"value": "../../../../Moewe-192x192"
|
||||
},
|
||||
"NUM_LINES": {
|
||||
"value": "192"
|
||||
},
|
||||
"NUM_PIX_PER_LINE": {
|
||||
"value": "192"
|
||||
},
|
||||
"PIXEL_FORMAT": {
|
||||
"value": "13"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_downsizer_0": {
|
||||
"vlnv": "xilinx.com:user:axis_downsizer:1.0",
|
||||
"xci_name": "design_1_axis_downsizer_0_0",
|
||||
"xci_path": "ip\\design_1_axis_downsizer_0_0\\design_1_axis_downsizer_0_0.xci",
|
||||
"inst_hier_path": "axis_downsizer_0",
|
||||
"parameters": {
|
||||
"SIZE_FACTOR": {
|
||||
"value": "4"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_linemem_single_0": {
|
||||
"vlnv": "xilinx.com:user:axis_linemem_single_master:1.0",
|
||||
"xci_name": "design_1_axis_linemem_single_0_0",
|
||||
"xci_path": "ip\\design_1_axis_linemem_single_0_0\\design_1_axis_linemem_single_0_0.xci",
|
||||
"inst_hier_path": "axis_linemem_single_0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "8"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_upsizer_0": {
|
||||
"vlnv": "xilinx.com:user:axis_upsizer:1.0",
|
||||
"xci_name": "design_1_axis_upsizer_0_0",
|
||||
"xci_path": "ip\\design_1_axis_upsizer_0_0\\design_1_axis_upsizer_0_0.xci",
|
||||
"inst_hier_path": "axis_upsizer_0",
|
||||
"parameters": {
|
||||
"SIZE_FACTOR": {
|
||||
"value": "4"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_video_filter_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_video_filter:1.0",
|
||||
"xci_name": "design_1_axis_video_filter_0_0",
|
||||
"xci_path": "ip\\design_1_axis_video_filter_0_0\\design_1_axis_video_filter_0_0.xci",
|
||||
"inst_hier_path": "axis_video_filter_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_video_filter",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TUSER": {
|
||||
"physical_name": "M_AXIS_TUSER",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "3",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "3",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "23",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TUSER": {
|
||||
"physical_name": "S_AXIS_TUSER",
|
||||
"direction": "I",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ADDR_WIDTH": {
|
||||
"value": "15",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
}
|
||||
},
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"port_maps": {
|
||||
"AWADDR": {
|
||||
"physical_name": "S_AXIL_AWADDR",
|
||||
"direction": "I",
|
||||
"left": "14",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "S_AXIL_AWVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "S_AXIL_AWREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "S_AXIL_WDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "S_AXIL_WSTRB",
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "S_AXIL_WVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "S_AXIL_WREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "S_AXIL_BRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "S_AXIL_BVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "S_AXIL_BREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "S_AXIL_ARADDR",
|
||||
"direction": "I",
|
||||
"left": "14",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "S_AXIL_ARVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "S_AXIL_ARREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "S_AXIL_RDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "S_AXIL_RRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "S_AXIL_RVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "S_AXIL_RREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXIS:S_AXIS:S_AXIL",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "ARESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axil_master_with_rom_0_M_AXIL": {
|
||||
"interface_ports": [
|
||||
"axil_master_with_rom_0/M_AXIL",
|
||||
"m_axi_lite"
|
||||
]
|
||||
},
|
||||
"axis_downsizer_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_downsizer_0/M_AXIS",
|
||||
"axis_linemem_single_0/s_axis"
|
||||
]
|
||||
},
|
||||
"axis_linemem_single_0_m_axis": {
|
||||
"interface_ports": [
|
||||
"axis_linemem_single_0/m_axis",
|
||||
"axis_video_filter_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_master_simmodel_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_master_simmodel_0/M_AXIS",
|
||||
"axis_downsizer_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_upsizer_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_upsizer_0/M_AXIS",
|
||||
"axis_slave_simmodel_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_video_filter_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_video_filter_0/M_AXIS",
|
||||
"axis_upsizer_0/S_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"Net": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axil_master_with_rom_0/M_AXIL_ACLK",
|
||||
"axis_slave_simmodel_0/S_AXIS_ACLK",
|
||||
"axis_master_simmodel_0/ACLK",
|
||||
"axis_downsizer_0/AXIS_ACLK",
|
||||
"axis_linemem_single_0/aclk",
|
||||
"axis_upsizer_0/AXIS_ACLK",
|
||||
"axis_video_filter_0/ACLK"
|
||||
]
|
||||
},
|
||||
"Net1": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axis_upsizer_0/AXIS_ARESETN",
|
||||
"axis_slave_simmodel_0/S_AXIS_ARESETN",
|
||||
"axil_master_with_rom_0/M_AXIL_ARESETN",
|
||||
"axis_master_simmodel_0/ARESETN",
|
||||
"axis_linemem_single_0/aresetn",
|
||||
"axis_downsizer_0/AXIS_ARESETN",
|
||||
"axis_video_filter_0/ARESETN"
|
||||
]
|
||||
},
|
||||
"axis_slave_simmodel_0_FINISHED": {
|
||||
"ports": [
|
||||
"axis_slave_simmodel_0/FINISHED",
|
||||
"clk_rst_generator_0/stop_simulation"
|
||||
]
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"/": {
|
||||
"memory_maps": {
|
||||
"m_axi_lite": {
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "64K",
|
||||
"width": "16",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+172
@@ -0,0 +1,172 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"cell_name": "axil_master_with_rom_0",
|
||||
"component_reference": "wg:user:axil_master_with_rom:1.0",
|
||||
"ip_revision": "19",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"REVISION_NO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"M_AXIL_ACLK": [ { "direction": "in" } ],
|
||||
"M_AXIL_ARESETN": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIL_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIL_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIL_AWREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_WREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_WVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXIL_BREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_BVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M_AXIL_AWADDR" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXIL_AWPROT" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXIL_ARADDR" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXIL_ARPROT" } ],
|
||||
"ARVALID": [ { "physical_name": "M_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "M_AXIL_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "M_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "M_AXIL_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "0x100000000",
|
||||
"display_name": "M_AXIL",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+148
@@ -0,0 +1,148 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_downsizer_0_0",
|
||||
"cell_name": "axis_downsizer_0",
|
||||
"component_reference": "xilinx.com:user:axis_downsizer:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"WIDTH_OUT": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_downsizer_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"WIDTH_OUT": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "2" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_downsizer_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"AXIS_ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_TUSER": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIS_TUSER": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXIS_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+150
@@ -0,0 +1,150 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_linemem_single_0_0",
|
||||
"cell_name": "axis_linemem_single_0",
|
||||
"component_reference": "xilinx.com:user:axis_linemem_single_master:1.0",
|
||||
"ip_revision": "17",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"MAX_LINELEN": [ { "value": "2048", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_linemem_single_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"MAX_LINELEN": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "17" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_linemem_single_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
|
||||
"s_axis_tlast": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axis_tready": [ { "direction": "out" } ],
|
||||
"s_axis_tuser": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"m_axis_tvalid": [ { "direction": "out" } ],
|
||||
"m_axis_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0" } ],
|
||||
"m_axis_tlast": [ { "direction": "out" } ],
|
||||
"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"m_axis_tuser": [ { "direction": "out", "size_left": "2", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"m_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "3", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "m_axis_tlast" } ],
|
||||
"TUSER": [ { "physical_name": "m_axis_tuser" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"s_axis": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ],
|
||||
"TLAST": [ { "physical_name": "s_axis_tlast" } ],
|
||||
"TUSER": [ { "physical_name": "s_axis_tuser" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "m_axis:s_axis", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+148
@@ -0,0 +1,148 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_master_simmodel_0_0",
|
||||
"cell_name": "axis_master_simmodel_0",
|
||||
"component_reference": "Gehrke:user:axis_master_simmodel:1.0",
|
||||
"ip_revision": "10",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_master_simmodel_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FRAMING_VAL_B_U": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FRAMING_VAL_G_Y": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FRAMING_VAL_R_V": [ { "value": "128", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FRAMING_LINES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FRAMING_PIXELS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ALPHA_VALUE": [ { "value": "255", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PIXEL_FORMAT": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RANDOM_TVALID": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_FRAMES_PER_FILE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_LINES": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_PIX_PER_LINE": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FILE_AUTONUMBERING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"FILE_EXTENSION": [ { "value": "bmp", "resolve_type": "user", "usage": "all" } ],
|
||||
"FILE_NAME": [ { "value": "../../../../Moewe-192x192", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TUSERWIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_REQUEST_TRESHOLD": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FIFO_AWIDTH": [ { "value": "11", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_FIFO_INTERFACE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_master_simmodel_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_FIFO_INTERFACE": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
"ASSOCIATED_RESET": [ { "value": "S_AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "S_AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+148
@@ -0,0 +1,148 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_upsizer_0_0",
|
||||
"cell_name": "axis_upsizer_0",
|
||||
"component_reference": "xilinx.com:user:axis_upsizer:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"WIDTH_IN": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_upsizer_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"WIDTH_IN": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SIZE_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"BIG_ENDIAN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
|
||||
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|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_upsizer_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"AXIS_ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_TUSER": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIS_TUSER": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXIS_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "AXIS_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+232
@@ -0,0 +1,232 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_video_filter_0_0",
|
||||
"cell_name": "axis_video_filter_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_video_filter:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"COEFF_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_video_filter_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"COEFF_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_axis_video_filter_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"ACLK": [ { "direction": "in" } ],
|
||||
"ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "23", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"S_AXIS_TUSER": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"M_AXIS_TUSER": [ { "direction": "out" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIL_AWREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIL_WREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_BVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIL_ARADDR": [ { "direction": "in", "size_left": "14", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIL_ARREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIL_RVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "M_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TUSER": [ { "physical_name": "S_AXIS_TUSER" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "15", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
|
||||
"AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
|
||||
"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS:S_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"display_name": "S_AXIL",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x8000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+55
@@ -0,0 +1,55 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.1" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../milestone6.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"0.705882",
|
||||
"Default View_TopLeft":"20,-153",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port m_axi_lite -pg 1 -lvl 7 -x 1640 -y 80 -defaultsOSRD
|
||||
preplace inst axis_slave_simmodel_0 -pg 1 -lvl 4 -x 1000 -y 320 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 5 -x 1240 -y 320 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 6 -x 1490 -y 80 -defaultsOSRD
|
||||
preplace inst axis_master_simmodel_0 -pg 1 -lvl 6 -x 1490 -y 200 -defaultsOSRD
|
||||
preplace inst axis_downsizer_0 -pg 1 -lvl 1 -x 170 -y 110 -defaultsOSRD
|
||||
preplace inst axis_linemem_single_0 -pg 1 -lvl 2 -x 450 -y 130 -defaultsOSRD
|
||||
preplace inst axis_upsizer_0 -pg 1 -lvl 3 -x 730 -y 300 -defaultsOSRD
|
||||
preplace inst axis_video_filter_0 -pg 1 -lvl 2 -x 450 -y 280 -defaultsOSRD
|
||||
preplace netloc Net 1 0 6 40 190 310 370 600 380 860 230 NJ 230 1350J
|
||||
preplace netloc Net1 1 0 6 30 30 300 380 590 390 870 240 N 240 1360
|
||||
preplace netloc axis_slave_simmodel_0_FINISHED 1 4 1 N 320
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 6 1 N 80
|
||||
preplace netloc axis_downsizer_0_M_AXIS 1 1 1 N 110
|
||||
preplace netloc axis_linemem_single_0_m_axis 1 1 2 320 50 580
|
||||
preplace netloc axis_master_simmodel_0_M_AXIS 1 0 7 40 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 1620
|
||||
preplace netloc axis_upsizer_0_M_AXIS 1 3 1 N 300
|
||||
preplace netloc axis_video_filter_0_M_AXIS 1 2 1 N 280
|
||||
levelinfo -pg 1 0 170 450 730 1000 1240 1490 1640
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1760 400
|
||||
"
|
||||
}
|
||||
0
|
||||
@@ -48,6 +48,7 @@
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../IP"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
@@ -60,20 +61,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="12"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="8"/>
|
||||
<Option Name="WTModelSimExportSim" Val="8"/>
|
||||
<Option Name="WTQuestaExportSim" Val="8"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="8"/>
|
||||
<Option Name="WTRivieraExportSim" Val="8"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="8"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -97,10 +98,23 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_video_filter"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
@@ -125,9 +139,10 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_video_filter"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
|
||||
Reference in New Issue
Block a user