matthias/es-praktikum
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Revert "M3: AXI-Lite Schnittstelle fast ergänzt"

Browse Source 
This reverts commit 914c9779c6.
This commit is contained in:
Matthias Biermann
2024-11-08 17:34:09 +01:00
parent 914c9779c6
commit 476e15ac75
2 changed files with 23 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Milestone3/es-milestone3/es-milestone3.xpr
+2 -1
View File
@@ -93,7 +93,6 @@
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../sources/axis_audio_filter3.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -120,6 +119,8 @@
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axis_prog_audio_filter3"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
Milestone3/sources/axis_audio_filter3.vhd
+21 -42
View File
@@ -56,17 +56,10 @@ end;
architecture rtl of axis_prog_audio_filter3 is
-- AXIL-Register
signal control_sig : std_logic := '1';
signal coeffs_sig ; std_logic_vector(26 downto 0) := (others=>'0');
signal m_valid_sig : std_logic := '0';
begin
S_AXIL_BRESP <= (others=>'0'); -- No write errors
S_AXIL_RRESP <= (others=>'0'); -- No read errors
S_AXIL_ARREADY <= '1'; -- IP is always ready
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID; -- Address Write Ready
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID; -- Data Write Ready
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
process
constant c0 : signed( 7 downto 0) := to_signed(COEFF_0,8);
@@ -81,44 +74,30 @@ begin
variable res : signed(25 downto 0);
begin
wait until rising_edge(AXI_ACLK);
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
M_AXIS_TVALID <= S_AXIS_TVALID;
if S_AXIL_AAXI_ARESETN = '1' then
S_AXIL_RVALID <= '0';
S_AXIL_BRESP <= '0';
res := (others=>'0');
else
-- Lesezugriff
-- Read Data Valid zuruecksetzen
if S_AXIL_RREADY = '1' then
S_AXIL_RVALID = '0';
end if;
if HAS_LAST then
M_AXIS_TLAST <= S_AXIS_TLAST;
end if;
-- Lesedaten rausgeben
if S_AXIL_ARVALID then
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
M_AXIS_TVALID <= S_AXIS_TVALID;
m_valid_sig <= S_AXIS_TVALID;
if HAS_LAST then
M_AXIS_TLAST <= S_AXIS_TLAST;
end if;
if S_AXIS_TVALID = '1' then
s2 := s1;
s1 := s0;
s0 := signed(S_AXIS_TDATA);
m_valid_sig <= S_AXIS_TVALID;
p0 := s0*c0;
p1 := s1*c1;
p2 := s2*c2;
if S_AXIS_TVALID = '1' then
s2 := s1;
s1 := s0;
s0 := signed(S_AXIS_TDATA);
res := (p0(23)&p0(23)&p0);
res := res + (p1(23)&p1(23)&p1);
res := res + (p2(23)&p2(23)&p2);
p0 := s0*c0;
p1 := s1*c1;
p2 := s2*c2;
res := (p0(23)&p0(23)&p0);
res := res + (p1(23)&p1(23)&p1);
res := res + (p2(23)&p2(23)&p2);
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
end if;
end if;
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
end if;
end if;
end process;
end;