M3: Timingpoblem behoben und verifiziert
This commit is contained in:
Matthias Biermann
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<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="af_sim_wrapper_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="af_sim_wrapper" />
|
||||
<top_module name="glbl" />
|
||||
<top_module name="wav_pkg" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="124,607,295.370 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="124,610,292.315 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="1,863,983,476.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="256"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="116"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="4" />
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_stereo2mo_0/AXIS_ACLK" type="logic">
|
||||
<obj_property name="ElementShortName">AXIS_ACLK</obj_property>
|
||||
<obj_property name="ObjectShortName">AXIS_ACLK</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_stereo2mo_0/M_AXIS" type="protoinst">
|
||||
<obj_property name="ElementShortName">M_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">M_AXIS</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_mono2ster_0/S_AXIS" type="protoinst">
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||||
<obj_property name="ElementShortName">S_AXIS</obj_property>
|
||||
<obj_property name="ObjectShortName">S_AXIS</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/af_sim_wrapper/af_sim_i/axis_audio_slave_sim_0/FINISHED" type="logic">
|
||||
<obj_property name="ElementShortName">FINISHED</obj_property>
|
||||
<obj_property name="ObjectShortName">FINISHED</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "af_sim",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "af_sim",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="af_sim" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1732621923"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732621924"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732621923"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732621924"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\af_sim.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\af_sim.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="af_sim_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\af_sim.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="af_sim.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\af_sim.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\af_sim.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
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|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
@@ -0,0 +1,24 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 12:52:03 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target af_sim_wrapper.bd
|
||||
--Design : af_sim_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
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||||
library IEEE;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
library UNISIM;
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||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity af_sim_wrapper is
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||||
end af_sim_wrapper;
|
||||
|
||||
architecture STRUCTURE of af_sim_wrapper is
|
||||
component af_sim is
|
||||
end component af_sim;
|
||||
begin
|
||||
af_sim_i: component af_sim
|
||||
;
|
||||
end STRUCTURE;
|
||||
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||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Nov 26 12:52:03 2024" VIVADOVERSION="2023.1">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="af_sim" PACKAGE="clg400" SPEEDGRADE="-1"/>
|
||||
|
||||
<EXTERNALPORTS/>
|
||||
|
||||
<EXTERNALINTERFACES/>
|
||||
|
||||
<MODULES>
|
||||
<MODULE COREREVISION="2" FULLNAME="/axis_audio_master_si_0" HWVERSION="1.0" INSTANCE="axis_audio_master_si_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_master_simmodel" VLNV="xilinx.com:user:axis_audio_master_simmodel:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="CLOCK_CYCLES_PER_SAMPLE" VALUE="5"/>
|
||||
<PARAMETER NAME="FILE_NAME" VALUE="../../../../HaveANiceDay"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_master_si_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="WAV_HEADER"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="3" FULLNAME="/axis_audio_mono2ster_0" HWVERSION="1.0" INSTANCE="axis_audio_mono2ster_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_mono2stereo" VLNV="xilinx.com:user:axis_audio_mono2stereo:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_mono2ster_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_prog_audio_filt_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="18" FULLNAME="/axis_audio_slave_sim_0" HWVERSION="1.0" INSTANCE="axis_audio_slave_sim_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_slave_simmodel" VLNV="xilinx.com:user:axis_audio_slave_simmodel:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="FILE_NAME" VALUE="../../../../sim_out"/>
|
||||
<PARAMETER NAME="RANDOM_TREADY" VALUE="true"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_slave_sim_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="FINISHED" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="stop_simulation"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="WAV_HEADER"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="4" FULLNAME="/axis_audio_stereo2mo_0" HWVERSION="1.0" INSTANCE="axis_audio_stereo2mo_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_stereo2mono" VLNV="xilinx.com:user:axis_audio_stereo2mono:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_stereo2mo_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="1" FULLNAME="/axis_prog_audio_filt_0" HWVERSION="1.0" INSTANCE="axis_prog_audio_filt_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_prog_audio_filter3" VLNV="xilinx.com:module_ref:axis_prog_audio_filter3:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="COEFF_0" VALUE="16"/>
|
||||
<PARAMETER NAME="COEFF_1" VALUE="32"/>
|
||||
<PARAMETER NAME="COEFF_2" VALUE="16"/>
|
||||
<PARAMETER NAME="SHIFT" VALUE="6"/>
|
||||
<PARAMETER NAME="RUN_AFTER_RESET" VALUE="true"/>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_prog_audio_filt_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXI_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="AXI_ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="7" NAME="S_AXIL_AWADDR" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="S_AXIL_AWVALID" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIL_AWREADY" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIL_WDATA" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="S_AXIL_WVALID" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIL_WREADY" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="3" NAME="S_AXIL_WSTRB" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIL_BVALID" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="S_AXIL_BREADY" SIGIS="undef"/>
|
||||
<PORT DIR="O" LEFT="1" NAME="S_AXIL_BRESP" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" LEFT="7" NAME="S_AXIL_ARADDR" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="S_AXIL_ARVALID" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIL_ARREADY" SIGIS="undef"/>
|
||||
<PORT DIR="O" LEFT="31" NAME="S_AXIL_RDATA" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIL_RVALID" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="S_AXIL_RREADY" SIGIS="undef"/>
|
||||
<PORT DIR="O" LEFT="1" NAME="S_AXIL_RRESP" RIGHT="0" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TLAST" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TLAST" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_prog_audio_filt_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TLAST" PHYSICAL="M_AXIS_TLAST"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TLAST" PHYSICAL="S_AXIS_TLAST"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="__NOC__" DATAWIDTH="32" NAME="S_AXIL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
|
||||
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
|
||||
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="ADDR_WIDTH" VALUE="8"/>
|
||||
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
|
||||
<PARAMETER NAME="HAS_BURST" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_LOCK" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_PROT" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_CACHE" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_QOS" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
|
||||
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
|
||||
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
|
||||
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
|
||||
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
|
||||
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
|
||||
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
|
||||
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXIL_AWADDR"/>
|
||||
<PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXIL_AWVALID"/>
|
||||
<PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXIL_AWREADY"/>
|
||||
<PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXIL_WDATA"/>
|
||||
<PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXIL_WSTRB"/>
|
||||
<PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXIL_WVALID"/>
|
||||
<PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXIL_WREADY"/>
|
||||
<PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXIL_BRESP"/>
|
||||
<PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXIL_BVALID"/>
|
||||
<PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXIL_BREADY"/>
|
||||
<PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXIL_ARADDR"/>
|
||||
<PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXIL_ARVALID"/>
|
||||
<PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXIL_ARREADY"/>
|
||||
<PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXIL_RDATA"/>
|
||||
<PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXIL_RRESP"/>
|
||||
<PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXIL_RVALID"/>
|
||||
<PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXIL_RREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="7" FULLNAME="/clk_rst_generator_0" HWVERSION="1.0" INSTANCE="clk_rst_generator_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_rst_generator" VLNV="wg:user:clk_rst_generator:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="CLOCK_PERIOD" VALUE="8000"/>
|
||||
<PARAMETER NAME="HAS_CLK_INPUT" VALUE="false"/>
|
||||
<PARAMETER NAME="HAS_RESET_INPUT" VALUE="false"/>
|
||||
<PARAMETER NAME="HAS_STOP_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="af_sim_clk_rst_generator_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT DIR="O" NAME="clk" SIGIS="undef" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ACLK"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="rst_n" SIGIS="undef" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ARESETN"/>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ARESETN"/>
|
||||
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ARESETN"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="stop_simulation" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="FINISHED"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES/>
|
||||
</MODULE>
|
||||
</MODULES>
|
||||
|
||||
</EDKSYSTEM>
|
||||
+506
@@ -0,0 +1,506 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_axis_audio_master_si_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">M_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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<spirit:name>GENtimestamp</spirit:name>
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||||
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||||
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||||
<spirit:name>outputProductCRC</spirit:name>
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||||
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|
||||
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|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
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|
||||
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|
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<spirit:port>
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||||
<spirit:name>ARESETN</spirit:name>
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||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
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|
||||
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||||
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|
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||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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<spirit:typeName>std_logic</spirit:typeName>
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</spirit:wireTypeDef>
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||||
<spirit:port>
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<spirit:name>WAV_HEADER</spirit:name>
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||||
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|
||||
<spirit:direction>out</spirit:direction>
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</spirit:port>
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</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_CYCLES_PER_SAMPLE</spirit:name>
|
||||
<spirit:displayName>Clock Cycles Per Sample</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_CYCLES_PER_SAMPLE">5</spirit:value>
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||||
<spirit:modelParameter spirit:dataType="string">
|
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<spirit:name>FILE_NAME</spirit:name>
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<spirit:displayName>File Name</spirit:displayName>
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<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FILE_NAME">../../../../HaveANiceDay</spirit:value>
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</spirit:modelParameter>
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||||
</spirit:modelParameters>
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||||
</spirit:model>
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<spirit:choices>
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<spirit:choice>
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<spirit:name>choice_list_9d8b0d81</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>../../ipshared/45f9/axis_audio_master_simmodel.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:name>FILE_NAME</spirit:name>
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</xilinx:tags>
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<xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_master_simmodel:1.0
|
||||
-- IP Revision: 2
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY af_sim_axis_audio_master_si_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END af_sim_axis_audio_master_si_0_0;
|
||||
|
||||
ARCHITECTURE af_sim_axis_audio_master_si_0_0_arch OF af_sim_axis_audio_master_si_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_master_si_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_master_simmodel IS
|
||||
GENERIC (
|
||||
CLOCK_CYCLES_PER_SAMPLE : INTEGER;
|
||||
FILE_NAME : STRING
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_audio_master_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_master_simmodel
|
||||
GENERIC MAP (
|
||||
CLOCK_CYCLES_PER_SAMPLE => 5,
|
||||
FILE_NAME => "../../../../HaveANiceDay"
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
WAV_HEADER => WAV_HEADER
|
||||
);
|
||||
END af_sim_axis_audio_master_si_0_0_arch;
|
||||
+695
@@ -0,0 +1,695 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_axis_audio_mono2ster_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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||||
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||||
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|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
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||||
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||||
<spirit:name>outputProductCRC</spirit:name>
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||||
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||||
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<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:name>outputProductCRC</spirit:name>
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
<spirit:port>
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||||
<spirit:name>S_AXIS_TVALID</spirit:name>
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||||
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||||
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||||
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||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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||||
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<spirit:typeName>std_logic</spirit:typeName>
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||||
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||||
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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|
||||
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||||
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|
||||
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||||
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|
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|
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c4329dc"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="dd41f636"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="7314069d"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY af_sim_axis_audio_mono2ster_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END af_sim_axis_audio_mono2ster_0_0;
|
||||
|
||||
ARCHITECTURE af_sim_axis_audio_mono2ster_0_0_arch OF af_sim_axis_audio_mono2ster_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_mono2stereo IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_mono2stereo;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_mono2stereo
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END af_sim_axis_audio_mono2ster_0_0_arch;
|
||||
+776
@@ -0,0 +1,776 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_axis_audio_slave_sim_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>S_AXIS_TREADY</spirit:name>
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</xilinx:tags>
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_NAME" xilinx:valueSource="user"/>
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</xilinx:configElementInfos>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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</spirit:vendorExtensions>
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||||
</spirit:component>
|
||||
+111
@@ -0,0 +1,111 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_slave_simmodel:1.0
|
||||
-- IP Revision: 18
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY af_sim_axis_audio_slave_sim_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END af_sim_axis_audio_slave_sim_0_0;
|
||||
|
||||
ARCHITECTURE af_sim_axis_audio_slave_sim_0_0_arch OF af_sim_axis_audio_slave_sim_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_slave_sim_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_slave_simmodel IS
|
||||
GENERIC (
|
||||
FILE_NAME : STRING;
|
||||
RANDOM_TREADY : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_audio_slave_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_slave_simmodel
|
||||
GENERIC MAP (
|
||||
FILE_NAME => "../../../../sim_out",
|
||||
RANDOM_TREADY => true
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
FINISHED => FINISHED,
|
||||
WAV_HEADER => WAV_HEADER
|
||||
);
|
||||
END af_sim_axis_audio_slave_sim_0_0_arch;
|
||||
+715
@@ -0,0 +1,715 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_axis_audio_stereo2mo_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
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||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5e4841b1_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@20365a96_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@68a00c4c_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@4660624d_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@5148e707_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@27bfd178_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@1d5b0ba5_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c033f11_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@63fad689_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3204f3cb_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@43b85df7_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1a2f7743"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="71e811ad"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="b17a0555"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY af_sim_axis_audio_stereo2mo_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END af_sim_axis_audio_stereo2mo_0_0;
|
||||
|
||||
ARCHITECTURE af_sim_axis_audio_stereo2mo_0_0_arch OF af_sim_axis_audio_stereo2mo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_stereo2mono IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_stereo2mono;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_stereo2mono
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END af_sim_axis_audio_stereo2mo_0_0_arch;
|
||||
+1482
File diff suppressed because it is too large
Load Diff
+204
@@ -0,0 +1,204 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY af_sim_axis_prog_audio_filt_0_0 IS
|
||||
PORT (
|
||||
AXI_ACLK : IN STD_LOGIC;
|
||||
AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END af_sim_axis_prog_audio_filt_0_0;
|
||||
|
||||
ARCHITECTURE af_sim_axis_prog_audio_filt_0_0_arch OF af_sim_axis_prog_audio_filt_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_prog_audio_filt_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_prog_audio_filter3 IS
|
||||
GENERIC (
|
||||
COEFF_0 : INTEGER;
|
||||
COEFF_1 : INTEGER;
|
||||
COEFF_2 : INTEGER;
|
||||
SHIFT : INTEGER;
|
||||
RUN_AFTER_RESET : BOOLEAN;
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXI_ACLK : IN STD_LOGIC;
|
||||
AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_prog_audio_filter3;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
|
||||
"ITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_prog_audio_filter3
|
||||
GENERIC MAP (
|
||||
COEFF_0 => 16,
|
||||
COEFF_1 => 32,
|
||||
COEFF_2 => 16,
|
||||
SHIFT => 6,
|
||||
RUN_AFTER_RESET => true,
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXI_ACLK => AXI_ACLK,
|
||||
AXI_ARESETN => AXI_ARESETN,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END af_sim_axis_prog_audio_filt_0_0_arch;
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>af_sim_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7ea0028a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>af_sim_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:7ea0028a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/af_sim_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">af_sim_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLOCK_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_CLK_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_RESET_INPUT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_STOP_INPUT" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY af_sim_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END af_sim_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE af_sim_clk_rst_generator_0_0_arch OF af_sim_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 8000,
|
||||
HAS_CLK_INPUT => false,
|
||||
HAS_RESET_INPUT => false,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END af_sim_clk_rst_generator_0_0_arch;
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_audio_master_simmodel.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
----------------------------------------------------------
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.wav_pkg.all;
|
||||
|
||||
entity axis_audio_master_simmodel is
|
||||
generic
|
||||
(
|
||||
CLOCK_CYCLES_PER_SAMPLE : integer := 2083;
|
||||
FILE_NAME : string := string'("tst")
|
||||
);
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic;
|
||||
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
|
||||
WAV_HEADER : out std_logic_vector(44*8-1 downto 0)
|
||||
);
|
||||
|
||||
end entity axis_audio_master_simmodel;
|
||||
|
||||
|
||||
architecture sim of axis_audio_master_simmodel is
|
||||
|
||||
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal local_clk : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
|
||||
local_clk <= ACLK;
|
||||
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd <= r;
|
||||
end process;
|
||||
|
||||
|
||||
process
|
||||
variable file_num : integer := 0;
|
||||
variable num_samples : integer;
|
||||
variable sample : std_logic_vector(31 downto 0);
|
||||
|
||||
variable delay_cnt : integer;
|
||||
variable tvalid_cnt : integer := 31415;
|
||||
|
||||
file f : WAV_FILE_TYPE;
|
||||
variable header : WAV_HEADER_TYPE;
|
||||
variable file_status : file_open_status;
|
||||
variable ok : boolean;
|
||||
variable cyccnt : integer;
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
if (ARESETN = '0') then
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TDATA <= (others=>'0');
|
||||
file_num := 0;
|
||||
tvalid_cnt := to_integer(rnd and x"0000001F");
|
||||
else
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
-- Start-Up delay
|
||||
for i in 0 to 100 loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
-- Create filename and try to open the file
|
||||
file_open ( file_status, f, FILE_NAME & ".wav", read_mode);
|
||||
|
||||
-- File open succeeded ?
|
||||
if file_status /= open_ok then
|
||||
assert false report "AXIS_AUDIO_MASTER_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
|
||||
else
|
||||
read_wav_header(ok,num_samples,header,f);
|
||||
|
||||
assert ok report "AXIS_AUDIO_MASTER_SIMMODEL: Input is not in WAV format." severity failure;
|
||||
|
||||
for i in 0 to 43 loop
|
||||
WAV_HEADER(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(header(i),8));
|
||||
end loop;
|
||||
if ok then
|
||||
for s in 0 to num_samples-1 loop -- sample loop
|
||||
M_AXIS_TDATA ( 7 downto 0) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TDATA (15 downto 8) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TDATA (23 downto 16) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TDATA (31 downto 24) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TVALID <= '1';
|
||||
-- wait until data has been acknowledged
|
||||
wait until rising_edge (local_clk);
|
||||
cyccnt := CLOCK_CYCLES_PER_SAMPLE;
|
||||
while M_AXIS_TREADY = '0' loop
|
||||
wait until rising_edge (local_clk);
|
||||
cyccnt := cyccnt - 1;
|
||||
end loop;
|
||||
M_AXIS_TVALID <= '0';
|
||||
while cyccnt > 0 loop
|
||||
wait until rising_edge (local_clk);
|
||||
cyccnt := cyccnt - 1;
|
||||
end loop;
|
||||
end loop; -- sample loop
|
||||
file_close(f);
|
||||
end if; -- if ok
|
||||
end if; -- if open_status ok
|
||||
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
-- wait until reset is activated
|
||||
while ARESETN = '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
|
||||
end sim;
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
package wav_pkg is
|
||||
|
||||
type WAV_FILE_TYPE is file of character;
|
||||
type WAV_HEADER_TYPE is array (0 to 43) of integer;
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE );
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer;
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
end;
|
||||
|
||||
package body wav_pkg is
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
write(f, character'val(value));
|
||||
end wavput8;
|
||||
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
for i in 0 to 43 loop
|
||||
wavput8(header(i),f);
|
||||
end loop;
|
||||
end write_wav_header;
|
||||
|
||||
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
|
||||
variable chr : character;
|
||||
begin
|
||||
read (f,chr);
|
||||
return character'pos(chr);
|
||||
end wavget8;
|
||||
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
variable chr : character;
|
||||
variable val : integer;
|
||||
begin
|
||||
success := true;
|
||||
for i in 0 to 43 loop
|
||||
header(i) := wavget8(f);
|
||||
end loop;
|
||||
numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
|
||||
|
||||
if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then -- check for 'RIFF'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then -- check for 'WAVE'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
end read_wav_header;
|
||||
|
||||
|
||||
end package body;
|
||||
|
||||
+51
@@ -0,0 +1,51 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- AXI Stream Audio Mono to Stereo
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
entity axis_audio_mono2stereo is
|
||||
generic
|
||||
(
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(15 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_audio_mono2stereo is
|
||||
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY;
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
|
||||
M_AXIS_TDATA (31 downto 16) <= S_AXIS_TDATA;
|
||||
M_AXIS_TDATA (15 downto 0) <= S_AXIS_TDATA;
|
||||
|
||||
end;
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- clk_rst_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_rst_generator is
|
||||
generic
|
||||
(
|
||||
CLOCK_PERIOD : integer := 10000;
|
||||
HAS_CLK_INPUT : boolean := true;
|
||||
HAS_RESET_INPUT : boolean := true;
|
||||
HAS_STOP_INPUT : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
clk_in : in std_logic := '1';
|
||||
rst_in : in std_logic := '0';
|
||||
|
||||
clk : out std_logic;
|
||||
rst_n : out std_logic;
|
||||
|
||||
stop_simulation : in std_logic := '0'
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of clk_rst_generator is
|
||||
|
||||
signal clk_sim : std_logic := '1';
|
||||
signal clk_in_sig : std_logic := '1';
|
||||
signal clk_sig : std_logic := '1';
|
||||
signal rst_sig : std_logic := '0';
|
||||
signal rst_in_sync : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk <= clk_sig;
|
||||
rst_n <= not rst_sig;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
clk_sig <= clk_in_sig and clk_sim;
|
||||
-- Dies ist kein gated Clock!
|
||||
-- Fuer die Synthese ist clk_sim konstant '1'
|
||||
-- somit wird die UND-Verknuepfung 'wegoptimiert'
|
||||
-- und was übrig bleibt, ist ein 'Draht'
|
||||
|
||||
-- synthesis translate_off
|
||||
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
-- synthesis translate_on
|
||||
|
||||
process (clk_in) begin
|
||||
clk_in_sig <= clk_in;
|
||||
-- synthesis translate_off
|
||||
clk_in_sig <= '1';
|
||||
-- synthesis translate_on
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- RESET GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
process
|
||||
variable rescnt : unsigned (6 downto 0) := (others=>'1');
|
||||
begin
|
||||
wait until rising_edge(clk_sig);
|
||||
|
||||
rst_in_sync <= rst_in;
|
||||
if rst_in_sync = '1' then
|
||||
rescnt := (others=>'1');
|
||||
end if;
|
||||
|
||||
if rescnt = 0 then
|
||||
rst_sig <= '0';
|
||||
else
|
||||
rescnt := rescnt - 1;
|
||||
rst_sig <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- STOP SIMULATION INPUT (simulation only)
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- synthesis translate_off
|
||||
process (stop_simulation) begin
|
||||
if stop_simulation = '1' then
|
||||
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
|
||||
end if;
|
||||
end process;
|
||||
-- synthesis translate_on
|
||||
|
||||
end rtl;
|
||||
+58
@@ -0,0 +1,58 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- AXI Stream Audio Stereo to Mono
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020/2021
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axis_audio_stereo2mono is
|
||||
generic
|
||||
(
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(15 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_audio_stereo2mono is
|
||||
signal m_valid_sig : std_logic := '0';
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
|
||||
|
||||
process begin
|
||||
wait until rising_edge(AXIS_ACLK);
|
||||
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
|
||||
M_AXIS_TDATA <= std_logic_vector(signed(S_AXIS_TDATA(31)&S_AXIS_TDATA(31 downto 17))+signed(S_AXIS_TDATA(15)&S_AXIS_TDATA(15 downto 1)));
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
m_valid_sig <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end;
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_audio_slave_simmodel.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
----------------------------------------------------------
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.wav_pkg.all;
|
||||
|
||||
entity axis_audio_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
FILE_NAME : string := string'("tst_out");
|
||||
RANDOM_TREADY : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic;
|
||||
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
FINISHED : out std_logic;
|
||||
WAV_HEADER : in std_logic_vector(11*32-1 downto 0)
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
architecture sim of axis_audio_slave_simmodel is
|
||||
|
||||
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal local_clk : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
|
||||
local_clk <= ACLK;
|
||||
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd <= r;
|
||||
end process;
|
||||
|
||||
|
||||
process
|
||||
variable num_samples : integer;
|
||||
|
||||
variable delay_cnt : integer;
|
||||
variable tready_cnt : integer := 31415;
|
||||
|
||||
file f : WAV_FILE_TYPE;
|
||||
variable header : WAV_HEADER_TYPE;
|
||||
variable file_status : file_open_status;
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
if (ARESETN = '0') then
|
||||
tready_cnt := to_integer(rnd and x"0000001F");
|
||||
FINISHED <= '0';
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
FINISHED <= '0';
|
||||
-- Create filename and try to open the file
|
||||
file_open ( file_status, f, FILE_NAME & ".wav", write_mode);
|
||||
|
||||
-- File open succeeded ?
|
||||
if file_status /= open_ok then
|
||||
assert false report "AXIS_AUDIO_SLAVE_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
|
||||
else
|
||||
|
||||
wait until S_AXIS_TVALID = '1';
|
||||
for i in 0 to 43 loop
|
||||
header(i) := to_integer(unsigned(WAV_HEADER(8*(i+1)-1 downto 8*i)));
|
||||
end loop;
|
||||
write_wav_header(header,f);
|
||||
|
||||
num_samples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
|
||||
|
||||
for s in 0 to num_samples-1 loop -- sample loop
|
||||
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge(local_clk);
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge(local_clk);
|
||||
end loop;
|
||||
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))),f);
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA(15 downto 8))),f);
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA(23 downto 16))),f);
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA(31 downto 24))),f);
|
||||
|
||||
tready_cnt := tready_cnt - 1;
|
||||
if RANDOM_TREADY and tready_cnt <= 0 then
|
||||
-- random TREADY delay
|
||||
delay_cnt := to_integer(rnd and x"00000007");
|
||||
while delay_cnt > 0 loop
|
||||
S_AXIS_TREADY <= '0';
|
||||
delay_cnt := delay_cnt - 1;
|
||||
wait until rising_edge (local_clk);
|
||||
tready_cnt := to_integer(rnd and x"0000001F");
|
||||
end loop;
|
||||
end if;
|
||||
end loop; -- sample loop
|
||||
|
||||
file_close(f);
|
||||
FINISHED <= '1';
|
||||
|
||||
end if; -- if open_status ok
|
||||
|
||||
-- wait until reset is activated
|
||||
while ARESETN = '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
|
||||
end sim;
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
package wav_pkg is
|
||||
|
||||
type WAV_FILE_TYPE is file of character;
|
||||
type WAV_HEADER_TYPE is array (0 to 43) of integer;
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE );
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer;
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
end;
|
||||
|
||||
package body wav_pkg is
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
write(f, character'val(value));
|
||||
end wavput8;
|
||||
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
for i in 0 to 43 loop
|
||||
wavput8(header(i),f);
|
||||
end loop;
|
||||
end write_wav_header;
|
||||
|
||||
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
|
||||
variable chr : character;
|
||||
begin
|
||||
read (f,chr);
|
||||
return character'pos(chr);
|
||||
end wavget8;
|
||||
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
variable chr : character;
|
||||
variable val : integer;
|
||||
begin
|
||||
success := true;
|
||||
for i in 0 to 43 loop
|
||||
header(i) := wavget8(f);
|
||||
end loop;
|
||||
numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
|
||||
|
||||
if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then -- check for 'RIFF'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then -- check for 'WAVE'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
end read_wav_header;
|
||||
|
||||
|
||||
end package body;
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"af_sim": {
|
||||
"proto_instances": {
|
||||
"/axis_audio_master_si_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "ACLK"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_slave_sim_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "ACLK"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_prog_audio_filt_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "M_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_prog_audio_filt_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "S_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,205 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 12:52:03 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target af_sim.bd
|
||||
--Design : af_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity af_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef";
|
||||
end af_sim;
|
||||
|
||||
architecture STRUCTURE of af_sim is
|
||||
component af_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_clk_rst_generator_0_0;
|
||||
component af_sim_axis_audio_master_si_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_master_si_0_0;
|
||||
component af_sim_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_mono2ster_0_0;
|
||||
component af_sim_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_stereo2mo_0_0;
|
||||
component af_sim_axis_audio_slave_sim_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_slave_sim_0_0;
|
||||
component af_sim_axis_prog_audio_filt_0_0 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_prog_audio_filt_0_0;
|
||||
signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
begin
|
||||
axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
FINISHED => axis_audio_slave_sim_0_FINISHED,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED,
|
||||
S_AXIL_ARVALID => '0',
|
||||
S_AXIL_AWADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED,
|
||||
S_AXIL_AWVALID => '0',
|
||||
S_AXIL_BREADY => '0',
|
||||
S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED,
|
||||
S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0),
|
||||
S_AXIL_RREADY => '0',
|
||||
S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED,
|
||||
S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED,
|
||||
S_AXIL_WSTRB(3 downto 0) => B"1111",
|
||||
S_AXIL_WVALID => '0',
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component af_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => axis_audio_slave_sim_0_FINISHED
|
||||
);
|
||||
end STRUCTURE;
|
||||
Binary file not shown.
@@ -0,0 +1,205 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Tue Nov 26 12:52:03 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target af_sim.bd
|
||||
--Design : af_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity af_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef";
|
||||
end af_sim;
|
||||
|
||||
architecture STRUCTURE of af_sim is
|
||||
component af_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_clk_rst_generator_0_0;
|
||||
component af_sim_axis_audio_master_si_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC;
|
||||
WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_master_si_0_0;
|
||||
component af_sim_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_mono2ster_0_0;
|
||||
component af_sim_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_audio_stereo2mo_0_0;
|
||||
component af_sim_axis_audio_slave_sim_0_0 is
|
||||
port (
|
||||
ACLK : in STD_LOGIC;
|
||||
ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
FINISHED : out STD_LOGIC;
|
||||
WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 )
|
||||
);
|
||||
end component af_sim_axis_audio_slave_sim_0_0;
|
||||
component af_sim_axis_prog_audio_filt_0_0 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component af_sim_axis_prog_audio_filt_0_0;
|
||||
signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
begin
|
||||
axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0
|
||||
port map (
|
||||
ACLK => clk_rst_generator_0_clk,
|
||||
ARESETN => clk_rst_generator_0_rst_n,
|
||||
FINISHED => axis_audio_slave_sim_0_FINISHED,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
|
||||
);
|
||||
axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED,
|
||||
S_AXIL_ARVALID => '0',
|
||||
S_AXIL_AWADDR(7 downto 0) => B"00000000",
|
||||
S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED,
|
||||
S_AXIL_AWVALID => '0',
|
||||
S_AXIL_BREADY => '0',
|
||||
S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED,
|
||||
S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0),
|
||||
S_AXIL_RREADY => '0',
|
||||
S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0),
|
||||
S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED,
|
||||
S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
|
||||
S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED,
|
||||
S_AXIL_WSTRB(3 downto 0) => B"1111",
|
||||
S_AXIL_WVALID => '0',
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component af_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => axis_audio_slave_sim_0_FINISHED
|
||||
);
|
||||
end STRUCTURE;
|
||||
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732293809"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732293809"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732293809"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732293809"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732628584"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732628584"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732628584"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732628584"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Nov 22 17:43:22 2024
|
||||
--Date : Tue Nov 26 14:42:59 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1_wrapper.bd
|
||||
--Design : design_1_wrapper
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Nov 22 17:43:29 2024" VIVADOVERSION="2023.1">
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Nov 26 14:43:04 2024" VIVADOVERSION="2023.1">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
|
||||
|
||||
|
||||
+3
-3
@@ -917,7 +917,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:45:19 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:45:05 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -948,7 +948,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -968,7 +968,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:29 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:04 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+132
-110
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Nov 22 17:45:19 2024
|
||||
// Date : Tue Nov 26 14:45:05 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_sim_netlist.v
|
||||
@@ -196,8 +196,10 @@ module design_1_axis_prog_audio_filt_0_1_axis_prog_audio_filter3
|
||||
wire \M_AXIS_TDATA[13]_i_1_n_0 ;
|
||||
wire \M_AXIS_TDATA[13]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[14]_i_1_n_0 ;
|
||||
wire \M_AXIS_TDATA[14]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_3_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_4_n_0 ;
|
||||
wire \M_AXIS_TDATA[1]_i_1_n_0 ;
|
||||
wire \M_AXIS_TDATA[1]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[2]_i_1_n_0 ;
|
||||
@@ -487,285 +489,305 @@ module design_1_axis_prog_audio_filt_0_1_axis_prog_audio_filter3
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair13" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[0]_i_1
|
||||
(.I0(\M_AXIS_TDATA[1]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[0]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[0]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[0]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[0]_i_2
|
||||
(.I0(res_reg_n_91),
|
||||
(.I0(res_reg_n_99),
|
||||
.I1(res_reg_n_103),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_93),
|
||||
.I3(res_reg_n_101),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_105),
|
||||
.O(\M_AXIS_TDATA[0]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair18" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[10]_i_1
|
||||
(.I0(\M_AXIS_TDATA[11]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[10]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[10]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[10]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[10]_i_2
|
||||
(.I0(res_reg_n_81),
|
||||
(.I0(res_reg_n_89),
|
||||
.I1(res_reg_n_93),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_83),
|
||||
.I3(res_reg_n_91),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_95),
|
||||
.O(\M_AXIS_TDATA[10]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair18" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[11]_i_1
|
||||
(.I0(\M_AXIS_TDATA[12]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[11]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[11]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[11]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[11]_i_2
|
||||
(.I0(res_reg_n_80),
|
||||
(.I0(res_reg_n_88),
|
||||
.I1(res_reg_n_92),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_82),
|
||||
.I3(res_reg_n_90),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_94),
|
||||
.O(\M_AXIS_TDATA[11]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair19" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[12]_i_1
|
||||
(.I0(\M_AXIS_TDATA[13]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[12]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[12]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[12]_i_1_n_0 ));
|
||||
LUT5 #(
|
||||
.INIT(32'h30BB3088))
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[12]_i_2
|
||||
(.I0(res_reg_n_91),
|
||||
.I1(shift_sig[1]),
|
||||
.I2(res_reg_n_81),
|
||||
.I3(shift_sig[2]),
|
||||
.I4(res_reg_n_93),
|
||||
.O(\M_AXIS_TDATA[12]_i_2_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'h00E4FFFF00E40000))
|
||||
\M_AXIS_TDATA[13]_i_1
|
||||
(.I0(shift_sig[1]),
|
||||
.I1(res_reg_n_91),
|
||||
.I2(res_reg_n_89),
|
||||
.I3(shift_sig[2]),
|
||||
.I4(shift_sig[0]),
|
||||
.I5(\M_AXIS_TDATA[13]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[13]_i_1_n_0 ));
|
||||
LUT5 #(
|
||||
.INIT(32'h30BB3088))
|
||||
\M_AXIS_TDATA[13]_i_2
|
||||
(.I0(res_reg_n_90),
|
||||
.I1(shift_sig[1]),
|
||||
.I2(res_reg_n_80),
|
||||
.I3(shift_sig[2]),
|
||||
.I4(res_reg_n_92),
|
||||
.O(\M_AXIS_TDATA[13]_i_2_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'h00000000FEAE5404))
|
||||
\M_AXIS_TDATA[14]_i_1
|
||||
(.I0(shift_sig[0]),
|
||||
(.I0(res_reg_n_87),
|
||||
.I1(res_reg_n_91),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_89),
|
||||
.I4(\M_AXIS_TDATA[15]_i_3_n_0 ),
|
||||
.I5(shift_sig[2]),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_93),
|
||||
.O(\M_AXIS_TDATA[12]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair19" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[13]_i_1
|
||||
(.I0(\M_AXIS_TDATA[14]_i_2_n_0 ),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[13]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[13]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[13]_i_2
|
||||
(.I0(res_reg_n_86),
|
||||
.I1(res_reg_n_90),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_88),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_92),
|
||||
.O(\M_AXIS_TDATA[13]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair20" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[14]_i_1
|
||||
(.I0(\M_AXIS_TDATA[15]_i_4_n_0 ),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[14]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[14]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[14]_i_2
|
||||
(.I0(res_reg_n_85),
|
||||
.I1(res_reg_n_89),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_87),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_91),
|
||||
.O(\M_AXIS_TDATA[14]_i_2_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\M_AXIS_TDATA[15]_i_1
|
||||
(.I0(AXI_ARESETN),
|
||||
.I1(state),
|
||||
.O(M_AXIS_TVALID1_out));
|
||||
LUT6 #(
|
||||
.INIT(64'h00000000EEE444E4))
|
||||
\M_AXIS_TDATA[15]_i_2
|
||||
(.I0(shift_sig[0]),
|
||||
.I1(\M_AXIS_TDATA[15]_i_3_n_0 ),
|
||||
.I2(res_reg_n_89),
|
||||
.I3(shift_sig[1]),
|
||||
.I4(res_reg_n_87),
|
||||
.I5(shift_sig[2]),
|
||||
.O(\M_AXIS_TDATA[15]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair20" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[15]_i_2
|
||||
(.I0(\M_AXIS_TDATA[15]_i_3_n_0 ),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[15]_i_4_n_0 ),
|
||||
.O(\M_AXIS_TDATA[15]_i_2_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[15]_i_3
|
||||
(.I0(res_reg_n_88),
|
||||
.I1(shift_sig[1]),
|
||||
.I2(res_reg_n_90),
|
||||
(.I0(res_reg_n_83),
|
||||
.I1(res_reg_n_87),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_85),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_89),
|
||||
.O(\M_AXIS_TDATA[15]_i_3_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[15]_i_4
|
||||
(.I0(res_reg_n_84),
|
||||
.I1(res_reg_n_88),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_86),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_90),
|
||||
.O(\M_AXIS_TDATA[15]_i_4_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair13" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[1]_i_1
|
||||
(.I0(\M_AXIS_TDATA[2]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[1]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[1]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[1]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[1]_i_2
|
||||
(.I0(res_reg_n_90),
|
||||
(.I0(res_reg_n_98),
|
||||
.I1(res_reg_n_102),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_92),
|
||||
.I3(res_reg_n_100),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_104),
|
||||
.O(\M_AXIS_TDATA[1]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair14" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[2]_i_1
|
||||
(.I0(\M_AXIS_TDATA[3]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[2]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[2]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[2]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[2]_i_2
|
||||
(.I0(res_reg_n_89),
|
||||
(.I0(res_reg_n_97),
|
||||
.I1(res_reg_n_101),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_91),
|
||||
.I3(res_reg_n_99),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_103),
|
||||
.O(\M_AXIS_TDATA[2]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair14" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[3]_i_1
|
||||
(.I0(\M_AXIS_TDATA[4]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[3]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[3]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[3]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[3]_i_2
|
||||
(.I0(res_reg_n_88),
|
||||
(.I0(res_reg_n_96),
|
||||
.I1(res_reg_n_100),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_90),
|
||||
.I3(res_reg_n_98),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_102),
|
||||
.O(\M_AXIS_TDATA[3]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair15" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[4]_i_1
|
||||
(.I0(\M_AXIS_TDATA[5]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[4]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[4]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[4]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[4]_i_2
|
||||
(.I0(res_reg_n_87),
|
||||
(.I0(res_reg_n_95),
|
||||
.I1(res_reg_n_99),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_89),
|
||||
.I3(res_reg_n_97),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_101),
|
||||
.O(\M_AXIS_TDATA[4]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair15" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[5]_i_1
|
||||
(.I0(\M_AXIS_TDATA[6]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[5]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[5]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[5]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[5]_i_2
|
||||
(.I0(res_reg_n_86),
|
||||
(.I0(res_reg_n_94),
|
||||
.I1(res_reg_n_98),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_88),
|
||||
.I3(res_reg_n_96),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_100),
|
||||
.O(\M_AXIS_TDATA[5]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair16" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[6]_i_1
|
||||
(.I0(\M_AXIS_TDATA[7]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[6]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[6]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[6]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[6]_i_2
|
||||
(.I0(res_reg_n_85),
|
||||
(.I0(res_reg_n_93),
|
||||
.I1(res_reg_n_97),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_87),
|
||||
.I3(res_reg_n_95),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_99),
|
||||
.O(\M_AXIS_TDATA[6]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair16" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[7]_i_1
|
||||
(.I0(\M_AXIS_TDATA[8]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[7]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[7]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[7]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[7]_i_2
|
||||
(.I0(res_reg_n_84),
|
||||
(.I0(res_reg_n_92),
|
||||
.I1(res_reg_n_96),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_86),
|
||||
.I3(res_reg_n_94),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_98),
|
||||
.O(\M_AXIS_TDATA[7]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair17" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[8]_i_1
|
||||
(.I0(\M_AXIS_TDATA[9]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[8]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[8]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[8]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[8]_i_2
|
||||
(.I0(res_reg_n_83),
|
||||
(.I0(res_reg_n_91),
|
||||
.I1(res_reg_n_95),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_85),
|
||||
.I3(res_reg_n_93),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_97),
|
||||
.O(\M_AXIS_TDATA[8]_i_2_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair17" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hAC))
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[9]_i_1
|
||||
(.I0(\M_AXIS_TDATA[10]_i_2_n_0 ),
|
||||
.I1(\M_AXIS_TDATA[9]_i_2_n_0 ),
|
||||
.I2(shift_sig[0]),
|
||||
.I1(shift_sig[0]),
|
||||
.I2(\M_AXIS_TDATA[9]_i_2_n_0 ),
|
||||
.O(\M_AXIS_TDATA[9]_i_1_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'hAFA0CFCFAFA0C0C0))
|
||||
\M_AXIS_TDATA[9]_i_2
|
||||
(.I0(res_reg_n_82),
|
||||
(.I0(res_reg_n_90),
|
||||
.I1(res_reg_n_94),
|
||||
.I2(shift_sig[1]),
|
||||
.I3(res_reg_n_84),
|
||||
.I3(res_reg_n_92),
|
||||
.I4(shift_sig[2]),
|
||||
.I5(res_reg_n_96),
|
||||
.O(\M_AXIS_TDATA[9]_i_2_n_0 ));
|
||||
|
||||
+151
-123
@@ -2,7 +2,7 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Fri Nov 22 17:45:19 2024
|
||||
-- Date : Tue Nov 26 14:45:05 2024
|
||||
-- Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_sim_netlist.vhdl
|
||||
@@ -53,8 +53,10 @@ architecture STRUCTURE of design_1_axis_prog_audio_filt_0_1_axis_prog_audio_filt
|
||||
signal \M_AXIS_TDATA[13]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[13]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[14]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[14]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_3_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_4_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[1]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[1]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[2]_i_1_n_0\ : STD_LOGIC;
|
||||
@@ -332,6 +334,10 @@ architecture STRUCTURE of design_1_axis_prog_audio_filt_0_1_axis_prog_audio_filt
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[0]_i_1\ : label is "soft_lutpair13";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[10]_i_1\ : label is "soft_lutpair18";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[11]_i_1\ : label is "soft_lutpair18";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[12]_i_1\ : label is "soft_lutpair19";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[13]_i_1\ : label is "soft_lutpair19";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[14]_i_1\ : label is "soft_lutpair20";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[15]_i_2\ : label is "soft_lutpair20";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[1]_i_1\ : label is "soft_lutpair13";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[2]_i_1\ : label is "soft_lutpair14";
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[3]_i_1\ : label is "soft_lutpair14";
|
||||
@@ -376,12 +382,12 @@ begin
|
||||
S_AXIL_RVALID <= \^s_axil_rvalid\;
|
||||
\M_AXIS_TDATA[0]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[1]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[0]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[0]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[0]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[0]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -389,22 +395,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_91,
|
||||
I0 => res_reg_n_99,
|
||||
I1 => res_reg_n_103,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_93,
|
||||
I3 => res_reg_n_101,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_105,
|
||||
O => \M_AXIS_TDATA[0]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[10]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[11]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[10]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[10]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[10]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[10]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -412,22 +418,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_81,
|
||||
I0 => res_reg_n_89,
|
||||
I1 => res_reg_n_93,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_83,
|
||||
I3 => res_reg_n_91,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_95,
|
||||
O => \M_AXIS_TDATA[10]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[11]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[12]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[11]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[11]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[11]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[11]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -435,74 +441,83 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_80,
|
||||
I0 => res_reg_n_88,
|
||||
I1 => res_reg_n_92,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_82,
|
||||
I3 => res_reg_n_90,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_94,
|
||||
O => \M_AXIS_TDATA[11]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[12]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[13]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[12]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[12]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[12]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[12]_i_2\: unisim.vcomponents.LUT5
|
||||
\M_AXIS_TDATA[12]_i_2\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"30BB3088"
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_91,
|
||||
I1 => shift_sig(1),
|
||||
I2 => res_reg_n_81,
|
||||
I3 => shift_sig(2),
|
||||
I4 => res_reg_n_93,
|
||||
O => \M_AXIS_TDATA[12]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[13]_i_1\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"00E4FFFF00E40000"
|
||||
)
|
||||
port map (
|
||||
I0 => shift_sig(1),
|
||||
I1 => res_reg_n_91,
|
||||
I2 => res_reg_n_89,
|
||||
I3 => shift_sig(2),
|
||||
I4 => shift_sig(0),
|
||||
I5 => \M_AXIS_TDATA[13]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[13]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[13]_i_2\: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"30BB3088"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_90,
|
||||
I1 => shift_sig(1),
|
||||
I2 => res_reg_n_80,
|
||||
I3 => shift_sig(2),
|
||||
I4 => res_reg_n_92,
|
||||
O => \M_AXIS_TDATA[13]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[14]_i_1\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"00000000FEAE5404"
|
||||
)
|
||||
port map (
|
||||
I0 => shift_sig(0),
|
||||
I0 => res_reg_n_87,
|
||||
I1 => res_reg_n_91,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_89,
|
||||
I4 => \M_AXIS_TDATA[15]_i_3_n_0\,
|
||||
I5 => shift_sig(2),
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_93,
|
||||
O => \M_AXIS_TDATA[12]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[13]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[14]_i_2_n_0\,
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[13]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[13]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[13]_i_2\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_86,
|
||||
I1 => res_reg_n_90,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_88,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_92,
|
||||
O => \M_AXIS_TDATA[13]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[14]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[15]_i_4_n_0\,
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[14]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[14]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[14]_i_2\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_85,
|
||||
I1 => res_reg_n_89,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_87,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_91,
|
||||
O => \M_AXIS_TDATA[14]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_1\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"8"
|
||||
@@ -512,37 +527,50 @@ begin
|
||||
I1 => state,
|
||||
O => M_AXIS_TVALID1_out
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_2\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"00000000EEE444E4"
|
||||
)
|
||||
port map (
|
||||
I0 => shift_sig(0),
|
||||
I1 => \M_AXIS_TDATA[15]_i_3_n_0\,
|
||||
I2 => res_reg_n_89,
|
||||
I3 => shift_sig(1),
|
||||
I4 => res_reg_n_87,
|
||||
I5 => shift_sig(2),
|
||||
O => \M_AXIS_TDATA[15]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_3\: unisim.vcomponents.LUT3
|
||||
\M_AXIS_TDATA[15]_i_2\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_88,
|
||||
I1 => shift_sig(1),
|
||||
I2 => res_reg_n_90,
|
||||
I0 => \M_AXIS_TDATA[15]_i_3_n_0\,
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[15]_i_4_n_0\,
|
||||
O => \M_AXIS_TDATA[15]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_3\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_83,
|
||||
I1 => res_reg_n_87,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_85,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_89,
|
||||
O => \M_AXIS_TDATA[15]_i_3_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_4\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_84,
|
||||
I1 => res_reg_n_88,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_86,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_90,
|
||||
O => \M_AXIS_TDATA[15]_i_4_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[1]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[2]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[1]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[1]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[1]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[1]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -550,22 +578,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_90,
|
||||
I0 => res_reg_n_98,
|
||||
I1 => res_reg_n_102,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_92,
|
||||
I3 => res_reg_n_100,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_104,
|
||||
O => \M_AXIS_TDATA[1]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[2]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[3]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[2]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[2]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[2]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[2]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -573,22 +601,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_89,
|
||||
I0 => res_reg_n_97,
|
||||
I1 => res_reg_n_101,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_91,
|
||||
I3 => res_reg_n_99,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_103,
|
||||
O => \M_AXIS_TDATA[2]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[3]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[4]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[3]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[3]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[3]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[3]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -596,22 +624,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_88,
|
||||
I0 => res_reg_n_96,
|
||||
I1 => res_reg_n_100,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_90,
|
||||
I3 => res_reg_n_98,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_102,
|
||||
O => \M_AXIS_TDATA[3]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[4]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[5]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[4]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[4]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[4]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[4]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -619,22 +647,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_87,
|
||||
I0 => res_reg_n_95,
|
||||
I1 => res_reg_n_99,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_89,
|
||||
I3 => res_reg_n_97,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_101,
|
||||
O => \M_AXIS_TDATA[4]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[5]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[6]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[5]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[5]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[5]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[5]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -642,22 +670,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_86,
|
||||
I0 => res_reg_n_94,
|
||||
I1 => res_reg_n_98,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_88,
|
||||
I3 => res_reg_n_96,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_100,
|
||||
O => \M_AXIS_TDATA[5]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[6]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[7]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[6]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[6]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[6]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[6]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -665,22 +693,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_85,
|
||||
I0 => res_reg_n_93,
|
||||
I1 => res_reg_n_97,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_87,
|
||||
I3 => res_reg_n_95,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_99,
|
||||
O => \M_AXIS_TDATA[6]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[7]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[8]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[7]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[7]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[7]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[7]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -688,22 +716,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_84,
|
||||
I0 => res_reg_n_92,
|
||||
I1 => res_reg_n_96,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_86,
|
||||
I3 => res_reg_n_94,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_98,
|
||||
O => \M_AXIS_TDATA[7]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[8]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[9]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[8]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[8]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[8]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[8]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -711,22 +739,22 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_83,
|
||||
I0 => res_reg_n_91,
|
||||
I1 => res_reg_n_95,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_85,
|
||||
I3 => res_reg_n_93,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_97,
|
||||
O => \M_AXIS_TDATA[8]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[9]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"AC"
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => \M_AXIS_TDATA[10]_i_2_n_0\,
|
||||
I1 => \M_AXIS_TDATA[9]_i_2_n_0\,
|
||||
I2 => shift_sig(0),
|
||||
I1 => shift_sig(0),
|
||||
I2 => \M_AXIS_TDATA[9]_i_2_n_0\,
|
||||
O => \M_AXIS_TDATA[9]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[9]_i_2\: unisim.vcomponents.LUT6
|
||||
@@ -734,10 +762,10 @@ begin
|
||||
INIT => X"AFA0CFCFAFA0C0C0"
|
||||
)
|
||||
port map (
|
||||
I0 => res_reg_n_82,
|
||||
I0 => res_reg_n_90,
|
||||
I1 => res_reg_n_94,
|
||||
I2 => shift_sig(1),
|
||||
I3 => res_reg_n_84,
|
||||
I3 => res_reg_n_92,
|
||||
I4 => shift_sig(2),
|
||||
I5 => res_reg_n_96,
|
||||
O => \M_AXIS_TDATA[9]_i_2_n_0\
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Nov 22 17:45:19 2024
|
||||
// Date : Tue Nov 26 14:45:05 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Fri Nov 22 17:45:19 2024
|
||||
-- Date : Tue Nov 26 14:45:05 2024
|
||||
-- Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.vhdl
|
||||
|
||||
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732293808"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732293808"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732293808"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732293808"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732628584"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732628584"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732628584"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732628584"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_f60c.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Nov 22 17:43:28 2024" VIVADOVERSION="2023.1">
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Nov 26 14:43:03 2024" VIVADOVERSION="2023.1">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="bd_f60c" PACKAGE="clg400" SPEEDGRADE="-1"/>
|
||||
|
||||
|
||||
+4
-4
@@ -1046,7 +1046,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:24 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:00 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1065,7 +1065,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:25 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:01 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1096,7 +1096,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:25 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:01 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1116,7 +1116,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:25 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:00 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:27 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:02 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-4
@@ -29,7 +29,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -49,7 +49,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -89,7 +89,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:28 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:03 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
BIN
Binary file not shown.
+5
-5
@@ -904,7 +904,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:23 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:00 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -922,7 +922,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Wed Nov 20 15:57:53 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 11:50:09 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -958,7 +958,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:46 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:15 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -977,7 +977,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:23 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:00 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -1030,7 +1030,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Nov 22 16:43:23 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Nov 26 13:43:00 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+66403
-66403
File diff suppressed because it is too large
Load Diff
+97400
-97400
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Nov 22 17:43:22 2024
|
||||
--Date : Tue Nov 26 14:42:59 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
|
||||
Binary file not shown.
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Nov 22 17:43:22 2024
|
||||
--Date : Tue Nov 26 14:42:59 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
|
||||
+3
-3
@@ -301,7 +301,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>631f893c</spirit:value>
|
||||
<spirit:value>f3a26ecd</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -314,7 +314,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>631f893c</spirit:value>
|
||||
<spirit:value>f3a26ecd</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -855,7 +855,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-11-22T16:42:28Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2024-11-26T11:51:57Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
@@ -0,0 +1,490 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../es-milestone3.gen/sources_1/bd/af_sim",
|
||||
"name": "af_sim",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
"axis_audio_master_si_0": "",
|
||||
"axis_audio_mono2ster_0": "",
|
||||
"axis_audio_stereo2mo_0": "",
|
||||
"axis_audio_slave_sim_0": "",
|
||||
"axis_prog_audio_filt_0": ""
|
||||
},
|
||||
"components": {
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "af_sim_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\af_sim_clk_rst_generator_0_0\\af_sim_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0",
|
||||
"parameters": {
|
||||
"CLOCK_PERIOD": {
|
||||
"value": "8000"
|
||||
},
|
||||
"HAS_CLK_INPUT": {
|
||||
"value": "false"
|
||||
},
|
||||
"HAS_RESET_INPUT": {
|
||||
"value": "false"
|
||||
},
|
||||
"HAS_STOP_INPUT": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_master_si_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_master_simmodel:1.0",
|
||||
"xci_name": "af_sim_axis_audio_master_si_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_master_si_0_0\\af_sim_axis_audio_master_si_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_master_si_0",
|
||||
"parameters": {
|
||||
"CLOCK_CYCLES_PER_SAMPLE": {
|
||||
"value": "5"
|
||||
},
|
||||
"FILE_NAME": {
|
||||
"value": "../../../../HaveANiceDay"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_mono2ster_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"xci_name": "af_sim_axis_audio_mono2ster_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_mono2ster_0_0\\af_sim_axis_audio_mono2ster_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_mono2ster_0"
|
||||
},
|
||||
"axis_audio_stereo2mo_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"xci_name": "af_sim_axis_audio_stereo2mo_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_stereo2mo_0_0\\af_sim_axis_audio_stereo2mo_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_stereo2mo_0"
|
||||
},
|
||||
"axis_audio_slave_sim_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_slave_simmodel:1.0",
|
||||
"xci_name": "af_sim_axis_audio_slave_sim_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_audio_slave_sim_0_0\\af_sim_axis_audio_slave_sim_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_slave_sim_0",
|
||||
"parameters": {
|
||||
"FILE_NAME": {
|
||||
"value": "../../../../sim_out"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_prog_audio_filt_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"xci_name": "af_sim_axis_prog_audio_filt_0_0",
|
||||
"xci_path": "ip\\af_sim_axis_prog_audio_filt_0_0\\af_sim_axis_prog_audio_filt_0_0.xci",
|
||||
"inst_hier_path": "axis_prog_audio_filt_0",
|
||||
"parameters": {
|
||||
"COEFF_0": {
|
||||
"value": "16"
|
||||
},
|
||||
"COEFF_1": {
|
||||
"value": "32"
|
||||
},
|
||||
"COEFF_2": {
|
||||
"value": "16"
|
||||
},
|
||||
"SHIFT": {
|
||||
"value": "6"
|
||||
}
|
||||
},
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_prog_audio_filter3",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ADDR_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
}
|
||||
},
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"port_maps": {
|
||||
"AWADDR": {
|
||||
"physical_name": "S_AXIL_AWADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "S_AXIL_AWVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "S_AXIL_AWREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "S_AXIL_WDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "S_AXIL_WSTRB",
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "S_AXIL_WVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "S_AXIL_WREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "S_AXIL_BRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "S_AXIL_BVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "S_AXIL_BREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "S_AXIL_ARADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "S_AXIL_ARVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "S_AXIL_ARREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "S_AXIL_RDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "S_AXIL_RRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "S_AXIL_RVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "S_AXIL_RREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"AXI_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "AXI_ARESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axis_audio_master_si_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_master_si_0/M_AXIS",
|
||||
"axis_audio_stereo2mo_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_audio_mono2ster_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_mono2ster_0/M_AXIS",
|
||||
"axis_audio_slave_sim_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_audio_stereo2mo_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_stereo2mo_0/M_AXIS",
|
||||
"axis_prog_audio_filt_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_prog_audio_filt_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_prog_audio_filt_0/M_AXIS",
|
||||
"axis_audio_mono2ster_0/S_AXIS"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"axis_audio_master_si_0_WAV_HEADER": {
|
||||
"ports": [
|
||||
"axis_audio_master_si_0/WAV_HEADER",
|
||||
"axis_audio_slave_sim_0/WAV_HEADER"
|
||||
]
|
||||
},
|
||||
"axis_audio_slave_sim_0_FINISHED": {
|
||||
"ports": [
|
||||
"axis_audio_slave_sim_0/FINISHED",
|
||||
"clk_rst_generator_0/stop_simulation"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_audio_master_si_0/ACLK",
|
||||
"axis_audio_stereo2mo_0/AXIS_ACLK",
|
||||
"axis_audio_mono2ster_0/AXIS_ACLK",
|
||||
"axis_audio_slave_sim_0/ACLK",
|
||||
"axis_prog_audio_filt_0/AXI_ACLK"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axis_audio_master_si_0/ARESETN",
|
||||
"axis_audio_slave_sim_0/ARESETN",
|
||||
"axis_prog_audio_filt_0/AXI_ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
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|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
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|
||||
"name": "vert_type",
|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
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|
||||
"name": "base_addr",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
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|
||||
"name": "high_param",
|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
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|
||||
"for": "node"
|
||||
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|
||||
{
|
||||
"abrv": "MI",
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
"abrv": "MV",
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||||
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||||
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|
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||||
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"type": "string",
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|
||||
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||||
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|
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"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
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|
||||
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|
||||
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|
||||
"abrv": "LT",
|
||||
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||||
"type": "string",
|
||||
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|
||||
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||||
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||||
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|
||||
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||||
"type": "string",
|
||||
"for": "node"
|
||||
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|
||||
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|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"abrv": "BC",
|
||||
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|
||||
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||||
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||||
"desc": "Parital Reference"
|
||||
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|
||||
{
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||||
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||||
"desc": "Variant"
|
||||
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|
||||
{
|
||||
"abrv": "PM",
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||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
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|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
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|
||||
{
|
||||
"abrv": "ACE",
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||||
"desc": "Excluded Assign Coordinate"
|
||||
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||||
{
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||||
"abrv": "APX",
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||||
"desc": "Boundary Aperture"
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||||
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||||
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|
||||
"abrv": "CIP",
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||||
"desc": "High level Processing System"
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||||
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||||
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|
||||
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|
||||
"V0": {
|
||||
"VM": "af_sim",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "af_sim",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
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||||
+111
@@ -0,0 +1,111 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_master_si_0_0",
|
||||
"cell_name": "axis_audio_master_si_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_master_simmodel:1.0",
|
||||
"ip_revision": "2",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_CYCLES_PER_SAMPLE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FILE_NAME": [ { "value": "../../../../HaveANiceDay", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_master_si_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_CYCLES_PER_SAMPLE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"FILE_NAME": [ { "value": "../../../../HaveANiceDay", "resolve_type": "generated", "usage": "all" } ]
|
||||
},
|
||||
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|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
},
|
||||
"runtime_parameters": {
|
||||
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|
||||
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|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"ACLK": [ { "direction": "in" } ],
|
||||
"ARESETN": [ { "direction": "in" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ],
|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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||||
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|
||||
"mode": "master",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
},
|
||||
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|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
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|
||||
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|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_mono2ster_0_0",
|
||||
"cell_name": "axis_audio_mono2ster_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_mono2ster_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXIS_ACLK": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+112
@@ -0,0 +1,112 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_slave_sim_0_0",
|
||||
"cell_name": "axis_audio_slave_sim_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_slave_simmodel:1.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"FILE_NAME": [ { "value": "../../../../sim_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"RANDOM_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_slave_sim_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"FILE_NAME": [ { "value": "../../../../sim_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"RANDOM_TREADY": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"ACLK": [ { "direction": "in" } ],
|
||||
"ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"FINISHED": [ { "direction": "out" } ],
|
||||
"WAV_HEADER": [ { "direction": "in", "size_left": "351", "size_right": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_axis_audio_stereo2mo_0_0",
|
||||
"cell_name": "axis_audio_stereo2mo_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_stereo2mo_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_axis_audio_stereo2mo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
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|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
|
||||
"AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
|
||||
"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXI_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "AXI_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXI_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"display_name": "S_AXIL",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x1000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+55
@@ -0,0 +1,55 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "af_sim_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "8000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "af_sim_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "8000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Interfaces View",
|
||||
"Default View_ScaleFactor":"1.43494",
|
||||
"Default View_TopLeft":"-250,-605",
|
||||
"Display-PortTypeOthers":"false",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_ExpandedHierarchyInLayout":"",
|
||||
"Interfaces View_Layout":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axis_audio_master_si_0 -pg 1 -lvl 2 -x 140 -y 60 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 780 -y 70 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 340 -y 60 -defaultsOSRD
|
||||
preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 980 -y 70 -defaultsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 560 -y 70 -defaultsOSRD
|
||||
preplace netloc axis_audio_master_si_0_WAV_HEADER 1 2 4 250J -40n NJ -40n NJ -40n 1080
|
||||
preplace netloc axis_audio_slave_sim_0_FINISHED 1 0 7 -240 -30n NJ -30n NJ -30n NJ -30n NJ -30n NJ -30n 1360
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 5 -10 -80n 260 -80n 540 -70n 830 -60n 1060
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 5 -20 -70n N -70n 530 -50n N -50n 1070
|
||||
preplace netloc axis_audio_master_si_0_M_AXIS 1 2 1 N 60
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 5 1 N 70
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 3 1 N 60
|
||||
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 4 1 N 70
|
||||
levelinfo -pg 1 0 20 140 340 560 780 980 1080
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1080 140
|
||||
",
|
||||
"Interfaces View_ScaleFactor":"1.39512",
|
||||
"Interfaces View_TopLeft":"32,-191",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 670 -y -160 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -130 -y -150 -defaultsOSRD
|
||||
preplace inst axis_audio_master_si_0 -pg 1 -lvl 2 -x 120 -y -150 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 940 -y -130 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 370 -y -150 -defaultsOSRD
|
||||
preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 1230 -y -140 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 5 -10 -80 260 -80 540 -70 830 -60 1050
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 5 -20 -70 N -70 530 -50 N -50 1060
|
||||
preplace netloc axis_audio_master_si_0_WAV_HEADER 1 2 4 250J -40 NJ -40 NJ -40 1070
|
||||
preplace netloc axis_audio_slave_sim_0_FINISHED 1 0 7 -240 -30 NJ -30 NJ -30 NJ -30 NJ -30 NJ -30 1360
|
||||
levelinfo -pg 1 -260 -130 120 370 670 940 1230 1380
|
||||
pagesize -pg 1 -db -bbox -sgen -260 -380 1380 350
|
||||
"
|
||||
}
|
||||
0
|
||||
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.42004",
|
||||
"Default View_TopLeft":"251,-182",
|
||||
"Default View_TopLeft":"251,-181",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
@@ -23,8 +23,8 @@ preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 940 -y 110 -defaultsOSRD
|
||||
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1170 -y 130 -defaultsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 640 -y -110 -defaultsOSRD
|
||||
preplace netloc clk_1 1 0 1 -220 -40n
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 500 0 820 180 1050
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 510 -20 830
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 480 0 800 180 1050
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 490 -20 810
|
||||
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 1060
|
||||
preplace netloc resez_1 1 0 1 N 0
|
||||
preplace netloc zybo_audio_0_bclk 1 5 1 1290 140n
|
||||
@@ -33,10 +33,10 @@ preplace netloc zybo_audio_0_mute 1 5 1 1290 10n
|
||||
preplace netloc zybo_audio_0_pb_dat 1 5 1 1300 40n
|
||||
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1280 180n
|
||||
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1320 190n
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 480 -210 NJ
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 460 -210 NJ
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 N 110
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 490 -200 770J
|
||||
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 810 -170n
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 470 -200 790J
|
||||
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 790 -170n
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1280
|
||||
preplace netloc zybo_audio_0_i2c 1 5 1 N 80
|
||||
levelinfo -pg 1 -240 -20 320 640 940 1170 1340
|
||||
|
||||
@@ -61,20 +61,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="6"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="20"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="2"/>
|
||||
<Option Name="WTModelSimExportSim" Val="2"/>
|
||||
<Option Name="WTQuestaExportSim" Val="2"/>
|
||||
<Option Name="WTXSimExportSim" Val="8"/>
|
||||
<Option Name="WTModelSimExportSim" Val="8"/>
|
||||
<Option Name="WTQuestaExportSim" Val="8"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="2"/>
|
||||
<Option Name="WTRivieraExportSim" Val="2"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="2"/>
|
||||
<Option Name="WTVcsExportSim" Val="8"/>
|
||||
<Option Name="WTRivieraExportSim" Val="8"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="8"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -102,20 +102,19 @@
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
|
||||
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
|
||||
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -123,6 +122,18 @@
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/af_sim/af_sim.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/af_sim/hdl/af_sim_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
@@ -146,14 +157,14 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/design_1_wrapper_behav.wcfg">
|
||||
<File Path="$PPRDIR/af_sim_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopModule" Val="af_sim_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
@@ -165,6 +176,7 @@
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/design_1_wrapper_behav.wcfg"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/af_sim_wrapper_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
|
||||
Binary file not shown.
@@ -62,7 +62,7 @@ architecture rtl of axis_prog_audio_filter3 is
|
||||
signal c0 : signed( 7 downto 0) := to_signed(COEFF_0,8);
|
||||
signal c1 : signed( 7 downto 0) := to_signed(COEFF_1,8);
|
||||
signal c2 : signed( 7 downto 0) := to_signed(COEFF_2,8);
|
||||
signal shift_sig : signed( 2 downto 0) := to_signed(SHIFT,3);
|
||||
signal shift_sig : unsigned( 2 downto 0) := to_unsigned(SHIFT,3);
|
||||
|
||||
type T_STATE is (IDLE, CALC);
|
||||
signal state : T_STATE := IDLE;
|
||||
@@ -130,7 +130,7 @@ begin
|
||||
c0 <= to_signed(COEFF_0,8);
|
||||
c1 <= to_signed(COEFF_1,8);
|
||||
c2 <= to_signed(COEFF_2,8);
|
||||
shift_sig <= to_signed(SHIFT,3);
|
||||
shift_sig <= to_unsigned(SHIFT,3);
|
||||
ip_active <= '1';
|
||||
else
|
||||
-- Lesezugriff
|
||||
@@ -172,7 +172,7 @@ begin
|
||||
c2 <= signed(S_AXIL_WDATA(23 downto 16));
|
||||
end if;
|
||||
if S_AXIL_WSTRB(3) = '1' then
|
||||
shift_sig <= signed(S_AXIL_WDATA(26 downto 24));
|
||||
shift_sig <= unsigned(S_AXIL_WDATA(26 downto 24));
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
Reference in New Issue
Block a user