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M1: Mealy-Ausgänge mit Registern

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This commit is contained in:
Matthias Biermann
2024-10-17 22:04:42 +02:00
parent e43074233f
commit 60548dd462
1 changed files with 31 additions and 16 deletions
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Milestone1/sources/spi_transmitter.vhd
+31 -16
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@@ -111,6 +111,13 @@ begin
-- Interne Signale fuer Rechenwerk
signal state : state_t := S_START;
signal state_next : state_t;
-- Interne Signale fuer "Mealy"- Ausgaenge
signal RegDataLd_next : std_logic := '0';
signal RegDataShift_next : std_logic := '0';
signal cntAddrEn_next : std_logic := '0';
signal CntBitsEn_next : std_logic := '0';
signal cntAddrRst_next : std_logic := '0';
begin
-- Kontrollbits
CtrlBits <= data(9 downto 8);
@@ -119,12 +126,12 @@ begin
Transition: process(Reset, CntSckTc, CntBitsTC, CtrlBits)
begin
-- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
state_next <= S_ERROR;
RegDataLd <= '0';
RegDataShift <= '0';
cntAddrEn <= '0';
CntBitsEn <= '0';
cntAddrRst <= '0';
state_next <= S_ERROR;
RegDataLd_next <= '0';
RegDataShift_next <= '0';
cntAddrEn_next <= '0';
CntBitsEn_next <= '0';
cntAddrRst_next <= '0';
-- Berechnung des Folgezustandes und der Mealy-Ausgaenge
case state is
@@ -133,7 +140,7 @@ begin
state_next <= S_START;
elsif CntSckTc = '1' then
state_next <= S_STEP_1;
RegDataLd <= '1';
RegDataLd_next <= '1';
elsif CntSckTc = '0' then
state_next <= S_START;
end if;
@@ -158,7 +165,7 @@ begin
state_next <= S_START;
elsif CntSckTc = '1' then
state_next <= S_STEP_4;
CntBitsEn <= '1';
CntBitsEn_next <= '1';
elsif CntSckTc = '0' then
state_next <= S_STEP_3;
end if;
@@ -169,16 +176,16 @@ begin
state_next <= S_STEP_4;
elsif CntSckTc = '1' and CntBitsTC = '0' then
state_next <= S_STEP_1;
RegDataShift <= '1';
RegDataShift_next <= '1';
elsif CntSckTc = '1' and CntBitsTC = '1' then
if CtrlBits = "10" then
state_next <= S_DEAD_END;
elsif CtrlBits = "00" then
state_next <= S_START;
cntAddrEn <= '1';
cntAddrEn_next <= '1';
elsif CtrlBits = "11" or CtrlBits = "01" then
state_next <= S_START;
cntAddrRst <= '1';
cntAddrRst_next <= '1';
end if;
end if;
when S_DEAD_END =>
@@ -192,20 +199,28 @@ begin
state_next <= S_START;
else
state_next <= S_ERROR;
RegDataLd <= 'X';
RegDataShift <= 'X';
cntAddrEn <= 'X';
RegDataLd_next <= 'X';
RegDataShift_next <= 'X';
cntAddrEn_next <= 'X';
end if;
end case;
end process;
-- Register fuer Zustand und Moore-Ausgaenge
-- Register fuer Zustand und Ausgaenge
Reg: process
begin
wait until rising_edge(clk);
-- Zustandswechsel
state <= state_next;
-- Berechnung der Moore-Ausgaenge
-- Ausgeange, welche abhaengig von Zustand und Eingaengen sind
RegDataLd <= RegDataLd_next;
RegDataShift <= RegDataShift_next;
cntAddrEn <= cntAddrEn_next;
CntBitsEn <= CntBitsEn_next;
cntAddrRst <= cntAddrRst_next;
-- Berechnung der Moore-Ausgaenge, die nur vom Zustand abhaengen
-- Default-Werte
ssel <= 'X';
sck <= 'X';