M1: Einfache Testbench für spi_transmitter

This commit is contained in:
Matthias Biermann
2024-10-21 00:48:18 +02:00
parent 5d6d85a198
commit 818f9b1333
3 changed files with 120 additions and 8 deletions
+3 -8
View File
@@ -67,10 +67,10 @@ begin
if CntBitsRst = '1' then
cntVal := to_unsigned(0, 3);
elsif CntBitsEn = '1' then
cntVal := cntVal - 1;
cntVal := cntVal + 1;
end if;
if cntVal = 0 then
if cntVal = 7 then
CntBitsTC <= '1';
else
CntBitsTC <= '0';
@@ -83,7 +83,7 @@ begin
begin
wait until rising_edge(clk);
if RegDataLd = '1' then
Q := data; -- laden
Q := s_data; -- laden
elsif RegDataEn = '1' then
Q := Q(6 downto 0) & '0'; -- linksschieben
end if;
@@ -135,7 +135,6 @@ begin
state_next <= S_IDLE;
elsif CntSckTc = '1' then
state_next <= S_STEP_4;
CntBitsEn <= '1';
elsif CntSckTc = '0' then
state_next <= S_STEP_3;
end if;
@@ -200,10 +199,6 @@ begin
ssel <= '0';
sck <= '0';
s_ready <= '0';
when S_DEAD_END =>
ssel <= '1';
sck <= '0';
s_ready <= '0';
when S_ERROR =>
ssel <= 'X';
sck <= 'X';
+73
View File
@@ -0,0 +1,73 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_transmitter_tb is
end;
architecture rtl of spi_transmitter_tb is
constant EXT_CLOCK_FREQ : integer := 125000000;
constant SCK_FREQ : integer := 1000000;
constant AW : POSITIVE := 8;
constant clk_half_period : time := 1 sec / EXT_CLOCK_FREQ / 2;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal s_data : std_logic_vector(7 downto 0) := (others=>'0') ;
signal s_valid : std_logic := '0';
signal s_ready : std_logic;
signal sck : std_logic;
signal mosi : std_logic;
signal ssel : std_logic;
begin
clk_proc: process (clk)
begin
clk <= not clk after clk_half_period;
end process;
stim: process
begin
reset <= '0' after 100 * clk_half_period;
wait until reset = '0';
wait until rising_edge(clk);
s_data <= x"48";
s_valid <= '1';
loop
wait until rising_edge(clk);
if s_ready = '1' then
s_valid <= '0';
s_data <= (others=>'0');
exit;
end if;
end loop;
wait;
end process;
dut: entity work.spi_transmitter
generic map (
AW => AW,
CLKDIV => EXT_CLOCK_FREQ / (SCK_FREQ * 4)
)
port map (
clk => clk,
reset => reset,
s_data => s_data,
s_valid => s_valid,
s_ready => s_ready,
mosi => mosi,
sck => sck,
ssel => ssel
);
end architecture;
@@ -0,0 +1,44 @@
# work-Bibliothek erzeugen, falls nicht schon vorhanden
if { [file exists work] == 0} {
vlib work
}
# Benoetigte Dateien uebersetzen
vcom -work work spi_transmitter.vhd
vcom -work work spi_transmitter_tb.vhd
# Simulator starten
vsim -voptargs=+acc spi_transmitter_tb
# Breite der Namensspalte
configure wave -namecolwidth 128
configure wave -datasetprefix 0
configure wave -signalnamewidth 1
configure wave -namecolwidth 154
configure wave -valuecolwidth 100
set NumericStdNoWarnings 1
add wave -divider "Externe Signale"
add wave -noupdate /spi_transmitter_tb/clk
add wave -noupdate /spi_transmitter_tb/reset
add wave -noupdate /spi_transmitter_tb/s_data
add wave -noupdate /spi_transmitter_tb/s_valid
add wave -noupdate /spi_transmitter_tb/s_ready
add wave -noupdate /spi_transmitter_tb/sck
add wave -noupdate /spi_transmitter_tb/mosi
add wave -noupdate /spi_transmitter_tb/ssel
add wave -divider "Interne Signale"
add wave -noupdate /spi_transmitter_tb/dut/state
add wave -noupdate /spi_transmitter_tb/dut/state_next
add wave -noupdate /spi_transmitter_tb/dut/CntSckTc
add wave -noupdate /spi_transmitter_tb/dut/CntSckRst
add wave -noupdate /spi_transmitter_tb/dut/RegDataLd
add wave -noupdate /spi_transmitter_tb/dut/RegDataEn
add wave -noupdate /spi_transmitter_tb/dut/CntBitsEn
add wave -noupdate /spi_transmitter_tb/dut/CntBitsTC
add wave -noupdate /spi_transmitter_tb/dut/CntBitsRst
add wave -noupdate -label CntBits /spi_transmitter_tb/dut/CntBits/cntVal
add wave -noupdate -label RegDataQ /spi_transmitter_tb/dut/RegData/Q
run 1000 us