M1: Einfache Testbench für spi_transmitter
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@@ -67,10 +67,10 @@ begin
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if CntBitsRst = '1' then
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cntVal := to_unsigned(0, 3);
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elsif CntBitsEn = '1' then
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cntVal := cntVal - 1;
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cntVal := cntVal + 1;
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end if;
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if cntVal = 0 then
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if cntVal = 7 then
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CntBitsTC <= '1';
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else
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CntBitsTC <= '0';
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@@ -83,7 +83,7 @@ begin
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begin
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wait until rising_edge(clk);
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if RegDataLd = '1' then
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Q := data; -- laden
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Q := s_data; -- laden
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elsif RegDataEn = '1' then
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Q := Q(6 downto 0) & '0'; -- linksschieben
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end if;
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@@ -135,7 +135,6 @@ begin
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state_next <= S_IDLE;
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elsif CntSckTc = '1' then
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state_next <= S_STEP_4;
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CntBitsEn <= '1';
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elsif CntSckTc = '0' then
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state_next <= S_STEP_3;
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end if;
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@@ -200,10 +199,6 @@ begin
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ssel <= '0';
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sck <= '0';
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s_ready <= '0';
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when S_DEAD_END =>
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ssel <= '1';
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sck <= '0';
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s_ready <= '0';
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when S_ERROR =>
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ssel <= 'X';
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sck <= 'X';
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@@ -0,0 +1,73 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity spi_transmitter_tb is
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end;
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architecture rtl of spi_transmitter_tb is
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constant EXT_CLOCK_FREQ : integer := 125000000;
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constant SCK_FREQ : integer := 1000000;
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constant AW : POSITIVE := 8;
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constant clk_half_period : time := 1 sec / EXT_CLOCK_FREQ / 2;
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal s_data : std_logic_vector(7 downto 0) := (others=>'0') ;
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signal s_valid : std_logic := '0';
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signal s_ready : std_logic;
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signal sck : std_logic;
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signal mosi : std_logic;
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signal ssel : std_logic;
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begin
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clk_proc: process (clk)
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begin
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clk <= not clk after clk_half_period;
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end process;
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stim: process
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begin
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reset <= '0' after 100 * clk_half_period;
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wait until reset = '0';
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wait until rising_edge(clk);
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s_data <= x"48";
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s_valid <= '1';
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loop
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wait until rising_edge(clk);
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if s_ready = '1' then
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s_valid <= '0';
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s_data <= (others=>'0');
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exit;
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end if;
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end loop;
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wait;
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end process;
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dut: entity work.spi_transmitter
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generic map (
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AW => AW,
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CLKDIV => EXT_CLOCK_FREQ / (SCK_FREQ * 4)
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)
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port map (
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clk => clk,
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reset => reset,
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s_data => s_data,
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s_valid => s_valid,
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s_ready => s_ready,
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mosi => mosi,
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sck => sck,
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ssel => ssel
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);
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end architecture;
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@@ -0,0 +1,44 @@
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# work-Bibliothek erzeugen, falls nicht schon vorhanden
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if { [file exists work] == 0} {
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vlib work
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}
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# Benoetigte Dateien uebersetzen
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vcom -work work spi_transmitter.vhd
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vcom -work work spi_transmitter_tb.vhd
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# Simulator starten
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vsim -voptargs=+acc spi_transmitter_tb
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# Breite der Namensspalte
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configure wave -namecolwidth 128
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configure wave -datasetprefix 0
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configure wave -signalnamewidth 1
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configure wave -namecolwidth 154
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configure wave -valuecolwidth 100
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set NumericStdNoWarnings 1
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add wave -divider "Externe Signale"
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add wave -noupdate /spi_transmitter_tb/clk
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add wave -noupdate /spi_transmitter_tb/reset
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add wave -noupdate /spi_transmitter_tb/s_data
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add wave -noupdate /spi_transmitter_tb/s_valid
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add wave -noupdate /spi_transmitter_tb/s_ready
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add wave -noupdate /spi_transmitter_tb/sck
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add wave -noupdate /spi_transmitter_tb/mosi
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add wave -noupdate /spi_transmitter_tb/ssel
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add wave -divider "Interne Signale"
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add wave -noupdate /spi_transmitter_tb/dut/state
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add wave -noupdate /spi_transmitter_tb/dut/state_next
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add wave -noupdate /spi_transmitter_tb/dut/CntSckTc
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add wave -noupdate /spi_transmitter_tb/dut/CntSckRst
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add wave -noupdate /spi_transmitter_tb/dut/RegDataLd
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add wave -noupdate /spi_transmitter_tb/dut/RegDataEn
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add wave -noupdate /spi_transmitter_tb/dut/CntBitsEn
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add wave -noupdate /spi_transmitter_tb/dut/CntBitsTC
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add wave -noupdate /spi_transmitter_tb/dut/CntBitsRst
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add wave -noupdate -label CntBits /spi_transmitter_tb/dut/CntBits/cntVal
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add wave -noupdate -label RegDataQ /spi_transmitter_tb/dut/RegData/Q
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run 1000 us
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