Milestone 2 ungetestet abgeschlossn + Audiodateien
This commit is contained in:
Sebastian Meyer
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+203
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
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"type": "string",
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"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
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||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "design_1_sim",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "design_1_sim",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1_sim" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1730144234"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1730144235"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1730144234"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730144235"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1_sim.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1_sim.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_sim_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_sim.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_sim.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_sim.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1_sim.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+10
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||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+19
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||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 20:37:14 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_sim_wrapper.bd
|
||||
//Design : design_1_sim_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_1_sim_wrapper
|
||||
();
|
||||
|
||||
|
||||
design_1_sim design_1_sim_i
|
||||
();
|
||||
endmodule
|
||||
+452
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|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Oct 28 20:37:14 2024" VIVADOVERSION="2023.1">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.1" DEVICE="7z020" NAME="design_1_sim" PACKAGE="clg400" SPEEDGRADE="-1"/>
|
||||
|
||||
<EXTERNALPORTS/>
|
||||
|
||||
<EXTERNALINTERFACES/>
|
||||
|
||||
<MODULES>
|
||||
<MODULE COREREVISION="1" FULLNAME="/axis_audio_bitcrusher_0" HWVERSION="1.0" INSTANCE="axis_audio_bitcrusher_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_bitcrusher" VLNV="xilinx.com:module_ref:axis_audio_bitcrusher:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="BIT_REDUCTION" VALUE="14"/>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_bitcrusher_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="AXIS_ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TLAST" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TLAST" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_bitcrusher_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TLAST" PHYSICAL="M_AXIS_TLAST"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TLAST" PHYSICAL="S_AXIS_TLAST"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="2" FULLNAME="/axis_audio_master_si_0" HWVERSION="1.0" INSTANCE="axis_audio_master_si_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_master_simmodel" VLNV="xilinx.com:user:axis_audio_master_simmodel:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="CLOCK_CYCLES_PER_SAMPLE" VALUE="3"/>
|
||||
<PARAMETER NAME="FILE_NAME" VALUE="../../../../HaveANiceDay"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_master_si_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="WAV_HEADER"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="3" FULLNAME="/axis_audio_mono2ster_0" HWVERSION="1.0" INSTANCE="axis_audio_mono2ster_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_mono2stereo" VLNV="xilinx.com:user:axis_audio_mono2stereo:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_mono2ster_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_bitcrusher_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="18" FULLNAME="/axis_audio_slave_sim_0" HWVERSION="1.0" INSTANCE="axis_audio_slave_sim_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_slave_simmodel" VLNV="xilinx.com:user:axis_audio_slave_simmodel:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="FILE_NAME" VALUE="../../../../tst_out"/>
|
||||
<PARAMETER NAME="RANDOM_TREADY" VALUE="true"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_slave_sim_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="FINISHED" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="stop_simulation"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="WAV_HEADER"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="4" FULLNAME="/axis_audio_stereo2mo_0" HWVERSION="1.0" INSTANCE="axis_audio_stereo2mo_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_stereo2mono" VLNV="xilinx.com:user:axis_audio_stereo2mono:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_axis_audio_stereo2mo_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TVALID">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="S_AXIS_TVALID"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TDATA">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="S_AXIS_TDATA"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_bitcrusher_0_S_AXIS_TREADY">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="S_AXIS_TREADY"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
|
||||
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
|
||||
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
|
||||
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
|
||||
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
|
||||
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
|
||||
<PARAMETER NAME="PHASE" VALUE="0.0"/>
|
||||
<PARAMETER NAME="CLK_DOMAIN"/>
|
||||
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
|
||||
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
|
||||
<PORTMAPS>
|
||||
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
|
||||
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
|
||||
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
|
||||
</PORTMAPS>
|
||||
</BUSINTERFACE>
|
||||
</BUSINTERFACES>
|
||||
</MODULE>
|
||||
<MODULE COREREVISION="7" FULLNAME="/clk_rst_generator_0" HWVERSION="1.0" INSTANCE="clk_rst_generator_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_rst_generator" VLNV="wg:user:clk_rst_generator:1.0">
|
||||
<DOCUMENTS/>
|
||||
<PARAMETERS>
|
||||
<PARAMETER NAME="CLOCK_PERIOD" VALUE="8000"/>
|
||||
<PARAMETER NAME="HAS_CLK_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="HAS_RESET_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="HAS_STOP_INPUT" VALUE="true"/>
|
||||
<PARAMETER NAME="Component_Name" VALUE="design_1_sim_clk_rst_generator_0_0"/>
|
||||
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
|
||||
</PARAMETERS>
|
||||
<PORTS>
|
||||
<PORT DIR="I" NAME="clk_in" SIGIS="undef"/>
|
||||
<PORT DIR="I" NAME="rst_in" SIGIS="undef"/>
|
||||
<PORT DIR="O" NAME="clk" SIGIS="undef" SIGNAME="clk_rst_generator_0_clk">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="AXIS_ACLK"/>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ACLK"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="O" NAME="rst_n" SIGIS="undef" SIGNAME="clk_rst_generator_0_rst_n">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ARESETN"/>
|
||||
<CONNECTION INSTANCE="axis_audio_bitcrusher_0" PORT="AXIS_ARESETN"/>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ARESETN"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
<PORT DIR="I" NAME="stop_simulation" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
|
||||
<CONNECTIONS>
|
||||
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="FINISHED"/>
|
||||
</CONNECTIONS>
|
||||
</PORT>
|
||||
</PORTS>
|
||||
<BUSINTERFACES/>
|
||||
</MODULE>
|
||||
</MODULES>
|
||||
|
||||
</EDKSYSTEM>
|
||||
+706
@@ -0,0 +1,706 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_sim_axis_audio_bitcrusher_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
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||||
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||||
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||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
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||||
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||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
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||||
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||||
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||||
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||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
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||||
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||||
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||||
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||||
</spirit:parameter>
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||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
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||||
<spirit:vendorExtensions>
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||||
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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||||
</spirit:vendorExtensions>
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||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
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||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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||||
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||||
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||||
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||||
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||||
<spirit:model>
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||||
<spirit:views>
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||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_bitcrusher</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5912d307</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
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||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
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||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
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||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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||||
<spirit:modelName>design_1_sim_axis_audio_bitcrusher_0_0</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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||||
<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Mon Oct 28 19:06:27 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
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||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:5912d307</spirit:value>
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||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
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||||
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wire>
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wire>
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
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<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>BIT_REDUCTION</spirit:name>
|
||||
<spirit:displayName>Bit Reduction</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIT_REDUCTION">14</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
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</spirit:choices>
|
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<spirit:fileSets>
|
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<spirit:fileSet>
|
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<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_sim_axis_audio_bitcrusher_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
|
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</spirit:fileSet>
|
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</spirit:fileSets>
|
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<spirit:description>xilinx.com:module_ref:axis_audio_bitcrusher:1.0</spirit:description>
|
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<spirit:parameters>
|
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<spirit:parameter>
|
||||
<spirit:name>BIT_REDUCTION</spirit:name>
|
||||
<spirit:displayName>Bit Reduction</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BIT_REDUCTION">14</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_sim_axis_audio_bitcrusher_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
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||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_audio_bitcrusher_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
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||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
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|
||||
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||||
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||||
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+110
@@ -0,0 +1,110 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:axis_audio_bitcrusher:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_sim_axis_audio_bitcrusher_0_0 (
|
||||
AXIS_ACLK,
|
||||
AXIS_ARESETN,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *)
|
||||
input wire AXIS_ACLK;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST" *)
|
||||
input wire AXIS_ARESETN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire S_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [15 : 0] S_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
|
||||
input wire S_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire S_AXIS_TREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire M_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [15 : 0] M_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
|
||||
output wire M_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire M_AXIS_TREADY;
|
||||
|
||||
axis_audio_bitcrusher #(
|
||||
.BIT_REDUCTION(14),
|
||||
.HAS_LAST(1'B0)
|
||||
) inst (
|
||||
.AXIS_ACLK(AXIS_ACLK),
|
||||
.AXIS_ARESETN(AXIS_ARESETN),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(S_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(S_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY)
|
||||
);
|
||||
endmodule
|
||||
+506
@@ -0,0 +1,506 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_sim_axis_audio_master_si_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">M_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
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|
||||
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||||
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<spirit:port>
|
||||
<spirit:name>ACLK</spirit:name>
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<spirit:name>ARESETN</spirit:name>
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||||
<spirit:port>
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||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
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||||
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|
||||
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|
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<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
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|
||||
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||||
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</spirit:wire>
|
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</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
|
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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||||
<spirit:name>WAV_HEADER</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">351</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_CYCLES_PER_SAMPLE</spirit:name>
|
||||
<spirit:displayName>Clock Cycles Per Sample</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_CYCLES_PER_SAMPLE">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="string">
|
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<spirit:name>FILE_NAME</spirit:name>
|
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<spirit:displayName>File Name</spirit:displayName>
|
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<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FILE_NAME">../../../../HaveANiceDay</spirit:value>
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</spirit:modelParameter>
|
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</spirit:modelParameters>
|
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</spirit:model>
|
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<spirit:choices>
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<spirit:choice>
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<spirit:name>choice_list_9d8b0d81</spirit:name>
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>../../ipshared/45f9/wav_pkg.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>../../ipshared/45f9/axis_audio_master_simmodel.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>sim/design_1_sim_axis_audio_master_si_0_0.vhd</spirit:name>
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<spirit:parameter>
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<spirit:displayName>Clock Cycles Per Sample</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_CYCLES_PER_SAMPLE">3</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FILE_NAME</spirit:name>
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<spirit:displayName>File Name</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FILE_NAME">../../../../HaveANiceDay</spirit:value>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_sim_axis_audio_master_si_0_0</spirit:value>
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</spirit:parameter>
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<xilinx:displayName>axis_audio_master_simmodel</xilinx:displayName>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:coreRevision>2</xilinx:coreRevision>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@3e522cdf_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_master_simmodel/axis_audio_master_simmodel.srcs/sources_1/new</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@74a9e3b0_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_master_simmodel/axis_audio_master_simmodel.srcs/sources_1/new</xilinx:tag>
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</xilinx:tags>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FILE_NAME" xilinx:valueSource="user"/>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
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</spirit:component>
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||||
+108
@@ -0,0 +1,108 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_master_simmodel:1.0
|
||||
-- IP Revision: 2
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_sim_axis_audio_master_si_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END design_1_sim_axis_audio_master_si_0_0;
|
||||
|
||||
ARCHITECTURE design_1_sim_axis_audio_master_si_0_0_arch OF design_1_sim_axis_audio_master_si_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sim_axis_audio_master_si_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_master_simmodel IS
|
||||
GENERIC (
|
||||
CLOCK_CYCLES_PER_SAMPLE : INTEGER;
|
||||
FILE_NAME : STRING
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_audio_master_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_master_simmodel
|
||||
GENERIC MAP (
|
||||
CLOCK_CYCLES_PER_SAMPLE => 3,
|
||||
FILE_NAME => "../../../../HaveANiceDay"
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
WAV_HEADER => WAV_HEADER
|
||||
);
|
||||
END design_1_sim_axis_audio_master_si_0_0_arch;
|
||||
+695
@@ -0,0 +1,695 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_sim_axis_audio_mono2ster_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>S_AXIS_TVALID</spirit:name>
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<spirit:port>
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||||
<spirit:name>S_AXIS_TDATA</spirit:name>
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||||
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<spirit:name>S_AXIS_TLAST</spirit:name>
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||||
<spirit:name>S_AXIS_TREADY</spirit:name>
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||||
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||||
<spirit:name>M_AXIS_TVALID</spirit:name>
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||||
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||||
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||||
<spirit:name>M_AXIS_TDATA</spirit:name>
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||||
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||||
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||||
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|
||||
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|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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||||
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||||
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|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c4329dc"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="dd41f636"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="7314069d"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_sim_axis_audio_mono2ster_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_sim_axis_audio_mono2ster_0_0;
|
||||
|
||||
ARCHITECTURE design_1_sim_axis_audio_mono2ster_0_0_arch OF design_1_sim_axis_audio_mono2ster_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sim_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_mono2stereo IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_mono2stereo;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_mono2stereo
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_sim_axis_audio_mono2ster_0_0_arch;
|
||||
+776
@@ -0,0 +1,776 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_sim_axis_audio_slave_sim_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>ACLK</spirit:name>
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<spirit:name>ARESETN</spirit:name>
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<spirit:port>
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<spirit:name>S_AXIS_TVALID</spirit:name>
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<spirit:port>
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<spirit:name>S_AXIS_TDATA</spirit:name>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
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|
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<spirit:name>FINISHED</spirit:name>
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<spirit:name>RANDOM_TREADY</spirit:name>
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</xilinx:tags>
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<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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</spirit:vendorExtensions>
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||||
</spirit:component>
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||||
+111
@@ -0,0 +1,111 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_slave_simmodel:1.0
|
||||
-- IP Revision: 18
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_sim_axis_audio_slave_sim_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END design_1_sim_axis_audio_slave_sim_0_0;
|
||||
|
||||
ARCHITECTURE design_1_sim_axis_audio_slave_sim_0_0_arch OF design_1_sim_axis_audio_slave_sim_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sim_axis_audio_slave_sim_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_slave_simmodel IS
|
||||
GENERIC (
|
||||
FILE_NAME : STRING;
|
||||
RANDOM_TREADY : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
FINISHED : OUT STD_LOGIC;
|
||||
WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_audio_slave_simmodel;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_slave_simmodel
|
||||
GENERIC MAP (
|
||||
FILE_NAME => "../../../../tst_out",
|
||||
RANDOM_TREADY => true
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
FINISHED => FINISHED,
|
||||
WAV_HEADER => WAV_HEADER
|
||||
);
|
||||
END design_1_sim_axis_audio_slave_sim_0_0_arch;
|
||||
+715
@@ -0,0 +1,715 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_sim_axis_audio_stereo2mo_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
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<xilinx:tag xilinx:name="ui.data.coregen.dd@63fad689_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3204f3cb_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@43b85df7_ARCHIVE_LOCATION">d:/netcase/Vorlesungen_Studis/ElektronischeSysteme_Studis/GIP/axis_audio_stereo2mono/axis_audio_stereo2mono.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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</xilinx:configElementInfos>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1a2f7743"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="71e811ad"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="b17a0555"/>
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</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_sim_axis_audio_stereo2mo_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_sim_axis_audio_stereo2mo_0_0;
|
||||
|
||||
ARCHITECTURE design_1_sim_axis_audio_stereo2mo_0_0_arch OF design_1_sim_axis_audio_stereo2mo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sim_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_stereo2mono IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_stereo2mono;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_stereo2mono
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_sim_axis_audio_stereo2mo_0_0_arch;
|
||||
+225
@@ -0,0 +1,225 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>wg</spirit:vendor>
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<spirit:library>customized_ip</spirit:library>
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<spirit:name>design_1_sim_clk_rst_generator_0_0</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:value>Mon Oct 28 19:06:26 UTC 2024</spirit:value>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>clk_in</spirit:name>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_sim_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">8000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_sim_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLOCK_PERIOD" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_sim_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_sim_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_sim_clk_rst_generator_0_0_arch OF design_1_sim_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_sim_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 8000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_sim_clk_rst_generator_0_0_arch;
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_audio_master_simmodel.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
----------------------------------------------------------
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.wav_pkg.all;
|
||||
|
||||
entity axis_audio_master_simmodel is
|
||||
generic
|
||||
(
|
||||
CLOCK_CYCLES_PER_SAMPLE : integer := 2083;
|
||||
FILE_NAME : string := string'("tst")
|
||||
);
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic;
|
||||
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
|
||||
WAV_HEADER : out std_logic_vector(44*8-1 downto 0)
|
||||
);
|
||||
|
||||
end entity axis_audio_master_simmodel;
|
||||
|
||||
|
||||
architecture sim of axis_audio_master_simmodel is
|
||||
|
||||
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal local_clk : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
|
||||
local_clk <= ACLK;
|
||||
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd <= r;
|
||||
end process;
|
||||
|
||||
|
||||
process
|
||||
variable file_num : integer := 0;
|
||||
variable num_samples : integer;
|
||||
variable sample : std_logic_vector(31 downto 0);
|
||||
|
||||
variable delay_cnt : integer;
|
||||
variable tvalid_cnt : integer := 31415;
|
||||
|
||||
file f : WAV_FILE_TYPE;
|
||||
variable header : WAV_HEADER_TYPE;
|
||||
variable file_status : file_open_status;
|
||||
variable ok : boolean;
|
||||
variable cyccnt : integer;
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
if (ARESETN = '0') then
|
||||
M_AXIS_TVALID <= '0';
|
||||
M_AXIS_TDATA <= (others=>'0');
|
||||
file_num := 0;
|
||||
tvalid_cnt := to_integer(rnd and x"0000001F");
|
||||
else
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
-- Start-Up delay
|
||||
for i in 0 to 100 loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
-- Create filename and try to open the file
|
||||
file_open ( file_status, f, FILE_NAME & ".wav", read_mode);
|
||||
|
||||
-- File open succeeded ?
|
||||
if file_status /= open_ok then
|
||||
assert false report "AXIS_AUDIO_MASTER_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
|
||||
else
|
||||
read_wav_header(ok,num_samples,header,f);
|
||||
|
||||
assert ok report "AXIS_AUDIO_MASTER_SIMMODEL: Input is not in WAV format." severity failure;
|
||||
|
||||
for i in 0 to 43 loop
|
||||
WAV_HEADER(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(header(i),8));
|
||||
end loop;
|
||||
if ok then
|
||||
for s in 0 to num_samples-1 loop -- sample loop
|
||||
M_AXIS_TDATA ( 7 downto 0) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TDATA (15 downto 8) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TDATA (23 downto 16) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TDATA (31 downto 24) <= std_logic_vector(to_unsigned(wavget8(f),8));
|
||||
M_AXIS_TVALID <= '1';
|
||||
-- wait until data has been acknowledged
|
||||
wait until rising_edge (local_clk);
|
||||
cyccnt := CLOCK_CYCLES_PER_SAMPLE;
|
||||
while M_AXIS_TREADY = '0' loop
|
||||
wait until rising_edge (local_clk);
|
||||
cyccnt := cyccnt - 1;
|
||||
end loop;
|
||||
M_AXIS_TVALID <= '0';
|
||||
while cyccnt > 0 loop
|
||||
wait until rising_edge (local_clk);
|
||||
cyccnt := cyccnt - 1;
|
||||
end loop;
|
||||
end loop; -- sample loop
|
||||
file_close(f);
|
||||
end if; -- if ok
|
||||
end if; -- if open_status ok
|
||||
|
||||
M_AXIS_TVALID <= '0';
|
||||
|
||||
-- wait until reset is activated
|
||||
while ARESETN = '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
|
||||
end sim;
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
package wav_pkg is
|
||||
|
||||
type WAV_FILE_TYPE is file of character;
|
||||
type WAV_HEADER_TYPE is array (0 to 43) of integer;
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE );
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer;
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
end;
|
||||
|
||||
package body wav_pkg is
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
write(f, character'val(value));
|
||||
end wavput8;
|
||||
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
for i in 0 to 43 loop
|
||||
wavput8(header(i),f);
|
||||
end loop;
|
||||
end write_wav_header;
|
||||
|
||||
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
|
||||
variable chr : character;
|
||||
begin
|
||||
read (f,chr);
|
||||
return character'pos(chr);
|
||||
end wavget8;
|
||||
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
variable chr : character;
|
||||
variable val : integer;
|
||||
begin
|
||||
success := true;
|
||||
for i in 0 to 43 loop
|
||||
header(i) := wavget8(f);
|
||||
end loop;
|
||||
numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
|
||||
|
||||
if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then -- check for 'RIFF'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then -- check for 'WAVE'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
end read_wav_header;
|
||||
|
||||
|
||||
end package body;
|
||||
|
||||
+51
@@ -0,0 +1,51 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- AXI Stream Audio Mono to Stereo
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
entity axis_audio_mono2stereo is
|
||||
generic
|
||||
(
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(15 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_audio_mono2stereo is
|
||||
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY;
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
|
||||
M_AXIS_TDATA (31 downto 16) <= S_AXIS_TDATA;
|
||||
M_AXIS_TDATA (15 downto 0) <= S_AXIS_TDATA;
|
||||
|
||||
end;
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- clk_rst_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_rst_generator is
|
||||
generic
|
||||
(
|
||||
CLOCK_PERIOD : integer := 10000;
|
||||
HAS_CLK_INPUT : boolean := true;
|
||||
HAS_RESET_INPUT : boolean := true;
|
||||
HAS_STOP_INPUT : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
clk_in : in std_logic := '1';
|
||||
rst_in : in std_logic := '0';
|
||||
|
||||
clk : out std_logic;
|
||||
rst_n : out std_logic;
|
||||
|
||||
stop_simulation : in std_logic := '0'
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of clk_rst_generator is
|
||||
|
||||
signal clk_sim : std_logic := '1';
|
||||
signal clk_in_sig : std_logic := '1';
|
||||
signal clk_sig : std_logic := '1';
|
||||
signal rst_sig : std_logic := '0';
|
||||
signal rst_in_sync : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk <= clk_sig;
|
||||
rst_n <= not rst_sig;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
clk_sig <= clk_in_sig and clk_sim;
|
||||
-- Dies ist kein gated Clock!
|
||||
-- Fuer die Synthese ist clk_sim konstant '1'
|
||||
-- somit wird die UND-Verknuepfung 'wegoptimiert'
|
||||
-- und was übrig bleibt, ist ein 'Draht'
|
||||
|
||||
-- synthesis translate_off
|
||||
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
-- synthesis translate_on
|
||||
|
||||
process (clk_in) begin
|
||||
clk_in_sig <= clk_in;
|
||||
-- synthesis translate_off
|
||||
clk_in_sig <= '1';
|
||||
-- synthesis translate_on
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- RESET GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
process
|
||||
variable rescnt : unsigned (6 downto 0) := (others=>'1');
|
||||
begin
|
||||
wait until rising_edge(clk_sig);
|
||||
|
||||
rst_in_sync <= rst_in;
|
||||
if rst_in_sync = '1' then
|
||||
rescnt := (others=>'1');
|
||||
end if;
|
||||
|
||||
if rescnt = 0 then
|
||||
rst_sig <= '0';
|
||||
else
|
||||
rescnt := rescnt - 1;
|
||||
rst_sig <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- STOP SIMULATION INPUT (simulation only)
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- synthesis translate_off
|
||||
process (stop_simulation) begin
|
||||
if stop_simulation = '1' then
|
||||
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
|
||||
end if;
|
||||
end process;
|
||||
-- synthesis translate_on
|
||||
|
||||
end rtl;
|
||||
+58
@@ -0,0 +1,58 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- AXI Stream Audio Stereo to Mono
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020/2021
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axis_audio_stereo2mono is
|
||||
generic
|
||||
(
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(15 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_audio_stereo2mono is
|
||||
signal m_valid_sig : std_logic := '0';
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
|
||||
|
||||
process begin
|
||||
wait until rising_edge(AXIS_ACLK);
|
||||
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
|
||||
M_AXIS_TDATA <= std_logic_vector(signed(S_AXIS_TDATA(31)&S_AXIS_TDATA(31 downto 17))+signed(S_AXIS_TDATA(15)&S_AXIS_TDATA(15 downto 1)));
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
m_valid_sig <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end;
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axis_audio_slave_simmodel.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
----------------------------------------------------------
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.wav_pkg.all;
|
||||
|
||||
entity axis_audio_slave_simmodel is
|
||||
generic
|
||||
(
|
||||
FILE_NAME : string := string'("tst_out");
|
||||
RANDOM_TREADY : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic;
|
||||
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
FINISHED : out std_logic;
|
||||
WAV_HEADER : in std_logic_vector(11*32-1 downto 0)
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
architecture sim of axis_audio_slave_simmodel is
|
||||
|
||||
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
|
||||
signal local_clk : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- synthesis translate_off
|
||||
-- translate off
|
||||
|
||||
local_clk <= ACLK;
|
||||
|
||||
-- uint32_t xorshift32() {
|
||||
-- static uint32_t x = 314159265;
|
||||
-- x ^= x << 13;
|
||||
-- x ^= x >> 17;
|
||||
-- x ^= x << 5;
|
||||
-- return x;
|
||||
-- }
|
||||
process
|
||||
variable r : unsigned (31 downto 0);
|
||||
begin
|
||||
wait until rising_edge(local_clk);
|
||||
r := rnd;
|
||||
r := r xor (r(18 downto 0)& x"000"&"0");
|
||||
r := r xor (x"0000"&"0"&r(31 downto 17));
|
||||
r := r xor (r(26 downto 0)& "00000");
|
||||
rnd <= r;
|
||||
end process;
|
||||
|
||||
|
||||
process
|
||||
variable num_samples : integer;
|
||||
|
||||
variable delay_cnt : integer;
|
||||
variable tready_cnt : integer := 31415;
|
||||
|
||||
file f : WAV_FILE_TYPE;
|
||||
variable header : WAV_HEADER_TYPE;
|
||||
variable file_status : file_open_status;
|
||||
|
||||
begin
|
||||
|
||||
wait until rising_edge (local_clk);
|
||||
if (ARESETN = '0') then
|
||||
tready_cnt := to_integer(rnd and x"0000001F");
|
||||
FINISHED <= '0';
|
||||
else
|
||||
S_AXIS_TREADY <= '1';
|
||||
FINISHED <= '0';
|
||||
-- Create filename and try to open the file
|
||||
file_open ( file_status, f, FILE_NAME & ".wav", write_mode);
|
||||
|
||||
-- File open succeeded ?
|
||||
if file_status /= open_ok then
|
||||
assert false report "AXIS_AUDIO_SLAVE_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
|
||||
else
|
||||
|
||||
wait until S_AXIS_TVALID = '1';
|
||||
for i in 0 to 43 loop
|
||||
header(i) := to_integer(unsigned(WAV_HEADER(8*(i+1)-1 downto 8*i)));
|
||||
end loop;
|
||||
write_wav_header(header,f);
|
||||
|
||||
num_samples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
|
||||
|
||||
for s in 0 to num_samples-1 loop -- sample loop
|
||||
|
||||
S_AXIS_TREADY <= '1';
|
||||
wait until rising_edge(local_clk);
|
||||
while S_AXIS_TVALID /= '1' loop
|
||||
wait until rising_edge(local_clk);
|
||||
end loop;
|
||||
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))),f);
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA(15 downto 8))),f);
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA(23 downto 16))),f);
|
||||
wavput8 (to_integer(unsigned(S_AXIS_TDATA(31 downto 24))),f);
|
||||
|
||||
tready_cnt := tready_cnt - 1;
|
||||
if RANDOM_TREADY and tready_cnt <= 0 then
|
||||
-- random TREADY delay
|
||||
delay_cnt := to_integer(rnd and x"00000007");
|
||||
while delay_cnt > 0 loop
|
||||
S_AXIS_TREADY <= '0';
|
||||
delay_cnt := delay_cnt - 1;
|
||||
wait until rising_edge (local_clk);
|
||||
tready_cnt := to_integer(rnd and x"0000001F");
|
||||
end loop;
|
||||
end if;
|
||||
end loop; -- sample loop
|
||||
|
||||
file_close(f);
|
||||
FINISHED <= '1';
|
||||
|
||||
end if; -- if open_status ok
|
||||
|
||||
-- wait until reset is activated
|
||||
while ARESETN = '1' loop
|
||||
wait until rising_edge (local_clk);
|
||||
end loop;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- synthesis translate_on
|
||||
-- translate on
|
||||
|
||||
|
||||
end sim;
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
package wav_pkg is
|
||||
|
||||
type WAV_FILE_TYPE is file of character;
|
||||
type WAV_HEADER_TYPE is array (0 to 43) of integer;
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE );
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer;
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
|
||||
|
||||
end;
|
||||
|
||||
package body wav_pkg is
|
||||
|
||||
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
write(f, character'val(value));
|
||||
end wavput8;
|
||||
|
||||
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
begin
|
||||
for i in 0 to 43 loop
|
||||
wavput8(header(i),f);
|
||||
end loop;
|
||||
end write_wav_header;
|
||||
|
||||
|
||||
|
||||
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
|
||||
variable chr : character;
|
||||
begin
|
||||
read (f,chr);
|
||||
return character'pos(chr);
|
||||
end wavget8;
|
||||
|
||||
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
|
||||
variable chr : character;
|
||||
variable val : integer;
|
||||
begin
|
||||
success := true;
|
||||
for i in 0 to 43 loop
|
||||
header(i) := wavget8(f);
|
||||
end loop;
|
||||
numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
|
||||
|
||||
if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then -- check for 'RIFF'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then -- check for 'WAVE'
|
||||
numsamples := 0;
|
||||
success := false;
|
||||
end if;
|
||||
|
||||
end read_wav_header;
|
||||
|
||||
|
||||
end package body;
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"design_1_sim": {
|
||||
"proto_instances": {
|
||||
"/axis_audio_bitcrusher_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"ARESETN": { "actual": "AXIS_ARESETN"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "M_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_bitcrusher_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"ARESETN": { "actual": "AXIS_ARESETN"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "S_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_master_si_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "ACLK"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_slave_sim_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "ACLK"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 20:37:14 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_sim.bd
|
||||
//Design : design_1_sim
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1_sim,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1_sim.hwdef" *)
|
||||
module design_1_sim
|
||||
();
|
||||
|
||||
wire [15:0]axis_audio_bitcrusher_0_M_AXIS_TDATA;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TREADY;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TVALID;
|
||||
wire [31:0]axis_audio_master_si_0_M_AXIS_TDATA;
|
||||
wire axis_audio_master_si_0_M_AXIS_TREADY;
|
||||
wire axis_audio_master_si_0_M_AXIS_TVALID;
|
||||
wire [351:0]axis_audio_master_si_0_WAV_HEADER;
|
||||
wire [31:0]axis_audio_mono2ster_0_M_AXIS_TDATA;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TREADY;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TVALID;
|
||||
wire axis_audio_slave_sim_0_FINISHED;
|
||||
wire [15:0]axis_audio_stereo2mo_0_M_AXIS_TDATA;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TREADY;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TVALID;
|
||||
wire clk_rst_generator_0_clk;
|
||||
wire clk_rst_generator_0_rst_n;
|
||||
|
||||
design_1_sim_axis_audio_bitcrusher_0_0 axis_audio_bitcrusher_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.AXIS_ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(1'b0),
|
||||
.S_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_master_si_0_0 axis_audio_master_si_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_mono2ster_0_0 axis_audio_mono2ster_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_slave_sim_0_0 axis_audio_slave_sim_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.FINISHED(axis_audio_slave_sim_0_FINISHED),
|
||||
.S_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_stereo2mo_0_0 axis_audio_stereo2mo_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID));
|
||||
design_1_sim_clk_rst_generator_0_0 clk_rst_generator_0
|
||||
(.clk(clk_rst_generator_0_clk),
|
||||
.clk_in(1'b1),
|
||||
.rst_in(1'b0),
|
||||
.rst_n(clk_rst_generator_0_rst_n),
|
||||
.stop_simulation(axis_audio_slave_sim_0_FINISHED));
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+81
@@ -0,0 +1,81 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 20:37:14 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_sim.bd
|
||||
//Design : design_1_sim
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "design_1_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1_sim,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1_sim.hwdef" *)
|
||||
module design_1_sim
|
||||
();
|
||||
|
||||
wire [15:0]axis_audio_bitcrusher_0_M_AXIS_TDATA;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TREADY;
|
||||
wire axis_audio_bitcrusher_0_M_AXIS_TVALID;
|
||||
wire [31:0]axis_audio_master_si_0_M_AXIS_TDATA;
|
||||
wire axis_audio_master_si_0_M_AXIS_TREADY;
|
||||
wire axis_audio_master_si_0_M_AXIS_TVALID;
|
||||
wire [351:0]axis_audio_master_si_0_WAV_HEADER;
|
||||
wire [31:0]axis_audio_mono2ster_0_M_AXIS_TDATA;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TREADY;
|
||||
wire axis_audio_mono2ster_0_M_AXIS_TVALID;
|
||||
wire axis_audio_slave_sim_0_FINISHED;
|
||||
wire [15:0]axis_audio_stereo2mo_0_M_AXIS_TDATA;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TREADY;
|
||||
wire axis_audio_stereo2mo_0_M_AXIS_TVALID;
|
||||
wire clk_rst_generator_0_clk;
|
||||
wire clk_rst_generator_0_rst_n;
|
||||
|
||||
design_1_sim_axis_audio_bitcrusher_0_0 axis_audio_bitcrusher_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.AXIS_ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(1'b0),
|
||||
.S_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_master_si_0_0 axis_audio_master_si_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.M_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_mono2ster_0_0 axis_audio_mono2ster_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_bitcrusher_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_bitcrusher_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_bitcrusher_0_M_AXIS_TVALID));
|
||||
design_1_sim_axis_audio_slave_sim_0_0 axis_audio_slave_sim_0
|
||||
(.ACLK(clk_rst_generator_0_clk),
|
||||
.ARESETN(clk_rst_generator_0_rst_n),
|
||||
.FINISHED(axis_audio_slave_sim_0_FINISHED),
|
||||
.S_AXIS_TDATA(axis_audio_mono2ster_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_mono2ster_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_mono2ster_0_M_AXIS_TVALID),
|
||||
.WAV_HEADER(axis_audio_master_si_0_WAV_HEADER));
|
||||
design_1_sim_axis_audio_stereo2mo_0_0 axis_audio_stereo2mo_0
|
||||
(.AXIS_ACLK(clk_rst_generator_0_clk),
|
||||
.M_AXIS_TDATA(axis_audio_stereo2mo_0_M_AXIS_TDATA),
|
||||
.M_AXIS_TREADY(axis_audio_stereo2mo_0_M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(axis_audio_stereo2mo_0_M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(axis_audio_master_si_0_M_AXIS_TDATA),
|
||||
.S_AXIS_TREADY(axis_audio_master_si_0_M_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(axis_audio_master_si_0_M_AXIS_TVALID));
|
||||
design_1_sim_clk_rst_generator_0_0 clk_rst_generator_0
|
||||
(.clk(clk_rst_generator_0_clk),
|
||||
.clk_in(1'b1),
|
||||
.rst_in(1'b0),
|
||||
.rst_n(clk_rst_generator_0_rst_n),
|
||||
.stop_simulation(axis_audio_slave_sim_0_FINISHED));
|
||||
endmodule
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "design_1_syn",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "design_1_syn",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="design_1_syn" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730149477"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730149477"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1_syn.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1_syn.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_syn_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_syn.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1_syn.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_syn.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1_syn.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
//Date : Mon Oct 28 22:04:25 2024
|
||||
//Host : Bastistablet running 64-bit major release (build 9200)
|
||||
//Command : generate_target design_1_syn_wrapper.bd
|
||||
//Design : design_1_syn_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module design_1_syn_wrapper
|
||||
(bclk,
|
||||
clk,
|
||||
i2c_scl_io,
|
||||
i2c_sda_io,
|
||||
mclk,
|
||||
mute,
|
||||
pb_dat,
|
||||
pb_lrc,
|
||||
rec_dat,
|
||||
rec_lrc,
|
||||
reset);
|
||||
output bclk;
|
||||
input clk;
|
||||
inout i2c_scl_io;
|
||||
inout i2c_sda_io;
|
||||
output mclk;
|
||||
output mute;
|
||||
output pb_dat;
|
||||
output pb_lrc;
|
||||
input rec_dat;
|
||||
output rec_lrc;
|
||||
input reset;
|
||||
|
||||
wire bclk;
|
||||
wire clk;
|
||||
wire i2c_scl_i;
|
||||
wire i2c_scl_io;
|
||||
wire i2c_scl_o;
|
||||
wire i2c_scl_t;
|
||||
wire i2c_sda_i;
|
||||
wire i2c_sda_io;
|
||||
wire i2c_sda_o;
|
||||
wire i2c_sda_t;
|
||||
wire mclk;
|
||||
wire mute;
|
||||
wire pb_dat;
|
||||
wire pb_lrc;
|
||||
wire rec_dat;
|
||||
wire rec_lrc;
|
||||
wire reset;
|
||||
|
||||
design_1_syn design_1_syn_i
|
||||
(.bclk(bclk),
|
||||
.clk(clk),
|
||||
.i2c_scl_i(i2c_scl_i),
|
||||
.i2c_scl_o(i2c_scl_o),
|
||||
.i2c_scl_t(i2c_scl_t),
|
||||
.i2c_sda_i(i2c_sda_i),
|
||||
.i2c_sda_o(i2c_sda_o),
|
||||
.i2c_sda_t(i2c_sda_t),
|
||||
.mclk(mclk),
|
||||
.mute(mute),
|
||||
.pb_dat(pb_dat),
|
||||
.pb_lrc(pb_lrc),
|
||||
.rec_dat(rec_dat),
|
||||
.rec_lrc(rec_lrc),
|
||||
.reset(reset));
|
||||
IOBUF i2c_scl_iobuf
|
||||
(.I(i2c_scl_o),
|
||||
.IO(i2c_scl_io),
|
||||
.O(i2c_scl_i),
|
||||
.T(i2c_scl_t));
|
||||
IOBUF i2c_sda_iobuf
|
||||
(.I(i2c_sda_o),
|
||||
.IO(i2c_sda_io),
|
||||
.O(i2c_sda_i),
|
||||
.T(i2c_sda_t));
|
||||
endmodule
|
||||
+4481
File diff suppressed because it is too large
Load Diff
+821
@@ -0,0 +1,821 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_syn_axis_audio_bitcrusher_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ARESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET">AXIS_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_bitcrusher</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:70d6c3bb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_bitcrusher</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:655531f7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:08:32 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:655531f7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:655531f7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>design_1_syn_axis_audio_bitcrusher_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:70d6c3bb</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>design_1_syn_axis_audio_bitcrusher_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:655531f7</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ARESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>BIT_REDUCTION</spirit:name>
|
||||
<spirit:displayName>Bit Reduction</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.BIT_REDUCTION">14</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_axis_audio_bitcrusher_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_axis_audio_bitcrusher_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_axis_audio_bitcrusher_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_axis_audio_bitcrusher_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_axis_audio_bitcrusher_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_syn_axis_audio_bitcrusher_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_syn_axis_audio_bitcrusher_0_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_audio_bitcrusher:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BIT_REDUCTION</spirit:name>
|
||||
<spirit:displayName>Bit Reduction</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BIT_REDUCTION">14</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_syn_axis_audio_bitcrusher_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_audio_bitcrusher_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ARESETN.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+278
@@ -0,0 +1,278 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:32 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_sim_netlist.v
|
||||
// Design : design_1_syn_axis_audio_bitcrusher_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_axis_audio_bitcrusher_0_0,axis_audio_bitcrusher,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* X_CORE_INFO = "axis_audio_bitcrusher,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_syn_axis_audio_bitcrusher_0_0
|
||||
(AXIS_ACLK,
|
||||
AXIS_ARESETN,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input AXIS_ARESETN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input S_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [15:0]S_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input S_AXIS_TLAST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output S_AXIS_TREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output M_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [15:0]M_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output M_AXIS_TLAST;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input M_AXIS_TREADY;
|
||||
|
||||
wire \<const0> ;
|
||||
wire AXIS_ACLK;
|
||||
wire [15:15]\^M_AXIS_TDATA ;
|
||||
wire M_AXIS_TREADY;
|
||||
wire M_AXIS_TVALID;
|
||||
wire [15:0]S_AXIS_TDATA;
|
||||
wire S_AXIS_TREADY;
|
||||
wire S_AXIS_TVALID;
|
||||
|
||||
assign M_AXIS_TDATA[15] = \^M_AXIS_TDATA [15];
|
||||
assign M_AXIS_TDATA[14] = \<const0> ;
|
||||
assign M_AXIS_TDATA[13] = \<const0> ;
|
||||
assign M_AXIS_TDATA[12] = \<const0> ;
|
||||
assign M_AXIS_TDATA[11] = \<const0> ;
|
||||
assign M_AXIS_TDATA[10] = \<const0> ;
|
||||
assign M_AXIS_TDATA[9] = \<const0> ;
|
||||
assign M_AXIS_TDATA[8] = \<const0> ;
|
||||
assign M_AXIS_TDATA[7] = \<const0> ;
|
||||
assign M_AXIS_TDATA[6] = \<const0> ;
|
||||
assign M_AXIS_TDATA[5] = \<const0> ;
|
||||
assign M_AXIS_TDATA[4] = \<const0> ;
|
||||
assign M_AXIS_TDATA[3] = \<const0> ;
|
||||
assign M_AXIS_TDATA[2] = \<const0> ;
|
||||
assign M_AXIS_TDATA[1] = \<const0> ;
|
||||
assign M_AXIS_TDATA[0] = \<const0> ;
|
||||
assign M_AXIS_TLAST = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher inst
|
||||
(.AXIS_ACLK(AXIS_ACLK),
|
||||
.M_AXIS_TDATA(\^M_AXIS_TDATA ),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(S_AXIS_TDATA[15]),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "axis_audio_bitcrusher" *)
|
||||
module design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher
|
||||
(S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
AXIS_ACLK,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TVALID,
|
||||
M_AXIS_TREADY);
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [0:0]M_AXIS_TDATA;
|
||||
input AXIS_ACLK;
|
||||
input [0:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TVALID;
|
||||
input M_AXIS_TREADY;
|
||||
|
||||
wire AXIS_ACLK;
|
||||
wire [0:0]M_AXIS_TDATA;
|
||||
wire \M_AXIS_TDATA[15]_i_1_n_0 ;
|
||||
wire M_AXIS_TREADY;
|
||||
wire M_AXIS_TVALID;
|
||||
wire RegInputEn;
|
||||
wire [0:0]S_AXIS_TDATA;
|
||||
wire S_AXIS_TREADY;
|
||||
wire S_AXIS_TVALID;
|
||||
wire \caculatorInput[15]_i_1_n_0 ;
|
||||
wire [15:15]caculatorOutput;
|
||||
wire [1:0]state;
|
||||
wire [1:1]state_next;
|
||||
wire [0:0]state_next__0;
|
||||
|
||||
LUT3 #(
|
||||
.INIT(8'h02))
|
||||
\FSM_sequential_state[0]_i_1
|
||||
(.I0(S_AXIS_TVALID),
|
||||
.I1(state[0]),
|
||||
.I2(state[1]),
|
||||
.O(state_next__0));
|
||||
(* FSM_ENCODED_STATES = "s_calculate:01,s_input:00,s_error:11,s_output:10" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\FSM_sequential_state_reg[0]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(1'b1),
|
||||
.D(state_next__0),
|
||||
.Q(state[0]),
|
||||
.R(1'b0));
|
||||
(* FSM_ENCODED_STATES = "s_calculate:01,s_input:00,s_error:11,s_output:10" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\FSM_sequential_state_reg[1]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(1'b1),
|
||||
.D(state_next),
|
||||
.Q(state[1]),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\M_AXIS_TDATA[15]_i_1
|
||||
(.I0(caculatorOutput),
|
||||
.I1(state[0]),
|
||||
.I2(M_AXIS_TDATA),
|
||||
.O(\M_AXIS_TDATA[15]_i_1_n_0 ));
|
||||
FDRE \M_AXIS_TDATA_reg[15]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(1'b1),
|
||||
.D(\M_AXIS_TDATA[15]_i_1_n_0 ),
|
||||
.Q(M_AXIS_TDATA),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h26))
|
||||
M_AXIS_TVALID_i_1
|
||||
(.I0(state[0]),
|
||||
.I1(state[1]),
|
||||
.I2(M_AXIS_TREADY),
|
||||
.O(state_next));
|
||||
FDRE M_AXIS_TVALID_reg
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(1'b1),
|
||||
.D(state_next),
|
||||
.Q(M_AXIS_TVALID),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'hF0C5))
|
||||
S_AXIS_TREADY_i_1
|
||||
(.I0(S_AXIS_TVALID),
|
||||
.I1(M_AXIS_TREADY),
|
||||
.I2(state[1]),
|
||||
.I3(state[0]),
|
||||
.O(RegInputEn));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
S_AXIS_TREADY_reg
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(1'b1),
|
||||
.D(RegInputEn),
|
||||
.Q(S_AXIS_TREADY),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'hB8))
|
||||
\caculatorInput[15]_i_1
|
||||
(.I0(S_AXIS_TDATA),
|
||||
.I1(S_AXIS_TREADY),
|
||||
.I2(caculatorOutput),
|
||||
.O(\caculatorInput[15]_i_1_n_0 ));
|
||||
FDRE \caculatorInput_reg[15]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(1'b1),
|
||||
.D(\caculatorInput[15]_i_1_n_0 ),
|
||||
.Q(caculatorOutput),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+242
@@ -0,0 +1,242 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:32 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_syn_axis_audio_bitcrusher_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher is
|
||||
port (
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher : entity is "axis_audio_bitcrusher";
|
||||
end design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher is
|
||||
signal \^m_axis_tdata\ : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal \M_AXIS_TDATA[15]_i_1_n_0\ : STD_LOGIC;
|
||||
signal RegInputEn : STD_LOGIC;
|
||||
signal \^s_axis_tready\ : STD_LOGIC;
|
||||
signal \caculatorInput[15]_i_1_n_0\ : STD_LOGIC;
|
||||
signal caculatorOutput : STD_LOGIC_VECTOR ( 15 to 15 );
|
||||
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal state_next : STD_LOGIC_VECTOR ( 1 to 1 );
|
||||
signal \state_next__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
attribute FSM_ENCODED_STATES : string;
|
||||
attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "s_calculate:01,s_input:00,s_error:11,s_output:10";
|
||||
attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "s_calculate:01,s_input:00,s_error:11,s_output:10";
|
||||
attribute SOFT_HLUTNM : string;
|
||||
attribute SOFT_HLUTNM of \M_AXIS_TDATA[15]_i_1\ : label is "soft_lutpair1";
|
||||
attribute SOFT_HLUTNM of M_AXIS_TVALID_i_1 : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of S_AXIS_TREADY_i_1 : label is "soft_lutpair0";
|
||||
attribute SOFT_HLUTNM of \caculatorInput[15]_i_1\ : label is "soft_lutpair1";
|
||||
begin
|
||||
M_AXIS_TDATA(0) <= \^m_axis_tdata\(0);
|
||||
S_AXIS_TREADY <= \^s_axis_tready\;
|
||||
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"02"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TVALID,
|
||||
I1 => state(0),
|
||||
I2 => state(1),
|
||||
O => \state_next__0\(0)
|
||||
);
|
||||
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => '1',
|
||||
D => \state_next__0\(0),
|
||||
Q => state(0),
|
||||
R => '0'
|
||||
);
|
||||
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => '1',
|
||||
D => state_next(1),
|
||||
Q => state(1),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => caculatorOutput(15),
|
||||
I1 => state(0),
|
||||
I2 => \^m_axis_tdata\(0),
|
||||
O => \M_AXIS_TDATA[15]_i_1_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA_reg[15]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => '1',
|
||||
D => \M_AXIS_TDATA[15]_i_1_n_0\,
|
||||
Q => \^m_axis_tdata\(0),
|
||||
R => '0'
|
||||
);
|
||||
M_AXIS_TVALID_i_1: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"26"
|
||||
)
|
||||
port map (
|
||||
I0 => state(0),
|
||||
I1 => state(1),
|
||||
I2 => M_AXIS_TREADY,
|
||||
O => state_next(1)
|
||||
);
|
||||
M_AXIS_TVALID_reg: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => '1',
|
||||
D => state_next(1),
|
||||
Q => M_AXIS_TVALID,
|
||||
R => '0'
|
||||
);
|
||||
S_AXIS_TREADY_i_1: unisim.vcomponents.LUT4
|
||||
generic map(
|
||||
INIT => X"F0C5"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TVALID,
|
||||
I1 => M_AXIS_TREADY,
|
||||
I2 => state(1),
|
||||
I3 => state(0),
|
||||
O => RegInputEn
|
||||
);
|
||||
S_AXIS_TREADY_reg: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => '1',
|
||||
D => RegInputEn,
|
||||
Q => \^s_axis_tready\,
|
||||
R => '0'
|
||||
);
|
||||
\caculatorInput[15]_i_1\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"B8"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(0),
|
||||
I1 => \^s_axis_tready\,
|
||||
I2 => caculatorOutput(15),
|
||||
O => \caculatorInput[15]_i_1_n_0\
|
||||
);
|
||||
\caculatorInput_reg[15]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => '1',
|
||||
D => \caculatorInput[15]_i_1_n_0\,
|
||||
Q => caculatorOutput(15),
|
||||
R => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_axis_audio_bitcrusher_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of design_1_syn_axis_audio_bitcrusher_0_0 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of design_1_syn_axis_audio_bitcrusher_0_0 : entity is "design_1_syn_axis_audio_bitcrusher_0_0,axis_audio_bitcrusher,{}";
|
||||
attribute DowngradeIPIdentifiedWarnings : string;
|
||||
attribute DowngradeIPIdentifiedWarnings of design_1_syn_axis_audio_bitcrusher_0_0 : entity is "yes";
|
||||
attribute IP_DEFINITION_SOURCE : string;
|
||||
attribute IP_DEFINITION_SOURCE of design_1_syn_axis_audio_bitcrusher_0_0 : entity is "module_ref";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of design_1_syn_axis_audio_bitcrusher_0_0 : entity is "axis_audio_bitcrusher,Vivado 2023.1";
|
||||
end design_1_syn_axis_audio_bitcrusher_0_0;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_axis_audio_bitcrusher_0_0 is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
signal \^m_axis_tdata\ : STD_LOGIC_VECTOR ( 15 to 15 );
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of AXIS_ARESETN : signal is "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of AXIS_ARESETN : signal is "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of M_AXIS_TLAST : signal is "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
attribute X_INTERFACE_INFO of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
attribute X_INTERFACE_PARAMETER of M_AXIS_TREADY : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
attribute X_INTERFACE_INFO of S_AXIS_TLAST : signal is "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
attribute X_INTERFACE_INFO of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
attribute X_INTERFACE_PARAMETER of S_AXIS_TREADY : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
attribute X_INTERFACE_INFO of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
attribute X_INTERFACE_INFO of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
attribute X_INTERFACE_INFO of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
begin
|
||||
M_AXIS_TDATA(15) <= \^m_axis_tdata\(15);
|
||||
M_AXIS_TDATA(14) <= \<const0>\;
|
||||
M_AXIS_TDATA(13) <= \<const0>\;
|
||||
M_AXIS_TDATA(12) <= \<const0>\;
|
||||
M_AXIS_TDATA(11) <= \<const0>\;
|
||||
M_AXIS_TDATA(10) <= \<const0>\;
|
||||
M_AXIS_TDATA(9) <= \<const0>\;
|
||||
M_AXIS_TDATA(8) <= \<const0>\;
|
||||
M_AXIS_TDATA(7) <= \<const0>\;
|
||||
M_AXIS_TDATA(6) <= \<const0>\;
|
||||
M_AXIS_TDATA(5) <= \<const0>\;
|
||||
M_AXIS_TDATA(4) <= \<const0>\;
|
||||
M_AXIS_TDATA(3) <= \<const0>\;
|
||||
M_AXIS_TDATA(2) <= \<const0>\;
|
||||
M_AXIS_TDATA(1) <= \<const0>\;
|
||||
M_AXIS_TDATA(0) <= \<const0>\;
|
||||
M_AXIS_TLAST <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst: entity work.design_1_syn_axis_audio_bitcrusher_0_0_axis_audio_bitcrusher
|
||||
port map (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
M_AXIS_TDATA(0) => \^m_axis_tdata\(15),
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(0) => S_AXIS_TDATA(15),
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:32 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_stub.v
|
||||
// Design : design_1_syn_axis_audio_bitcrusher_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axis_audio_bitcrusher,Vivado 2023.1" *)
|
||||
module design_1_syn_axis_audio_bitcrusher_0_0(AXIS_ACLK, AXIS_ARESETN, S_AXIS_TVALID,
|
||||
S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST,
|
||||
M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="AXIS_ARESETN,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY" */
|
||||
/* synthesis syn_force_seq_prim="AXIS_ACLK" */;
|
||||
input AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input AXIS_ARESETN;
|
||||
input S_AXIS_TVALID;
|
||||
input [15:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [15:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
endmodule
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:32 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0_stub.vhdl
|
||||
-- Design : design_1_syn_axis_audio_bitcrusher_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_1_syn_axis_audio_bitcrusher_0_0 is
|
||||
Port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
AXIS_ARESETN : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end design_1_syn_axis_audio_bitcrusher_0_0;
|
||||
|
||||
architecture stub of design_1_syn_axis_audio_bitcrusher_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,AXIS_ARESETN,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axis_audio_bitcrusher,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+110
@@ -0,0 +1,110 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:axis_audio_bitcrusher:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_syn_axis_audio_bitcrusher_0_0 (
|
||||
AXIS_ACLK,
|
||||
AXIS_ARESETN,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *)
|
||||
input wire AXIS_ACLK;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST" *)
|
||||
input wire AXIS_ARESETN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire S_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [15 : 0] S_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
|
||||
input wire S_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire S_AXIS_TREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire M_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [15 : 0] M_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
|
||||
output wire M_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire M_AXIS_TREADY;
|
||||
|
||||
axis_audio_bitcrusher #(
|
||||
.BIT_REDUCTION(14),
|
||||
.HAS_LAST(1'B0)
|
||||
) inst (
|
||||
.AXIS_ACLK(AXIS_ACLK),
|
||||
.AXIS_ARESETN(AXIS_ARESETN),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(S_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(S_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY)
|
||||
);
|
||||
endmodule
|
||||
+111
@@ -0,0 +1,111 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:axis_audio_bitcrusher:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "axis_audio_bitcrusher,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_axis_audio_bitcrusher_0_0,axis_audio_bitcrusher,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_syn_axis_audio_bitcrusher_0_0,axis_audio_bitcrusher,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_audio_bitcrusher,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,BIT_REDUCTION=14,HAS_LAST=false}" *)
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_syn_axis_audio_bitcrusher_0_0 (
|
||||
AXIS_ACLK,
|
||||
AXIS_ARESETN,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *)
|
||||
input wire AXIS_ACLK;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AXIS_ARESETN RST" *)
|
||||
input wire AXIS_ARESETN;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
|
||||
input wire S_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
|
||||
input wire [15 : 0] S_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
|
||||
input wire S_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
|
||||
output wire S_AXIS_TREADY;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
|
||||
output wire M_AXIS_TVALID;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
|
||||
output wire [15 : 0] M_AXIS_TDATA;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
|
||||
output wire M_AXIS_TLAST;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
|
||||
input wire M_AXIS_TREADY;
|
||||
|
||||
axis_audio_bitcrusher #(
|
||||
.BIT_REDUCTION(14),
|
||||
.HAS_LAST(1'B0)
|
||||
) inst (
|
||||
.AXIS_ACLK(AXIS_ACLK),
|
||||
.AXIS_ARESETN(AXIS_ARESETN),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(S_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(S_AXIS_TLAST),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(M_AXIS_TLAST),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY)
|
||||
);
|
||||
endmodule
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 10.000 [get_ports AXIS_ACLK]
|
||||
+836
@@ -0,0 +1,836 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_syn_axis_audio_mono2ster_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
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</spirit:parameter>
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||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_audio_mono2stereo</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>3</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@33527e3f_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@60b70a2a_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@b393973_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@11107b6b_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@306669e8_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@3d4dbd54_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@50f254d8_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@267e2692_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@6fdc1ebf_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@79b365fa_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@425bf28e_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d012246_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@714d7ede_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c4329dc"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="dd41f636"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="7314069d"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+172
@@ -0,0 +1,172 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:32 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0_sim_netlist.v
|
||||
// Design : design_1_syn_axis_audio_mono2ster_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
|
||||
(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_syn_axis_audio_mono2ster_0_0
|
||||
(AXIS_ACLK,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TREADY);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [15:0]S_AXIS_TDATA;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [31:0]M_AXIS_TDATA;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
|
||||
|
||||
wire [31:0]M_AXIS_TDATA;
|
||||
wire M_AXIS_TREADY;
|
||||
wire M_AXIS_TVALID;
|
||||
wire [15:0]S_AXIS_TDATA;
|
||||
wire S_AXIS_TREADY;
|
||||
wire S_AXIS_TVALID;
|
||||
wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
|
||||
|
||||
(* HAS_LAST = "FALSE" *)
|
||||
design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo U0
|
||||
(.AXIS_ACLK(1'b0),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA(S_AXIS_TDATA),
|
||||
.S_AXIS_TLAST(1'b0),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID));
|
||||
endmodule
|
||||
|
||||
(* HAS_LAST = "FALSE" *) (* ORIG_REF_NAME = "axis_audio_mono2stereo" *)
|
||||
module design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
|
||||
(AXIS_ACLK,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY);
|
||||
input AXIS_ACLK;
|
||||
input S_AXIS_TVALID;
|
||||
input [15:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
|
||||
wire \<const0> ;
|
||||
wire M_AXIS_TREADY;
|
||||
wire [15:0]S_AXIS_TDATA;
|
||||
wire S_AXIS_TVALID;
|
||||
|
||||
assign M_AXIS_TDATA[31:16] = S_AXIS_TDATA;
|
||||
assign M_AXIS_TDATA[15:0] = S_AXIS_TDATA;
|
||||
assign M_AXIS_TLAST = \<const0> ;
|
||||
assign M_AXIS_TVALID = S_AXIS_TVALID;
|
||||
assign S_AXIS_TREADY = M_AXIS_TREADY;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+110
@@ -0,0 +1,110 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:32 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_syn_axis_audio_mono2ster_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
attribute HAS_LAST : string;
|
||||
attribute HAS_LAST of design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo : entity is "FALSE";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo : entity is "axis_audio_mono2stereo";
|
||||
end design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
signal \^m_axis_tready\ : STD_LOGIC;
|
||||
signal \^s_axis_tdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal \^s_axis_tvalid\ : STD_LOGIC;
|
||||
begin
|
||||
M_AXIS_TDATA(31 downto 16) <= \^s_axis_tdata\(15 downto 0);
|
||||
M_AXIS_TDATA(15 downto 0) <= \^s_axis_tdata\(15 downto 0);
|
||||
M_AXIS_TLAST <= \<const0>\;
|
||||
M_AXIS_TVALID <= \^s_axis_tvalid\;
|
||||
S_AXIS_TREADY <= \^m_axis_tready\;
|
||||
\^m_axis_tready\ <= M_AXIS_TREADY;
|
||||
\^s_axis_tdata\(15 downto 0) <= S_AXIS_TDATA(15 downto 0);
|
||||
\^s_axis_tvalid\ <= S_AXIS_TVALID;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of design_1_syn_axis_audio_mono2ster_0_0 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of design_1_syn_axis_audio_mono2ster_0_0 : entity is "design_1_syn_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of design_1_syn_axis_audio_mono2ster_0_0 : entity is "yes";
|
||||
attribute ip_definition_source : string;
|
||||
attribute ip_definition_source of design_1_syn_axis_audio_mono2ster_0_0 : entity is "package_project";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of design_1_syn_axis_audio_mono2ster_0_0 : entity is "axis_audio_mono2stereo,Vivado 2023.1";
|
||||
end design_1_syn_axis_audio_mono2ster_0_0;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_axis_audio_mono2ster_0_0 is
|
||||
signal NLW_U0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
|
||||
attribute HAS_LAST : string;
|
||||
attribute HAS_LAST of U0 : label is "FALSE";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute x_interface_info of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
attribute x_interface_info of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
attribute x_interface_parameter of M_AXIS_TVALID : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
attribute x_interface_info of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
attribute x_interface_info of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
attribute x_interface_parameter of S_AXIS_TVALID : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
attribute x_interface_info of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
attribute x_interface_info of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
begin
|
||||
U0: entity work.design_1_syn_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
|
||||
port map (
|
||||
AXIS_ACLK => '0',
|
||||
M_AXIS_TDATA(31 downto 0) => M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TLAST => NLW_U0_M_AXIS_TLAST_UNCONNECTED,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => S_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:32 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0_stub.v
|
||||
// Design : design_1_syn_axis_audio_mono2ster_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
|
||||
module design_1_syn_axis_audio_mono2ster_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA,
|
||||
S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY" */;
|
||||
input AXIS_ACLK;
|
||||
input S_AXIS_TVALID;
|
||||
input [15:0]S_AXIS_TDATA;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
input M_AXIS_TREADY;
|
||||
endmodule
|
||||
+37
@@ -0,0 +1,37 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:32 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0_stub.vhdl
|
||||
-- Design : design_1_syn_axis_audio_mono2ster_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_1_syn_axis_audio_mono2ster_0_0 is
|
||||
Port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end design_1_syn_axis_audio_mono2ster_0_0;
|
||||
|
||||
architecture stub of design_1_syn_axis_audio_mono2ster_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axis_audio_mono2stereo,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_syn_axis_audio_mono2ster_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_syn_axis_audio_mono2ster_0_0;
|
||||
|
||||
ARCHITECTURE design_1_syn_axis_audio_mono2ster_0_0_arch OF design_1_syn_axis_audio_mono2ster_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_syn_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_mono2stereo IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_mono2stereo;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_mono2stereo
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_syn_axis_audio_mono2ster_0_0_arch;
|
||||
+122
@@ -0,0 +1,122 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_syn_axis_audio_mono2ster_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_syn_axis_audio_mono2ster_0_0;
|
||||
|
||||
ARCHITECTURE design_1_syn_axis_audio_mono2ster_0_0_arch OF design_1_syn_axis_audio_mono2ster_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_syn_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_mono2stereo IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_mono2stereo;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_syn_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "axis_audio_mono2stereo,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_syn_axis_audio_mono2ster_0_0_arch : ARCHITECTURE IS "design_1_syn_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_syn_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "design_1_syn_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_mono2stereo,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,HAS_LAST=false}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_syn_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_mono2stereo
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_syn_axis_audio_mono2ster_0_0_arch;
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 10.000 [get_ports AXIS_ACLK]
|
||||
+856
@@ -0,0 +1,856 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_syn_axis_audio_stereo2mo_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
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|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
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|
||||
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|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
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|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
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|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
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|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
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|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
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|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2dca7dbe</spirit:value>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1f04baa8</spirit:value>
|
||||
</spirit:parameter>
|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
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<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
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|
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|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:08:33 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1f04baa8</spirit:value>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1f04baa8</spirit:value>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_syn_axis_audio_stereo2mo_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2dca7dbe</spirit:value>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_syn_axis_audio_stereo2mo_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
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|
||||
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|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:1f04baa8</spirit:value>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
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|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
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|
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|
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|
||||
<xilinx:portInfo>
|
||||
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|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
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|
||||
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|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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<spirit:parameter>
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<spirit:name>HAS_LAST</spirit:name>
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<spirit:displayName>Has Last</spirit:displayName>
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<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LAST">false</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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||||
</spirit:component>
|
||||
+439
@@ -0,0 +1,439 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:33 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0_sim_netlist.v
|
||||
// Design : design_1_syn_axis_audio_stereo2mo_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
|
||||
(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_syn_axis_audio_stereo2mo_0_0
|
||||
(AXIS_ACLK,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TREADY);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [31:0]S_AXIS_TDATA;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [15:0]M_AXIS_TDATA;
|
||||
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
|
||||
|
||||
wire AXIS_ACLK;
|
||||
wire [15:0]M_AXIS_TDATA;
|
||||
wire M_AXIS_TREADY;
|
||||
wire M_AXIS_TVALID;
|
||||
wire [31:0]S_AXIS_TDATA;
|
||||
wire S_AXIS_TREADY;
|
||||
wire S_AXIS_TVALID;
|
||||
wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
|
||||
|
||||
(* HAS_LAST = "FALSE" *)
|
||||
design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono U0
|
||||
(.AXIS_ACLK(AXIS_ACLK),
|
||||
.M_AXIS_TDATA(M_AXIS_TDATA),
|
||||
.M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
|
||||
.M_AXIS_TREADY(M_AXIS_TREADY),
|
||||
.M_AXIS_TVALID(M_AXIS_TVALID),
|
||||
.S_AXIS_TDATA({S_AXIS_TDATA[31:17],1'b0,S_AXIS_TDATA[15:1],1'b0}),
|
||||
.S_AXIS_TLAST(1'b0),
|
||||
.S_AXIS_TREADY(S_AXIS_TREADY),
|
||||
.S_AXIS_TVALID(S_AXIS_TVALID));
|
||||
endmodule
|
||||
|
||||
(* HAS_LAST = "FALSE" *) (* ORIG_REF_NAME = "axis_audio_stereo2mono" *)
|
||||
module design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
|
||||
(AXIS_ACLK,
|
||||
S_AXIS_TVALID,
|
||||
S_AXIS_TDATA,
|
||||
S_AXIS_TLAST,
|
||||
S_AXIS_TREADY,
|
||||
M_AXIS_TVALID,
|
||||
M_AXIS_TDATA,
|
||||
M_AXIS_TLAST,
|
||||
M_AXIS_TREADY);
|
||||
input AXIS_ACLK;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [15:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
|
||||
wire \<const0> ;
|
||||
wire AXIS_ACLK;
|
||||
wire [15:0]M_AXIS_TDATA;
|
||||
wire \M_AXIS_TDATA[11]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[11]_i_3_n_0 ;
|
||||
wire \M_AXIS_TDATA[11]_i_4_n_0 ;
|
||||
wire \M_AXIS_TDATA[11]_i_5_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_3_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_4_n_0 ;
|
||||
wire \M_AXIS_TDATA[15]_i_5_n_0 ;
|
||||
wire \M_AXIS_TDATA[3]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[3]_i_3_n_0 ;
|
||||
wire \M_AXIS_TDATA[3]_i_4_n_0 ;
|
||||
wire \M_AXIS_TDATA[3]_i_5_n_0 ;
|
||||
wire \M_AXIS_TDATA[7]_i_2_n_0 ;
|
||||
wire \M_AXIS_TDATA[7]_i_3_n_0 ;
|
||||
wire \M_AXIS_TDATA[7]_i_4_n_0 ;
|
||||
wire \M_AXIS_TDATA[7]_i_5_n_0 ;
|
||||
wire \M_AXIS_TDATA_reg[11]_i_1_n_0 ;
|
||||
wire \M_AXIS_TDATA_reg[11]_i_1_n_1 ;
|
||||
wire \M_AXIS_TDATA_reg[11]_i_1_n_2 ;
|
||||
wire \M_AXIS_TDATA_reg[11]_i_1_n_3 ;
|
||||
wire \M_AXIS_TDATA_reg[15]_i_1_n_1 ;
|
||||
wire \M_AXIS_TDATA_reg[15]_i_1_n_2 ;
|
||||
wire \M_AXIS_TDATA_reg[15]_i_1_n_3 ;
|
||||
wire \M_AXIS_TDATA_reg[3]_i_1_n_0 ;
|
||||
wire \M_AXIS_TDATA_reg[3]_i_1_n_1 ;
|
||||
wire \M_AXIS_TDATA_reg[3]_i_1_n_2 ;
|
||||
wire \M_AXIS_TDATA_reg[3]_i_1_n_3 ;
|
||||
wire \M_AXIS_TDATA_reg[7]_i_1_n_0 ;
|
||||
wire \M_AXIS_TDATA_reg[7]_i_1_n_1 ;
|
||||
wire \M_AXIS_TDATA_reg[7]_i_1_n_2 ;
|
||||
wire \M_AXIS_TDATA_reg[7]_i_1_n_3 ;
|
||||
wire M_AXIS_TREADY;
|
||||
wire M_AXIS_TVALID;
|
||||
wire [31:0]S_AXIS_TDATA;
|
||||
wire S_AXIS_TREADY;
|
||||
wire S_AXIS_TVALID;
|
||||
wire [15:0]p_0_in;
|
||||
wire [3:3]\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED ;
|
||||
|
||||
assign M_AXIS_TLAST = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[11]_i_2
|
||||
(.I0(S_AXIS_TDATA[28]),
|
||||
.I1(S_AXIS_TDATA[12]),
|
||||
.O(\M_AXIS_TDATA[11]_i_2_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[11]_i_3
|
||||
(.I0(S_AXIS_TDATA[27]),
|
||||
.I1(S_AXIS_TDATA[11]),
|
||||
.O(\M_AXIS_TDATA[11]_i_3_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[11]_i_4
|
||||
(.I0(S_AXIS_TDATA[26]),
|
||||
.I1(S_AXIS_TDATA[10]),
|
||||
.O(\M_AXIS_TDATA[11]_i_4_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[11]_i_5
|
||||
(.I0(S_AXIS_TDATA[25]),
|
||||
.I1(S_AXIS_TDATA[9]),
|
||||
.O(\M_AXIS_TDATA[11]_i_5_n_0 ));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\M_AXIS_TDATA[15]_i_2
|
||||
(.I0(S_AXIS_TDATA[31]),
|
||||
.O(\M_AXIS_TDATA[15]_i_2_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[15]_i_3
|
||||
(.I0(S_AXIS_TDATA[31]),
|
||||
.I1(S_AXIS_TDATA[15]),
|
||||
.O(\M_AXIS_TDATA[15]_i_3_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[15]_i_4
|
||||
(.I0(S_AXIS_TDATA[30]),
|
||||
.I1(S_AXIS_TDATA[14]),
|
||||
.O(\M_AXIS_TDATA[15]_i_4_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[15]_i_5
|
||||
(.I0(S_AXIS_TDATA[29]),
|
||||
.I1(S_AXIS_TDATA[13]),
|
||||
.O(\M_AXIS_TDATA[15]_i_5_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[3]_i_2
|
||||
(.I0(S_AXIS_TDATA[20]),
|
||||
.I1(S_AXIS_TDATA[4]),
|
||||
.O(\M_AXIS_TDATA[3]_i_2_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[3]_i_3
|
||||
(.I0(S_AXIS_TDATA[19]),
|
||||
.I1(S_AXIS_TDATA[3]),
|
||||
.O(\M_AXIS_TDATA[3]_i_3_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[3]_i_4
|
||||
(.I0(S_AXIS_TDATA[18]),
|
||||
.I1(S_AXIS_TDATA[2]),
|
||||
.O(\M_AXIS_TDATA[3]_i_4_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[3]_i_5
|
||||
(.I0(S_AXIS_TDATA[17]),
|
||||
.I1(S_AXIS_TDATA[1]),
|
||||
.O(\M_AXIS_TDATA[3]_i_5_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[7]_i_2
|
||||
(.I0(S_AXIS_TDATA[24]),
|
||||
.I1(S_AXIS_TDATA[8]),
|
||||
.O(\M_AXIS_TDATA[7]_i_2_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[7]_i_3
|
||||
(.I0(S_AXIS_TDATA[23]),
|
||||
.I1(S_AXIS_TDATA[7]),
|
||||
.O(\M_AXIS_TDATA[7]_i_3_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[7]_i_4
|
||||
(.I0(S_AXIS_TDATA[22]),
|
||||
.I1(S_AXIS_TDATA[6]),
|
||||
.O(\M_AXIS_TDATA[7]_i_4_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\M_AXIS_TDATA[7]_i_5
|
||||
(.I0(S_AXIS_TDATA[21]),
|
||||
.I1(S_AXIS_TDATA[5]),
|
||||
.O(\M_AXIS_TDATA[7]_i_5_n_0 ));
|
||||
FDRE \M_AXIS_TDATA_reg[0]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[0]),
|
||||
.Q(M_AXIS_TDATA[0]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[10]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[10]),
|
||||
.Q(M_AXIS_TDATA[10]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[11]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[11]),
|
||||
.Q(M_AXIS_TDATA[11]),
|
||||
.R(1'b0));
|
||||
CARRY4 \M_AXIS_TDATA_reg[11]_i_1
|
||||
(.CI(\M_AXIS_TDATA_reg[7]_i_1_n_0 ),
|
||||
.CO({\M_AXIS_TDATA_reg[11]_i_1_n_0 ,\M_AXIS_TDATA_reg[11]_i_1_n_1 ,\M_AXIS_TDATA_reg[11]_i_1_n_2 ,\M_AXIS_TDATA_reg[11]_i_1_n_3 }),
|
||||
.CYINIT(1'b0),
|
||||
.DI(S_AXIS_TDATA[28:25]),
|
||||
.O(p_0_in[11:8]),
|
||||
.S({\M_AXIS_TDATA[11]_i_2_n_0 ,\M_AXIS_TDATA[11]_i_3_n_0 ,\M_AXIS_TDATA[11]_i_4_n_0 ,\M_AXIS_TDATA[11]_i_5_n_0 }));
|
||||
FDRE \M_AXIS_TDATA_reg[12]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[12]),
|
||||
.Q(M_AXIS_TDATA[12]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[13]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[13]),
|
||||
.Q(M_AXIS_TDATA[13]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[14]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[14]),
|
||||
.Q(M_AXIS_TDATA[14]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[15]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[15]),
|
||||
.Q(M_AXIS_TDATA[15]),
|
||||
.R(1'b0));
|
||||
CARRY4 \M_AXIS_TDATA_reg[15]_i_1
|
||||
(.CI(\M_AXIS_TDATA_reg[11]_i_1_n_0 ),
|
||||
.CO({\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED [3],\M_AXIS_TDATA_reg[15]_i_1_n_1 ,\M_AXIS_TDATA_reg[15]_i_1_n_2 ,\M_AXIS_TDATA_reg[15]_i_1_n_3 }),
|
||||
.CYINIT(1'b0),
|
||||
.DI({1'b0,\M_AXIS_TDATA[15]_i_2_n_0 ,S_AXIS_TDATA[30:29]}),
|
||||
.O(p_0_in[15:12]),
|
||||
.S({1'b1,\M_AXIS_TDATA[15]_i_3_n_0 ,\M_AXIS_TDATA[15]_i_4_n_0 ,\M_AXIS_TDATA[15]_i_5_n_0 }));
|
||||
FDRE \M_AXIS_TDATA_reg[1]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[1]),
|
||||
.Q(M_AXIS_TDATA[1]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[2]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[2]),
|
||||
.Q(M_AXIS_TDATA[2]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[3]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[3]),
|
||||
.Q(M_AXIS_TDATA[3]),
|
||||
.R(1'b0));
|
||||
CARRY4 \M_AXIS_TDATA_reg[3]_i_1
|
||||
(.CI(1'b0),
|
||||
.CO({\M_AXIS_TDATA_reg[3]_i_1_n_0 ,\M_AXIS_TDATA_reg[3]_i_1_n_1 ,\M_AXIS_TDATA_reg[3]_i_1_n_2 ,\M_AXIS_TDATA_reg[3]_i_1_n_3 }),
|
||||
.CYINIT(1'b0),
|
||||
.DI(S_AXIS_TDATA[20:17]),
|
||||
.O(p_0_in[3:0]),
|
||||
.S({\M_AXIS_TDATA[3]_i_2_n_0 ,\M_AXIS_TDATA[3]_i_3_n_0 ,\M_AXIS_TDATA[3]_i_4_n_0 ,\M_AXIS_TDATA[3]_i_5_n_0 }));
|
||||
FDRE \M_AXIS_TDATA_reg[4]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[4]),
|
||||
.Q(M_AXIS_TDATA[4]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[5]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[5]),
|
||||
.Q(M_AXIS_TDATA[5]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[6]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[6]),
|
||||
.Q(M_AXIS_TDATA[6]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[7]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[7]),
|
||||
.Q(M_AXIS_TDATA[7]),
|
||||
.R(1'b0));
|
||||
CARRY4 \M_AXIS_TDATA_reg[7]_i_1
|
||||
(.CI(\M_AXIS_TDATA_reg[3]_i_1_n_0 ),
|
||||
.CO({\M_AXIS_TDATA_reg[7]_i_1_n_0 ,\M_AXIS_TDATA_reg[7]_i_1_n_1 ,\M_AXIS_TDATA_reg[7]_i_1_n_2 ,\M_AXIS_TDATA_reg[7]_i_1_n_3 }),
|
||||
.CYINIT(1'b0),
|
||||
.DI(S_AXIS_TDATA[24:21]),
|
||||
.O(p_0_in[7:4]),
|
||||
.S({\M_AXIS_TDATA[7]_i_2_n_0 ,\M_AXIS_TDATA[7]_i_3_n_0 ,\M_AXIS_TDATA[7]_i_4_n_0 ,\M_AXIS_TDATA[7]_i_5_n_0 }));
|
||||
FDRE \M_AXIS_TDATA_reg[8]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[8]),
|
||||
.Q(M_AXIS_TDATA[8]),
|
||||
.R(1'b0));
|
||||
FDRE \M_AXIS_TDATA_reg[9]
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(p_0_in[9]),
|
||||
.Q(M_AXIS_TDATA[9]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
M_AXIS_TVALID_reg
|
||||
(.C(AXIS_ACLK),
|
||||
.CE(S_AXIS_TREADY),
|
||||
.D(S_AXIS_TVALID),
|
||||
.Q(M_AXIS_TVALID),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
S_AXIS_TREADY_INST_0
|
||||
(.I0(M_AXIS_TREADY),
|
||||
.I1(M_AXIS_TVALID),
|
||||
.O(S_AXIS_TREADY));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+493
@@ -0,0 +1,493 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:33 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_syn_axis_audio_stereo2mo_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
attribute HAS_LAST : string;
|
||||
attribute HAS_LAST of design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono : entity is "FALSE";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono : entity is "axis_audio_stereo2mono";
|
||||
end design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[11]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[11]_i_3_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[11]_i_4_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[11]_i_5_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_3_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_4_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[15]_i_5_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[3]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[3]_i_3_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[3]_i_4_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[3]_i_5_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[7]_i_2_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[7]_i_3_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[7]_i_4_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA[7]_i_5_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[11]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[11]_i_1_n_1\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[11]_i_1_n_2\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[11]_i_1_n_3\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[15]_i_1_n_1\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[15]_i_1_n_2\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[15]_i_1_n_3\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[3]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[3]_i_1_n_1\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[3]_i_1_n_2\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[3]_i_1_n_3\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[7]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[7]_i_1_n_1\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[7]_i_1_n_2\ : STD_LOGIC;
|
||||
signal \M_AXIS_TDATA_reg[7]_i_1_n_3\ : STD_LOGIC;
|
||||
signal \^m_axis_tvalid\ : STD_LOGIC;
|
||||
signal \^s_axis_tready\ : STD_LOGIC;
|
||||
signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal \NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
|
||||
begin
|
||||
M_AXIS_TLAST <= \<const0>\;
|
||||
M_AXIS_TVALID <= \^m_axis_tvalid\;
|
||||
S_AXIS_TREADY <= \^s_axis_tready\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
\M_AXIS_TDATA[11]_i_2\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(28),
|
||||
I1 => S_AXIS_TDATA(12),
|
||||
O => \M_AXIS_TDATA[11]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[11]_i_3\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(27),
|
||||
I1 => S_AXIS_TDATA(11),
|
||||
O => \M_AXIS_TDATA[11]_i_3_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[11]_i_4\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(26),
|
||||
I1 => S_AXIS_TDATA(10),
|
||||
O => \M_AXIS_TDATA[11]_i_4_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[11]_i_5\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(25),
|
||||
I1 => S_AXIS_TDATA(9),
|
||||
O => \M_AXIS_TDATA[11]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_2\: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(31),
|
||||
O => \M_AXIS_TDATA[15]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_3\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(31),
|
||||
I1 => S_AXIS_TDATA(15),
|
||||
O => \M_AXIS_TDATA[15]_i_3_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_4\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(30),
|
||||
I1 => S_AXIS_TDATA(14),
|
||||
O => \M_AXIS_TDATA[15]_i_4_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[15]_i_5\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(29),
|
||||
I1 => S_AXIS_TDATA(13),
|
||||
O => \M_AXIS_TDATA[15]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[3]_i_2\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(20),
|
||||
I1 => S_AXIS_TDATA(4),
|
||||
O => \M_AXIS_TDATA[3]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[3]_i_3\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(19),
|
||||
I1 => S_AXIS_TDATA(3),
|
||||
O => \M_AXIS_TDATA[3]_i_3_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[3]_i_4\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(18),
|
||||
I1 => S_AXIS_TDATA(2),
|
||||
O => \M_AXIS_TDATA[3]_i_4_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[3]_i_5\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(17),
|
||||
I1 => S_AXIS_TDATA(1),
|
||||
O => \M_AXIS_TDATA[3]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[7]_i_2\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(24),
|
||||
I1 => S_AXIS_TDATA(8),
|
||||
O => \M_AXIS_TDATA[7]_i_2_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[7]_i_3\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(23),
|
||||
I1 => S_AXIS_TDATA(7),
|
||||
O => \M_AXIS_TDATA[7]_i_3_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[7]_i_4\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(22),
|
||||
I1 => S_AXIS_TDATA(6),
|
||||
O => \M_AXIS_TDATA[7]_i_4_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA[7]_i_5\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"6"
|
||||
)
|
||||
port map (
|
||||
I0 => S_AXIS_TDATA(21),
|
||||
I1 => S_AXIS_TDATA(5),
|
||||
O => \M_AXIS_TDATA[7]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA_reg[0]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(0),
|
||||
Q => M_AXIS_TDATA(0),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[10]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(10),
|
||||
Q => M_AXIS_TDATA(10),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[11]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(11),
|
||||
Q => M_AXIS_TDATA(11),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[11]_i_1\: unisim.vcomponents.CARRY4
|
||||
port map (
|
||||
CI => \M_AXIS_TDATA_reg[7]_i_1_n_0\,
|
||||
CO(3) => \M_AXIS_TDATA_reg[11]_i_1_n_0\,
|
||||
CO(2) => \M_AXIS_TDATA_reg[11]_i_1_n_1\,
|
||||
CO(1) => \M_AXIS_TDATA_reg[11]_i_1_n_2\,
|
||||
CO(0) => \M_AXIS_TDATA_reg[11]_i_1_n_3\,
|
||||
CYINIT => '0',
|
||||
DI(3 downto 0) => S_AXIS_TDATA(28 downto 25),
|
||||
O(3 downto 0) => p_0_in(11 downto 8),
|
||||
S(3) => \M_AXIS_TDATA[11]_i_2_n_0\,
|
||||
S(2) => \M_AXIS_TDATA[11]_i_3_n_0\,
|
||||
S(1) => \M_AXIS_TDATA[11]_i_4_n_0\,
|
||||
S(0) => \M_AXIS_TDATA[11]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA_reg[12]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(12),
|
||||
Q => M_AXIS_TDATA(12),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[13]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(13),
|
||||
Q => M_AXIS_TDATA(13),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[14]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(14),
|
||||
Q => M_AXIS_TDATA(14),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[15]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(15),
|
||||
Q => M_AXIS_TDATA(15),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[15]_i_1\: unisim.vcomponents.CARRY4
|
||||
port map (
|
||||
CI => \M_AXIS_TDATA_reg[11]_i_1_n_0\,
|
||||
CO(3) => \NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED\(3),
|
||||
CO(2) => \M_AXIS_TDATA_reg[15]_i_1_n_1\,
|
||||
CO(1) => \M_AXIS_TDATA_reg[15]_i_1_n_2\,
|
||||
CO(0) => \M_AXIS_TDATA_reg[15]_i_1_n_3\,
|
||||
CYINIT => '0',
|
||||
DI(3) => '0',
|
||||
DI(2) => \M_AXIS_TDATA[15]_i_2_n_0\,
|
||||
DI(1 downto 0) => S_AXIS_TDATA(30 downto 29),
|
||||
O(3 downto 0) => p_0_in(15 downto 12),
|
||||
S(3) => '1',
|
||||
S(2) => \M_AXIS_TDATA[15]_i_3_n_0\,
|
||||
S(1) => \M_AXIS_TDATA[15]_i_4_n_0\,
|
||||
S(0) => \M_AXIS_TDATA[15]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA_reg[1]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(1),
|
||||
Q => M_AXIS_TDATA(1),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[2]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(2),
|
||||
Q => M_AXIS_TDATA(2),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[3]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(3),
|
||||
Q => M_AXIS_TDATA(3),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[3]_i_1\: unisim.vcomponents.CARRY4
|
||||
port map (
|
||||
CI => '0',
|
||||
CO(3) => \M_AXIS_TDATA_reg[3]_i_1_n_0\,
|
||||
CO(2) => \M_AXIS_TDATA_reg[3]_i_1_n_1\,
|
||||
CO(1) => \M_AXIS_TDATA_reg[3]_i_1_n_2\,
|
||||
CO(0) => \M_AXIS_TDATA_reg[3]_i_1_n_3\,
|
||||
CYINIT => '0',
|
||||
DI(3 downto 0) => S_AXIS_TDATA(20 downto 17),
|
||||
O(3 downto 0) => p_0_in(3 downto 0),
|
||||
S(3) => \M_AXIS_TDATA[3]_i_2_n_0\,
|
||||
S(2) => \M_AXIS_TDATA[3]_i_3_n_0\,
|
||||
S(1) => \M_AXIS_TDATA[3]_i_4_n_0\,
|
||||
S(0) => \M_AXIS_TDATA[3]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA_reg[4]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(4),
|
||||
Q => M_AXIS_TDATA(4),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[5]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(5),
|
||||
Q => M_AXIS_TDATA(5),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[6]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(6),
|
||||
Q => M_AXIS_TDATA(6),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[7]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(7),
|
||||
Q => M_AXIS_TDATA(7),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[7]_i_1\: unisim.vcomponents.CARRY4
|
||||
port map (
|
||||
CI => \M_AXIS_TDATA_reg[3]_i_1_n_0\,
|
||||
CO(3) => \M_AXIS_TDATA_reg[7]_i_1_n_0\,
|
||||
CO(2) => \M_AXIS_TDATA_reg[7]_i_1_n_1\,
|
||||
CO(1) => \M_AXIS_TDATA_reg[7]_i_1_n_2\,
|
||||
CO(0) => \M_AXIS_TDATA_reg[7]_i_1_n_3\,
|
||||
CYINIT => '0',
|
||||
DI(3 downto 0) => S_AXIS_TDATA(24 downto 21),
|
||||
O(3 downto 0) => p_0_in(7 downto 4),
|
||||
S(3) => \M_AXIS_TDATA[7]_i_2_n_0\,
|
||||
S(2) => \M_AXIS_TDATA[7]_i_3_n_0\,
|
||||
S(1) => \M_AXIS_TDATA[7]_i_4_n_0\,
|
||||
S(0) => \M_AXIS_TDATA[7]_i_5_n_0\
|
||||
);
|
||||
\M_AXIS_TDATA_reg[8]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(8),
|
||||
Q => M_AXIS_TDATA(8),
|
||||
R => '0'
|
||||
);
|
||||
\M_AXIS_TDATA_reg[9]\: unisim.vcomponents.FDRE
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => p_0_in(9),
|
||||
Q => M_AXIS_TDATA(9),
|
||||
R => '0'
|
||||
);
|
||||
M_AXIS_TVALID_reg: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => AXIS_ACLK,
|
||||
CE => \^s_axis_tready\,
|
||||
D => S_AXIS_TVALID,
|
||||
Q => \^m_axis_tvalid\,
|
||||
R => '0'
|
||||
);
|
||||
S_AXIS_TREADY_INST_0: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"B"
|
||||
)
|
||||
port map (
|
||||
I0 => M_AXIS_TREADY,
|
||||
I1 => \^m_axis_tvalid\,
|
||||
O => \^s_axis_tready\
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of design_1_syn_axis_audio_stereo2mo_0_0 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of design_1_syn_axis_audio_stereo2mo_0_0 : entity is "design_1_syn_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of design_1_syn_axis_audio_stereo2mo_0_0 : entity is "yes";
|
||||
attribute ip_definition_source : string;
|
||||
attribute ip_definition_source of design_1_syn_axis_audio_stereo2mo_0_0 : entity is "package_project";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of design_1_syn_axis_audio_stereo2mo_0_0 : entity is "axis_audio_stereo2mono,Vivado 2023.1";
|
||||
end design_1_syn_axis_audio_stereo2mo_0_0;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_axis_audio_stereo2mo_0_0 is
|
||||
signal NLW_U0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
|
||||
attribute HAS_LAST : string;
|
||||
attribute HAS_LAST of U0 : label is "FALSE";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
attribute x_interface_info of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
attribute x_interface_info of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
attribute x_interface_parameter of M_AXIS_TVALID : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
attribute x_interface_info of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
attribute x_interface_info of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
attribute x_interface_parameter of S_AXIS_TVALID : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
attribute x_interface_info of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
attribute x_interface_info of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
begin
|
||||
U0: entity work.design_1_syn_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
|
||||
port map (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
M_AXIS_TDATA(15 downto 0) => M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => NLW_U0_M_AXIS_TLAST_UNCONNECTED,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 17) => S_AXIS_TDATA(31 downto 17),
|
||||
S_AXIS_TDATA(16) => '0',
|
||||
S_AXIS_TDATA(15 downto 1) => S_AXIS_TDATA(15 downto 1),
|
||||
S_AXIS_TDATA(0) => '0',
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID
|
||||
);
|
||||
end STRUCTURE;
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:08:33 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0_stub.v
|
||||
// Design : design_1_syn_axis_audio_stereo2mo_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
|
||||
module design_1_syn_axis_audio_stereo2mo_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA,
|
||||
S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY" */
|
||||
/* synthesis syn_force_seq_prim="AXIS_ACLK" */;
|
||||
input AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [15:0]M_AXIS_TDATA;
|
||||
input M_AXIS_TREADY;
|
||||
endmodule
|
||||
+37
@@ -0,0 +1,37 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:08:33 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0_stub.vhdl
|
||||
-- Design : design_1_syn_axis_audio_stereo2mo_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_1_syn_axis_audio_stereo2mo_0_0 is
|
||||
Port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
|
||||
end design_1_syn_axis_audio_stereo2mo_0_0;
|
||||
|
||||
architecture stub of design_1_syn_axis_audio_stereo2mo_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axis_audio_stereo2mono,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_syn_axis_audio_stereo2mo_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_syn_axis_audio_stereo2mo_0_0;
|
||||
|
||||
ARCHITECTURE design_1_syn_axis_audio_stereo2mo_0_0_arch OF design_1_syn_axis_audio_stereo2mo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_syn_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_stereo2mono IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_stereo2mono;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_stereo2mono
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_syn_axis_audio_stereo2mo_0_0_arch;
|
||||
+122
@@ -0,0 +1,122 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_syn_axis_audio_stereo2mo_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_syn_axis_audio_stereo2mo_0_0;
|
||||
|
||||
ARCHITECTURE design_1_syn_axis_audio_stereo2mo_0_0_arch OF design_1_syn_axis_audio_stereo2mo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_syn_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_stereo2mono IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_stereo2mono;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_syn_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "axis_audio_stereo2mono,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_syn_axis_audio_stereo2mo_0_0_arch : ARCHITECTURE IS "design_1_syn_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_syn_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "design_1_syn_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_stereo2mono,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,HAS_LAST=false}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_syn_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_stereo2mono
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_syn_axis_audio_stereo2mo_0_0_arch;
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 10.000 -name clk_in -waveform {0.000 5.000} [get_ports clk_in]
|
||||
+358
@@ -0,0 +1,358 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_syn_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:23a729f5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e41f4595</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:11:10 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e41f4595</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e41f4595</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_syn_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:23a729f5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_syn_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 21:04:26 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:e41f4595</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/clk_rst_generator.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/clk_rst_generator_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/clk_rst_generator_clocks.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_clk_rst_generator_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_clk_rst_generator_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_clk_rst_generator_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_clk_rst_generator_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_syn_clk_rst_generator_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_syn_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_syn_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_syn_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+375
@@ -0,0 +1,375 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:11:10 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_clk_rst_generator_0_0/design_1_syn_clk_rst_generator_0_0_sim_netlist.v
|
||||
// Design : design_1_syn_clk_rst_generator_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_syn_clk_rst_generator_0_0,clk_rst_generator,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
|
||||
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_syn_clk_rst_generator_0_0
|
||||
(clk_in,
|
||||
rst_in,
|
||||
clk,
|
||||
rst_n,
|
||||
stop_simulation);
|
||||
input clk_in;
|
||||
input rst_in;
|
||||
output clk;
|
||||
output rst_n;
|
||||
input stop_simulation;
|
||||
|
||||
wire clk;
|
||||
wire clk_in;
|
||||
wire rst_in;
|
||||
wire rst_n;
|
||||
|
||||
(* CLOCK_PERIOD = "10000" *)
|
||||
(* HAS_CLK_INPUT = "TRUE" *)
|
||||
(* HAS_RESET_INPUT = "TRUE" *)
|
||||
(* HAS_STOP_INPUT = "TRUE" *)
|
||||
design_1_syn_clk_rst_generator_0_0_clk_rst_generator U0
|
||||
(.clk(clk),
|
||||
.clk_in(clk_in),
|
||||
.rst_in(rst_in),
|
||||
.rst_n(rst_n),
|
||||
.stop_simulation(1'b0));
|
||||
endmodule
|
||||
|
||||
(* CLOCK_PERIOD = "10000" *) (* HAS_CLK_INPUT = "TRUE" *) (* HAS_RESET_INPUT = "TRUE" *)
|
||||
(* HAS_STOP_INPUT = "TRUE" *) (* ORIG_REF_NAME = "clk_rst_generator" *)
|
||||
module design_1_syn_clk_rst_generator_0_0_clk_rst_generator
|
||||
(clk_in,
|
||||
rst_in,
|
||||
clk,
|
||||
rst_n,
|
||||
stop_simulation);
|
||||
input clk_in;
|
||||
input rst_in;
|
||||
output clk;
|
||||
output rst_n;
|
||||
input stop_simulation;
|
||||
|
||||
wire [4:0]L;
|
||||
wire clk_in;
|
||||
wire [6:0]rescnt;
|
||||
wire \rescnt[3]_i_5_n_0 ;
|
||||
wire \rescnt[3]_i_6_n_0 ;
|
||||
wire \rescnt[3]_i_7_n_0 ;
|
||||
wire \rescnt[3]_i_8_n_0 ;
|
||||
wire \rescnt[6]_i_4_n_0 ;
|
||||
wire \rescnt[6]_i_5_n_0 ;
|
||||
wire \rescnt[6]_i_6_n_0 ;
|
||||
wire [6:0]rescnt_reg;
|
||||
wire \rescnt_reg[3]_i_1_n_0 ;
|
||||
wire \rescnt_reg[3]_i_1_n_1 ;
|
||||
wire \rescnt_reg[3]_i_1_n_2 ;
|
||||
wire \rescnt_reg[3]_i_1_n_3 ;
|
||||
wire \rescnt_reg[6]_i_1_n_2 ;
|
||||
wire \rescnt_reg[6]_i_1_n_3 ;
|
||||
wire rst_in;
|
||||
wire rst_in_sync;
|
||||
wire rst_n;
|
||||
wire rst_sig;
|
||||
wire rst_sig_i_1_n_0;
|
||||
wire rst_sig_i_2_n_0;
|
||||
wire rst_sig_reg_n_0;
|
||||
wire [3:2]\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED ;
|
||||
wire [3:3]\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED ;
|
||||
|
||||
assign clk = clk_in;
|
||||
LUT2 #(
|
||||
.INIT(4'hE))
|
||||
\rescnt[3]_i_2
|
||||
(.I0(rst_in_sync),
|
||||
.I1(rescnt_reg[2]),
|
||||
.O(L[2]));
|
||||
LUT5 #(
|
||||
.INIT(32'h00000001))
|
||||
\rescnt[3]_i_3
|
||||
(.I0(rescnt_reg[6]),
|
||||
.I1(rescnt_reg[4]),
|
||||
.I2(rst_in_sync),
|
||||
.I3(rescnt_reg[5]),
|
||||
.I4(rst_sig_i_2_n_0),
|
||||
.O(rst_sig));
|
||||
LUT2 #(
|
||||
.INIT(4'hE))
|
||||
\rescnt[3]_i_4
|
||||
(.I0(rst_in_sync),
|
||||
.I1(rescnt_reg[0]),
|
||||
.O(L[0]));
|
||||
LUT3 #(
|
||||
.INIT(8'hF9))
|
||||
\rescnt[3]_i_5
|
||||
(.I0(rescnt_reg[2]),
|
||||
.I1(rescnt_reg[3]),
|
||||
.I2(rst_in_sync),
|
||||
.O(\rescnt[3]_i_5_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'h000000000001FFFE))
|
||||
\rescnt[3]_i_6
|
||||
(.I0(rst_sig_i_2_n_0),
|
||||
.I1(rescnt_reg[5]),
|
||||
.I2(rescnt_reg[4]),
|
||||
.I3(rescnt_reg[6]),
|
||||
.I4(rescnt_reg[2]),
|
||||
.I5(rst_in_sync),
|
||||
.O(\rescnt[3]_i_6_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'h000000000001FFFE))
|
||||
\rescnt[3]_i_7
|
||||
(.I0(rst_sig_i_2_n_0),
|
||||
.I1(rescnt_reg[5]),
|
||||
.I2(rescnt_reg[4]),
|
||||
.I3(rescnt_reg[6]),
|
||||
.I4(rescnt_reg[1]),
|
||||
.I5(rst_in_sync),
|
||||
.O(\rescnt[3]_i_7_n_0 ));
|
||||
LUT6 #(
|
||||
.INIT(64'h0055005500550056))
|
||||
\rescnt[3]_i_8
|
||||
(.I0(rescnt_reg[0]),
|
||||
.I1(rst_sig_i_2_n_0),
|
||||
.I2(rescnt_reg[5]),
|
||||
.I3(rst_in_sync),
|
||||
.I4(rescnt_reg[4]),
|
||||
.I5(rescnt_reg[6]),
|
||||
.O(\rescnt[3]_i_8_n_0 ));
|
||||
LUT2 #(
|
||||
.INIT(4'hE))
|
||||
\rescnt[6]_i_2
|
||||
(.I0(rst_in_sync),
|
||||
.I1(rescnt_reg[4]),
|
||||
.O(L[4]));
|
||||
LUT2 #(
|
||||
.INIT(4'hE))
|
||||
\rescnt[6]_i_3
|
||||
(.I0(rst_in_sync),
|
||||
.I1(rescnt_reg[3]),
|
||||
.O(L[3]));
|
||||
LUT3 #(
|
||||
.INIT(8'hF9))
|
||||
\rescnt[6]_i_4
|
||||
(.I0(rescnt_reg[5]),
|
||||
.I1(rescnt_reg[6]),
|
||||
.I2(rst_in_sync),
|
||||
.O(\rescnt[6]_i_4_n_0 ));
|
||||
LUT3 #(
|
||||
.INIT(8'hF9))
|
||||
\rescnt[6]_i_5
|
||||
(.I0(rescnt_reg[4]),
|
||||
.I1(rescnt_reg[5]),
|
||||
.I2(rst_in_sync),
|
||||
.O(\rescnt[6]_i_5_n_0 ));
|
||||
LUT3 #(
|
||||
.INIT(8'hF9))
|
||||
\rescnt[6]_i_6
|
||||
(.I0(rescnt_reg[3]),
|
||||
.I1(rescnt_reg[4]),
|
||||
.I2(rst_in_sync),
|
||||
.O(\rescnt[6]_i_6_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[0]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[0]),
|
||||
.Q(rescnt_reg[0]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[1]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[1]),
|
||||
.Q(rescnt_reg[1]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[2]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[2]),
|
||||
.Q(rescnt_reg[2]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[3]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[3]),
|
||||
.Q(rescnt_reg[3]),
|
||||
.R(1'b0));
|
||||
(* ADDER_THRESHOLD = "35" *)
|
||||
CARRY4 \rescnt_reg[3]_i_1
|
||||
(.CI(1'b0),
|
||||
.CO({\rescnt_reg[3]_i_1_n_0 ,\rescnt_reg[3]_i_1_n_1 ,\rescnt_reg[3]_i_1_n_2 ,\rescnt_reg[3]_i_1_n_3 }),
|
||||
.CYINIT(1'b0),
|
||||
.DI({L[2],rst_sig,rst_sig_i_1_n_0,L[0]}),
|
||||
.O(rescnt[3:0]),
|
||||
.S({\rescnt[3]_i_5_n_0 ,\rescnt[3]_i_6_n_0 ,\rescnt[3]_i_7_n_0 ,\rescnt[3]_i_8_n_0 }));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[4]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[4]),
|
||||
.Q(rescnt_reg[4]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[5]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[5]),
|
||||
.Q(rescnt_reg[5]),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\rescnt_reg[6]
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rescnt[6]),
|
||||
.Q(rescnt_reg[6]),
|
||||
.R(1'b0));
|
||||
(* ADDER_THRESHOLD = "35" *)
|
||||
CARRY4 \rescnt_reg[6]_i_1
|
||||
(.CI(\rescnt_reg[3]_i_1_n_0 ),
|
||||
.CO({\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED [3:2],\rescnt_reg[6]_i_1_n_2 ,\rescnt_reg[6]_i_1_n_3 }),
|
||||
.CYINIT(1'b0),
|
||||
.DI({1'b0,1'b0,L[4:3]}),
|
||||
.O({\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED [3],rescnt[6:4]}),
|
||||
.S({1'b0,\rescnt[6]_i_4_n_0 ,\rescnt[6]_i_5_n_0 ,\rescnt[6]_i_6_n_0 }));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
rst_in_sync_reg
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rst_in),
|
||||
.Q(rst_in_sync),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
rst_n_INST_0
|
||||
(.I0(rst_sig_reg_n_0),
|
||||
.O(rst_n));
|
||||
LUT5 #(
|
||||
.INIT(32'hFFFFFFFE))
|
||||
rst_sig_i_1
|
||||
(.I0(rst_sig_i_2_n_0),
|
||||
.I1(rescnt_reg[5]),
|
||||
.I2(rst_in_sync),
|
||||
.I3(rescnt_reg[4]),
|
||||
.I4(rescnt_reg[6]),
|
||||
.O(rst_sig_i_1_n_0));
|
||||
LUT5 #(
|
||||
.INIT(32'hFFFFFFFE))
|
||||
rst_sig_i_2
|
||||
(.I0(rescnt_reg[2]),
|
||||
.I1(rescnt_reg[3]),
|
||||
.I2(rst_in_sync),
|
||||
.I3(rescnt_reg[0]),
|
||||
.I4(rescnt_reg[1]),
|
||||
.O(rst_sig_i_2_n_0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
rst_sig_reg
|
||||
(.C(clk_in),
|
||||
.CE(1'b1),
|
||||
.D(rst_sig_i_1_n_0),
|
||||
.Q(rst_sig_reg_n_0),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+404
@@ -0,0 +1,404 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:11:10 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_clk_rst_generator_0_0/design_1_syn_clk_rst_generator_0_0_sim_netlist.vhdl
|
||||
-- Design : design_1_syn_clk_rst_generator_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_clk_rst_generator_0_0_clk_rst_generator is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
attribute CLOCK_PERIOD : integer;
|
||||
attribute CLOCK_PERIOD of design_1_syn_clk_rst_generator_0_0_clk_rst_generator : entity is 10000;
|
||||
attribute HAS_CLK_INPUT : string;
|
||||
attribute HAS_CLK_INPUT of design_1_syn_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
|
||||
attribute HAS_RESET_INPUT : string;
|
||||
attribute HAS_RESET_INPUT of design_1_syn_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
|
||||
attribute HAS_STOP_INPUT : string;
|
||||
attribute HAS_STOP_INPUT of design_1_syn_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of design_1_syn_clk_rst_generator_0_0_clk_rst_generator : entity is "clk_rst_generator";
|
||||
end design_1_syn_clk_rst_generator_0_0_clk_rst_generator;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_clk_rst_generator_0_0_clk_rst_generator is
|
||||
signal L : STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||
signal \^clk_in\ : STD_LOGIC;
|
||||
signal rescnt : STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
signal \rescnt[3]_i_5_n_0\ : STD_LOGIC;
|
||||
signal \rescnt[3]_i_6_n_0\ : STD_LOGIC;
|
||||
signal \rescnt[3]_i_7_n_0\ : STD_LOGIC;
|
||||
signal \rescnt[3]_i_8_n_0\ : STD_LOGIC;
|
||||
signal \rescnt[6]_i_4_n_0\ : STD_LOGIC;
|
||||
signal \rescnt[6]_i_5_n_0\ : STD_LOGIC;
|
||||
signal \rescnt[6]_i_6_n_0\ : STD_LOGIC;
|
||||
signal rescnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
signal \rescnt_reg[3]_i_1_n_0\ : STD_LOGIC;
|
||||
signal \rescnt_reg[3]_i_1_n_1\ : STD_LOGIC;
|
||||
signal \rescnt_reg[3]_i_1_n_2\ : STD_LOGIC;
|
||||
signal \rescnt_reg[3]_i_1_n_3\ : STD_LOGIC;
|
||||
signal \rescnt_reg[6]_i_1_n_2\ : STD_LOGIC;
|
||||
signal \rescnt_reg[6]_i_1_n_3\ : STD_LOGIC;
|
||||
signal rst_in_sync : STD_LOGIC;
|
||||
signal rst_sig : STD_LOGIC;
|
||||
signal rst_sig_i_1_n_0 : STD_LOGIC;
|
||||
signal rst_sig_i_2_n_0 : STD_LOGIC;
|
||||
signal rst_sig_reg_n_0 : STD_LOGIC;
|
||||
signal \NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
|
||||
signal \NLW_rescnt_reg[6]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
|
||||
attribute ADDER_THRESHOLD : integer;
|
||||
attribute ADDER_THRESHOLD of \rescnt_reg[3]_i_1\ : label is 35;
|
||||
attribute ADDER_THRESHOLD of \rescnt_reg[6]_i_1\ : label is 35;
|
||||
begin
|
||||
\^clk_in\ <= clk_in;
|
||||
clk <= \^clk_in\;
|
||||
\rescnt[3]_i_2\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"E"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_in_sync,
|
||||
I1 => rescnt_reg(2),
|
||||
O => L(2)
|
||||
);
|
||||
\rescnt[3]_i_3\: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"00000001"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(6),
|
||||
I1 => rescnt_reg(4),
|
||||
I2 => rst_in_sync,
|
||||
I3 => rescnt_reg(5),
|
||||
I4 => rst_sig_i_2_n_0,
|
||||
O => rst_sig
|
||||
);
|
||||
\rescnt[3]_i_4\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"E"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_in_sync,
|
||||
I1 => rescnt_reg(0),
|
||||
O => L(0)
|
||||
);
|
||||
\rescnt[3]_i_5\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"F9"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(2),
|
||||
I1 => rescnt_reg(3),
|
||||
I2 => rst_in_sync,
|
||||
O => \rescnt[3]_i_5_n_0\
|
||||
);
|
||||
\rescnt[3]_i_6\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"000000000001FFFE"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_sig_i_2_n_0,
|
||||
I1 => rescnt_reg(5),
|
||||
I2 => rescnt_reg(4),
|
||||
I3 => rescnt_reg(6),
|
||||
I4 => rescnt_reg(2),
|
||||
I5 => rst_in_sync,
|
||||
O => \rescnt[3]_i_6_n_0\
|
||||
);
|
||||
\rescnt[3]_i_7\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"000000000001FFFE"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_sig_i_2_n_0,
|
||||
I1 => rescnt_reg(5),
|
||||
I2 => rescnt_reg(4),
|
||||
I3 => rescnt_reg(6),
|
||||
I4 => rescnt_reg(1),
|
||||
I5 => rst_in_sync,
|
||||
O => \rescnt[3]_i_7_n_0\
|
||||
);
|
||||
\rescnt[3]_i_8\: unisim.vcomponents.LUT6
|
||||
generic map(
|
||||
INIT => X"0055005500550056"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(0),
|
||||
I1 => rst_sig_i_2_n_0,
|
||||
I2 => rescnt_reg(5),
|
||||
I3 => rst_in_sync,
|
||||
I4 => rescnt_reg(4),
|
||||
I5 => rescnt_reg(6),
|
||||
O => \rescnt[3]_i_8_n_0\
|
||||
);
|
||||
\rescnt[6]_i_2\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"E"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_in_sync,
|
||||
I1 => rescnt_reg(4),
|
||||
O => L(4)
|
||||
);
|
||||
\rescnt[6]_i_3\: unisim.vcomponents.LUT2
|
||||
generic map(
|
||||
INIT => X"E"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_in_sync,
|
||||
I1 => rescnt_reg(3),
|
||||
O => L(3)
|
||||
);
|
||||
\rescnt[6]_i_4\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"F9"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(5),
|
||||
I1 => rescnt_reg(6),
|
||||
I2 => rst_in_sync,
|
||||
O => \rescnt[6]_i_4_n_0\
|
||||
);
|
||||
\rescnt[6]_i_5\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"F9"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(4),
|
||||
I1 => rescnt_reg(5),
|
||||
I2 => rst_in_sync,
|
||||
O => \rescnt[6]_i_5_n_0\
|
||||
);
|
||||
\rescnt[6]_i_6\: unisim.vcomponents.LUT3
|
||||
generic map(
|
||||
INIT => X"F9"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(3),
|
||||
I1 => rescnt_reg(4),
|
||||
I2 => rst_in_sync,
|
||||
O => \rescnt[6]_i_6_n_0\
|
||||
);
|
||||
\rescnt_reg[0]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(0),
|
||||
Q => rescnt_reg(0),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[1]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(1),
|
||||
Q => rescnt_reg(1),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[2]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(2),
|
||||
Q => rescnt_reg(2),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[3]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(3),
|
||||
Q => rescnt_reg(3),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[3]_i_1\: unisim.vcomponents.CARRY4
|
||||
port map (
|
||||
CI => '0',
|
||||
CO(3) => \rescnt_reg[3]_i_1_n_0\,
|
||||
CO(2) => \rescnt_reg[3]_i_1_n_1\,
|
||||
CO(1) => \rescnt_reg[3]_i_1_n_2\,
|
||||
CO(0) => \rescnt_reg[3]_i_1_n_3\,
|
||||
CYINIT => '0',
|
||||
DI(3) => L(2),
|
||||
DI(2) => rst_sig,
|
||||
DI(1) => rst_sig_i_1_n_0,
|
||||
DI(0) => L(0),
|
||||
O(3 downto 0) => rescnt(3 downto 0),
|
||||
S(3) => \rescnt[3]_i_5_n_0\,
|
||||
S(2) => \rescnt[3]_i_6_n_0\,
|
||||
S(1) => \rescnt[3]_i_7_n_0\,
|
||||
S(0) => \rescnt[3]_i_8_n_0\
|
||||
);
|
||||
\rescnt_reg[4]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(4),
|
||||
Q => rescnt_reg(4),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[5]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(5),
|
||||
Q => rescnt_reg(5),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[6]\: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '1'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rescnt(6),
|
||||
Q => rescnt_reg(6),
|
||||
R => '0'
|
||||
);
|
||||
\rescnt_reg[6]_i_1\: unisim.vcomponents.CARRY4
|
||||
port map (
|
||||
CI => \rescnt_reg[3]_i_1_n_0\,
|
||||
CO(3 downto 2) => \NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED\(3 downto 2),
|
||||
CO(1) => \rescnt_reg[6]_i_1_n_2\,
|
||||
CO(0) => \rescnt_reg[6]_i_1_n_3\,
|
||||
CYINIT => '0',
|
||||
DI(3 downto 2) => B"00",
|
||||
DI(1 downto 0) => L(4 downto 3),
|
||||
O(3) => \NLW_rescnt_reg[6]_i_1_O_UNCONNECTED\(3),
|
||||
O(2 downto 0) => rescnt(6 downto 4),
|
||||
S(3) => '0',
|
||||
S(2) => \rescnt[6]_i_4_n_0\,
|
||||
S(1) => \rescnt[6]_i_5_n_0\,
|
||||
S(0) => \rescnt[6]_i_6_n_0\
|
||||
);
|
||||
rst_in_sync_reg: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rst_in,
|
||||
Q => rst_in_sync,
|
||||
R => '0'
|
||||
);
|
||||
rst_n_INST_0: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_sig_reg_n_0,
|
||||
O => rst_n
|
||||
);
|
||||
rst_sig_i_1: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"FFFFFFFE"
|
||||
)
|
||||
port map (
|
||||
I0 => rst_sig_i_2_n_0,
|
||||
I1 => rescnt_reg(5),
|
||||
I2 => rst_in_sync,
|
||||
I3 => rescnt_reg(4),
|
||||
I4 => rescnt_reg(6),
|
||||
O => rst_sig_i_1_n_0
|
||||
);
|
||||
rst_sig_i_2: unisim.vcomponents.LUT5
|
||||
generic map(
|
||||
INIT => X"FFFFFFFE"
|
||||
)
|
||||
port map (
|
||||
I0 => rescnt_reg(2),
|
||||
I1 => rescnt_reg(3),
|
||||
I2 => rst_in_sync,
|
||||
I3 => rescnt_reg(0),
|
||||
I4 => rescnt_reg(1),
|
||||
O => rst_sig_i_2_n_0
|
||||
);
|
||||
rst_sig_reg: unisim.vcomponents.FDRE
|
||||
generic map(
|
||||
INIT => '0'
|
||||
)
|
||||
port map (
|
||||
C => \^clk_in\,
|
||||
CE => '1',
|
||||
D => rst_sig_i_1_n_0,
|
||||
Q => rst_sig_reg_n_0,
|
||||
R => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_syn_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of design_1_syn_clk_rst_generator_0_0 : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of design_1_syn_clk_rst_generator_0_0 : entity is "design_1_syn_clk_rst_generator_0_0,clk_rst_generator,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of design_1_syn_clk_rst_generator_0_0 : entity is "yes";
|
||||
attribute ip_definition_source : string;
|
||||
attribute ip_definition_source of design_1_syn_clk_rst_generator_0_0 : entity is "package_project";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of design_1_syn_clk_rst_generator_0_0 : entity is "clk_rst_generator,Vivado 2023.1";
|
||||
end design_1_syn_clk_rst_generator_0_0;
|
||||
|
||||
architecture STRUCTURE of design_1_syn_clk_rst_generator_0_0 is
|
||||
attribute CLOCK_PERIOD : integer;
|
||||
attribute CLOCK_PERIOD of U0 : label is 10000;
|
||||
attribute HAS_CLK_INPUT : string;
|
||||
attribute HAS_CLK_INPUT of U0 : label is "TRUE";
|
||||
attribute HAS_RESET_INPUT : string;
|
||||
attribute HAS_RESET_INPUT of U0 : label is "TRUE";
|
||||
attribute HAS_STOP_INPUT : string;
|
||||
attribute HAS_STOP_INPUT of U0 : label is "TRUE";
|
||||
begin
|
||||
U0: entity work.design_1_syn_clk_rst_generator_0_0_clk_rst_generator
|
||||
port map (
|
||||
clk => clk,
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
+27
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Mon Oct 28 22:11:10 2024
|
||||
// Host : Bastistablet running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_clk_rst_generator_0_0/design_1_syn_clk_rst_generator_0_0_stub.v
|
||||
// Design : design_1_syn_clk_rst_generator_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
|
||||
module design_1_syn_clk_rst_generator_0_0(clk_in, rst_in, clk, rst_n, stop_simulation)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst_in,rst_n,stop_simulation" */
|
||||
/* synthesis syn_force_seq_prim="clk_in" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk_in /* synthesis syn_isclock = 1 */;
|
||||
input rst_in;
|
||||
output clk /* synthesis syn_isclock = 1 */;
|
||||
output rst_n;
|
||||
input stop_simulation;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Mon Oct 28 22:11:10 2024
|
||||
-- Host : Bastistablet running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.gen/sources_1/bd/design_1_syn/ip/design_1_syn_clk_rst_generator_0_0/design_1_syn_clk_rst_generator_0_0_stub.vhdl
|
||||
-- Design : design_1_syn_clk_rst_generator_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_1_syn_clk_rst_generator_0_0 is
|
||||
Port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
|
||||
end design_1_syn_clk_rst_generator_0_0;
|
||||
|
||||
architecture stub of design_1_syn_clk_rst_generator_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_in,rst_in,clk,rst_n,stop_simulation";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "clk_rst_generator,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_syn_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_syn_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_syn_clk_rst_generator_0_0_arch OF design_1_syn_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_syn_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 10000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_syn_clk_rst_generator_0_0_arch;
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_syn_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_syn_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_syn_clk_rst_generator_0_0_arch OF design_1_syn_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_syn_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_syn_clk_rst_generator_0_0_arch: ARCHITECTURE IS "clk_rst_generator,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_syn_clk_rst_generator_0_0_arch : ARCHITECTURE IS "design_1_syn_clk_rst_generator_0_0,clk_rst_generator,{}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_syn_clk_rst_generator_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 10000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_syn_clk_rst_generator_0_0_arch;
|
||||
+429
@@ -0,0 +1,429 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x14BE19C5147B5D81",
|
||||
"design_src": "SBD",
|
||||
"device": "xc7z020clg400-1",
|
||||
"name": "bd_3e86",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"scoped": "true",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"ila_lib": "",
|
||||
"g_inst": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "SLOT_0_AXIS:SLOT_1_AXIS"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "resetn"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"ila_lib": {
|
||||
"vlnv": "xilinx.com:ip:ila:6.2",
|
||||
"xci_name": "bd_3e86_ila_lib_0",
|
||||
"xci_path": "ip\\ip_0\\bd_3e86_ila_lib_0.xci",
|
||||
"inst_hier_path": "ila_lib",
|
||||
"parameters": {
|
||||
"ALL_PROBE_SAME_MU": {
|
||||
"value": "TRUE"
|
||||
},
|
||||
"ALL_PROBE_SAME_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_ADV_TRIGGER": {
|
||||
"value": "FALSE"
|
||||
},
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "1024"
|
||||
},
|
||||
"C_EN_STRG_QUAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_ILA_CLK_FREQ": {
|
||||
"value": "100000000"
|
||||
},
|
||||
"C_INPUT_PIPE_STAGES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_MONITOR_TYPE": {
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "8"
|
||||
},
|
||||
"C_PROBE0_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE0_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE2_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE2_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE3_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE3_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE4_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE4_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE5_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE5_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE6_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE6_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE7_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE7_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_TRIGIN_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_TRIGOUT_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_XLNX_HW_PROBE_INFO": {
|
||||
"value": "DEFAULT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"g_inst": {
|
||||
"vlnv": "xilinx.com:ip:gigantic_mux:1.0",
|
||||
"xci_name": "bd_3e86_g_inst_0",
|
||||
"xci_path": "ip\\ip_1\\bd_3e86_g_inst_0.xci",
|
||||
"inst_hier_path": "g_inst",
|
||||
"parameters": {
|
||||
"C_EN_GIGAMUX": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_0_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_1_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_MON_MODE": {
|
||||
"value": "FT"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"SLOT_0_AXIS",
|
||||
"g_inst/slot_0_axis"
|
||||
]
|
||||
},
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"SLOT_1_AXIS",
|
||||
"g_inst/slot_1_axis"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"ila_lib/clk",
|
||||
"g_inst/aclk"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tdata",
|
||||
"ila_lib/probe0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tlast",
|
||||
"ila_lib/probe3"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tready",
|
||||
"ila_lib/probe2"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tvalid",
|
||||
"ila_lib/probe1"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tdata",
|
||||
"ila_lib/probe4"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tlast",
|
||||
"ila_lib/probe7"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tready",
|
||||
"ila_lib/probe6"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tvalid",
|
||||
"ila_lib/probe5"
|
||||
]
|
||||
},
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
"g_inst/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+51
@@ -0,0 +1,51 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_3e86" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730149476"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1730149476"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730149476"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730149476"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_3e86.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_3e86.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_3e86_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_syn_system_ila_0_2.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_syn_system_ila_0_2.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_3e86.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+54
@@ -0,0 +1,54 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86_wrapper.bd
|
||||
//Design : bd_3e86_wrapper
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module bd_3e86_wrapper
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
input [15:0]SLOT_0_AXIS_tdata;
|
||||
input SLOT_0_AXIS_tlast;
|
||||
input SLOT_0_AXIS_tready;
|
||||
input SLOT_0_AXIS_tvalid;
|
||||
input [15:0]SLOT_1_AXIS_tdata;
|
||||
input SLOT_1_AXIS_tlast;
|
||||
input SLOT_1_AXIS_tready;
|
||||
input SLOT_1_AXIS_tvalid;
|
||||
input clk;
|
||||
input resetn;
|
||||
|
||||
wire [15:0]SLOT_0_AXIS_tdata;
|
||||
wire SLOT_0_AXIS_tlast;
|
||||
wire SLOT_0_AXIS_tready;
|
||||
wire SLOT_0_AXIS_tvalid;
|
||||
wire [15:0]SLOT_1_AXIS_tdata;
|
||||
wire SLOT_1_AXIS_tlast;
|
||||
wire SLOT_1_AXIS_tready;
|
||||
wire SLOT_1_AXIS_tvalid;
|
||||
wire clk;
|
||||
wire resetn;
|
||||
|
||||
bd_3e86 bd_3e86_i
|
||||
(.SLOT_0_AXIS_tdata(SLOT_0_AXIS_tdata),
|
||||
.SLOT_0_AXIS_tlast(SLOT_0_AXIS_tlast),
|
||||
.SLOT_0_AXIS_tready(SLOT_0_AXIS_tready),
|
||||
.SLOT_0_AXIS_tvalid(SLOT_0_AXIS_tvalid),
|
||||
.SLOT_1_AXIS_tdata(SLOT_1_AXIS_tdata),
|
||||
.SLOT_1_AXIS_tlast(SLOT_1_AXIS_tlast),
|
||||
.SLOT_1_AXIS_tready(SLOT_1_AXIS_tready),
|
||||
.SLOT_1_AXIS_tvalid(SLOT_1_AXIS_tvalid),
|
||||
.clk(clk),
|
||||
.resetn(resetn));
|
||||
endmodule
|
||||
+4824
File diff suppressed because it is too large
Load Diff
+6306
File diff suppressed because it is too large
Load Diff
+74950
File diff suppressed because it is too large
Load Diff
+69
@@ -0,0 +1,69 @@
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for ILA core
|
||||
|
||||
|
||||
|
||||
create_clock -name ILA_CLK -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+103
@@ -0,0 +1,103 @@
|
||||
##
|
||||
## ARM and HALT transfer false paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Register False Paths
|
||||
##
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
|
||||
#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
|
||||
|
||||
##
|
||||
## ILA Capture Block False Paths
|
||||
##
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Capture State to XSDB register False Paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
|
||||
|
||||
|
||||
##
|
||||
## Waivers
|
||||
##
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
|
||||
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
|
||||
+76
@@ -0,0 +1,76 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module bd_3e86_ila_lib_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [15 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [15 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [0 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
|
||||
|
||||
endmodule
|
||||
+4254
File diff suppressed because it is too large
Load Diff
+2882
File diff suppressed because it is too large
Load Diff
+113892
File diff suppressed because it is too large
Load Diff
+4882
File diff suppressed because it is too large
Load Diff
+4118
File diff suppressed because it is too large
Load Diff
+4178
File diff suppressed because it is too large
Load Diff
+9
@@ -0,0 +1,9 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"bd_3e86": {
|
||||
"proto_instances": {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86.bd
|
||||
//Design : bd_3e86
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_3e86,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_3e86,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_syn_system_ila_0_2.hwdef" *)
|
||||
module bd_3e86
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_0_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_0_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TLAST" *) input SLOT_0_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TREADY" *) input SLOT_0_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TVALID" *) input SLOT_0_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_1_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST" *) input SLOT_1_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY" *) input SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID" *) input SLOT_1_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXIS:SLOT_1_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
|
||||
|
||||
wire [15:0]Conn1_TDATA;
|
||||
wire Conn1_TLAST;
|
||||
wire Conn1_TREADY;
|
||||
wire Conn1_TVALID;
|
||||
wire [15:0]Conn_TDATA;
|
||||
wire Conn_TLAST;
|
||||
wire Conn_TREADY;
|
||||
wire Conn_TVALID;
|
||||
wire clk_1;
|
||||
wire [15:0]net_slot_0_axis_tdata;
|
||||
wire net_slot_0_axis_tlast;
|
||||
wire net_slot_0_axis_tready;
|
||||
wire net_slot_0_axis_tvalid;
|
||||
wire [15:0]net_slot_1_axis_tdata;
|
||||
wire net_slot_1_axis_tlast;
|
||||
wire net_slot_1_axis_tready;
|
||||
wire net_slot_1_axis_tvalid;
|
||||
wire resetn_1;
|
||||
|
||||
assign Conn1_TDATA = SLOT_1_AXIS_tdata[15:0];
|
||||
assign Conn1_TLAST = SLOT_1_AXIS_tlast;
|
||||
assign Conn1_TREADY = SLOT_1_AXIS_tready;
|
||||
assign Conn1_TVALID = SLOT_1_AXIS_tvalid;
|
||||
assign Conn_TDATA = SLOT_0_AXIS_tdata[15:0];
|
||||
assign Conn_TLAST = SLOT_0_AXIS_tlast;
|
||||
assign Conn_TREADY = SLOT_0_AXIS_tready;
|
||||
assign Conn_TVALID = SLOT_0_AXIS_tvalid;
|
||||
assign clk_1 = clk;
|
||||
assign resetn_1 = resetn;
|
||||
bd_3e86_g_inst_0 g_inst
|
||||
(.aclk(clk_1),
|
||||
.aresetn(resetn_1),
|
||||
.m_slot_0_axis_tdata(net_slot_0_axis_tdata),
|
||||
.m_slot_0_axis_tlast(net_slot_0_axis_tlast),
|
||||
.m_slot_0_axis_tready(net_slot_0_axis_tready),
|
||||
.m_slot_0_axis_tvalid(net_slot_0_axis_tvalid),
|
||||
.m_slot_1_axis_tdata(net_slot_1_axis_tdata),
|
||||
.m_slot_1_axis_tlast(net_slot_1_axis_tlast),
|
||||
.m_slot_1_axis_tready(net_slot_1_axis_tready),
|
||||
.m_slot_1_axis_tvalid(net_slot_1_axis_tvalid),
|
||||
.slot_0_axis_tdata(Conn_TDATA),
|
||||
.slot_0_axis_tlast(Conn_TLAST),
|
||||
.slot_0_axis_tready(Conn_TREADY),
|
||||
.slot_0_axis_tvalid(Conn_TVALID),
|
||||
.slot_1_axis_tdata(Conn1_TDATA),
|
||||
.slot_1_axis_tlast(Conn1_TLAST),
|
||||
.slot_1_axis_tready(Conn1_TREADY),
|
||||
.slot_1_axis_tvalid(Conn1_TVALID));
|
||||
bd_3e86_ila_lib_0 ila_lib
|
||||
(.clk(clk_1),
|
||||
.probe0(net_slot_0_axis_tdata),
|
||||
.probe1(net_slot_0_axis_tvalid),
|
||||
.probe2(net_slot_0_axis_tready),
|
||||
.probe3(net_slot_0_axis_tlast),
|
||||
.probe4(net_slot_1_axis_tdata),
|
||||
.probe5(net_slot_1_axis_tvalid),
|
||||
.probe6(net_slot_1_axis_tready),
|
||||
.probe7(net_slot_1_axis_tlast));
|
||||
endmodule
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86.bd
|
||||
//Design : bd_3e86
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_3e86,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_3e86,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_syn_system_ila_0_2.hwdef" *)
|
||||
module bd_3e86
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_0_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_0_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TLAST" *) input SLOT_0_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TREADY" *) input SLOT_0_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TVALID" *) input SLOT_0_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_1_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST" *) input SLOT_1_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY" *) input SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID" *) input SLOT_1_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXIS:SLOT_1_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
|
||||
|
||||
wire [15:0]Conn1_TDATA;
|
||||
wire Conn1_TLAST;
|
||||
wire Conn1_TREADY;
|
||||
wire Conn1_TVALID;
|
||||
wire [15:0]Conn_TDATA;
|
||||
wire Conn_TLAST;
|
||||
wire Conn_TREADY;
|
||||
wire Conn_TVALID;
|
||||
wire clk_1;
|
||||
wire [15:0]net_slot_0_axis_tdata;
|
||||
wire net_slot_0_axis_tlast;
|
||||
wire net_slot_0_axis_tready;
|
||||
wire net_slot_0_axis_tvalid;
|
||||
wire [15:0]net_slot_1_axis_tdata;
|
||||
wire net_slot_1_axis_tlast;
|
||||
wire net_slot_1_axis_tready;
|
||||
wire net_slot_1_axis_tvalid;
|
||||
wire resetn_1;
|
||||
|
||||
assign Conn1_TDATA = SLOT_1_AXIS_tdata[15:0];
|
||||
assign Conn1_TLAST = SLOT_1_AXIS_tlast;
|
||||
assign Conn1_TREADY = SLOT_1_AXIS_tready;
|
||||
assign Conn1_TVALID = SLOT_1_AXIS_tvalid;
|
||||
assign Conn_TDATA = SLOT_0_AXIS_tdata[15:0];
|
||||
assign Conn_TLAST = SLOT_0_AXIS_tlast;
|
||||
assign Conn_TREADY = SLOT_0_AXIS_tready;
|
||||
assign Conn_TVALID = SLOT_0_AXIS_tvalid;
|
||||
assign clk_1 = clk;
|
||||
assign resetn_1 = resetn;
|
||||
bd_3e86_g_inst_0 g_inst
|
||||
(.aclk(clk_1),
|
||||
.aresetn(resetn_1),
|
||||
.m_slot_0_axis_tdata(net_slot_0_axis_tdata),
|
||||
.m_slot_0_axis_tlast(net_slot_0_axis_tlast),
|
||||
.m_slot_0_axis_tready(net_slot_0_axis_tready),
|
||||
.m_slot_0_axis_tvalid(net_slot_0_axis_tvalid),
|
||||
.m_slot_1_axis_tdata(net_slot_1_axis_tdata),
|
||||
.m_slot_1_axis_tlast(net_slot_1_axis_tlast),
|
||||
.m_slot_1_axis_tready(net_slot_1_axis_tready),
|
||||
.m_slot_1_axis_tvalid(net_slot_1_axis_tvalid),
|
||||
.slot_0_axis_tdata(Conn_TDATA),
|
||||
.slot_0_axis_tlast(Conn_TLAST),
|
||||
.slot_0_axis_tready(Conn_TREADY),
|
||||
.slot_0_axis_tvalid(Conn_TVALID),
|
||||
.slot_1_axis_tdata(Conn1_TDATA),
|
||||
.slot_1_axis_tlast(Conn1_TLAST),
|
||||
.slot_1_axis_tready(Conn1_TREADY),
|
||||
.slot_1_axis_tvalid(Conn1_TVALID));
|
||||
bd_3e86_ila_lib_0 ila_lib
|
||||
(.clk(clk_1),
|
||||
.probe0(net_slot_0_axis_tdata),
|
||||
.probe1(net_slot_0_axis_tvalid),
|
||||
.probe2(net_slot_0_axis_tready),
|
||||
.probe3(net_slot_0_axis_tlast),
|
||||
.probe4(net_slot_1_axis_tdata),
|
||||
.probe5(net_slot_1_axis_tvalid),
|
||||
.probe6(net_slot_1_axis_tready),
|
||||
.probe7(net_slot_1_axis_tlast));
|
||||
endmodule
|
||||
BIN
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user