M5: Hardware Design fertig
This commit is contained in:
Matthias Biermann
@@ -0,0 +1,86 @@
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# Created by https://www.toptal.com/developers/gitignore/api/vivado
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# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
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### Vivado ###
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#########################################################################################################
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## This is an example .gitignore file for Vivado, please treat it as an example as
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## it might not be complete. In addition, XAPP 1165 should be followed.
|
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#########
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#Exclude all
|
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*
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!*/
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!.gitignore
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###########################################################################
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## VIVADO
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#Source files:
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#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
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!*.vhd
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!*.v
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!*.sv
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!*.bd
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||||
!*.edif
|
||||
#IP files
|
||||
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
|
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#.xci + .dcp: implementation possible but not re-synthesis
|
||||
#*.xci(www.spiritconsortium.org)
|
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!*.xci
|
||||
#.xcix: Core container file
|
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#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
|
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!*.xcix
|
||||
#*.dcp(checkpoint files)
|
||||
!*.dcp
|
||||
!*.vds
|
||||
!*.pb
|
||||
#All bd comments and layout coordinates are stored within .ui
|
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!*.ui
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||||
!*.ooc
|
||||
#System Generator
|
||||
!*.mdl
|
||||
!*.slx
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||||
!*.bxml
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||||
#Simulation logic analyzer
|
||||
!*.wcfg
|
||||
!*.coe
|
||||
#MIG
|
||||
!*.prj
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!*.mem
|
||||
#Project files
|
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#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
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#Do NOT ignore *.xpr files
|
||||
!*.xpr
|
||||
#Include *.xml files for 2013.4 or earlier version
|
||||
!*.xml
|
||||
#Constraint files
|
||||
#Do NOT ignore *.xdc files
|
||||
!*.xdc
|
||||
#TCL - files
|
||||
!*.tcl
|
||||
#Journal - files
|
||||
!*.jou
|
||||
#Reports
|
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!*.rpt
|
||||
!*.txt
|
||||
!*.vdi
|
||||
#C-files
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!*.c
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!*.h
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!*.elf
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!*.bmm
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!*.xmp
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# End of https://www.toptal.com/developers/gitignore/api/vivado
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# Vidado project directories which are not needed
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.Xil/
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*.cache/
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*.hw/
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*.ip_user_files/
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*.runs/
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*.sim/
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# design checkpoint file
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*.dcp
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# ignore Vivado log files
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*.log
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*.jou
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vivado_pid*.str
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@@ -0,0 +1,56 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1733073470"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1733073470"/>
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<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1733073470"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1733073470"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\design_1.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
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<UsedIn Val="SYNTHESIS"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="sim\design_1.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
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<UsedIn Val="SIMULATION"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="design_1_ooc.xdc" Type="XDC">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<Library Name="xil_defaultlib"/>
|
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<UsedIn Val="SYNTHESIS"/>
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<UsedIn Val="IMPLEMENTATION"/>
|
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<UsedIn Val="OUT_OF_CONTEXT"/>
|
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<ProcessingOrder Val="NORMAL"/>
|
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</File>
|
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<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
|
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
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<ProcessingOrder Val="NORMAL"/>
|
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</File>
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<File Name="design_1.bda">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="synth\design_1.hwdef">
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||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="HW_HANDOFF"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="sim\design_1.protoinst">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
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<ProcessingOrder Val="NORMAL"/>
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</File>
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</FileCollection>
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</CompositeFile>
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</Root>
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@@ -0,0 +1,14 @@
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################################################################################
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# This XDC is used only for OOC mode of synthesis, implementation
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# This constraints file contains default clock frequencies to be used during
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# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
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# This constraints file is not used in normal top-down synthesis (default flow
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# of Vivado)
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################################################################################
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create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
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create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
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create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
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create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
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################################################################################
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+149
@@ -0,0 +1,149 @@
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--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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--Date : Sun Dec 1 18:17:13 2024
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--Host : BiermannSurface running 64-bit major release (build 9200)
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--Command : generate_target design_1_wrapper.bd
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--Design : design_1_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity design_1_wrapper is
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port (
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DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
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DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
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DDR_cas_n : inout STD_LOGIC;
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DDR_ck_n : inout STD_LOGIC;
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DDR_ck_p : inout STD_LOGIC;
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DDR_cke : inout STD_LOGIC;
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DDR_cs_n : inout STD_LOGIC;
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DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
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DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_odt : inout STD_LOGIC;
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DDR_ras_n : inout STD_LOGIC;
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DDR_reset_n : inout STD_LOGIC;
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DDR_we_n : inout STD_LOGIC;
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FIXED_IO_ddr_vrn : inout STD_LOGIC;
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FIXED_IO_ddr_vrp : inout STD_LOGIC;
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FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
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FIXED_IO_ps_clk : inout STD_LOGIC;
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FIXED_IO_ps_porb : inout STD_LOGIC;
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FIXED_IO_ps_srstb : inout STD_LOGIC;
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bclk : out STD_LOGIC;
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i2c_scl_io : inout STD_LOGIC;
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i2c_sda_io : inout STD_LOGIC;
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mclk : out STD_LOGIC;
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mute : out STD_LOGIC;
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pb_dat : out STD_LOGIC;
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pb_lrc : out STD_LOGIC
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);
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end design_1_wrapper;
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architecture STRUCTURE of design_1_wrapper is
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component design_1 is
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port (
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DDR_cas_n : inout STD_LOGIC;
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DDR_cke : inout STD_LOGIC;
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DDR_ck_n : inout STD_LOGIC;
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DDR_ck_p : inout STD_LOGIC;
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DDR_cs_n : inout STD_LOGIC;
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DDR_reset_n : inout STD_LOGIC;
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DDR_odt : inout STD_LOGIC;
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DDR_ras_n : inout STD_LOGIC;
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DDR_we_n : inout STD_LOGIC;
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DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
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DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
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DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
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DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
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FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
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FIXED_IO_ddr_vrn : inout STD_LOGIC;
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FIXED_IO_ddr_vrp : inout STD_LOGIC;
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FIXED_IO_ps_srstb : inout STD_LOGIC;
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FIXED_IO_ps_clk : inout STD_LOGIC;
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FIXED_IO_ps_porb : inout STD_LOGIC;
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pb_dat : out STD_LOGIC;
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bclk : out STD_LOGIC;
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mclk : out STD_LOGIC;
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mute : out STD_LOGIC;
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pb_lrc : out STD_LOGIC;
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i2c_scl_t : out STD_LOGIC;
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i2c_sda_o : out STD_LOGIC;
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i2c_sda_i : in STD_LOGIC;
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i2c_scl_o : out STD_LOGIC;
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i2c_scl_i : in STD_LOGIC;
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i2c_sda_t : out STD_LOGIC
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);
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end component design_1;
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component IOBUF is
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port (
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I : in STD_LOGIC;
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O : out STD_LOGIC;
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T : in STD_LOGIC;
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IO : inout STD_LOGIC
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);
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end component IOBUF;
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signal i2c_scl_i : STD_LOGIC;
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signal i2c_scl_o : STD_LOGIC;
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signal i2c_scl_t : STD_LOGIC;
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signal i2c_sda_i : STD_LOGIC;
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signal i2c_sda_o : STD_LOGIC;
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signal i2c_sda_t : STD_LOGIC;
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begin
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design_1_i: component design_1
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port map (
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DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
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DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
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DDR_cas_n => DDR_cas_n,
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DDR_ck_n => DDR_ck_n,
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DDR_ck_p => DDR_ck_p,
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DDR_cke => DDR_cke,
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DDR_cs_n => DDR_cs_n,
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DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
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DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
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DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
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DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
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DDR_odt => DDR_odt,
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DDR_ras_n => DDR_ras_n,
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DDR_reset_n => DDR_reset_n,
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DDR_we_n => DDR_we_n,
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FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
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FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
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FIXED_IO_ps_clk => FIXED_IO_ps_clk,
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FIXED_IO_ps_porb => FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
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bclk => bclk,
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i2c_scl_i => i2c_scl_i,
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i2c_scl_o => i2c_scl_o,
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i2c_scl_t => i2c_scl_t,
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i2c_sda_i => i2c_sda_i,
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i2c_sda_o => i2c_sda_o,
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i2c_sda_t => i2c_sda_t,
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mclk => mclk,
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||||
mute => mute,
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pb_dat => pb_dat,
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||||
pb_lrc => pb_lrc
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);
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i2c_scl_iobuf: component IOBUF
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port map (
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||||
I => i2c_scl_o,
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||||
IO => i2c_scl_io,
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||||
O => i2c_scl_i,
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||||
T => i2c_scl_t
|
||||
);
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||||
i2c_sda_iobuf: component IOBUF
|
||||
port map (
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||||
I => i2c_sda_o,
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||||
IO => i2c_sda_io,
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||||
O => i2c_sda_i,
|
||||
T => i2c_sda_t
|
||||
);
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||||
end STRUCTURE;
|
||||
+4638
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+57
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||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+12783
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Load Diff
+89
@@ -0,0 +1,89 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:13 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.v
|
||||
// Design : design_1_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+573
@@ -0,0 +1,573 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_PC_0_H_
|
||||
#define IP_DESIGN_1_AUTO_PC_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "design_1_auto_pc_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_pc_0 : public design_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_DESIGN_1_AUTO_PC_0_H_
|
||||
+354
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_28_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_PC_0_SC_H_
|
||||
#define IP_DESIGN_1_AUTO_PC_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_protocol_converter;
|
||||
|
||||
class DllExport design_1_auto_pc_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_pc_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_pc_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_protocol_converter* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
design_1_auto_pc_0_sc(const design_1_auto_pc_0_sc&);
|
||||
const design_1_auto_pc_0_sc& operator=(const design_1_auto_pc_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_DESIGN_1_AUTO_PC_0_SC_H_
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: design_1_auto_pc_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_auto_pc_0 (
|
||||
input bit_as_bool aclk,
|
||||
input bit_as_bool aresetn,
|
||||
input bit [11 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [1 : 0] s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit [3 : 0] s_axi_awqos,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [11 : 0] s_axi_wid,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [11 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [11 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [1 : 0] s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit [3 : 0] s_axi_arqos,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [11 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit [31 : 0] m_axi_awaddr,
|
||||
output bit [2 : 0] m_axi_awprot,
|
||||
output bit_as_bool m_axi_awvalid,
|
||||
input bit_as_bool m_axi_awready,
|
||||
output bit [31 : 0] m_axi_wdata,
|
||||
output bit [3 : 0] m_axi_wstrb,
|
||||
output bit_as_bool m_axi_wvalid,
|
||||
input bit_as_bool m_axi_wready,
|
||||
input bit [1 : 0] m_axi_bresp,
|
||||
input bit_as_bool m_axi_bvalid,
|
||||
output bit_as_bool m_axi_bready,
|
||||
output bit [31 : 0] m_axi_araddr,
|
||||
output bit [2 : 0] m_axi_arprot,
|
||||
output bit_as_bool m_axi_arvalid,
|
||||
input bit_as_bool m_axi_arready,
|
||||
input bit [31 : 0] m_axi_rdata,
|
||||
input bit [1 : 0] m_axi_rresp,
|
||||
input bit_as_bool m_axi_rvalid,
|
||||
output bit_as_bool m_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_auto_pc_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit aclk;
|
||||
input bit aresetn;
|
||||
input bit [11 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [1 : 0] s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit [3 : 0] s_axi_awqos;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [11 : 0] s_axi_wid;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [11 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [1 : 0] s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit [3 : 0] s_axi_arqos;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
output wire m_axi_awvalid;
|
||||
input bit m_axi_awready;
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
output wire m_axi_wvalid;
|
||||
input bit m_axi_wready;
|
||||
input bit [1 : 0] m_axi_bresp;
|
||||
input bit m_axi_bvalid;
|
||||
output wire m_axi_bready;
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
output wire m_axi_arvalid;
|
||||
input bit m_axi_arready;
|
||||
input bit [31 : 0] m_axi_rdata;
|
||||
input bit [1 : 0] m_axi_rresp;
|
||||
input bit m_axi_rvalid;
|
||||
output wire m_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
#ifndef _axi_protocol_converter_
|
||||
#define _axi_protocol_converter_
|
||||
#include <xtlm.h>
|
||||
#include <utils/xtlm_aximm_passthru_module.h>
|
||||
#include <systemc>
|
||||
|
||||
class axi_protocol_converter:public sc_module{
|
||||
public:
|
||||
axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_protocol_converter();
|
||||
SC_HAS_PROCESS(axi_protocol_converter);
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
sc_in<bool> aclk;
|
||||
sc_in<bool> aresetn;
|
||||
private:
|
||||
xtlm::xtlm_aximm_passthru_module *P1;
|
||||
xtlm::xtlm_aximm_passthru_module *P2;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+356
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=28,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WI\
|
||||
DTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
|
||||
NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_28_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+4472
File diff suppressed because it is too large
Load Diff
+7
@@ -0,0 +1,7 @@
|
||||
###############################################################################################################
|
||||
# Core-Level Timing Constraints for axi_dwidth_converter Component "design_1_auto_us_0"
|
||||
###############################################################################################################
|
||||
#
|
||||
# This component is not configured to perform asynchronous clock-domain-crossing.
|
||||
# No timing core-level constraints are needed.
|
||||
# (Synchronous clock-domain-crossings, if any, remain covered by your system-level PERIOD constraints.)
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name s_axi_aclk [get_ports s_axi_aclk]
|
||||
|
||||
|
||||
+11670
File diff suppressed because it is too large
Load Diff
+105
@@ -0,0 +1,105 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:15 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_auto_us_0/design_1_auto_us_0_stub.v
|
||||
// Design : design_1_auto_us_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_28_top,Vivado 2023.1" *)
|
||||
module design_1_auto_us_0(s_axi_aclk, s_axi_aresetn, s_axi_awid,
|
||||
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
|
||||
s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
|
||||
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
|
||||
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
|
||||
s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen,
|
||||
m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
|
||||
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
|
||||
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
|
||||
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
|
||||
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
|
||||
m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awid[0:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[0:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[0:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awlen[3:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[1:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
|
||||
input s_axi_aclk /* synthesis syn_isclock = 1 */;
|
||||
input s_axi_aresetn;
|
||||
input [0:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [0:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [0:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [0:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [3:0]m_axi_awlen;
|
||||
output [2:0]m_axi_awsize;
|
||||
output [1:0]m_axi_awburst;
|
||||
output [1:0]m_axi_awlock;
|
||||
output [3:0]m_axi_awcache;
|
||||
output [2:0]m_axi_awprot;
|
||||
output [3:0]m_axi_awqos;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [63:0]m_axi_wdata;
|
||||
output [7:0]m_axi_wstrb;
|
||||
output m_axi_wlast;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [3:0]m_axi_arlen;
|
||||
output [2:0]m_axi_arsize;
|
||||
output [1:0]m_axi_arburst;
|
||||
output [1:0]m_axi_arlock;
|
||||
output [3:0]m_axi_arcache;
|
||||
output [2:0]m_axi_arprot;
|
||||
output [3:0]m_axi_arqos;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [63:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rlast;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+688
@@ -0,0 +1,688 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_US_0_H_
|
||||
#define IP_DESIGN_1_AUTO_US_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "design_1_auto_us_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_auto_us_0 : public design_1_auto_us_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wlast;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arlen;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arlock;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rlast;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_transactor_rst_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<64,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_awlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_awlock_converter;
|
||||
sc_signal< bool > m_m_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_m_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_m_axi_arlen_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_m_axi_arlock_converter;
|
||||
sc_signal< bool > m_m_axi_arlock_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_DESIGN_1_AUTO_US_0_H_
|
||||
+379
@@ -0,0 +1,379 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_us_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [0 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, \
|
||||
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [3 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [1 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [63 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [7 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [3 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [1 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [63 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, \
|
||||
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_dwidth_converter_v2_1_28_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_AXI_PROTOCOL(1),
|
||||
.C_S_AXI_ID_WIDTH(1),
|
||||
.C_SUPPORTS_ID(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.C_M_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_FIFO_MODE(0),
|
||||
.C_S_AXI_ACLK_RATIO(1),
|
||||
.C_M_AXI_ACLK_RATIO(2),
|
||||
.C_AXI_IS_ACLK_ASYNC(0),
|
||||
.C_MAX_SPLIT_BEATS(16),
|
||||
.C_PACKING_LEVEL(1),
|
||||
.C_SYNCHRONIZER_STAGE(3)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_aclk(1'H0),
|
||||
.m_axi_aresetn(1'H0),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_DESIGN_1_AUTO_US_0_SC_H_
|
||||
#define IP_DESIGN_1_AUTO_US_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_dwidth_converter;
|
||||
|
||||
class DllExport design_1_auto_us_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_auto_us_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_auto_us_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_dwidth_converter* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
design_1_auto_us_0_sc(const design_1_auto_us_0_sc&);
|
||||
const design_1_auto_us_0_sc& operator=(const design_1_auto_us_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_DESIGN_1_AUTO_US_0_SC_H_
|
||||
+223
@@ -0,0 +1,223 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: design_1_auto_us_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_auto_us_0 (
|
||||
input bit_as_bool s_axi_aclk,
|
||||
input bit_as_bool s_axi_aresetn,
|
||||
input bit [0 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [1 : 0] s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit [3 : 0] s_axi_awqos,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [0 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [0 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [1 : 0] s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit [3 : 0] s_axi_arqos,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [0 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit [31 : 0] m_axi_awaddr,
|
||||
output bit [3 : 0] m_axi_awlen,
|
||||
output bit [2 : 0] m_axi_awsize,
|
||||
output bit [1 : 0] m_axi_awburst,
|
||||
output bit [1 : 0] m_axi_awlock,
|
||||
output bit [3 : 0] m_axi_awcache,
|
||||
output bit [2 : 0] m_axi_awprot,
|
||||
output bit [3 : 0] m_axi_awqos,
|
||||
output bit_as_bool m_axi_awvalid,
|
||||
input bit_as_bool m_axi_awready,
|
||||
output bit [63 : 0] m_axi_wdata,
|
||||
output bit [7 : 0] m_axi_wstrb,
|
||||
output bit_as_bool m_axi_wlast,
|
||||
output bit_as_bool m_axi_wvalid,
|
||||
input bit_as_bool m_axi_wready,
|
||||
input bit [1 : 0] m_axi_bresp,
|
||||
input bit_as_bool m_axi_bvalid,
|
||||
output bit_as_bool m_axi_bready,
|
||||
output bit [31 : 0] m_axi_araddr,
|
||||
output bit [3 : 0] m_axi_arlen,
|
||||
output bit [2 : 0] m_axi_arsize,
|
||||
output bit [1 : 0] m_axi_arburst,
|
||||
output bit [1 : 0] m_axi_arlock,
|
||||
output bit [3 : 0] m_axi_arcache,
|
||||
output bit [2 : 0] m_axi_arprot,
|
||||
output bit [3 : 0] m_axi_arqos,
|
||||
output bit_as_bool m_axi_arvalid,
|
||||
input bit_as_bool m_axi_arready,
|
||||
input bit [63 : 0] m_axi_rdata,
|
||||
input bit [1 : 0] m_axi_rresp,
|
||||
input bit_as_bool m_axi_rlast,
|
||||
input bit_as_bool m_axi_rvalid,
|
||||
output bit_as_bool m_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_auto_us_0 (s_axi_aclk,s_axi_aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awqos,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arqos,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rlast,m_axi_rvalid,m_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit s_axi_aclk;
|
||||
input bit s_axi_aresetn;
|
||||
input bit [0 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [1 : 0] s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit [3 : 0] s_axi_awqos;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [0 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [1 : 0] s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit [3 : 0] s_axi_arqos;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
output wire [3 : 0] m_axi_awlen;
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
output wire [1 : 0] m_axi_awlock;
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
output wire m_axi_awvalid;
|
||||
input bit m_axi_awready;
|
||||
output wire [63 : 0] m_axi_wdata;
|
||||
output wire [7 : 0] m_axi_wstrb;
|
||||
output wire m_axi_wlast;
|
||||
output wire m_axi_wvalid;
|
||||
input bit m_axi_wready;
|
||||
input bit [1 : 0] m_axi_bresp;
|
||||
input bit m_axi_bvalid;
|
||||
output wire m_axi_bready;
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
output wire [3 : 0] m_axi_arlen;
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
output wire [1 : 0] m_axi_arlock;
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
output wire m_axi_arvalid;
|
||||
input bit m_axi_arready;
|
||||
input bit [63 : 0] m_axi_rdata;
|
||||
input bit [1 : 0] m_axi_rresp;
|
||||
input bit m_axi_rlast;
|
||||
input bit m_axi_rvalid;
|
||||
output wire m_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
+118
@@ -0,0 +1,118 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef _AXI_DWIDTH_CONVERTER_H_
|
||||
#define _AXI_DWIDTH_CONVERTER_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "report_handler.h"
|
||||
|
||||
class axi_dwidth_converter: public sc_core::sc_module {
|
||||
public:
|
||||
SC_HAS_PROCESS(axi_dwidth_converter);
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
sc_core::sc_in<bool> s_axi_aclk;
|
||||
sc_core::sc_in<bool> s_axi_aresetn;
|
||||
sc_core::sc_in<bool> m_axi_aclk;
|
||||
sc_core::sc_in<bool> m_axi_aresetn;
|
||||
sc_core::sc_signal<bool> clk;
|
||||
sc_core::sc_signal<bool> resetn;
|
||||
axi_dwidth_converter(sc_core::sc_module_name p_name,
|
||||
xsc::common_cpp::properties& m_properties);
|
||||
xtlm::xtlm_aximm_target_rd_socket_util* rd_target_util;
|
||||
xtlm::xtlm_aximm_target_wr_socket_util* wr_target_util;
|
||||
xtlm::xtlm_aximm_initiator_rd_socket_util* rd_initiator_util;
|
||||
xtlm::xtlm_aximm_initiator_wr_socket_util* wr_initiator_util;
|
||||
xtlm::xtlm_aximm_mem_manager* mem_manager;
|
||||
~axi_dwidth_converter();
|
||||
unsigned int SI_DATA_WIDTH;
|
||||
unsigned int MI_DATA_WIDTH;
|
||||
unsigned int FIFO_MODE;
|
||||
unsigned int ratio;
|
||||
|
||||
void wr_handler();
|
||||
void rd_handler();
|
||||
void wr_upsizing();
|
||||
void wr_downsizing();
|
||||
void rd_upsizing();
|
||||
void rd_downsizing();
|
||||
|
||||
/**
|
||||
* @brief Method to send transaction on master interface
|
||||
*/
|
||||
void m_downsize_interface_txn_sender();
|
||||
void m_upsize_interface_txn_sender();
|
||||
|
||||
void m_downsize_interface_response_sender();
|
||||
void m_upsize_interface_response_sender();
|
||||
|
||||
private:
|
||||
xtlm::aximm_payload* m_rd_trans;
|
||||
xtlm::aximm_payload* m_wr_trans;
|
||||
std::queue<xtlm::aximm_payload*> m_upsize_rd_payld_queue;
|
||||
std::queue<xtlm::aximm_payload*> m_upsize_wr_payld_queue;
|
||||
std::queue<xtlm::aximm_payload*> m_interface_wr_payload_queue;
|
||||
std::queue<xtlm::aximm_payload*> m_interface_rd_payload_queue;
|
||||
sc_core::sc_event event_downsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||
sc_core::sc_event event_upsize_trig_txn_sender; //!< Event to trigger Txn Sender Method
|
||||
sc_core::sc_event event_trig_rd_handler;
|
||||
sc_core::sc_event event_trig_wr_handler;
|
||||
std::list<xtlm::aximm_payload* > *m_response_list;
|
||||
std::map<xtlm::aximm_payload*,std::list<xtlm::aximm_payload*>*> m_response_mapper_downsize;
|
||||
std::map<xtlm::aximm_payload*,xtlm::aximm_payload*> m_response_mapper_upsize;
|
||||
xsc::common_cpp::report_handler m_logger;
|
||||
std::string m_log_msg;
|
||||
};
|
||||
|
||||
#endif /* _AXI_DWIDTH_CONVERTER_H_ */
|
||||
|
||||
|
||||
|
||||
+381
@@ -0,0 +1,381 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_28_top,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_auto_us_0,axi_dwidth_converter_v2_1_28_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_auto_us_0,axi_dwidth_converter_v2_1_28_top,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=28,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=1,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=1,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PA\
|
||||
CKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_auto_us_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awsize,
|
||||
m_axi_awburst,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arsize,
|
||||
m_axi_arburst,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [0 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [0 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [0 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [0 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, \
|
||||
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [3 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
|
||||
output wire [2 : 0] m_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
|
||||
output wire [1 : 0] m_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [1 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [63 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [7 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [3 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
|
||||
output wire [2 : 0] m_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
|
||||
output wire [1 : 0] m_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [1 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [63 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, \
|
||||
NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_dwidth_converter_v2_1_28_top #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_AXI_PROTOCOL(1),
|
||||
.C_S_AXI_ID_WIDTH(1),
|
||||
.C_SUPPORTS_ID(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_S_AXI_DATA_WIDTH(32),
|
||||
.C_M_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_FIFO_MODE(0),
|
||||
.C_S_AXI_ACLK_RATIO(1),
|
||||
.C_M_AXI_ACLK_RATIO(2),
|
||||
.C_AXI_IS_ACLK_ASYNC(0),
|
||||
.C_MAX_SPLIT_BEATS(16),
|
||||
.C_PACKING_LEVEL(1),
|
||||
.C_SYNCHRONIZER_STAGE(3)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_aclk(1'H0),
|
||||
.m_axi_aresetn(1'H0),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
create_clock -period 10.000 -name S_AXIL_ACLK -waveform {0.000 5.000} [get_ports S_AXIL_ACLK]
|
||||
create_clock -period 10.000 -name M_AXIS_ACLK -waveform {0.000 5.000} [get_ports M_AXIS_ACLK]
|
||||
create_clock -period 10.000 -name S_AXIS_ACLK -waveform {0.000 5.000} [get_ports S_AXIS_ACLK]
|
||||
create_clock -period 10.000 -name M_AXI_ACLK -waveform {0.000 5.000} [get_ports M_AXI_ACLK]
|
||||
create_clock -period 10.000 -name ACLK -waveform {0.000 5.000} [get_ports ACLK]
|
||||
+4292
File diff suppressed because it is too large
Load Diff
+12867
File diff suppressed because it is too large
Load Diff
+89
@@ -0,0 +1,89 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:20:11 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_axi_2d_mmvs_0_0/design_1_axi_2d_mmvs_0_0_stub.v
|
||||
// Design : design_1_axi_2d_mmvs_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_2d_mmvs,Vivado 2023.1" *)
|
||||
module design_1_axi_2d_mmvs_0_0(ACLK, ARESETN, M_AXIS_TVALID, M_AXIS_TDATA,
|
||||
M_AXIS_TLAST, M_AXIS_TREADY, M_AXIS_TUSER, MM2VS_INTERRUPT, S_AXIL_AWADDR, S_AXIL_AWVALID,
|
||||
S_AXIL_WDATA, S_AXIL_WSTRB, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_BRESP, S_AXIL_BVALID,
|
||||
S_AXIL_AWREADY, S_AXIL_BREADY, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_RREADY,
|
||||
S_AXIL_ARREADY, S_AXIL_RDATA, S_AXIL_RRESP, S_AXIL_RVALID, M_AXI_ARREADY, M_AXI_ARVALID,
|
||||
M_AXI_ARADDR, M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT, M_AXI_ARID,
|
||||
M_AXI_ARCACHE, M_AXI_RREADY, M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST,
|
||||
M_AXI_AWREADY, M_AXI_AWVALID, M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID,
|
||||
M_AXI_AWBURST, M_AXI_AWPROT, M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA,
|
||||
M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID, M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP)
|
||||
/* synthesis syn_black_box black_box_pad_pin="ARESETN,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY,M_AXIS_TUSER[0:0],MM2VS_INTERRUPT,S_AXIL_AWADDR[15:0],S_AXIL_AWVALID,S_AXIL_WDATA[31:0],S_AXIL_WSTRB[3:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_BRESP[1:0],S_AXIL_BVALID,S_AXIL_AWREADY,S_AXIL_BREADY,S_AXIL_ARADDR[15:0],S_AXIL_ARVALID,S_AXIL_RREADY,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RRESP[1:0],S_AXIL_RVALID,M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARID[0:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[0:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[0:0],M_AXI_BRESP[1:0]" */
|
||||
/* synthesis syn_force_seq_prim="ACLK" */;
|
||||
input ACLK /* synthesis syn_isclock = 1 */;
|
||||
input ARESETN;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
output [0:0]M_AXIS_TUSER;
|
||||
output MM2VS_INTERRUPT;
|
||||
input [15:0]S_AXIL_AWADDR;
|
||||
input S_AXIL_AWVALID;
|
||||
input [31:0]S_AXIL_WDATA;
|
||||
input [3:0]S_AXIL_WSTRB;
|
||||
input S_AXIL_WVALID;
|
||||
output S_AXIL_WREADY;
|
||||
output [1:0]S_AXIL_BRESP;
|
||||
output S_AXIL_BVALID;
|
||||
output S_AXIL_AWREADY;
|
||||
input S_AXIL_BREADY;
|
||||
input [15:0]S_AXIL_ARADDR;
|
||||
input S_AXIL_ARVALID;
|
||||
input S_AXIL_RREADY;
|
||||
output S_AXIL_ARREADY;
|
||||
output [31:0]S_AXIL_RDATA;
|
||||
output [1:0]S_AXIL_RRESP;
|
||||
output S_AXIL_RVALID;
|
||||
input M_AXI_ARREADY;
|
||||
output M_AXI_ARVALID;
|
||||
output [31:0]M_AXI_ARADDR;
|
||||
output [3:0]M_AXI_ARLEN;
|
||||
output [2:0]M_AXI_ARSIZE;
|
||||
output [1:0]M_AXI_ARBURST;
|
||||
output [2:0]M_AXI_ARPROT;
|
||||
output [0:0]M_AXI_ARID;
|
||||
output [3:0]M_AXI_ARCACHE;
|
||||
output M_AXI_RREADY;
|
||||
input M_AXI_RVALID;
|
||||
input [31:0]M_AXI_RDATA;
|
||||
input [1:0]M_AXI_RRESP;
|
||||
input [0:0]M_AXI_RID;
|
||||
input M_AXI_RLAST;
|
||||
input M_AXI_AWREADY;
|
||||
output M_AXI_AWVALID;
|
||||
output [31:0]M_AXI_AWADDR;
|
||||
output [3:0]M_AXI_AWLEN;
|
||||
output [2:0]M_AXI_AWSIZE;
|
||||
output [0:0]M_AXI_AWID;
|
||||
output [1:0]M_AXI_AWBURST;
|
||||
output [2:0]M_AXI_AWPROT;
|
||||
output [3:0]M_AXI_AWCACHE;
|
||||
input M_AXI_WREADY;
|
||||
output M_AXI_WVALID;
|
||||
output [31:0]M_AXI_WDATA;
|
||||
output [3:0]M_AXI_WSTRB;
|
||||
output M_AXI_WLAST;
|
||||
output [0:0]M_AXI_WID;
|
||||
output M_AXI_BREADY;
|
||||
input M_AXI_BVALID;
|
||||
input [0:0]M_AXI_BID;
|
||||
input [1:0]M_AXI_BRESP;
|
||||
endmodule
|
||||
+414
@@ -0,0 +1,414 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axi_2d_mmvs:1.0
|
||||
-- IP Revision: 44
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axi_2d_mmvs_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
MM2VS_INTERRUPT : OUT STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_2d_mmvs_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_2d_mmvs_0_0_arch OF design_1_axi_2d_mmvs_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_2d_mmvs_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_2d_mmvs IS
|
||||
GENERIC (
|
||||
AXIL_ENABLE : BOOLEAN;
|
||||
MM2VS_VS2MM_DWIDTH : INTEGER;
|
||||
MM2VS_ENABLE : BOOLEAN;
|
||||
MM2VS_MAX_BURSTLEN : INTEGER;
|
||||
MM2VS_MAX_PIPELINED_BURSTS : INTEGER;
|
||||
MM2VS_FIFO_AWIDTH : INTEGER;
|
||||
DEFAULT_MM2VS_REG_STARTADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES : INTEGER;
|
||||
DEFAULT_MM2VS_REG_STRIDE : INTEGER;
|
||||
DEFAULT_MM2VS_REG_VER_LINES : INTEGER;
|
||||
DEFAULT_MM2VS_REG_INT_LINE : INTEGER;
|
||||
VS2MM_ENABLE : BOOLEAN;
|
||||
VS2MM_MAX_BURSTLEN : INTEGER;
|
||||
VS2MM_FIFO_AWIDTH : INTEGER;
|
||||
DEFAULT_VS2MM_REG_STARTADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES : INTEGER;
|
||||
DEFAULT_VS2MM_REG_STRIDE : INTEGER;
|
||||
DEFAULT_VS2MM_REG_VER_LINES : INTEGER;
|
||||
DEFAULT_VS2MM_REG_INT_LINE : INTEGER;
|
||||
DEFAULT_REG_INT_ENABLE : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_RUN : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_SYNC_SOF : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_NUM_BUFF : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_AxCACHE : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_RUN : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_SYNC_SOF : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_NUM_BUFF : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_AxCACHE : INTEGER;
|
||||
MM2VS_VS2MM_IDWIDTH : INTEGER;
|
||||
HAS_INTERRUPT_OUTPUT : BOOLEAN;
|
||||
HAS_FINISHED_OUTPUT : BOOLEAN;
|
||||
SINGLE_CLOCK_AND_RESETN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
MM2VS_INTERRUPT : OUT STD_LOGIC;
|
||||
MM2VS_FINISHED_PULSE : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
VS2MM_INTERRUPT : OUT STD_LOGIC;
|
||||
VS2MM_FINISHED_PULSE : OUT STD_LOGIC;
|
||||
S_AXIL_ACLK : IN STD_LOGIC;
|
||||
S_AXIL_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
M_AXI_ACLK : IN STD_LOGIC;
|
||||
M_AXI_ARESETN : IN STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_2d_mmvs;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_RESET ARESETN, ASSOCIATED_BUSIF M_AXI:S_AXIL:S_AXIS:M_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF MM2VS_INTERRUPT: SIGNAL IS "XIL_INTERFACENAME MM2VS_INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF MM2VS_INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2VS_INTERRUPT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axi_2d_mmvs
|
||||
GENERIC MAP (
|
||||
AXIL_ENABLE => true,
|
||||
MM2VS_VS2MM_DWIDTH => 32,
|
||||
MM2VS_ENABLE => true,
|
||||
MM2VS_MAX_BURSTLEN => 16,
|
||||
MM2VS_MAX_PIPELINED_BURSTS => 3,
|
||||
MM2VS_FIFO_AWIDTH => 9,
|
||||
DEFAULT_MM2VS_REG_STARTADDR => X"38000000",
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES => 1024,
|
||||
DEFAULT_MM2VS_REG_STRIDE => 1024,
|
||||
DEFAULT_MM2VS_REG_VER_LINES => 1024,
|
||||
DEFAULT_MM2VS_REG_INT_LINE => 0,
|
||||
VS2MM_ENABLE => false,
|
||||
VS2MM_MAX_BURSTLEN => 16,
|
||||
VS2MM_FIFO_AWIDTH => 9,
|
||||
DEFAULT_VS2MM_REG_STARTADDR => X"38000000",
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES => 1024,
|
||||
DEFAULT_VS2MM_REG_STRIDE => 1024,
|
||||
DEFAULT_VS2MM_REG_VER_LINES => 1024,
|
||||
DEFAULT_VS2MM_REG_INT_LINE => 0,
|
||||
DEFAULT_REG_INT_ENABLE => 0,
|
||||
DEFAULT_MM2VS_REG_CTRL_RUN => 0,
|
||||
DEFAULT_MM2VS_REG_CTRL_SYNC_SOF => 0,
|
||||
DEFAULT_MM2VS_REG_CTRL_NUM_BUFF => 1,
|
||||
DEFAULT_MM2VS_REG_CTRL_AxCACHE => 0,
|
||||
DEFAULT_VS2MM_REG_CTRL_RUN => 0,
|
||||
DEFAULT_VS2MM_REG_CTRL_SYNC_SOF => 0,
|
||||
DEFAULT_VS2MM_REG_CTRL_NUM_BUFF => 1,
|
||||
DEFAULT_VS2MM_REG_CTRL_AxCACHE => 0,
|
||||
MM2VS_VS2MM_IDWIDTH => 1,
|
||||
HAS_INTERRUPT_OUTPUT => true,
|
||||
HAS_FINISHED_OUTPUT => false,
|
||||
SINGLE_CLOCK_AND_RESETN => true
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
M_AXIS_ACLK => '0',
|
||||
M_AXIS_ARESETN => '1',
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
MM2VS_INTERRUPT => MM2VS_INTERRUPT,
|
||||
S_AXIS_ACLK => '0',
|
||||
S_AXIS_ARESETN => '1',
|
||||
S_AXIS_TVALID => '0',
|
||||
S_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
S_AXIL_ACLK => '0',
|
||||
S_AXIL_ARESETN => '0',
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
M_AXI_ACLK => '0',
|
||||
M_AXI_ARESETN => '0',
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END design_1_axi_2d_mmvs_0_0_arch;
|
||||
+418
@@ -0,0 +1,418 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axi_2d_mmvs:1.0
|
||||
-- IP Revision: 44
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axi_2d_mmvs_0_0 IS
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
MM2VS_INTERRUPT : OUT STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axi_2d_mmvs_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axi_2d_mmvs_0_0_arch OF design_1_axi_2d_mmvs_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_2d_mmvs_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_2d_mmvs IS
|
||||
GENERIC (
|
||||
AXIL_ENABLE : BOOLEAN;
|
||||
MM2VS_VS2MM_DWIDTH : INTEGER;
|
||||
MM2VS_ENABLE : BOOLEAN;
|
||||
MM2VS_MAX_BURSTLEN : INTEGER;
|
||||
MM2VS_MAX_PIPELINED_BURSTS : INTEGER;
|
||||
MM2VS_FIFO_AWIDTH : INTEGER;
|
||||
DEFAULT_MM2VS_REG_STARTADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES : INTEGER;
|
||||
DEFAULT_MM2VS_REG_STRIDE : INTEGER;
|
||||
DEFAULT_MM2VS_REG_VER_LINES : INTEGER;
|
||||
DEFAULT_MM2VS_REG_INT_LINE : INTEGER;
|
||||
VS2MM_ENABLE : BOOLEAN;
|
||||
VS2MM_MAX_BURSTLEN : INTEGER;
|
||||
VS2MM_FIFO_AWIDTH : INTEGER;
|
||||
DEFAULT_VS2MM_REG_STARTADDR : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES : INTEGER;
|
||||
DEFAULT_VS2MM_REG_STRIDE : INTEGER;
|
||||
DEFAULT_VS2MM_REG_VER_LINES : INTEGER;
|
||||
DEFAULT_VS2MM_REG_INT_LINE : INTEGER;
|
||||
DEFAULT_REG_INT_ENABLE : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_RUN : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_SYNC_SOF : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_NUM_BUFF : INTEGER;
|
||||
DEFAULT_MM2VS_REG_CTRL_AxCACHE : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_RUN : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_SYNC_SOF : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_NUM_BUFF : INTEGER;
|
||||
DEFAULT_VS2MM_REG_CTRL_AxCACHE : INTEGER;
|
||||
MM2VS_VS2MM_IDWIDTH : INTEGER;
|
||||
HAS_INTERRUPT_OUTPUT : BOOLEAN;
|
||||
HAS_FINISHED_OUTPUT : BOOLEAN;
|
||||
SINGLE_CLOCK_AND_RESETN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
ACLK : IN STD_LOGIC;
|
||||
ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
MM2VS_INTERRUPT : OUT STD_LOGIC;
|
||||
MM2VS_FINISHED_PULSE : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
VS2MM_INTERRUPT : OUT STD_LOGIC;
|
||||
VS2MM_FINISHED_PULSE : OUT STD_LOGIC;
|
||||
S_AXIL_ACLK : IN STD_LOGIC;
|
||||
S_AXIL_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
M_AXI_ACLK : IN STD_LOGIC;
|
||||
M_AXI_ARESETN : IN STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_2d_mmvs;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_axi_2d_mmvs_0_0_arch: ARCHITECTURE IS "axi_2d_mmvs,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_2d_mmvs_0_0_arch : ARCHITECTURE IS "design_1_axi_2d_mmvs_0_0,axi_2d_mmvs,{}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_RESET ARESETN, ASSOCIATED_BUSIF M_AXI:S_AXIL:S_AXIS:M_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF MM2VS_INTERRUPT: SIGNAL IS "XIL_INTERFACENAME MM2VS_INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF MM2VS_INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2VS_INTERRUPT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, " &
|
||||
"NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS" &
|
||||
" 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axi_2d_mmvs
|
||||
GENERIC MAP (
|
||||
AXIL_ENABLE => true,
|
||||
MM2VS_VS2MM_DWIDTH => 32,
|
||||
MM2VS_ENABLE => true,
|
||||
MM2VS_MAX_BURSTLEN => 16,
|
||||
MM2VS_MAX_PIPELINED_BURSTS => 3,
|
||||
MM2VS_FIFO_AWIDTH => 9,
|
||||
DEFAULT_MM2VS_REG_STARTADDR => X"38000000",
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES => 1024,
|
||||
DEFAULT_MM2VS_REG_STRIDE => 1024,
|
||||
DEFAULT_MM2VS_REG_VER_LINES => 1024,
|
||||
DEFAULT_MM2VS_REG_INT_LINE => 0,
|
||||
VS2MM_ENABLE => false,
|
||||
VS2MM_MAX_BURSTLEN => 16,
|
||||
VS2MM_FIFO_AWIDTH => 9,
|
||||
DEFAULT_VS2MM_REG_STARTADDR => X"38000000",
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES => 1024,
|
||||
DEFAULT_VS2MM_REG_STRIDE => 1024,
|
||||
DEFAULT_VS2MM_REG_VER_LINES => 1024,
|
||||
DEFAULT_VS2MM_REG_INT_LINE => 0,
|
||||
DEFAULT_REG_INT_ENABLE => 0,
|
||||
DEFAULT_MM2VS_REG_CTRL_RUN => 0,
|
||||
DEFAULT_MM2VS_REG_CTRL_SYNC_SOF => 0,
|
||||
DEFAULT_MM2VS_REG_CTRL_NUM_BUFF => 1,
|
||||
DEFAULT_MM2VS_REG_CTRL_AxCACHE => 0,
|
||||
DEFAULT_VS2MM_REG_CTRL_RUN => 0,
|
||||
DEFAULT_VS2MM_REG_CTRL_SYNC_SOF => 0,
|
||||
DEFAULT_VS2MM_REG_CTRL_NUM_BUFF => 1,
|
||||
DEFAULT_VS2MM_REG_CTRL_AxCACHE => 0,
|
||||
MM2VS_VS2MM_IDWIDTH => 1,
|
||||
HAS_INTERRUPT_OUTPUT => true,
|
||||
HAS_FINISHED_OUTPUT => false,
|
||||
SINGLE_CLOCK_AND_RESETN => true
|
||||
)
|
||||
PORT MAP (
|
||||
ACLK => ACLK,
|
||||
ARESETN => ARESETN,
|
||||
M_AXIS_ACLK => '0',
|
||||
M_AXIS_ARESETN => '1',
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
MM2VS_INTERRUPT => MM2VS_INTERRUPT,
|
||||
S_AXIS_ACLK => '0',
|
||||
S_AXIS_ARESETN => '1',
|
||||
S_AXIS_TVALID => '0',
|
||||
S_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
S_AXIL_ACLK => '0',
|
||||
S_AXIL_ARESETN => '0',
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
M_AXI_ACLK => '0',
|
||||
M_AXI_ARESETN => '0',
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END design_1_axi_2d_mmvs_0_0_arch;
|
||||
+1644
File diff suppressed because it is too large
Load Diff
+710
@@ -0,0 +1,710 @@
|
||||
############################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2006 www.xilinx.com
|
||||
############################################################################
|
||||
## File name : ps7_constraints.xdc
|
||||
##
|
||||
## Details : Constraints file
|
||||
## FPGA family: zynq
|
||||
## FPGA: xc7z020clg400-1
|
||||
## Device Size: xc7z020
|
||||
## Package: clg400
|
||||
## Speedgrade: -1
|
||||
##
|
||||
##
|
||||
############################################################################
|
||||
############################################################################
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_3 -period "14.999" [get_pins "PS7_i/FCLKCLK[3]"]
|
||||
set_input_jitter clk_fpga_3 0.44997
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_1 -period "8" [get_pins "PS7_i/FCLKCLK[1]"]
|
||||
set_input_jitter clk_fpga_1 0.24
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"]
|
||||
set_input_jitter clk_fpga_2 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
|
||||
############################################################################
|
||||
# I/O STANDARDS and Location Constraints #
|
||||
############################################################################
|
||||
|
||||
# Enet 0 / mdio / MIO[53]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
|
||||
set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
|
||||
set_property slew "slow" [get_ports "MIO[53]"]
|
||||
set_property drive "8" [get_ports "MIO[53]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[53]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
|
||||
# Enet 0 / mdc / MIO[52]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
|
||||
set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
|
||||
set_property slew "slow" [get_ports "MIO[52]"]
|
||||
set_property drive "8" [get_ports "MIO[52]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[52]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
|
||||
# GPIO / gpio[51] / MIO[51]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
|
||||
set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
|
||||
set_property slew "slow" [get_ports "MIO[51]"]
|
||||
set_property drive "8" [get_ports "MIO[51]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[51]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
|
||||
# GPIO / gpio[50] / MIO[50]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
|
||||
set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
|
||||
set_property slew "slow" [get_ports "MIO[50]"]
|
||||
set_property drive "8" [get_ports "MIO[50]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[50]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
|
||||
# UART 1 / rx / MIO[49]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
|
||||
set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
|
||||
set_property slew "slow" [get_ports "MIO[49]"]
|
||||
set_property drive "8" [get_ports "MIO[49]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[49]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
|
||||
# UART 1 / tx / MIO[48]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
|
||||
set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
|
||||
set_property slew "slow" [get_ports "MIO[48]"]
|
||||
set_property drive "8" [get_ports "MIO[48]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[48]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
|
||||
# SD 0 / cd / MIO[47]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
|
||||
set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
|
||||
set_property slew "slow" [get_ports "MIO[47]"]
|
||||
set_property drive "8" [get_ports "MIO[47]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[47]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
|
||||
# USB Reset / reset / MIO[46]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
|
||||
set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
|
||||
set_property slew "slow" [get_ports "MIO[46]"]
|
||||
set_property drive "8" [get_ports "MIO[46]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[46]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[46]"]
|
||||
# SD 0 / data[3] / MIO[45]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
|
||||
set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
|
||||
set_property slew "slow" [get_ports "MIO[45]"]
|
||||
set_property drive "8" [get_ports "MIO[45]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[45]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
|
||||
# SD 0 / data[2] / MIO[44]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
|
||||
set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
|
||||
set_property slew "slow" [get_ports "MIO[44]"]
|
||||
set_property drive "8" [get_ports "MIO[44]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[44]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
|
||||
# SD 0 / data[1] / MIO[43]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
|
||||
set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
|
||||
set_property slew "slow" [get_ports "MIO[43]"]
|
||||
set_property drive "8" [get_ports "MIO[43]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[43]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
|
||||
# SD 0 / data[0] / MIO[42]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
|
||||
set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
|
||||
set_property slew "slow" [get_ports "MIO[42]"]
|
||||
set_property drive "8" [get_ports "MIO[42]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[42]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
|
||||
# SD 0 / cmd / MIO[41]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
|
||||
set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
|
||||
set_property slew "slow" [get_ports "MIO[41]"]
|
||||
set_property drive "8" [get_ports "MIO[41]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[41]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
|
||||
# SD 0 / clk / MIO[40]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
|
||||
set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
|
||||
set_property slew "slow" [get_ports "MIO[40]"]
|
||||
set_property drive "8" [get_ports "MIO[40]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[40]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
|
||||
# USB 0 / data[7] / MIO[39]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
|
||||
set_property slew "fast" [get_ports "MIO[39]"]
|
||||
set_property drive "8" [get_ports "MIO[39]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[39]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
|
||||
# USB 0 / data[6] / MIO[38]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
|
||||
set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
|
||||
set_property slew "fast" [get_ports "MIO[38]"]
|
||||
set_property drive "8" [get_ports "MIO[38]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[38]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
|
||||
# USB 0 / data[5] / MIO[37]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
|
||||
set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
|
||||
set_property slew "fast" [get_ports "MIO[37]"]
|
||||
set_property drive "8" [get_ports "MIO[37]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[37]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
|
||||
# USB 0 / clk / MIO[36]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
|
||||
set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
|
||||
set_property slew "fast" [get_ports "MIO[36]"]
|
||||
set_property drive "8" [get_ports "MIO[36]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[36]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
|
||||
# USB 0 / data[3] / MIO[35]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
|
||||
set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
|
||||
set_property slew "fast" [get_ports "MIO[35]"]
|
||||
set_property drive "8" [get_ports "MIO[35]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[35]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
|
||||
# USB 0 / data[2] / MIO[34]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
|
||||
set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
|
||||
set_property slew "fast" [get_ports "MIO[34]"]
|
||||
set_property drive "8" [get_ports "MIO[34]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[34]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
|
||||
# USB 0 / data[1] / MIO[33]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
|
||||
set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
|
||||
set_property slew "fast" [get_ports "MIO[33]"]
|
||||
set_property drive "8" [get_ports "MIO[33]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[33]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
|
||||
# USB 0 / data[0] / MIO[32]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
|
||||
set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
|
||||
set_property slew "fast" [get_ports "MIO[32]"]
|
||||
set_property drive "8" [get_ports "MIO[32]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[32]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
|
||||
# USB 0 / nxt / MIO[31]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
|
||||
set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
|
||||
set_property slew "fast" [get_ports "MIO[31]"]
|
||||
set_property drive "8" [get_ports "MIO[31]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[31]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
|
||||
# USB 0 / stp / MIO[30]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
|
||||
set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
|
||||
set_property slew "fast" [get_ports "MIO[30]"]
|
||||
set_property drive "8" [get_ports "MIO[30]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[30]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
|
||||
# USB 0 / dir / MIO[29]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
|
||||
set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
|
||||
set_property slew "fast" [get_ports "MIO[29]"]
|
||||
set_property drive "8" [get_ports "MIO[29]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[29]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
|
||||
# USB 0 / data[4] / MIO[28]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
|
||||
set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
|
||||
set_property slew "fast" [get_ports "MIO[28]"]
|
||||
set_property drive "8" [get_ports "MIO[28]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
|
||||
# Enet 0 / rx_ctl / MIO[27]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
|
||||
set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
|
||||
set_property slew "fast" [get_ports "MIO[27]"]
|
||||
set_property drive "8" [get_ports "MIO[27]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[27]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
|
||||
# Enet 0 / rxd[3] / MIO[26]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
|
||||
set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
|
||||
set_property slew "fast" [get_ports "MIO[26]"]
|
||||
set_property drive "8" [get_ports "MIO[26]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[26]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
|
||||
# Enet 0 / rxd[2] / MIO[25]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
|
||||
set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
|
||||
set_property slew "fast" [get_ports "MIO[25]"]
|
||||
set_property drive "8" [get_ports "MIO[25]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[25]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
|
||||
# Enet 0 / rxd[1] / MIO[24]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
|
||||
set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
|
||||
set_property slew "fast" [get_ports "MIO[24]"]
|
||||
set_property drive "8" [get_ports "MIO[24]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[24]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
|
||||
# Enet 0 / rxd[0] / MIO[23]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
|
||||
set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
|
||||
set_property slew "fast" [get_ports "MIO[23]"]
|
||||
set_property drive "8" [get_ports "MIO[23]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[23]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
|
||||
# Enet 0 / rx_clk / MIO[22]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
|
||||
set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
|
||||
set_property slew "fast" [get_ports "MIO[22]"]
|
||||
set_property drive "8" [get_ports "MIO[22]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[22]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
|
||||
# Enet 0 / tx_ctl / MIO[21]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
|
||||
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
|
||||
set_property slew "fast" [get_ports "MIO[21]"]
|
||||
set_property drive "8" [get_ports "MIO[21]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[21]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
|
||||
# Enet 0 / txd[3] / MIO[20]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
|
||||
set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
|
||||
set_property slew "fast" [get_ports "MIO[20]"]
|
||||
set_property drive "8" [get_ports "MIO[20]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[20]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
|
||||
# Enet 0 / txd[2] / MIO[19]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
|
||||
set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
|
||||
set_property slew "fast" [get_ports "MIO[19]"]
|
||||
set_property drive "8" [get_ports "MIO[19]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[19]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
|
||||
# Enet 0 / txd[1] / MIO[18]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
|
||||
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
|
||||
set_property slew "fast" [get_ports "MIO[18]"]
|
||||
set_property drive "8" [get_ports "MIO[18]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[18]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
|
||||
# Enet 0 / txd[0] / MIO[17]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
|
||||
set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
|
||||
set_property slew "fast" [get_ports "MIO[17]"]
|
||||
set_property drive "8" [get_ports "MIO[17]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[17]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
|
||||
# Enet 0 / tx_clk / MIO[16]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
|
||||
set_property slew "fast" [get_ports "MIO[16]"]
|
||||
set_property drive "8" [get_ports "MIO[16]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[16]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
|
||||
# I2C 0 / sda / MIO[15]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
|
||||
set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
|
||||
set_property slew "slow" [get_ports "MIO[15]"]
|
||||
set_property drive "8" [get_ports "MIO[15]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
|
||||
# I2C 0 / scl / MIO[14]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
|
||||
set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
|
||||
set_property slew "slow" [get_ports "MIO[14]"]
|
||||
set_property drive "8" [get_ports "MIO[14]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
|
||||
# I2C 1 / sda / MIO[13]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
|
||||
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
|
||||
set_property slew "slow" [get_ports "MIO[13]"]
|
||||
set_property drive "8" [get_ports "MIO[13]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
|
||||
# I2C 1 / scl / MIO[12]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
|
||||
set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
|
||||
set_property slew "slow" [get_ports "MIO[12]"]
|
||||
set_property drive "8" [get_ports "MIO[12]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
|
||||
# UART 0 / tx / MIO[11]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
|
||||
set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
|
||||
set_property slew "slow" [get_ports "MIO[11]"]
|
||||
set_property drive "8" [get_ports "MIO[11]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[11]"]
|
||||
# UART 0 / rx / MIO[10]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
|
||||
set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
|
||||
set_property slew "slow" [get_ports "MIO[10]"]
|
||||
set_property drive "8" [get_ports "MIO[10]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[10]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[10]"]
|
||||
# GPIO / gpio[9] / MIO[9]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
|
||||
set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
|
||||
set_property slew "slow" [get_ports "MIO[9]"]
|
||||
set_property drive "8" [get_ports "MIO[9]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
|
||||
# Quad SPI Flash / qspi_fbclk / MIO[8]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
|
||||
set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
|
||||
set_property slew "slow" [get_ports "MIO[8]"]
|
||||
set_property drive "8" [get_ports "MIO[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
|
||||
# GPIO / gpio[7] / MIO[7]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
|
||||
set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
|
||||
set_property slew "slow" [get_ports "MIO[7]"]
|
||||
set_property drive "8" [get_ports "MIO[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
|
||||
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
|
||||
set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
|
||||
set_property slew "slow" [get_ports "MIO[6]"]
|
||||
set_property drive "8" [get_ports "MIO[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
|
||||
# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
|
||||
set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
|
||||
set_property slew "slow" [get_ports "MIO[5]"]
|
||||
set_property drive "8" [get_ports "MIO[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
|
||||
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
|
||||
set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
|
||||
set_property slew "slow" [get_ports "MIO[4]"]
|
||||
set_property drive "8" [get_ports "MIO[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
|
||||
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
|
||||
set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
|
||||
set_property slew "slow" [get_ports "MIO[3]"]
|
||||
set_property drive "8" [get_ports "MIO[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
|
||||
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
|
||||
set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
|
||||
set_property slew "slow" [get_ports "MIO[2]"]
|
||||
set_property drive "8" [get_ports "MIO[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
|
||||
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
|
||||
set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
|
||||
set_property slew "slow" [get_ports "MIO[1]"]
|
||||
set_property drive "8" [get_ports "MIO[1]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
|
||||
# GPIO / gpio[0] / MIO[0]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
|
||||
set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
|
||||
set_property slew "slow" [get_ports "MIO[0]"]
|
||||
set_property drive "8" [get_ports "MIO[0]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"]
|
||||
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRP"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"]
|
||||
set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRN"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_WEB"]
|
||||
set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
|
||||
set_property slew "SLOW" [get_ports "DDR_WEB"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"]
|
||||
set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_ODT"]
|
||||
set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
|
||||
set_property slew "SLOW" [get_ports "DDR_ODT"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"]
|
||||
set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
|
||||
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"]
|
||||
set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"]
|
||||
set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"]
|
||||
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"]
|
||||
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"]
|
||||
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"]
|
||||
set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"]
|
||||
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"]
|
||||
set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"]
|
||||
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"]
|
||||
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"]
|
||||
set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"]
|
||||
set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"]
|
||||
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"]
|
||||
set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"]
|
||||
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"]
|
||||
set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"]
|
||||
set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"]
|
||||
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"]
|
||||
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"]
|
||||
set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"]
|
||||
set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"]
|
||||
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"]
|
||||
set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"]
|
||||
set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"]
|
||||
set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"]
|
||||
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"]
|
||||
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"]
|
||||
set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"]
|
||||
set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"]
|
||||
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"]
|
||||
set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"]
|
||||
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"]
|
||||
set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"]
|
||||
set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"]
|
||||
set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"]
|
||||
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"]
|
||||
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"]
|
||||
set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"]
|
||||
set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"]
|
||||
set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CS_n"]
|
||||
set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CKE"]
|
||||
set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CKE"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
|
||||
set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"]
|
||||
set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
|
||||
set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"]
|
||||
set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"]
|
||||
set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"]
|
||||
set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"]
|
||||
set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"]
|
||||
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"]
|
||||
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"]
|
||||
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"]
|
||||
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"]
|
||||
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"]
|
||||
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"]
|
||||
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"]
|
||||
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"]
|
||||
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"]
|
||||
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"]
|
||||
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"]
|
||||
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"]
|
||||
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
|
||||
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
|
||||
set_property slew "fast" [get_ports "PS_PORB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
||||
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
|
||||
set_property slew "fast" [get_ports "PS_SRSTB"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
|
||||
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
|
||||
set_property slew "fast" [get_ports "PS_CLK"]
|
||||
|
||||
+41293
File diff suppressed because it is too large
Load Diff
+6429
File diff suppressed because it is too large
Load Diff
+161
@@ -0,0 +1,161 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:52 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v
|
||||
// Design : design_1_processing_system7_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.1" *)
|
||||
module design_1_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
|
||||
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
|
||||
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_ACP_ARREADY, S_AXI_ACP_AWREADY, S_AXI_ACP_BVALID,
|
||||
S_AXI_ACP_RLAST, S_AXI_ACP_RVALID, S_AXI_ACP_WREADY, S_AXI_ACP_BRESP, S_AXI_ACP_RRESP,
|
||||
S_AXI_ACP_BID, S_AXI_ACP_RID, S_AXI_ACP_RDATA, S_AXI_ACP_ACLK, S_AXI_ACP_ARVALID,
|
||||
S_AXI_ACP_AWVALID, S_AXI_ACP_BREADY, S_AXI_ACP_RREADY, S_AXI_ACP_WLAST, S_AXI_ACP_WVALID,
|
||||
S_AXI_ACP_ARID, S_AXI_ACP_ARPROT, S_AXI_ACP_AWID, S_AXI_ACP_AWPROT, S_AXI_ACP_WID,
|
||||
S_AXI_ACP_ARADDR, S_AXI_ACP_AWADDR, S_AXI_ACP_ARCACHE, S_AXI_ACP_ARLEN, S_AXI_ACP_ARQOS,
|
||||
S_AXI_ACP_AWCACHE, S_AXI_ACP_AWLEN, S_AXI_ACP_AWQOS, S_AXI_ACP_ARBURST, S_AXI_ACP_ARLOCK,
|
||||
S_AXI_ACP_ARSIZE, S_AXI_ACP_AWBURST, S_AXI_ACP_AWLOCK, S_AXI_ACP_AWSIZE,
|
||||
S_AXI_ACP_ARUSER, S_AXI_ACP_AWUSER, S_AXI_ACP_WDATA, S_AXI_ACP_WSTRB, IRQ_F2P, FCLK_CLK0,
|
||||
FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk,
|
||||
DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM,
|
||||
DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
|
||||
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_ACP_ARREADY,S_AXI_ACP_AWREADY,S_AXI_ACP_BVALID,S_AXI_ACP_RLAST,S_AXI_ACP_RVALID,S_AXI_ACP_WREADY,S_AXI_ACP_BRESP[1:0],S_AXI_ACP_RRESP[1:0],S_AXI_ACP_BID[2:0],S_AXI_ACP_RID[2:0],S_AXI_ACP_RDATA[63:0],S_AXI_ACP_ARVALID,S_AXI_ACP_AWVALID,S_AXI_ACP_BREADY,S_AXI_ACP_RREADY,S_AXI_ACP_WLAST,S_AXI_ACP_WVALID,S_AXI_ACP_ARID[2:0],S_AXI_ACP_ARPROT[2:0],S_AXI_ACP_AWID[2:0],S_AXI_ACP_AWPROT[2:0],S_AXI_ACP_WID[2:0],S_AXI_ACP_ARADDR[31:0],S_AXI_ACP_AWADDR[31:0],S_AXI_ACP_ARCACHE[3:0],S_AXI_ACP_ARLEN[3:0],S_AXI_ACP_ARQOS[3:0],S_AXI_ACP_AWCACHE[3:0],S_AXI_ACP_AWLEN[3:0],S_AXI_ACP_AWQOS[3:0],S_AXI_ACP_ARBURST[1:0],S_AXI_ACP_ARLOCK[1:0],S_AXI_ACP_ARSIZE[2:0],S_AXI_ACP_AWBURST[1:0],S_AXI_ACP_AWLOCK[1:0],S_AXI_ACP_AWSIZE[2:0],S_AXI_ACP_ARUSER[4:0],S_AXI_ACP_AWUSER[4:0],S_AXI_ACP_WDATA[63:0],S_AXI_ACP_WSTRB[7:0],IRQ_F2P[0:0],FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */
|
||||
/* synthesis syn_force_seq_prim="M_AXI_GP0_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="S_AXI_ACP_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK0" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK1" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK2" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK3" */;
|
||||
input SDIO0_WP;
|
||||
output TTC0_WAVE0_OUT;
|
||||
output TTC0_WAVE1_OUT;
|
||||
output TTC0_WAVE2_OUT;
|
||||
output [1:0]USB0_PORT_INDCTL;
|
||||
output USB0_VBUS_PWRSELECT;
|
||||
input USB0_VBUS_PWRFAULT;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11:0]M_AXI_GP0_ARID;
|
||||
output [11:0]M_AXI_GP0_AWID;
|
||||
output [11:0]M_AXI_GP0_WID;
|
||||
output [1:0]M_AXI_GP0_ARBURST;
|
||||
output [1:0]M_AXI_GP0_ARLOCK;
|
||||
output [2:0]M_AXI_GP0_ARSIZE;
|
||||
output [1:0]M_AXI_GP0_AWBURST;
|
||||
output [1:0]M_AXI_GP0_AWLOCK;
|
||||
output [2:0]M_AXI_GP0_AWSIZE;
|
||||
output [2:0]M_AXI_GP0_ARPROT;
|
||||
output [2:0]M_AXI_GP0_AWPROT;
|
||||
output [31:0]M_AXI_GP0_ARADDR;
|
||||
output [31:0]M_AXI_GP0_AWADDR;
|
||||
output [31:0]M_AXI_GP0_WDATA;
|
||||
output [3:0]M_AXI_GP0_ARCACHE;
|
||||
output [3:0]M_AXI_GP0_ARLEN;
|
||||
output [3:0]M_AXI_GP0_ARQOS;
|
||||
output [3:0]M_AXI_GP0_AWCACHE;
|
||||
output [3:0]M_AXI_GP0_AWLEN;
|
||||
output [3:0]M_AXI_GP0_AWQOS;
|
||||
output [3:0]M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11:0]M_AXI_GP0_BID;
|
||||
input [11:0]M_AXI_GP0_RID;
|
||||
input [1:0]M_AXI_GP0_BRESP;
|
||||
input [1:0]M_AXI_GP0_RRESP;
|
||||
input [31:0]M_AXI_GP0_RDATA;
|
||||
output S_AXI_ACP_ARREADY;
|
||||
output S_AXI_ACP_AWREADY;
|
||||
output S_AXI_ACP_BVALID;
|
||||
output S_AXI_ACP_RLAST;
|
||||
output S_AXI_ACP_RVALID;
|
||||
output S_AXI_ACP_WREADY;
|
||||
output [1:0]S_AXI_ACP_BRESP;
|
||||
output [1:0]S_AXI_ACP_RRESP;
|
||||
output [2:0]S_AXI_ACP_BID;
|
||||
output [2:0]S_AXI_ACP_RID;
|
||||
output [63:0]S_AXI_ACP_RDATA;
|
||||
input S_AXI_ACP_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXI_ACP_ARVALID;
|
||||
input S_AXI_ACP_AWVALID;
|
||||
input S_AXI_ACP_BREADY;
|
||||
input S_AXI_ACP_RREADY;
|
||||
input S_AXI_ACP_WLAST;
|
||||
input S_AXI_ACP_WVALID;
|
||||
input [2:0]S_AXI_ACP_ARID;
|
||||
input [2:0]S_AXI_ACP_ARPROT;
|
||||
input [2:0]S_AXI_ACP_AWID;
|
||||
input [2:0]S_AXI_ACP_AWPROT;
|
||||
input [2:0]S_AXI_ACP_WID;
|
||||
input [31:0]S_AXI_ACP_ARADDR;
|
||||
input [31:0]S_AXI_ACP_AWADDR;
|
||||
input [3:0]S_AXI_ACP_ARCACHE;
|
||||
input [3:0]S_AXI_ACP_ARLEN;
|
||||
input [3:0]S_AXI_ACP_ARQOS;
|
||||
input [3:0]S_AXI_ACP_AWCACHE;
|
||||
input [3:0]S_AXI_ACP_AWLEN;
|
||||
input [3:0]S_AXI_ACP_AWQOS;
|
||||
input [1:0]S_AXI_ACP_ARBURST;
|
||||
input [1:0]S_AXI_ACP_ARLOCK;
|
||||
input [2:0]S_AXI_ACP_ARSIZE;
|
||||
input [1:0]S_AXI_ACP_AWBURST;
|
||||
input [1:0]S_AXI_ACP_AWLOCK;
|
||||
input [2:0]S_AXI_ACP_AWSIZE;
|
||||
input [4:0]S_AXI_ACP_ARUSER;
|
||||
input [4:0]S_AXI_ACP_AWUSER;
|
||||
input [63:0]S_AXI_ACP_WDATA;
|
||||
input [7:0]S_AXI_ACP_WSTRB;
|
||||
input [0:0]IRQ_F2P;
|
||||
output FCLK_CLK0 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK1 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK2 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK3 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53:0]MIO;
|
||||
inout DDR_CAS_n;
|
||||
inout DDR_CKE;
|
||||
inout DDR_Clk_n;
|
||||
inout DDR_Clk;
|
||||
inout DDR_CS_n;
|
||||
inout DDR_DRSTB;
|
||||
inout DDR_ODT;
|
||||
inout DDR_RAS_n;
|
||||
inout DDR_WEB;
|
||||
inout [2:0]DDR_BankAddr;
|
||||
inout [14:0]DDR_Addr;
|
||||
inout DDR_VRN;
|
||||
inout DDR_VRP;
|
||||
inout [3:0]DDR_DM;
|
||||
inout [31:0]DDR_DQ;
|
||||
inout [3:0]DDR_DQS_n;
|
||||
inout [3:0]DDR_DQS;
|
||||
inout PS_SRSTB;
|
||||
inout PS_CLK;
|
||||
inout PS_PORB;
|
||||
endmodule
|
||||
+3934
File diff suppressed because it is too large
Load Diff
+12598
File diff suppressed because it is too large
Load Diff
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 125000000
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 66666672
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+853
@@ -0,0 +1,853 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 667000000
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+12611
File diff suppressed because it is too large
Load Diff
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 125000000
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 66666672
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="4" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="125" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="65" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 14 .. 15" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="MIO 12 .. 13" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 47" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 10 .. 11" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.221" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.222" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.217" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.244" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="22.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="27.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="22.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="29.4" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.050" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="-0.044" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.035" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="22.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="27.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="22.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="29.4" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3 (Low Voltage)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 46" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="100.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="125.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="200.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="66.666672" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
+898
@@ -0,0 +1,898 @@
|
||||
#ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
#define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "design_1_processing_system7_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_ACP_RDATA;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_ARUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_AWUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_ACP_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_ACP_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<64,32,3,5,1,1,5,1>* mp_S_AXI_ACP_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_AWLEN_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_AWLOCK_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_ACP_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_ACP_RDATA;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_ARUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_AWUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_ACP_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_ACP_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout< bool > DDR_CAS_n;
|
||||
sc_core::sc_inout< bool > DDR_CKE;
|
||||
sc_core::sc_inout< bool > DDR_Clk_n;
|
||||
sc_core::sc_inout< bool > DDR_Clk;
|
||||
sc_core::sc_inout< bool > DDR_CS_n;
|
||||
sc_core::sc_inout< bool > DDR_DRSTB;
|
||||
sc_core::sc_inout< bool > DDR_ODT;
|
||||
sc_core::sc_inout< bool > DDR_RAS_n;
|
||||
sc_core::sc_inout< bool > DDR_WEB;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout< bool > DDR_VRN;
|
||||
sc_core::sc_inout< bool > DDR_VRP;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout< bool > PS_SRSTB;
|
||||
sc_core::sc_inout< bool > PS_CLK;
|
||||
sc_core::sc_inout< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<64,32,3,5,1,1,5,1>* mp_S_AXI_ACP_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_AWLEN_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_AWLOCK_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_ACP_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_ACP_RDATA;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_ARUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_AWUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_ACP_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_ACP_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<64,32,3,5,1,1,5,1>* mp_S_AXI_ACP_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_AWLEN_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_AWLOCK_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_ACP_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_ACP_RDATA;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_ARUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_AWUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_ACP_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_ACP_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<64,32,3,5,1,1,5,1>* mp_S_AXI_ACP_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_AWLEN_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_AWLOCK_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_ACP_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_ACP_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_ACP_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport design_1_processing_system7_0_0 : public design_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_ACP_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_ACP_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_ACP_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<64> > S_AXI_ACP_RDATA;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_ACP_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_ACP_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_ACP_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_ACP_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_ACP_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_ARUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<5> > S_AXI_ACP_AWUSER;
|
||||
sc_core::sc_in< sc_dt::sc_bv<64> > S_AXI_ACP_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > S_AXI_ACP_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<64,32,3,5,1,1,5,1>* mp_S_AXI_ACP_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_ACP_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_ACP_AWLEN_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_ACP_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_ACP_AWLOCK_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_ACP_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_ACP_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_ACP_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
+1395
File diff suppressed because it is too large
Load Diff
+682
@@ -0,0 +1,682 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module design_1_processing_system7_0_0 (
|
||||
SDIO0_WP,
|
||||
TTC0_WAVE0_OUT,
|
||||
TTC0_WAVE1_OUT,
|
||||
TTC0_WAVE2_OUT,
|
||||
USB0_PORT_INDCTL,
|
||||
USB0_VBUS_PWRSELECT,
|
||||
USB0_VBUS_PWRFAULT,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
S_AXI_ACP_ARREADY,
|
||||
S_AXI_ACP_AWREADY,
|
||||
S_AXI_ACP_BVALID,
|
||||
S_AXI_ACP_RLAST,
|
||||
S_AXI_ACP_RVALID,
|
||||
S_AXI_ACP_WREADY,
|
||||
S_AXI_ACP_BRESP,
|
||||
S_AXI_ACP_RRESP,
|
||||
S_AXI_ACP_BID,
|
||||
S_AXI_ACP_RID,
|
||||
S_AXI_ACP_RDATA,
|
||||
S_AXI_ACP_ACLK,
|
||||
S_AXI_ACP_ARVALID,
|
||||
S_AXI_ACP_AWVALID,
|
||||
S_AXI_ACP_BREADY,
|
||||
S_AXI_ACP_RREADY,
|
||||
S_AXI_ACP_WLAST,
|
||||
S_AXI_ACP_WVALID,
|
||||
S_AXI_ACP_ARID,
|
||||
S_AXI_ACP_ARPROT,
|
||||
S_AXI_ACP_AWID,
|
||||
S_AXI_ACP_AWPROT,
|
||||
S_AXI_ACP_WID,
|
||||
S_AXI_ACP_ARADDR,
|
||||
S_AXI_ACP_AWADDR,
|
||||
S_AXI_ACP_ARCACHE,
|
||||
S_AXI_ACP_ARLEN,
|
||||
S_AXI_ACP_ARQOS,
|
||||
S_AXI_ACP_AWCACHE,
|
||||
S_AXI_ACP_AWLEN,
|
||||
S_AXI_ACP_AWQOS,
|
||||
S_AXI_ACP_ARBURST,
|
||||
S_AXI_ACP_ARLOCK,
|
||||
S_AXI_ACP_ARSIZE,
|
||||
S_AXI_ACP_AWBURST,
|
||||
S_AXI_ACP_AWLOCK,
|
||||
S_AXI_ACP_AWSIZE,
|
||||
S_AXI_ACP_ARUSER,
|
||||
S_AXI_ACP_AWUSER,
|
||||
S_AXI_ACP_WDATA,
|
||||
S_AXI_ACP_WSTRB,
|
||||
IRQ_F2P,
|
||||
FCLK_CLK0,
|
||||
FCLK_CLK1,
|
||||
FCLK_CLK2,
|
||||
FCLK_CLK3,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input SDIO0_WP;
|
||||
output TTC0_WAVE0_OUT;
|
||||
output TTC0_WAVE1_OUT;
|
||||
output TTC0_WAVE2_OUT;
|
||||
output [1 : 0] USB0_PORT_INDCTL;
|
||||
output USB0_VBUS_PWRSELECT;
|
||||
input USB0_VBUS_PWRFAULT;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
output S_AXI_ACP_ARREADY;
|
||||
output S_AXI_ACP_AWREADY;
|
||||
output S_AXI_ACP_BVALID;
|
||||
output S_AXI_ACP_RLAST;
|
||||
output S_AXI_ACP_RVALID;
|
||||
output S_AXI_ACP_WREADY;
|
||||
output [1 : 0] S_AXI_ACP_BRESP;
|
||||
output [1 : 0] S_AXI_ACP_RRESP;
|
||||
output [2 : 0] S_AXI_ACP_BID;
|
||||
output [2 : 0] S_AXI_ACP_RID;
|
||||
output [63 : 0] S_AXI_ACP_RDATA;
|
||||
input S_AXI_ACP_ACLK;
|
||||
input S_AXI_ACP_ARVALID;
|
||||
input S_AXI_ACP_AWVALID;
|
||||
input S_AXI_ACP_BREADY;
|
||||
input S_AXI_ACP_RREADY;
|
||||
input S_AXI_ACP_WLAST;
|
||||
input S_AXI_ACP_WVALID;
|
||||
input [2 : 0] S_AXI_ACP_ARID;
|
||||
input [2 : 0] S_AXI_ACP_ARPROT;
|
||||
input [2 : 0] S_AXI_ACP_AWID;
|
||||
input [2 : 0] S_AXI_ACP_AWPROT;
|
||||
input [2 : 0] S_AXI_ACP_WID;
|
||||
input [31 : 0] S_AXI_ACP_ARADDR;
|
||||
input [31 : 0] S_AXI_ACP_AWADDR;
|
||||
input [3 : 0] S_AXI_ACP_ARCACHE;
|
||||
input [3 : 0] S_AXI_ACP_ARLEN;
|
||||
input [3 : 0] S_AXI_ACP_ARQOS;
|
||||
input [3 : 0] S_AXI_ACP_AWCACHE;
|
||||
input [3 : 0] S_AXI_ACP_AWLEN;
|
||||
input [3 : 0] S_AXI_ACP_AWQOS;
|
||||
input [1 : 0] S_AXI_ACP_ARBURST;
|
||||
input [1 : 0] S_AXI_ACP_ARLOCK;
|
||||
input [2 : 0] S_AXI_ACP_ARSIZE;
|
||||
input [1 : 0] S_AXI_ACP_AWBURST;
|
||||
input [1 : 0] S_AXI_ACP_AWLOCK;
|
||||
input [2 : 0] S_AXI_ACP_AWSIZE;
|
||||
input [4 : 0] S_AXI_ACP_ARUSER;
|
||||
input [4 : 0] S_AXI_ACP_AWUSER;
|
||||
input [63 : 0] S_AXI_ACP_WDATA;
|
||||
input [7 : 0] S_AXI_ACP_WSTRB;
|
||||
input [0 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_CLK2;
|
||||
output FCLK_CLK3;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_16 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(1),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(100.0),
|
||||
.C_FCLK_CLK1_FREQ(125.0),
|
||||
.C_FCLK_CLK2_FREQ(200.0),
|
||||
.C_FCLK_CLK3_FREQ(66.666672),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(S_AXI_ACP_ARREADY),
|
||||
.S_AXI_ACP_AWREADY(S_AXI_ACP_AWREADY),
|
||||
.S_AXI_ACP_BVALID(S_AXI_ACP_BVALID),
|
||||
.S_AXI_ACP_RLAST(S_AXI_ACP_RLAST),
|
||||
.S_AXI_ACP_RVALID(S_AXI_ACP_RVALID),
|
||||
.S_AXI_ACP_WREADY(S_AXI_ACP_WREADY),
|
||||
.S_AXI_ACP_BRESP(S_AXI_ACP_BRESP),
|
||||
.S_AXI_ACP_RRESP(S_AXI_ACP_RRESP),
|
||||
.S_AXI_ACP_BID(S_AXI_ACP_BID),
|
||||
.S_AXI_ACP_RID(S_AXI_ACP_RID),
|
||||
.S_AXI_ACP_RDATA(S_AXI_ACP_RDATA),
|
||||
.S_AXI_ACP_ACLK(S_AXI_ACP_ACLK),
|
||||
.S_AXI_ACP_ARVALID(S_AXI_ACP_ARVALID),
|
||||
.S_AXI_ACP_AWVALID(S_AXI_ACP_AWVALID),
|
||||
.S_AXI_ACP_BREADY(S_AXI_ACP_BREADY),
|
||||
.S_AXI_ACP_RREADY(S_AXI_ACP_RREADY),
|
||||
.S_AXI_ACP_WLAST(S_AXI_ACP_WLAST),
|
||||
.S_AXI_ACP_WVALID(S_AXI_ACP_WVALID),
|
||||
.S_AXI_ACP_ARID(S_AXI_ACP_ARID),
|
||||
.S_AXI_ACP_ARPROT(S_AXI_ACP_ARPROT),
|
||||
.S_AXI_ACP_AWID(S_AXI_ACP_AWID),
|
||||
.S_AXI_ACP_AWPROT(S_AXI_ACP_AWPROT),
|
||||
.S_AXI_ACP_WID(S_AXI_ACP_WID),
|
||||
.S_AXI_ACP_ARADDR(S_AXI_ACP_ARADDR),
|
||||
.S_AXI_ACP_AWADDR(S_AXI_ACP_AWADDR),
|
||||
.S_AXI_ACP_ARCACHE(S_AXI_ACP_ARCACHE),
|
||||
.S_AXI_ACP_ARLEN(S_AXI_ACP_ARLEN),
|
||||
.S_AXI_ACP_ARQOS(S_AXI_ACP_ARQOS),
|
||||
.S_AXI_ACP_AWCACHE(S_AXI_ACP_AWCACHE),
|
||||
.S_AXI_ACP_AWLEN(S_AXI_ACP_AWLEN),
|
||||
.S_AXI_ACP_AWQOS(S_AXI_ACP_AWQOS),
|
||||
.S_AXI_ACP_ARBURST(S_AXI_ACP_ARBURST),
|
||||
.S_AXI_ACP_ARLOCK(S_AXI_ACP_ARLOCK),
|
||||
.S_AXI_ACP_ARSIZE(S_AXI_ACP_ARSIZE),
|
||||
.S_AXI_ACP_AWBURST(S_AXI_ACP_AWBURST),
|
||||
.S_AXI_ACP_AWLOCK(S_AXI_ACP_AWLOCK),
|
||||
.S_AXI_ACP_AWSIZE(S_AXI_ACP_AWSIZE),
|
||||
.S_AXI_ACP_ARUSER(S_AXI_ACP_ARUSER),
|
||||
.S_AXI_ACP_AWUSER(S_AXI_ACP_AWUSER),
|
||||
.S_AXI_ACP_WDATA(S_AXI_ACP_WDATA),
|
||||
.S_AXI_ACP_WSTRB(S_AXI_ACP_WSTRB),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(FCLK_CLK1),
|
||||
|
||||
.FCLK_CLK2(FCLK_CLK2),
|
||||
|
||||
.FCLK_CLK3(FCLK_CLK3),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
#define IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class processing_system7_v5_5_tlm;
|
||||
|
||||
class DllExport design_1_processing_system7_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
design_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~design_1_processing_system7_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_ACP_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_ACP_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
processing_system7_v5_5_tlm* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
design_1_processing_system7_0_0_sc(const design_1_processing_system7_0_0_sc&);
|
||||
const design_1_processing_system7_0_0_sc& operator=(const design_1_processing_system7_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_DESIGN_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
+307
@@ -0,0 +1,307 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: design_1_processing_system7_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_processing_system7_0_0 (
|
||||
input bit_as_bool SDIO0_WP,
|
||||
output bit_as_bool TTC0_WAVE0_OUT,
|
||||
output bit_as_bool TTC0_WAVE1_OUT,
|
||||
output bit_as_bool TTC0_WAVE2_OUT,
|
||||
output bit [1 : 0] USB0_PORT_INDCTL,
|
||||
output bit_as_bool USB0_VBUS_PWRSELECT,
|
||||
input bit_as_bool USB0_VBUS_PWRFAULT,
|
||||
output bit_as_bool M_AXI_GP0_ARVALID,
|
||||
output bit_as_bool M_AXI_GP0_AWVALID,
|
||||
output bit_as_bool M_AXI_GP0_BREADY,
|
||||
output bit_as_bool M_AXI_GP0_RREADY,
|
||||
output bit_as_bool M_AXI_GP0_WLAST,
|
||||
output bit_as_bool M_AXI_GP0_WVALID,
|
||||
output bit [11 : 0] M_AXI_GP0_ARID,
|
||||
output bit [11 : 0] M_AXI_GP0_AWID,
|
||||
output bit [11 : 0] M_AXI_GP0_WID,
|
||||
output bit [1 : 0] M_AXI_GP0_ARBURST,
|
||||
output bit [1 : 0] M_AXI_GP0_ARLOCK,
|
||||
output bit [2 : 0] M_AXI_GP0_ARSIZE,
|
||||
output bit [1 : 0] M_AXI_GP0_AWBURST,
|
||||
output bit [1 : 0] M_AXI_GP0_AWLOCK,
|
||||
output bit [2 : 0] M_AXI_GP0_AWSIZE,
|
||||
output bit [2 : 0] M_AXI_GP0_ARPROT,
|
||||
output bit [2 : 0] M_AXI_GP0_AWPROT,
|
||||
output bit [31 : 0] M_AXI_GP0_ARADDR,
|
||||
output bit [31 : 0] M_AXI_GP0_AWADDR,
|
||||
output bit [31 : 0] M_AXI_GP0_WDATA,
|
||||
output bit [3 : 0] M_AXI_GP0_ARCACHE,
|
||||
output bit [3 : 0] M_AXI_GP0_ARLEN,
|
||||
output bit [3 : 0] M_AXI_GP0_ARQOS,
|
||||
output bit [3 : 0] M_AXI_GP0_AWCACHE,
|
||||
output bit [3 : 0] M_AXI_GP0_AWLEN,
|
||||
output bit [3 : 0] M_AXI_GP0_AWQOS,
|
||||
output bit [3 : 0] M_AXI_GP0_WSTRB,
|
||||
input bit_as_bool M_AXI_GP0_ACLK,
|
||||
input bit_as_bool M_AXI_GP0_ARREADY,
|
||||
input bit_as_bool M_AXI_GP0_AWREADY,
|
||||
input bit_as_bool M_AXI_GP0_BVALID,
|
||||
input bit_as_bool M_AXI_GP0_RLAST,
|
||||
input bit_as_bool M_AXI_GP0_RVALID,
|
||||
input bit_as_bool M_AXI_GP0_WREADY,
|
||||
input bit [11 : 0] M_AXI_GP0_BID,
|
||||
input bit [11 : 0] M_AXI_GP0_RID,
|
||||
input bit [1 : 0] M_AXI_GP0_BRESP,
|
||||
input bit [1 : 0] M_AXI_GP0_RRESP,
|
||||
input bit [31 : 0] M_AXI_GP0_RDATA,
|
||||
output bit_as_bool S_AXI_ACP_ARREADY,
|
||||
output bit_as_bool S_AXI_ACP_AWREADY,
|
||||
output bit_as_bool S_AXI_ACP_BVALID,
|
||||
output bit_as_bool S_AXI_ACP_RLAST,
|
||||
output bit_as_bool S_AXI_ACP_RVALID,
|
||||
output bit_as_bool S_AXI_ACP_WREADY,
|
||||
output bit [1 : 0] S_AXI_ACP_BRESP,
|
||||
output bit [1 : 0] S_AXI_ACP_RRESP,
|
||||
output bit [2 : 0] S_AXI_ACP_BID,
|
||||
output bit [2 : 0] S_AXI_ACP_RID,
|
||||
output bit [63 : 0] S_AXI_ACP_RDATA,
|
||||
input bit_as_bool S_AXI_ACP_ACLK,
|
||||
input bit_as_bool S_AXI_ACP_ARVALID,
|
||||
input bit_as_bool S_AXI_ACP_AWVALID,
|
||||
input bit_as_bool S_AXI_ACP_BREADY,
|
||||
input bit_as_bool S_AXI_ACP_RREADY,
|
||||
input bit_as_bool S_AXI_ACP_WLAST,
|
||||
input bit_as_bool S_AXI_ACP_WVALID,
|
||||
input bit [2 : 0] S_AXI_ACP_ARID,
|
||||
input bit [2 : 0] S_AXI_ACP_ARPROT,
|
||||
input bit [2 : 0] S_AXI_ACP_AWID,
|
||||
input bit [2 : 0] S_AXI_ACP_AWPROT,
|
||||
input bit [2 : 0] S_AXI_ACP_WID,
|
||||
input bit [31 : 0] S_AXI_ACP_ARADDR,
|
||||
input bit [31 : 0] S_AXI_ACP_AWADDR,
|
||||
input bit [3 : 0] S_AXI_ACP_ARCACHE,
|
||||
input bit [3 : 0] S_AXI_ACP_ARLEN,
|
||||
input bit [3 : 0] S_AXI_ACP_ARQOS,
|
||||
input bit [3 : 0] S_AXI_ACP_AWCACHE,
|
||||
input bit [3 : 0] S_AXI_ACP_AWLEN,
|
||||
input bit [3 : 0] S_AXI_ACP_AWQOS,
|
||||
input bit [1 : 0] S_AXI_ACP_ARBURST,
|
||||
input bit [1 : 0] S_AXI_ACP_ARLOCK,
|
||||
input bit [2 : 0] S_AXI_ACP_ARSIZE,
|
||||
input bit [1 : 0] S_AXI_ACP_AWBURST,
|
||||
input bit [1 : 0] S_AXI_ACP_AWLOCK,
|
||||
input bit [2 : 0] S_AXI_ACP_AWSIZE,
|
||||
input bit [4 : 0] S_AXI_ACP_ARUSER,
|
||||
input bit [4 : 0] S_AXI_ACP_AWUSER,
|
||||
input bit [63 : 0] S_AXI_ACP_WDATA,
|
||||
input bit [7 : 0] S_AXI_ACP_WSTRB,
|
||||
input bit [0 : 0] IRQ_F2P,
|
||||
output bit_as_bool FCLK_CLK0,
|
||||
output bit_as_bool FCLK_CLK1,
|
||||
output bit_as_bool FCLK_CLK2,
|
||||
output bit_as_bool FCLK_CLK3,
|
||||
output bit_as_bool FCLK_RESET0_N,
|
||||
output bit [53 : 0] MIO,
|
||||
output bit_as_bool DDR_CAS_n,
|
||||
output bit_as_bool DDR_CKE,
|
||||
output bit_as_bool DDR_Clk_n,
|
||||
output bit_as_bool DDR_Clk,
|
||||
output bit_as_bool DDR_CS_n,
|
||||
output bit_as_bool DDR_DRSTB,
|
||||
output bit_as_bool DDR_ODT,
|
||||
output bit_as_bool DDR_RAS_n,
|
||||
output bit_as_bool DDR_WEB,
|
||||
output bit [2 : 0] DDR_BankAddr,
|
||||
output bit [14 : 0] DDR_Addr,
|
||||
output bit_as_bool DDR_VRN,
|
||||
output bit_as_bool DDR_VRP,
|
||||
output bit [3 : 0] DDR_DM,
|
||||
output bit [31 : 0] DDR_DQ,
|
||||
output bit [3 : 0] DDR_DQS_n,
|
||||
output bit [3 : 0] DDR_DQS,
|
||||
output bit_as_bool PS_SRSTB,
|
||||
output bit_as_bool PS_CLK,
|
||||
output bit_as_bool PS_PORB
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_processing_system7_0_0 (SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL,USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID,M_AXI_GP0_AWID,M_AXI_GP0_WID,M_AXI_GP0_ARBURST,M_AXI_GP0_ARLOCK,M_AXI_GP0_ARSIZE,M_AXI_GP0_AWBURST,M_AXI_GP0_AWLOCK,M_AXI_GP0_AWSIZE,M_AXI_GP0_ARPROT,M_AXI_GP0_AWPROT,M_AXI_GP0_ARADDR,M_AXI_GP0_AWADDR,M_AXI_GP0_WDATA,M_AXI_GP0_ARCACHE,M_AXI_GP0_ARLEN,M_AXI_GP0_ARQOS,M_AXI_GP0_AWCACHE,M_AXI_GP0_AWLEN,M_AXI_GP0_AWQOS,M_AXI_GP0_WSTRB,M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID,M_AXI_GP0_RID,M_AXI_GP0_BRESP,M_AXI_GP0_RRESP,M_AXI_GP0_RDATA,S_AXI_ACP_ARREADY,S_AXI_ACP_AWREADY,S_AXI_ACP_BVALID,S_AXI_ACP_RLAST,S_AXI_ACP_RVALID,S_AXI_ACP_WREADY,S_AXI_ACP_BRESP,S_AXI_ACP_RRESP,S_AXI_ACP_BID,S_AXI_ACP_RID,S_AXI_ACP_RDATA,S_AXI_ACP_ACLK,S_AXI_ACP_ARVALID,S_AXI_ACP_AWVALID,S_AXI_ACP_BREADY,S_AXI_ACP_RREADY,S_AXI_ACP_WLAST,S_AXI_ACP_WVALID,S_AXI_ACP_ARID,S_AXI_ACP_ARPROT,S_AXI_ACP_AWID,S_AXI_ACP_AWPROT,S_AXI_ACP_WID,S_AXI_ACP_ARADDR,S_AXI_ACP_AWADDR,S_AXI_ACP_ARCACHE,S_AXI_ACP_ARLEN,S_AXI_ACP_ARQOS,S_AXI_ACP_AWCACHE,S_AXI_ACP_AWLEN,S_AXI_ACP_AWQOS,S_AXI_ACP_ARBURST,S_AXI_ACP_ARLOCK,S_AXI_ACP_ARSIZE,S_AXI_ACP_AWBURST,S_AXI_ACP_AWLOCK,S_AXI_ACP_AWSIZE,S_AXI_ACP_ARUSER,S_AXI_ACP_AWUSER,S_AXI_ACP_WDATA,S_AXI_ACP_WSTRB,IRQ_F2P,FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit SDIO0_WP;
|
||||
output wire TTC0_WAVE0_OUT;
|
||||
output wire TTC0_WAVE1_OUT;
|
||||
output wire TTC0_WAVE2_OUT;
|
||||
output wire [1 : 0] USB0_PORT_INDCTL;
|
||||
output wire USB0_VBUS_PWRSELECT;
|
||||
input bit USB0_VBUS_PWRFAULT;
|
||||
output wire M_AXI_GP0_ARVALID;
|
||||
output wire M_AXI_GP0_AWVALID;
|
||||
output wire M_AXI_GP0_BREADY;
|
||||
output wire M_AXI_GP0_RREADY;
|
||||
output wire M_AXI_GP0_WLAST;
|
||||
output wire M_AXI_GP0_WVALID;
|
||||
output wire [11 : 0] M_AXI_GP0_ARID;
|
||||
output wire [11 : 0] M_AXI_GP0_AWID;
|
||||
output wire [11 : 0] M_AXI_GP0_WID;
|
||||
output wire [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output wire [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output wire [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output wire [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output wire [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output wire [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output wire [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output wire [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output wire [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output wire [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output wire [31 : 0] M_AXI_GP0_WDATA;
|
||||
output wire [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output wire [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output wire [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output wire [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output wire [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input bit M_AXI_GP0_ACLK;
|
||||
input bit M_AXI_GP0_ARREADY;
|
||||
input bit M_AXI_GP0_AWREADY;
|
||||
input bit M_AXI_GP0_BVALID;
|
||||
input bit M_AXI_GP0_RLAST;
|
||||
input bit M_AXI_GP0_RVALID;
|
||||
input bit M_AXI_GP0_WREADY;
|
||||
input bit [11 : 0] M_AXI_GP0_BID;
|
||||
input bit [11 : 0] M_AXI_GP0_RID;
|
||||
input bit [1 : 0] M_AXI_GP0_BRESP;
|
||||
input bit [1 : 0] M_AXI_GP0_RRESP;
|
||||
input bit [31 : 0] M_AXI_GP0_RDATA;
|
||||
output wire S_AXI_ACP_ARREADY;
|
||||
output wire S_AXI_ACP_AWREADY;
|
||||
output wire S_AXI_ACP_BVALID;
|
||||
output wire S_AXI_ACP_RLAST;
|
||||
output wire S_AXI_ACP_RVALID;
|
||||
output wire S_AXI_ACP_WREADY;
|
||||
output wire [1 : 0] S_AXI_ACP_BRESP;
|
||||
output wire [1 : 0] S_AXI_ACP_RRESP;
|
||||
output wire [2 : 0] S_AXI_ACP_BID;
|
||||
output wire [2 : 0] S_AXI_ACP_RID;
|
||||
output wire [63 : 0] S_AXI_ACP_RDATA;
|
||||
input bit S_AXI_ACP_ACLK;
|
||||
input bit S_AXI_ACP_ARVALID;
|
||||
input bit S_AXI_ACP_AWVALID;
|
||||
input bit S_AXI_ACP_BREADY;
|
||||
input bit S_AXI_ACP_RREADY;
|
||||
input bit S_AXI_ACP_WLAST;
|
||||
input bit S_AXI_ACP_WVALID;
|
||||
input bit [2 : 0] S_AXI_ACP_ARID;
|
||||
input bit [2 : 0] S_AXI_ACP_ARPROT;
|
||||
input bit [2 : 0] S_AXI_ACP_AWID;
|
||||
input bit [2 : 0] S_AXI_ACP_AWPROT;
|
||||
input bit [2 : 0] S_AXI_ACP_WID;
|
||||
input bit [31 : 0] S_AXI_ACP_ARADDR;
|
||||
input bit [31 : 0] S_AXI_ACP_AWADDR;
|
||||
input bit [3 : 0] S_AXI_ACP_ARCACHE;
|
||||
input bit [3 : 0] S_AXI_ACP_ARLEN;
|
||||
input bit [3 : 0] S_AXI_ACP_ARQOS;
|
||||
input bit [3 : 0] S_AXI_ACP_AWCACHE;
|
||||
input bit [3 : 0] S_AXI_ACP_AWLEN;
|
||||
input bit [3 : 0] S_AXI_ACP_AWQOS;
|
||||
input bit [1 : 0] S_AXI_ACP_ARBURST;
|
||||
input bit [1 : 0] S_AXI_ACP_ARLOCK;
|
||||
input bit [2 : 0] S_AXI_ACP_ARSIZE;
|
||||
input bit [1 : 0] S_AXI_ACP_AWBURST;
|
||||
input bit [1 : 0] S_AXI_ACP_AWLOCK;
|
||||
input bit [2 : 0] S_AXI_ACP_AWSIZE;
|
||||
input bit [4 : 0] S_AXI_ACP_ARUSER;
|
||||
input bit [4 : 0] S_AXI_ACP_AWUSER;
|
||||
input bit [63 : 0] S_AXI_ACP_WDATA;
|
||||
input bit [7 : 0] S_AXI_ACP_WSTRB;
|
||||
input bit [0 : 0] IRQ_F2P;
|
||||
output wire FCLK_CLK0;
|
||||
output wire FCLK_CLK1;
|
||||
output wire FCLK_CLK2;
|
||||
output wire FCLK_CLK3;
|
||||
output wire FCLK_RESET0_N;
|
||||
inout wire [53 : 0] MIO;
|
||||
inout wire DDR_CAS_n;
|
||||
inout wire DDR_CKE;
|
||||
inout wire DDR_Clk_n;
|
||||
inout wire DDR_Clk;
|
||||
inout wire DDR_CS_n;
|
||||
inout wire DDR_DRSTB;
|
||||
inout wire DDR_ODT;
|
||||
inout wire DDR_RAS_n;
|
||||
inout wire DDR_WEB;
|
||||
inout wire [2 : 0] DDR_BankAddr;
|
||||
inout wire [14 : 0] DDR_Addr;
|
||||
inout wire DDR_VRN;
|
||||
inout wire DDR_VRP;
|
||||
inout wire [3 : 0] DDR_DM;
|
||||
inout wire [31 : 0] DDR_DQ;
|
||||
inout wire [3 : 0] DDR_DQS_n;
|
||||
inout wire [3 : 0] DDR_DQS;
|
||||
inout wire PS_SRSTB;
|
||||
inout wire PS_CLK;
|
||||
inout wire PS_PORB;
|
||||
endmodule
|
||||
`endif
|
||||
+170
@@ -0,0 +1,170 @@
|
||||
// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#ifndef _B_TRANSPORT_CONVERTER_H_
|
||||
#define _B_TRANSPORT_CONVERTER_H_
|
||||
|
||||
#include <systemc>
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
class b_transport_converter: public sc_core::sc_module
|
||||
{
|
||||
enum TLM_IF_TYPE
|
||||
{
|
||||
B_TRANSPORT = 0,
|
||||
NB_TRANSPORT,
|
||||
TRANSPORT_DBG,
|
||||
DMI_IF,
|
||||
INVALID_IF
|
||||
};
|
||||
typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(b_transport_converter);
|
||||
b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
|
||||
sc_module(name)
|
||||
{
|
||||
target_socket.register_b_transport(
|
||||
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
|
||||
initiator_socket.register_nb_transport_bw(
|
||||
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
|
||||
|
||||
}
|
||||
|
||||
//simple tlm target/initiator socket...
|
||||
tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
|
||||
tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
|
||||
|
||||
|
||||
public:
|
||||
void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
|
||||
{
|
||||
tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
|
||||
switch(get_tlm_if_type(payload.get_address()))
|
||||
{
|
||||
case B_TRANSPORT:
|
||||
initiator_socket->b_transport(payload, time);
|
||||
break;
|
||||
|
||||
case NB_TRANSPORT:
|
||||
initiator_socket->nb_transport_fw(payload, phase, time);
|
||||
wait(resp_complete_event); //! Wait for the response to complete
|
||||
break;
|
||||
|
||||
case TRANSPORT_DBG:
|
||||
initiator_socket->transport_dbg(payload);
|
||||
break;
|
||||
|
||||
case DMI_IF:
|
||||
break;
|
||||
|
||||
default:
|
||||
SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
|
||||
}
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum
|
||||
nb_transport_bw(tlm::tlm_generic_payload& payload,
|
||||
tlm::tlm_phase& phase, sc_core::sc_time& time)
|
||||
{
|
||||
if(phase == tlm::BEGIN_RESP) {
|
||||
resp_complete_event.notify();
|
||||
phase = tlm::END_RESP;
|
||||
return tlm::TLM_UPDATED;
|
||||
}
|
||||
return tlm::TLM_ACCEPTED;
|
||||
}
|
||||
|
||||
private:
|
||||
TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
|
||||
{
|
||||
//check for b_transport addresses
|
||||
for(auto& addr_range: m_b_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return B_TRANSPORT;
|
||||
}
|
||||
}
|
||||
|
||||
//check for nb_transport addresses
|
||||
for(auto& addr_range: m_nb_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return NB_TRANSPORT;
|
||||
}
|
||||
}
|
||||
//check for dbg_transport addresses
|
||||
for(auto& addr_range: m_dbg_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return TRANSPORT_DBG;
|
||||
}
|
||||
}
|
||||
|
||||
//By default return NB_TRANSPORT
|
||||
return NB_TRANSPORT;
|
||||
}
|
||||
|
||||
//Start and End Address List for each of interfaces...
|
||||
static addr_range_list m_b_transport_addr_list;
|
||||
static addr_range_list m_nb_transport_addr_list;
|
||||
static addr_range_list m_dbg_transport_addr_list;
|
||||
|
||||
//event to notify completion of transaction
|
||||
sc_core::sc_event resp_complete_event;
|
||||
};
|
||||
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
|
||||
|
||||
|
||||
#endif /* _B_TRANSPORT_CONVERTER_H_ */
|
||||
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
#ifndef __PS7_H__
|
||||
#define __PS7_H__
|
||||
|
||||
#include "systemc.h"
|
||||
#include "xtlm.h"
|
||||
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
|
||||
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "genattr.h"
|
||||
#include "xilinx-zynq.h"
|
||||
#include "b_transport_converter.h"
|
||||
#include "utils/xtlm_aximm_fifo.h"
|
||||
|
||||
/***************************************************************************************
|
||||
*
|
||||
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
|
||||
* calls to xTLM sockets bn_transport_x() calls..
|
||||
*
|
||||
* This is Only specific to remote-port so not creating seperate header for it.
|
||||
*
|
||||
***************************************************************************************/
|
||||
template <int IN_WIDTH, int OUT_WIDTH>
|
||||
class rptlm2xtlm_converter : public sc_module{
|
||||
public:
|
||||
tlm::tlm_target_socket<IN_WIDTH> target_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket rd_socket;
|
||||
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
|
||||
void registerUserExtensionHandlerCallback(
|
||||
void (*callback)(xtlm::aximm_payload*,
|
||||
const tlm::tlm_generic_payload*));
|
||||
|
||||
private:
|
||||
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
|
||||
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
|
||||
};
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with tlm2xtlm bridge
|
||||
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
|
||||
*
|
||||
* caller: tlm2xtlm bridge
|
||||
* purpose: To get master id and other parameters out of genattr_extension
|
||||
* and use master id to AxUSER PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with xtlm2tlm bridge
|
||||
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
|
||||
*
|
||||
* caller: xtlm2tlm bridge
|
||||
* purpose: To create and add master id and other parameters to genattr_extension.
|
||||
* Master id red from AxID PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// //
|
||||
// File: processing_system7_tlm.h //
|
||||
// //
|
||||
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
|
||||
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
|
||||
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
|
||||
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
|
||||
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
|
||||
// it fill the the gap between input/output ports of vivado generated wrapper to //
|
||||
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
|
||||
// based on IP configuration in vivado. //
|
||||
// //
|
||||
// //
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
class processing_system7_v5_5_tlm : public sc_core::sc_module {
|
||||
|
||||
public:
|
||||
// Non-AXI ports are declared here
|
||||
sc_core::sc_in<bool> SDIO0_WP;
|
||||
sc_core::sc_out<bool> TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out<bool> TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out<bool> TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in<bool> S_AXI_ACP_ACLK;
|
||||
sc_core::sc_in<sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out<bool> FCLK_CLK0;
|
||||
sc_core::sc_out<bool> FCLK_CLK1;
|
||||
sc_core::sc_out<bool> FCLK_CLK2;
|
||||
sc_core::sc_out<bool> FCLK_CLK3;
|
||||
sc_core::sc_out<bool> FCLK_RESET0_N;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout<bool> DDR_CAS_n;
|
||||
sc_core::sc_inout<bool> DDR_CKE;
|
||||
sc_core::sc_inout<bool> DDR_Clk_n;
|
||||
sc_core::sc_inout<bool> DDR_Clk;
|
||||
sc_core::sc_inout<bool> DDR_CS_n;
|
||||
sc_core::sc_inout<bool> DDR_DRSTB;
|
||||
sc_core::sc_inout<bool> DDR_ODT;
|
||||
sc_core::sc_inout<bool> DDR_RAS_n;
|
||||
sc_core::sc_inout<bool> DDR_WEB;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout<bool> DDR_VRN;
|
||||
sc_core::sc_inout<bool> DDR_VRP;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout<bool> PS_SRSTB;
|
||||
sc_core::sc_inout<bool> PS_CLK;
|
||||
sc_core::sc_inout<bool> PS_PORB;
|
||||
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_ACP_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_ACP_rd_socket;
|
||||
|
||||
//constructor having three paramters
|
||||
// 1. module name in sc_module_name objec,
|
||||
// 2. reference to map object of name and integer value pairs
|
||||
// 3. reference to map object of name and string value pairs
|
||||
// All the model parameters (integer and string) which are configuration parameters
|
||||
// of Processing System 7 IP propogated from Vivado
|
||||
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties&);
|
||||
|
||||
~processing_system7_v5_5_tlm();
|
||||
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
|
||||
|
||||
private:
|
||||
|
||||
//zynq tlm wrapper provided by Edgar
|
||||
//module with interfaces of standard tlm
|
||||
//and input/output ports at signal level
|
||||
xilinx_zynq* m_zynq_tlm_model;
|
||||
|
||||
// Xtlm2tlm_t Bridges
|
||||
// Converts Xtlm transactions to tlm transactions
|
||||
// Bridge's Xtlm wr/rd target sockets binds with
|
||||
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
|
||||
// socket with xilinx_zynq's target socket
|
||||
xtlm::xaximm_xtlm2tlm_t<64,32> S_AXI_ACP_xtlm_brdg;
|
||||
xtlm::xtlm_aximm_fifo *S_AXI_ACP_buff;
|
||||
|
||||
// This Bridges converts b_transport to nb_transports and also
|
||||
// Converts tlm transactions to xtlm transactions.
|
||||
// Bridge's tlm simple target socket binds with
|
||||
// simple initiator socket of xilinx_zynqmp and xtlm
|
||||
// socket with xilinx_zynq's simple target socket
|
||||
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
|
||||
|
||||
// sc_clocks for generating pl clocks
|
||||
// output pins FCLK_CLK0..3 are drived by these clocks
|
||||
sc_core::sc_clock FCLK_CLK0_clk;
|
||||
sc_core::sc_clock FCLK_CLK1_clk;
|
||||
sc_core::sc_clock FCLK_CLK2_clk;
|
||||
sc_core::sc_clock FCLK_CLK3_clk;
|
||||
|
||||
|
||||
//Method which is sentive to FCLK_CLK0_clk sc_clock object
|
||||
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
|
||||
void trigger_FCLK_CLK0_pin();
|
||||
//Method which is sentive to FCLK_CLK1_clk sc_clock object
|
||||
//FCLK_CLK1 pin written based on FCLK_CLK1_clk clock value
|
||||
void trigger_FCLK_CLK1_pin();
|
||||
//Method which is sentive to FCLK_CLK2_clk sc_clock object
|
||||
//FCLK_CLK2 pin written based on FCLK_CLK2_clk clock value
|
||||
void trigger_FCLK_CLK2_pin();
|
||||
//Method which is sentive to FCLK_CLK3_clk sc_clock object
|
||||
//FCLK_CLK3 pin written based on FCLK_CLK3_clk clock value
|
||||
void trigger_FCLK_CLK3_pin();
|
||||
|
||||
void IRQ_F2P_method();
|
||||
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
|
||||
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
|
||||
void FCLK_RESET0_N_trigger();
|
||||
|
||||
sc_signal<bool> qemu_rst;
|
||||
void start_of_simulation();
|
||||
|
||||
xsc::common_cpp::properties prop;
|
||||
|
||||
};
|
||||
#endif
|
||||
+104
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "systemc.h"
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "tlm_utils/tlm_quantumkeeper.h"
|
||||
|
||||
#include "remote-port-tlm.h"
|
||||
#include "remote-port-tlm-memory-master.h"
|
||||
#include "remote-port-tlm-memory-slave.h"
|
||||
#include "remote-port-tlm-wires.h"
|
||||
|
||||
class xilinx_zynq
|
||||
: public remoteport_tlm
|
||||
{
|
||||
private:
|
||||
remoteport_tlm_memory_master rp_m_axi_gp0;
|
||||
remoteport_tlm_memory_master rp_m_axi_gp1;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_gp0;
|
||||
remoteport_tlm_memory_slave rp_s_axi_gp1;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp0;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp1;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp2;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp3;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_acp;
|
||||
|
||||
remoteport_tlm_wires rp_wires_in;
|
||||
remoteport_tlm_wires rp_wires_out;
|
||||
remoteport_tlm_wires rp_irq_out;
|
||||
|
||||
public:
|
||||
/*
|
||||
* M_AXI_GP 0 - 1.
|
||||
* These sockets represent the High speed PS to PL interfaces.
|
||||
* These are AXI Slave ports on the PS side and AXI Master ports
|
||||
* on the PL side.
|
||||
*
|
||||
* Used to transfer data from the PS to the PL.
|
||||
*/
|
||||
tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
|
||||
|
||||
/*
|
||||
* S_AXI_GP0 - 1.
|
||||
* These sockets represent the High speed IO Coherent PL to PS
|
||||
* interfaces.
|
||||
*
|
||||
* HP0 - 3.
|
||||
* These sockets represent the High performance dataflow PL to PS interfaces.
|
||||
*
|
||||
* ACP
|
||||
* Accelerator Coherency Port, used to transfered coherent data to
|
||||
* the PS via the Cortex-A9 subsystem.
|
||||
*
|
||||
* These are AXI Master ports on the PS side and AXI Slave ports
|
||||
* on the PL side.
|
||||
*
|
||||
* Used to transfer data from the PL to the PS.
|
||||
*/
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
|
||||
|
||||
/* PL (fabric) to PS interrupt signals. */
|
||||
sc_vector<sc_signal<bool> > pl2ps_irq;
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
sc_vector<sc_signal<bool> > ps2pl_irq;
|
||||
|
||||
/* FPGA out resets. */
|
||||
sc_vector<sc_signal<bool> > ps2pl_rst;
|
||||
|
||||
xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
|
||||
//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync = NULL);
|
||||
};
|
||||
+1148
File diff suppressed because it is too large
Load Diff
+1644
File diff suppressed because it is too large
Load Diff
+49
@@ -0,0 +1,49 @@
|
||||
|
||||
# file: design_1_rst_ps7_0_100M_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
+978
@@ -0,0 +1,978 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_rst_ps7_0_100M_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clock</spirit:name>
|
||||
<spirit:displayName>Clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">design_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_reset</spirit:name>
|
||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:presence>required</xilinx:presence>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
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<spirit:name>INSERT_VIP</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:997014a8</spirit:value>
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<spirit:name>xilinx_implementation</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:0cff2c90</spirit:value>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>GENtimestamp</spirit:name>
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||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_rst_ps7_0_100M_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk]
|
||||
|
||||
|
||||
+985
@@ -0,0 +1,985 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:53 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Design : design_1_rst_ps7_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module design_1_rst_ps7_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
design_1_rst_ps7_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module design_1_rst_ps7_0_100M_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module design_1_rst_ps7_0_100M_0_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "lpf" *)
|
||||
module design_1_rst_ps7_0_100M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
design_1_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
design_1_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
(* ORIG_REF_NAME = "proc_sys_reset" *)
|
||||
module design_1_rst_ps7_0_100M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
design_1_rst_ps7_0_100M_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
design_1_rst_ps7_0_100M_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "sequence_psr" *)
|
||||
module design_1_rst_ps7_0_100M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
design_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "upcnt_n" *)
|
||||
module design_1_rst_ps7_0_100M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:53 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_stub.v
|
||||
// Design : design_1_rst_ps7_0_100M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
module design_1_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
|
||||
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
|
||||
interconnect_aresetn, peripheral_aresetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="slowest_sync_clk" */;
|
||||
input slowest_sync_clk /* synthesis syn_isclock = 1 */;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
endmodule
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY design_1_rst_ps7_0_100M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_1_rst_ps7_0_100M_0;
|
||||
|
||||
ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END design_1_rst_ps7_0_100M_0_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY design_1_rst_ps7_0_100M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END design_1_rst_ps7_0_100M_0;
|
||||
|
||||
ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END design_1_rst_ps7_0_100M_0_arch;
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
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// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
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// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
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//
|
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// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _design_1_xlconstant_0_0_H_
|
||||
#define _design_1_xlconstant_0_0_H_
|
||||
|
||||
#include "xlconstant_v1_1_7.h"
|
||||
#include "systemc.h"
|
||||
class design_1_xlconstant_0_0 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_7<1,1> mod;
|
||||
sc_out< sc_bv<1> > dout;
|
||||
design_1_xlconstant_0_0 (sc_core::sc_module_name name);
|
||||
};
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
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// (2) AMD shall not be liable (whether in contract or tort,
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||||
// including negligence, or under any other theory of
|
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// liability) for any loss or damage of any kind or nature
|
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
|
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// special, incidental, or consequential loss or damage
|
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
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//
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// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
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||||
// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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||||
// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:xlconstant:1.1
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// IP Revision: 7
|
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`timescale 1ns/1ps
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|
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(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconstant_0_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: xl_Constant_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`ifdef XILINX_SIMULATOR
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_xlconstant_0_0 (
|
||||
output bit [0 : 0 ] dout
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_xlconstant_0_0 (dout)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
output wire [0 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _xlconstant_v1_1_7_H_
|
||||
#define _xlconstant_v1_1_7_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,long int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_7) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_7) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_xlconstant_0_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconstant_0_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_xlconstant_0_1</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
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||||
<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:01882201</spirit:value>
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||||
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||||
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||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_systemcsimulation</spirit:name>
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||||
<spirit:displayName>SystemC Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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||||
<spirit:language>systemc</spirit:language>
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||||
<spirit:modelName>xlconstant_v1_1_7</spirit:modelName>
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||||
<spirit:fileSetRef>
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<spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:7b885469</spirit:value>
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<spirit:name>sim_type</spirit:name>
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<spirit:value>tlm</spirit:value>
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<spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
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<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:language>systemc</spirit:language>
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<spirit:modelName>design_1_xlconstant_0_1</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>sim_type</spirit:name>
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<spirit:value>tlm</spirit:value>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
|
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<spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sun Dec 01 17:17:47 UTC 2024</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:7b885469</spirit:value>
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<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
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<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sun Dec 01 17:17:50 UTC 2024</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:7b885469</spirit:value>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:modelName>xlconstant_v1_1_7_xlconstant</spirit:modelName>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
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<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>design_1_xlconstant_0_1</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sun Dec 01 17:17:50 UTC 2024</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:01882201</spirit:value>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>dout</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.CONST_WIDTH')) - 1)">0</spirit:left>
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<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
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</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CONST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Const Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>CONST_VAL</spirit:name>
|
||||
<spirit:displayName>Const Val</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x1</spirit:value>
|
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</spirit:modelParameter>
|
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</spirit:modelParameters>
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</spirit:model>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:isIncludeFile>true</spirit:isIncludeFile>
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</spirit:file>
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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</spirit:component>
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+65
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|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _design_1_xlconstant_0_1_H_
|
||||
#define _design_1_xlconstant_0_1_H_
|
||||
|
||||
#include "xlconstant_v1_1_7.h"
|
||||
#include "systemc.h"
|
||||
class design_1_xlconstant_0_1 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_7<1,1> mod;
|
||||
sc_out< sc_bv<1> > dout;
|
||||
design_1_xlconstant_0_1 (sc_core::sc_module_name name);
|
||||
};
|
||||
|
||||
#endif
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconstant_0_1 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: xl_Constant_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`ifdef XILINX_SIMULATOR
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module design_1_xlconstant_0_1 (
|
||||
output bit [0 : 0 ] dout
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module design_1_xlconstant_0_1 (dout)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
output wire [0 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _xlconstant_v1_1_7_H_
|
||||
#define _xlconstant_v1_1_7_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,long int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_7) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_7) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
+69
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "design_1_xlconstant_0_1,xlconstant_v1_1_7_xlconstant,{}" *)
|
||||
(* CORE_GENERATION_INFO = "design_1_xlconstant_0_1,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module design_1_xlconstant_0_1 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 8.00 [get_ports clk ];
|
||||
+1438
File diff suppressed because it is too large
Load Diff
+3881
File diff suppressed because it is too large
Load Diff
+43
@@ -0,0 +1,43 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Dec 1 18:19:55 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-praktikum/Milestone5/es-milestone5/es-milestone5.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
|
||||
// Design : design_1_zybo_audio_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "zybo_audio,Vivado 2023.1" *)
|
||||
module design_1_zybo_audio_0_0(clk, axis_pb_data, axis_pb_valid,
|
||||
axis_pb_ready, axis_rec_data, axis_rec_valid, axis_rec_ready, mute, mclk, bclk, pb_dat, pb_lrc,
|
||||
rec_dat, rec_lrc, scl_i, scl_o, scl_t, sda_i, sda_o, sda_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="axis_pb_data[31:0],axis_pb_valid,axis_pb_ready,axis_rec_data[31:0],axis_rec_valid,axis_rec_ready,mute,mclk,bclk,pb_dat,pb_lrc,rec_dat,rec_lrc,scl_i,scl_o,scl_t,sda_i,sda_o,sda_t" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]axis_pb_data;
|
||||
input axis_pb_valid;
|
||||
output axis_pb_ready;
|
||||
output [31:0]axis_rec_data;
|
||||
output axis_rec_valid;
|
||||
input axis_rec_ready;
|
||||
output mute;
|
||||
output mclk;
|
||||
output bclk;
|
||||
output pb_dat;
|
||||
output pb_lrc;
|
||||
input rec_dat;
|
||||
output rec_lrc;
|
||||
input scl_i;
|
||||
output scl_o;
|
||||
output scl_t;
|
||||
input sda_i;
|
||||
output sda_o;
|
||||
output sda_t;
|
||||
endmodule
|
||||
+166
@@ -0,0 +1,166 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:zybo_audio:1.0
|
||||
-- IP Revision: 22
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_zybo_audio_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END design_1_zybo_audio_0_0;
|
||||
|
||||
ARCHITECTURE design_1_zybo_audio_0_0_arch OF design_1_zybo_audio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT zybo_audio IS
|
||||
GENERIC (
|
||||
MIC_IN : INTEGER;
|
||||
I2C_CLKDIV : INTEGER;
|
||||
I2S_CLKDIV : INTEGER;
|
||||
HAS_RESET_PIN : BOOLEAN;
|
||||
SRR_70 : STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT zybo_audio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_pb_data: SIGNAL IS "XIL_INTERFACENAME axis_pb, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_rec_data: SIGNAL IS "XIL_INTERFACENAME axis_rec, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF axis_rec:axis_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
BEGIN
|
||||
U0 : zybo_audio
|
||||
GENERIC MAP (
|
||||
MIC_IN => 0,
|
||||
I2C_CLKDIV => 9999,
|
||||
I2S_CLKDIV => 3,
|
||||
HAS_RESET_PIN => false,
|
||||
SRR_70 => B"00000000"
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => '1',
|
||||
axis_pb_data => axis_pb_data,
|
||||
axis_pb_valid => axis_pb_valid,
|
||||
axis_pb_ready => axis_pb_ready,
|
||||
axis_rec_data => axis_rec_data,
|
||||
axis_rec_valid => axis_rec_valid,
|
||||
axis_rec_ready => axis_rec_ready,
|
||||
mute => mute,
|
||||
mclk => mclk,
|
||||
bclk => bclk,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc,
|
||||
scl_i => scl_i,
|
||||
scl_o => scl_o,
|
||||
scl_t => scl_t,
|
||||
sda_i => sda_i,
|
||||
sda_o => sda_o,
|
||||
sda_t => sda_t
|
||||
);
|
||||
END design_1_zybo_audio_0_0_arch;
|
||||
+174
@@ -0,0 +1,174 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:zybo_audio:1.0
|
||||
-- IP Revision: 22
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_zybo_audio_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END design_1_zybo_audio_0_0;
|
||||
|
||||
ARCHITECTURE design_1_zybo_audio_0_0_arch OF design_1_zybo_audio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT zybo_audio IS
|
||||
GENERIC (
|
||||
MIC_IN : INTEGER;
|
||||
I2C_CLKDIV : INTEGER;
|
||||
I2S_CLKDIV : INTEGER;
|
||||
HAS_RESET_PIN : BOOLEAN;
|
||||
SRR_70 : STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT zybo_audio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "zybo_audio,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_zybo_audio_0_0_arch : ARCHITECTURE IS "design_1_zybo_audio_0_0,zybo_audio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "design_1_zybo_audio_0_0,zybo_audio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zybo_audio,x_ipVersion=1.0,x_ipCoreRevision=22,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,MIC_IN=0,I2C_CLKDIV=9999,I2S_CLKDIV=3,HAS_RESET_PIN=false,SRR_70=00000000}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_pb_data: SIGNAL IS "XIL_INTERFACENAME axis_pb, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_rec_data: SIGNAL IS "XIL_INTERFACENAME axis_rec, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF axis_rec:axis_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
BEGIN
|
||||
U0 : zybo_audio
|
||||
GENERIC MAP (
|
||||
MIC_IN => 0,
|
||||
I2C_CLKDIV => 9999,
|
||||
I2S_CLKDIV => 3,
|
||||
HAS_RESET_PIN => false,
|
||||
SRR_70 => B"00000000"
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => '1',
|
||||
axis_pb_data => axis_pb_data,
|
||||
axis_pb_valid => axis_pb_valid,
|
||||
axis_pb_ready => axis_pb_ready,
|
||||
axis_rec_data => axis_rec_data,
|
||||
axis_rec_valid => axis_rec_valid,
|
||||
axis_rec_ready => axis_rec_ready,
|
||||
mute => mute,
|
||||
mclk => mclk,
|
||||
bclk => bclk,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc,
|
||||
scl_i => scl_i,
|
||||
scl_o => scl_o,
|
||||
scl_t => scl_t,
|
||||
sda_i => sda_i,
|
||||
sda_o => sda_o,
|
||||
sda_t => sda_t
|
||||
);
|
||||
END design_1_zybo_audio_0_0_arch;
|
||||
+15354
File diff suppressed because it is too large
Load Diff
+15354
File diff suppressed because it is too large
Load Diff
+2177
File diff suppressed because it is too large
Load Diff
+147
@@ -0,0 +1,147 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2c_transmitter is
|
||||
generic(
|
||||
AW : positive := 8;
|
||||
I2C_CLKDIV : positive := 9999
|
||||
);
|
||||
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic;
|
||||
data : in std_logic_vector ( 11 downto 0);
|
||||
addr : out std_logic_vector (AW-1 downto 0);
|
||||
done : out std_logic:='0';
|
||||
scl_i : in std_logic;
|
||||
scl_o : out std_logic:='1';
|
||||
scl_t : out std_logic:='1';
|
||||
sda_i : in std_logic;
|
||||
sda_o : out std_logic:='1';
|
||||
sda_t : out std_logic:='1'
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of i2c_transmitter is
|
||||
|
||||
signal nextstep : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- clock divider
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
variable cnt : unsigned(31 downto 0) := (others=>'0');
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if resetn='0' then
|
||||
nextstep <= '0';
|
||||
cnt := (others=>'0');
|
||||
else
|
||||
nextstep <= '0';
|
||||
if cnt = to_unsigned(I2C_CLKDIV,32) then
|
||||
nextstep <= '1';
|
||||
cnt := (others=>'0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- transmitter core
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
type state_type is (IDLE, TRANSMIT, DEADEND);
|
||||
variable state : state_type;
|
||||
|
||||
constant NSTEPS : integer := 42;
|
||||
-- St D7 D6 D5 D4 D3 D2 D1 D0 ACK Sp
|
||||
variable sclbuffer : std_logic_vector (0 to NSTEPS-1) := "110011001100110011001100110011001100110011";
|
||||
variable sdabuffer : std_logic_vector (0 to NSTEPS-1) := "100111100001111000011110000111100001111001";
|
||||
|
||||
variable stepcnt : unsigned( 5 downto 0) := (others=>'0');
|
||||
variable addrcnt : unsigned(AW-1 downto 0) := (others=>'0');
|
||||
|
||||
variable startcond : std_logic;
|
||||
variable stopcond : std_logic;
|
||||
variable finished : std_logic;
|
||||
variable restart : std_logic;
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
if resetn='0' then
|
||||
done <= '0';
|
||||
state := IDLE;
|
||||
addrcnt := (others=>'0');
|
||||
else
|
||||
addr <= std_logic_vector(addrcnt);
|
||||
sda_o <= '0';
|
||||
sda_t <= '1';
|
||||
scl_o <= '0';
|
||||
scl_t <= '1';
|
||||
case state is
|
||||
when IDLE =>
|
||||
done <= '0';
|
||||
if nextstep = '1' then
|
||||
stepcnt := (others=>'0');
|
||||
|
||||
startcond := data(11); -- 1 = send start condition
|
||||
stopcond := data(10); -- 1 = send stop condition
|
||||
finished := data( 9); -- 1 = stop fsm after sending current byte
|
||||
restart := data( 8); -- 1 = restart transfer sequence from address 0 ELSE stop FSM
|
||||
for i in 0 to 7 loop
|
||||
sdabuffer(3+4*i to 6+4*i) := (others=>data(7-i));
|
||||
end loop;
|
||||
sdabuffer( 1 to 2) := (others=>not startcond);
|
||||
sdabuffer(NSTEPS-3 to NSTEPS-2) := (others=>not stopcond);
|
||||
sclbuffer(NSTEPS-4 to NSTEPS-3) := (others=>not stopcond);
|
||||
|
||||
state := TRANSMIT;
|
||||
end if;
|
||||
|
||||
|
||||
when TRANSMIT =>
|
||||
done <= '0'; -- default assignment
|
||||
if sclbuffer(to_integer(stepcnt)) = '0' then
|
||||
scl_t <= '0';
|
||||
else
|
||||
scl_t <= '1';
|
||||
end if;
|
||||
if sdabuffer(to_integer(stepcnt)) = '0' then
|
||||
sda_t <= '0';
|
||||
else
|
||||
sda_t <= '1';
|
||||
end if;
|
||||
|
||||
if nextstep = '1' then
|
||||
if stepcnt = NSTEPS-1 then -- byte finished ?
|
||||
stepcnt := (others=>'0');
|
||||
if finished = '0' then -- sequence of I2C commands finished?
|
||||
addrcnt:= addrcnt + 1;
|
||||
state := IDLE;
|
||||
elsif restart = '1' then -- restart (send again) ?
|
||||
addrcnt:= (others=>'0');
|
||||
state := IDLE;
|
||||
else
|
||||
state := DEADEND;
|
||||
end if;
|
||||
else
|
||||
stepcnt := stepcnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DEADEND => -- this is the point of no return
|
||||
done <= '1';
|
||||
sda_t <= '1';
|
||||
scl_t <= '1';
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
+135
@@ -0,0 +1,135 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2s_transceiver is
|
||||
generic(
|
||||
I2S_CLKDIV : natural := 4 -- fs = sysclk / 512 / (clkdiv+1)
|
||||
);
|
||||
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic;
|
||||
i2c_done : in std_logic;
|
||||
|
||||
axis_pb_data : in std_logic_vector (31 downto 0);
|
||||
axis_pb_valid : in std_logic;
|
||||
axis_pb_ready : out std_logic;
|
||||
|
||||
axis_rec_data : out std_logic_vector (31 downto 0);
|
||||
axis_rec_valid : out std_logic;
|
||||
axis_rec_ready : in std_logic;
|
||||
|
||||
mclk : out std_logic;
|
||||
mute : out std_logic;
|
||||
|
||||
bclk : out std_logic;
|
||||
pb_dat : out std_logic;
|
||||
pb_lrc : out std_logic;
|
||||
rec_dat : in std_logic;
|
||||
rec_lrc : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of i2s_transceiver is
|
||||
|
||||
signal mclk_s : std_logic := '0';
|
||||
signal bclk_s : std_logic := '0';
|
||||
signal bclk_period_s : unsigned(5 downto 0) := (others=>'0');
|
||||
|
||||
begin
|
||||
|
||||
mute <= i2c_done;
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- mclk / bclk generation
|
||||
-- mclk = sysclk / 2 / (clkdiv+1) = 256*fs
|
||||
-- bclk = mclk / 4 = 64 * fs
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
variable mcnt : unsigned(7 downto 0) := (others=>'0');
|
||||
variable bcnt : unsigned(1 downto 0) := (others=>'0');
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if resetn='0' or i2c_done = '0' then
|
||||
mcnt := (others=>'0');
|
||||
mclk_s <= '0';
|
||||
bclk_s <= '0';
|
||||
bclk_period_s <= (others=>'0');
|
||||
else
|
||||
if mcnt = to_unsigned(I2S_CLKDIV,8) then
|
||||
mclk_s <= not mclk_s;
|
||||
if bcnt = "11" then
|
||||
if (bclk_s = '1') then
|
||||
bclk_period_s <= bclk_period_s + 1;
|
||||
end if;
|
||||
bclk_s <= not bclk_s;
|
||||
end if;
|
||||
mcnt := (others=>'0');
|
||||
bcnt := bcnt + 1;
|
||||
else
|
||||
mcnt := mcnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- data transmission
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
variable pb_buffer : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable rec_buffer : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable bclk_period_i : integer;
|
||||
variable pb_buff_loaded : boolean := false;
|
||||
variable rec_buff_transmitted : boolean := false;
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
bclk_period_i := to_integer(bclk_period_s);
|
||||
|
||||
if resetn='0' or i2c_done = '0' then
|
||||
axis_rec_data <=(others =>'0');
|
||||
axis_rec_valid <= '0';
|
||||
axis_pb_ready <= '0';
|
||||
pb_dat <= '0';
|
||||
pb_lrc <= '0';
|
||||
rec_lrc <= '0';
|
||||
else
|
||||
axis_pb_ready <= '0';
|
||||
if axis_rec_ready = '1' then -- keep valid until data has been consumed (if ready is not asserted in time, data will be lost)
|
||||
axis_rec_valid <= '0';
|
||||
end if;
|
||||
pb_dat <= '0';
|
||||
if bclk_period_i = 0 and not pb_buff_loaded then
|
||||
pb_buff_loaded := true;
|
||||
rec_buff_transmitted := false;
|
||||
pb_buffer := axis_pb_data;
|
||||
axis_pb_ready <= '1';
|
||||
elsif bclk_period_i >= 1 and bclk_period_i <= 16 then
|
||||
pb_buff_loaded := false;
|
||||
pb_dat <= pb_buffer(32-bclk_period_i);
|
||||
if bclk_s = '1' then
|
||||
rec_buffer(32-bclk_period_i) := rec_dat;
|
||||
end if ;
|
||||
elsif bclk_period_i >= 33 and bclk_period_i <= 48 then
|
||||
pb_dat <= pb_buffer(48-bclk_period_i);
|
||||
if bclk_s = '1' then
|
||||
rec_buffer(48-bclk_period_i) := rec_dat;
|
||||
end if ;
|
||||
elsif bclk_period_i = 63 and not rec_buff_transmitted then
|
||||
rec_buff_transmitted := true;
|
||||
axis_rec_data <= rec_buffer;
|
||||
axis_rec_valid <= '1';
|
||||
end if;
|
||||
|
||||
pb_lrc <= not bclk_period_s(5);
|
||||
rec_lrc <= not bclk_period_s(5);
|
||||
end if;
|
||||
|
||||
mclk <= mclk_s;
|
||||
bclk <= bclk_s;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- This IP supports standalone audio without CPU intervention on ZyBO-Boards
|
||||
------------------------------------------------------------------------------
|
||||
-- Output/input data is delivered as AXI-Stream
|
||||
-- Initially (or after reset) the ZyBo Audio Codec is programmed via I2C
|
||||
-- The I2C sequence is defined by the "ROM" contents
|
||||
-- After programming is finished Audio Data is delivered via AXIS interfaces
|
||||
-- Audio Stream Data is 32 bits wide => [31:16] right channel [15:0] left channel
|
||||
|
||||
-- Master Clock and Bit Clock for the Audio Codec are derived from internal clock dividers
|
||||
-- Clock division is controlled by Generics (see comments below)
|
||||
|
||||
-- OOC synthesis is setup for a clk frequency of 125 MHz -> see contraints file
|
||||
|
||||
-- Prof. Dr.-Ing W. Gehrke, 06/2020
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
------------------------
|
||||
-- entity section
|
||||
------------------------
|
||||
|
||||
entity zybo_audio is
|
||||
generic (
|
||||
HAS_RESET_PIN : boolean := false; -- use reset pin?
|
||||
MIC_IN : natural := 0; -- 0 => Line In Input, 1=> Mic input
|
||||
SRR_70 : std_logic_vector(7 downto 0) := "00000000"; -- sample rate register [7:0]
|
||||
I2C_CLKDIV : positive := 9999; -- SCL = clk / 4 / (I2C_CLKDIV+1)
|
||||
I2S_CLKDIV : natural := 4 -- mclk = clk / 2 / (I2S_CLKDIV+1)
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic := '1'; -- reset can be left unconnected
|
||||
|
||||
-- AXIS playback data
|
||||
axis_pb_data : in std_logic_vector (31 downto 0);
|
||||
axis_pb_valid : in std_logic; -- ignored! (added for compatibility), we assume that sender can deliver data when needed
|
||||
axis_pb_ready : out std_logic;
|
||||
|
||||
-- AXIS record data
|
||||
axis_rec_data : out std_logic_vector (31 downto 0);
|
||||
axis_rec_valid : out std_logic;
|
||||
axis_rec_ready : in std_logic; -- ignored! (added for compatibility), we assume data sink can receive data when needed
|
||||
|
||||
-- Audio Codec Connections
|
||||
mute : out std_logic; -- active low mute
|
||||
mclk : out std_logic; -- master clock, 256*fs
|
||||
bclk : out std_logic; -- I2S bit clock, 64 * fs
|
||||
pb_dat : out std_logic; -- I2S playback data (out)
|
||||
pb_lrc : out std_logic; -- I2S playback channel select
|
||||
rec_dat : in std_logic; -- I2S record data (in)
|
||||
rec_lrc : out std_logic; -- I2S record channel select
|
||||
|
||||
-- I2C Control for Audio Codec on ZyBo Board (SSM2603) -- insertion of Tristate-IO-Buffer is handled by Vivado
|
||||
scl_i : in std_logic;
|
||||
scl_o : out std_logic:='1';
|
||||
scl_t : out std_logic:='1';
|
||||
sda_i : in std_logic;
|
||||
sda_o : out std_logic:='1';
|
||||
sda_t : out std_logic:='1'
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
------------------------
|
||||
-- architecture section
|
||||
------------------------
|
||||
|
||||
architecture rtl of zybo_audio is
|
||||
constant I2C_ROM_ADDR_WIDTH : positive := 8; -- 8 is a bit overdone ;-) -- but let's stick to the save side in case of future extensions
|
||||
|
||||
signal resetn_internal : std_logic;
|
||||
signal i2c_addr : std_logic_vector(I2C_ROM_ADDR_WIDTH-1 downto 0);
|
||||
signal i2c_data : std_logic_vector(11 downto 0);
|
||||
signal i2c_done : std_logic;
|
||||
|
||||
begin
|
||||
resetn_internal <= resetn when HAS_RESET_PIN else '1'; -- if reset used, reset feed through, else always 1
|
||||
|
||||
-- "ROM" containing I2C sequence for audio codec setup
|
||||
i2c_rom : entity work.zybo_audio_i2c_rom
|
||||
generic map(
|
||||
MIC_IN => MIC_IN,
|
||||
SRR_70 => SRR_70,
|
||||
AW => I2C_ROM_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
addr => i2c_addr, -- "ROM" addr
|
||||
dout => i2c_data -- 8 bit output data
|
||||
);
|
||||
|
||||
-- I2C Transmitter FSM
|
||||
i2c : entity work.i2c_transmitter
|
||||
generic map(
|
||||
AW => I2C_ROM_ADDR_WIDTH,
|
||||
I2C_CLKDIV => I2C_CLKDIV
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
resetn => resetn_internal,
|
||||
|
||||
-- Internal I2C data from "ROM"
|
||||
data => i2c_data, -- 8 bit output data
|
||||
addr => i2c_addr, -- "ROM" addr
|
||||
done => i2c_done, -- 1 if I2C sequence finished
|
||||
|
||||
-- I2C IO
|
||||
sda_i => sda_i, -- Input (not used)
|
||||
sda_o => sda_o, -- Output
|
||||
sda_t => sda_t, -- Tristate Enable (1=Tristate)
|
||||
scl_i => scl_i, -- Input (not used)
|
||||
scl_o => scl_o, -- Output
|
||||
scl_t => scl_t -- Tristate Enable (1=Tristate)
|
||||
);
|
||||
|
||||
-- I2S <-> AXIS Transceiver
|
||||
i2s : entity work.i2s_transceiver
|
||||
generic map(
|
||||
I2S_CLKDIV => I2S_CLKDIV -- fs = sysclk / 512 / (clkdiv+1)
|
||||
)
|
||||
port map(
|
||||
clk => clk,
|
||||
resetn => resetn_internal,
|
||||
i2c_done => i2c_done, -- 1= I2C Transmitter has finished transmission
|
||||
|
||||
-- Playback (Output) data
|
||||
axis_pb_data => axis_pb_data,
|
||||
axis_pb_valid => axis_pb_valid,
|
||||
axis_pb_ready => axis_pb_ready,
|
||||
|
||||
-- Record (Input) data
|
||||
axis_rec_data => axis_rec_data,
|
||||
axis_rec_valid => axis_rec_valid,
|
||||
axis_rec_ready => axis_rec_ready,
|
||||
|
||||
-- Connections to audio codec on Zybo Board (SSM2603)
|
||||
mclk => mclk,
|
||||
mute => mute,
|
||||
bclk => bclk,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc
|
||||
);
|
||||
|
||||
end;
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity zybo_audio_i2c_rom is
|
||||
generic(
|
||||
MIC_IN : natural := 0;
|
||||
SRR_70 : std_logic_vector(7 downto 0) := "00000000"; -- sample rate register [7:0]
|
||||
AW : positive := 8
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
dout : out std_logic_vector(11 downto 0) -- Data out
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of zybo_audio_i2c_rom is
|
||||
|
||||
constant R0_LEFT_ADC_VOL : std_logic_vector (6 downto 0) := "0000000";
|
||||
constant R1_RIGHT_ADC_VOL : std_logic_vector (6 downto 0) := "0000001";
|
||||
constant R2_LEFT_DAC_VOL : std_logic_vector (6 downto 0) := "0000010";
|
||||
constant R3_RIGHT_DAC_VOL : std_logic_vector (6 downto 0) := "0000011";
|
||||
constant R4_ANALOG_PATH : std_logic_vector (6 downto 0) := "0000100";
|
||||
constant R5_DIGITAL_PATH : std_logic_vector (6 downto 0) := "0000101";
|
||||
constant R6_POWER_MGMT : std_logic_vector (6 downto 0) := "0000110";
|
||||
constant R7_DIGITAL_IF : std_logic_vector (6 downto 0) := "0000111";
|
||||
constant R8_SAMPLE_RATE : std_logic_vector (6 downto 0) := "0001000";
|
||||
constant R9_ACTIVE : std_logic_vector (6 downto 0) := "0001001";
|
||||
constant R15_SOFTWARE_RESET : std_logic_vector (6 downto 0) := "0001111";
|
||||
constant R16_ALC_CONTROL_1 : std_logic_vector (6 downto 0) := "0010000";
|
||||
constant R17_ALC_CONTROL_2 : std_logic_vector (6 downto 0) := "0010001";
|
||||
constant R18_ALC_CONTROL_2 : std_logic_vector (6 downto 0) := "0010010";
|
||||
|
||||
constant USE_MIC_INPUT : std_logic_vector (0 downto 0) := std_logic_vector(to_unsigned(MIC_IN,1));
|
||||
constant MIC_MUTE : std_logic_vector (0 downto 0) := (others=>not USE_MIC_INPUT(0));
|
||||
|
||||
|
||||
constant i2c_addr : std_logic_vector(6 downto 0) := "0011010"; -- SSM2603 I2C address
|
||||
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(11 downto 0);
|
||||
signal mem : tmem := (
|
||||
"1000"&i2c_addr&"0" , "0000"&R9_ACTIVE &"0", "0100"&"00000001", -- Diese beiden I2C-Zugriffe von R.H. (06/20)
|
||||
"1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT &"0", "0100"&"00100000", -- In SW-Ansteuerung des Codecs läuft dieser nicht, wenn diese Zeilen fehlen (Erklärung unklar)
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- Praktische Tests zeigen, dass dies mit dieser Implementierung nicht der Fall ist
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- dennoch wird die beiden Zugriffe hier mit aufgenommen - schaden werden sie nicht
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- anschließend ein paar dummy Zugriffe als Delay
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
|
||||
"1000"&i2c_addr&"0" , "0000"&R15_SOFTWARE_RESET&"0","0100"&"00000000",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- dummy => approx. 1 ms delay @ 100 kHz SCL freq
|
||||
"1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT &"0", "0100"&"00110000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R0_LEFT_ADC_VOL &"0", "0100"&"00010111",
|
||||
"1000"&i2c_addr&"0" , "0000"&R1_RIGHT_ADC_VOL&"0", "0100"&"00010111",
|
||||
"1000"&i2c_addr&"0" , "0000"&R2_LEFT_DAC_VOL &"1", "0100"&"01111001",
|
||||
"1000"&i2c_addr&"0" , "0000"&R3_RIGHT_DAC_VOL&"1", "0100"&"01111001",
|
||||
"1000"&i2c_addr&"0" , "0000"&R4_ANALOG_PATH &"0", "0100"&"00000000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R5_DIGITAL_PATH &"0", "0100"&"00000000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R7_DIGITAL_IF &"0", "0100"&"00001010",
|
||||
"1000"&i2c_addr&"0" , "0000"&R8_SAMPLE_RATE &"0", "0100"&SRR_70,
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- dummy => approx. 1 ms delay @ 100 kHz SCL freq
|
||||
"1000"&i2c_addr&"0" , "0000"&R9_ACTIVE &"0", "0100"&"00000001",
|
||||
"1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT &"0", "0100"&"00000000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R4_ANALOG_PATH &"0", "0100"&"00010"&USE_MIC_INPUT&MIC_MUTE&"0",
|
||||
|
||||
others=>"0010"&x"FF");
|
||||
|
||||
begin
|
||||
process begin
|
||||
wait until rising_edge(clk);
|
||||
dout <= mem(to_integer(unsigned(addr)));
|
||||
end process;
|
||||
end;
|
||||
|
||||
+4843
File diff suppressed because it is too large
Load Diff
+1646
File diff suppressed because it is too large
Load Diff
+497
@@ -0,0 +1,497 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axi_2d_mmvs.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2015 /2020
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity axi_2d_mmvs is
|
||||
generic
|
||||
(
|
||||
AXIL_ENABLE : boolean := true;
|
||||
|
||||
HAS_INTERRUPT_OUTPUT : boolean := false;
|
||||
HAS_FINISHED_OUTPUT : boolean := false;
|
||||
SINGLE_CLOCK_AND_RESETN : boolean := true;
|
||||
|
||||
MM2VS_VS2MM_DWIDTH : integer := 32;
|
||||
MM2VS_VS2MM_IDWIDTH : integer := 1;
|
||||
|
||||
MM2VS_ENABLE : boolean := true;
|
||||
MM2VS_MAX_BURSTLEN : integer := 16;
|
||||
MM2VS_MAX_PIPELINED_BURSTS : integer := 3;
|
||||
MM2VS_FIFO_AWIDTH : integer := 9;
|
||||
DEFAULT_MM2VS_REG_CTRL_RUN : integer := 0;
|
||||
DEFAULT_MM2VS_REG_CTRL_SYNC_SOF : integer := 0;
|
||||
DEFAULT_MM2VS_REG_CTRL_NUM_BUFF : integer := 1;
|
||||
DEFAULT_MM2VS_REG_CTRL_AxCACHE : integer := 0;
|
||||
DEFAULT_MM2VS_REG_STARTADDR : std_logic_vector(31 downto 0) := x"38000000";
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES : integer := 1024;
|
||||
DEFAULT_MM2VS_REG_STRIDE : integer := 1024;
|
||||
DEFAULT_MM2VS_REG_VER_LINES : integer := 1024;
|
||||
DEFAULT_MM2VS_REG_INT_LINE : integer := 0;
|
||||
|
||||
VS2MM_ENABLE : boolean := true;
|
||||
VS2MM_MAX_BURSTLEN : integer := 16;
|
||||
VS2MM_FIFO_AWIDTH : integer := 9;
|
||||
DEFAULT_VS2MM_REG_CTRL_RUN : integer := 0;
|
||||
DEFAULT_VS2MM_REG_CTRL_SYNC_SOF : integer := 0;
|
||||
DEFAULT_VS2MM_REG_CTRL_NUM_BUFF : integer := 1;
|
||||
DEFAULT_VS2MM_REG_CTRL_AxCACHE : integer := 0;
|
||||
DEFAULT_VS2MM_REG_STARTADDR : std_logic_vector(31 downto 0) := x"38000000";
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES : integer := 1024;
|
||||
DEFAULT_VS2MM_REG_STRIDE : integer := 1024;
|
||||
DEFAULT_VS2MM_REG_VER_LINES : integer := 1024;
|
||||
DEFAULT_VS2MM_REG_INT_LINE : integer := 0;
|
||||
|
||||
DEFAULT_REG_INT_ENABLE : integer := 0
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
ACLK : in std_logic;
|
||||
ARESETN : in std_logic := '1';
|
||||
|
||||
-- AXIS Initiator/Master Interface
|
||||
M_AXIS_ACLK : in std_logic;
|
||||
M_AXIS_ARESETN : in std_logic := '1';
|
||||
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(MM2VS_VS2MM_DWIDTH-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic := '0';
|
||||
M_AXIS_TUSER : out std_logic_vector(0 downto 0);
|
||||
|
||||
MM2VS_INTERRUPT : out std_logic;
|
||||
MM2VS_FINISHED_PULSE : out std_logic;
|
||||
|
||||
-- AXIS Target/Slave Interface
|
||||
S_AXIS_ACLK : in std_logic;
|
||||
S_AXIS_ARESETN : in std_logic := '1';
|
||||
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(MM2VS_VS2MM_DWIDTH-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic := '0';
|
||||
S_AXIS_TUSER : in std_logic_vector(0 downto 0);
|
||||
|
||||
VS2MM_INTERRUPT : out std_logic;
|
||||
VS2MM_FINISHED_PULSE : out std_logic;
|
||||
|
||||
-- AXI-Lite Slave Interface (CPU)
|
||||
S_AXIL_ACLK : in std_logic;
|
||||
S_AXIL_ARESETN : in std_logic;
|
||||
|
||||
S_AXIL_AWADDR : in std_logic_vector(15 downto 0);
|
||||
S_AXIL_AWVALID : in std_logic;
|
||||
S_AXIL_WDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIL_WSTRB : in std_logic_vector( 3 downto 0);
|
||||
S_AXIL_WVALID : in std_logic;
|
||||
S_AXIL_WREADY : out std_logic;
|
||||
S_AXIL_BRESP : out std_logic_vector( 1 downto 0);
|
||||
S_AXIL_BVALID : out std_logic;
|
||||
S_AXIL_AWREADY : out std_logic;
|
||||
S_AXIL_BREADY : in std_logic;
|
||||
|
||||
S_AXIL_ARADDR : in std_logic_vector(15 downto 0);
|
||||
S_AXIL_ARVALID : in std_logic;
|
||||
S_AXIL_RREADY : in std_logic;
|
||||
S_AXIL_ARREADY : out std_logic;
|
||||
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
|
||||
S_AXIL_RRESP : out std_logic_vector( 1 downto 0);
|
||||
S_AXIL_RVALID : out std_logic;
|
||||
|
||||
-- AXI Master Interface (Memory)
|
||||
M_AXI_ACLK : in std_logic := '0';
|
||||
M_AXI_ARESETN : in std_logic := '0';
|
||||
|
||||
M_AXI_ARREADY : in std_logic := '0';
|
||||
M_AXI_ARVALID : out std_logic;
|
||||
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
|
||||
M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_ARID : out std_logic_vector(MM2VS_VS2MM_IDWIDTH-1 downto 0);
|
||||
M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_RREADY : out std_logic;
|
||||
M_AXI_RVALID : in std_logic := '0';
|
||||
M_AXI_RDATA : in std_logic_vector(MM2VS_VS2MM_DWIDTH-1 downto 0);
|
||||
M_AXI_RRESP : in std_logic_vector( 1 downto 0);
|
||||
M_AXI_RID : in std_logic_vector(MM2VS_VS2MM_IDWIDTH-1 downto 0);
|
||||
M_AXI_RLAST : in std_logic := '0';
|
||||
|
||||
M_AXI_AWREADY : in std_logic := '0';
|
||||
M_AXI_AWVALID : out std_logic;
|
||||
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_AWID : out std_logic_vector(MM2VS_VS2MM_IDWIDTH-1 downto 0);
|
||||
M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
|
||||
M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_WREADY : in std_logic := '0';
|
||||
M_AXI_WVALID : out std_logic;
|
||||
M_AXI_WDATA : out std_logic_vector(MM2VS_VS2MM_DWIDTH-1 downto 0);
|
||||
M_AXI_WSTRB : out std_logic_vector(MM2VS_VS2MM_DWIDTH/8-1 downto 0);
|
||||
M_AXI_WLAST : out std_logic;
|
||||
M_AXI_WID : out std_logic_vector(MM2VS_VS2MM_IDWIDTH-1 downto 0);
|
||||
M_AXI_BREADY : out std_logic;
|
||||
M_AXI_BVALID : in std_logic := '0';
|
||||
M_AXI_BID : in std_logic_vector(MM2VS_VS2MM_IDWIDTH-1 downto 0);
|
||||
M_AXI_BRESP : in std_logic_vector( 1 downto 0)
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture struct of axi_2d_mmvs is
|
||||
constant REG_MM2VS_CTRL_DEFAULT : integer := DEFAULT_MM2VS_REG_CTRL_RUN*1 + DEFAULT_MM2VS_REG_CTRL_SYNC_SOF*2 + DEFAULT_MM2VS_REG_CTRL_NUM_BUFF*16 + DEFAULT_MM2VS_REG_CTRL_AxCACHE*4096;
|
||||
constant REG_VS2MM_CTRL_DEFAULT : integer := DEFAULT_VS2MM_REG_CTRL_RUN*1 + DEFAULT_VS2MM_REG_CTRL_SYNC_SOF*2 + DEFAULT_VS2MM_REG_CTRL_NUM_BUFF*16 + DEFAULT_VS2MM_REG_CTRL_AxCACHE*4096;
|
||||
|
||||
constant NUM_INT_SOURCES : integer := 2;
|
||||
|
||||
signal VS2MM_AXIS_TVALID : std_logic;
|
||||
signal VS2MM_AXIS_TDATA : std_logic_vector(MM2VS_VS2MM_DWIDTH-1 downto 0);
|
||||
signal VS2MM_AXIS_TLAST : std_logic;
|
||||
signal VS2MM_AXIS_TREADY : std_logic;
|
||||
signal VS2MM_AXIS_TUSER : std_logic_vector(0 downto 0);
|
||||
signal VS2MM_AXIS_NUM_AVAIL : std_logic_vector(VS2MM_FIFO_AWIDTH-1 downto 0); -- Free Entries
|
||||
|
||||
signal VS2MM_REG_CONTROL : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_STARTADDR : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_HOR_BYTES : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_STRIDE : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_VER_LINES : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_INT_LINE : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_FRAME_NUM : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_LINE_NUM : std_logic_vector(31 downto 0);
|
||||
signal VS2MM_REG_LAST_FRAME_ST : std_logic_vector(31 downto 0);
|
||||
signal SIG_VS2MM_INTERRUPT : std_logic;
|
||||
|
||||
signal MM2VS_AXIS_TVALID : std_logic;
|
||||
signal MM2VS_AXIS_TDATA : std_logic_vector(MM2VS_VS2MM_DWIDTH-1 downto 0);
|
||||
signal MM2VS_AXIS_TLAST : std_logic;
|
||||
signal MM2VS_AXIS_TREADY : std_logic;
|
||||
signal MM2VS_AXIS_TUSER : std_logic_vector(0 downto 0);
|
||||
signal MM2VS_NUM_FREE : std_logic_vector(MM2VS_FIFO_AWIDTH-1 downto 0); -- Free Entries
|
||||
|
||||
signal MM2VS_REG_CONTROL : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_STARTADDR : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_HOR_BYTES : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_STRIDE : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_VER_LINES : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_INT_LINE : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_FRAME_NUM : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_LINE_NUM : std_logic_vector(31 downto 0);
|
||||
signal MM2VS_REG_LAST_FRAME_ST : std_logic_vector(31 downto 0);
|
||||
signal SIG_MM2VS_INTERRUPT : std_logic;
|
||||
|
||||
signal INTERRUPTS : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal INTERNAL_INTERRUPT : std_logic_vector(NUM_INT_SOURCES-1 downto 0) := (others => '0');
|
||||
|
||||
signal axil_aclk : std_logic;
|
||||
signal axil_aresetn : std_logic;
|
||||
signal vs2mm_aclk : std_logic;
|
||||
signal vs2mm_aresetn : std_logic;
|
||||
signal mm2vs_aclk : std_logic;
|
||||
signal mm2vs_aresetn : std_logic;
|
||||
signal memif_aclk : std_logic;
|
||||
signal memif_aresetn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
INTERNAL_INTERRUPT(0) <= SIG_MM2VS_INTERRUPT;
|
||||
INTERNAL_INTERRUPT(1) <= SIG_VS2MM_INTERRUPT;
|
||||
|
||||
MM2VS_INTERRUPT <= INTERRUPTS(0);
|
||||
VS2MM_INTERRUPT <= INTERRUPTS(1);
|
||||
|
||||
axil_aclk <= ACLK when SINGLE_CLOCK_AND_RESETN else S_AXIL_ACLK;
|
||||
axil_aresetn <= ARESETN when SINGLE_CLOCK_AND_RESETN else S_AXIL_ARESETN;
|
||||
memif_aclk <= ACLK when SINGLE_CLOCK_AND_RESETN else M_AXI_ACLK;
|
||||
memif_aresetn <= ARESETN when SINGLE_CLOCK_AND_RESETN else M_AXI_ARESETN;
|
||||
vs2mm_aclk <= ACLK when SINGLE_CLOCK_AND_RESETN else S_AXIS_ACLK;
|
||||
vs2mm_aresetn <= ARESETN when SINGLE_CLOCK_AND_RESETN else S_AXIS_ARESETN;
|
||||
mm2vs_aclk <= ACLK when SINGLE_CLOCK_AND_RESETN else M_AXIS_ACLK;
|
||||
mm2vs_aresetn <= ARESETN when SINGLE_CLOCK_AND_RESETN else M_AXIS_ARESETN;
|
||||
|
||||
|
||||
NO_AXIL_GEN: if not AXIL_ENABLE generate
|
||||
MM2VS_REG_CONTROL <= std_logic_vector(to_unsigned(REG_MM2VS_CTRL_DEFAULT ,32));
|
||||
MM2VS_REG_STARTADDR <= DEFAULT_MM2VS_REG_STARTADDR;
|
||||
MM2VS_REG_HOR_BYTES <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_HOR_BYTES,32));
|
||||
MM2VS_REG_STRIDE <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_STRIDE ,32));
|
||||
MM2VS_REG_VER_LINES <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_VER_LINES,32));
|
||||
MM2VS_REG_INT_LINE <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_INT_LINE ,32));
|
||||
|
||||
VS2MM_REG_CONTROL <= std_logic_vector(to_unsigned(REG_VS2MM_CTRL_DEFAULT ,32));
|
||||
VS2MM_REG_STARTADDR <= DEFAULT_VS2MM_REG_STARTADDR;
|
||||
VS2MM_REG_HOR_BYTES <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_HOR_BYTES,32));
|
||||
VS2MM_REG_STRIDE <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_STRIDE ,32));
|
||||
VS2MM_REG_VER_LINES <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_VER_LINES,32));
|
||||
VS2MM_REG_INT_LINE <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_INT_LINE ,32));
|
||||
end generate;
|
||||
|
||||
AXIL_GEN: if AXIL_ENABLE generate
|
||||
axi_lite_if: entity work.axil_if_axi_2d_mmvs
|
||||
generic map (
|
||||
NUM_INTS => NUM_INT_SOURCES,
|
||||
MM2VS_ENABLE => MM2VS_ENABLE,
|
||||
DEFAULT_MM2VS_REG_CONTROL => REG_MM2VS_CTRL_DEFAULT,
|
||||
DEFAULT_MM2VS_REG_STARTADDR => DEFAULT_MM2VS_REG_STARTADDR,
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES => DEFAULT_MM2VS_REG_HOR_BYTES,
|
||||
DEFAULT_MM2VS_REG_STRIDE => DEFAULT_MM2VS_REG_STRIDE,
|
||||
DEFAULT_MM2VS_REG_VER_LINES => DEFAULT_MM2VS_REG_VER_LINES,
|
||||
DEFAULT_MM2VS_REG_INT_LINE => DEFAULT_MM2VS_REG_INT_LINE,
|
||||
VS2MM_ENABLE => VS2MM_ENABLE,
|
||||
DEFAULT_VS2MM_REG_CONTROL => REG_VS2MM_CTRL_DEFAULT,
|
||||
DEFAULT_VS2MM_REG_STARTADDR => DEFAULT_VS2MM_REG_STARTADDR,
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES => DEFAULT_VS2MM_REG_HOR_BYTES,
|
||||
DEFAULT_VS2MM_REG_STRIDE => DEFAULT_VS2MM_REG_STRIDE,
|
||||
DEFAULT_VS2MM_REG_VER_LINES => DEFAULT_VS2MM_REG_VER_LINES,
|
||||
DEFAULT_VS2MM_REG_INT_LINE => DEFAULT_VS2MM_REG_INT_LINE,
|
||||
DEFAULT_REG_INT_ENABLE => DEFAULT_REG_INT_ENABLE
|
||||
)
|
||||
|
||||
port map (
|
||||
S_AXIL_ACLK => axil_aclk,
|
||||
S_AXIL_ARESETN => axil_aresetn,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
|
||||
MM2VS_REG_CONTROL => MM2VS_REG_CONTROL,
|
||||
MM2VS_REG_STARTADDR => MM2VS_REG_STARTADDR,
|
||||
MM2VS_REG_HOR_BYTES => MM2VS_REG_HOR_BYTES,
|
||||
MM2VS_REG_STRIDE => MM2VS_REG_STRIDE,
|
||||
MM2VS_REG_VER_LINES => MM2VS_REG_VER_LINES,
|
||||
MM2VS_REG_INT_LINE => MM2VS_REG_INT_LINE,
|
||||
MM2VS_REG_FRAME_NUM => MM2VS_REG_FRAME_NUM,
|
||||
MM2VS_REG_LINE_NUM => MM2VS_REG_LINE_NUM,
|
||||
MM2VS_REG_LAST_FRAME_ST => MM2VS_REG_LAST_FRAME_ST,
|
||||
|
||||
VS2MM_REG_CONTROL => VS2MM_REG_CONTROL,
|
||||
VS2MM_REG_STARTADDR => VS2MM_REG_STARTADDR,
|
||||
VS2MM_REG_HOR_BYTES => VS2MM_REG_HOR_BYTES,
|
||||
VS2MM_REG_STRIDE => VS2MM_REG_STRIDE,
|
||||
VS2MM_REG_VER_LINES => VS2MM_REG_VER_LINES,
|
||||
VS2MM_REG_INT_LINE => VS2MM_REG_INT_LINE,
|
||||
VS2MM_REG_FRAME_NUM => VS2MM_REG_FRAME_NUM,
|
||||
VS2MM_REG_LINE_NUM => VS2MM_REG_LINE_NUM,
|
||||
VS2MM_REG_LAST_FRAME_ST => VS2MM_REG_LAST_FRAME_ST,
|
||||
|
||||
INTERN_INTERRUPT_IN => INTERNAL_INTERRUPT,
|
||||
INTERRUPTS => INTERRUPTS
|
||||
);
|
||||
end generate;
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- MM2VS Section
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
MM2VS_GEN: if MM2VS_ENABLE generate
|
||||
|
||||
mm2vs_core: entity work.mm2vs_2d_core
|
||||
generic map (
|
||||
DWIDTH => MM2VS_VS2MM_DWIDTH,
|
||||
IDWIDTH => MM2VS_VS2MM_IDWIDTH,
|
||||
MAX_BURSTLEN => MM2VS_MAX_BURSTLEN,
|
||||
MAX_PIPELINED_BURSTS => MM2VS_MAX_PIPELINED_BURSTS,
|
||||
FIFO_AWIDTH => MM2VS_FIFO_AWIDTH
|
||||
)
|
||||
|
||||
port map (
|
||||
CLK => memif_aclk,
|
||||
RESETN => memif_aresetn,
|
||||
|
||||
M_AXIS_TVALID => MM2VS_AXIS_TVALID,
|
||||
M_AXIS_TDATA => MM2VS_AXIS_TDATA,
|
||||
M_AXIS_TLAST => MM2VS_AXIS_TLAST,
|
||||
M_AXIS_TREADY => MM2VS_AXIS_TREADY,
|
||||
M_AXIS_TUSER => MM2VS_AXIS_TUSER,
|
||||
M_AXIS_NUM_FREE => MM2VS_NUM_FREE,
|
||||
|
||||
REG_CONTROL => MM2VS_REG_CONTROL,
|
||||
REG_STARTADDR => MM2VS_REG_STARTADDR,
|
||||
REG_HOR_BYTES => MM2VS_REG_HOR_BYTES,
|
||||
REG_STRIDE => MM2VS_REG_STRIDE,
|
||||
REG_VER_LINES => MM2VS_REG_VER_LINES,
|
||||
REG_INT_LINE => MM2VS_REG_INT_LINE,
|
||||
REG_FRAME_NUM => MM2VS_REG_FRAME_NUM,
|
||||
REG_LINE_NUM => MM2VS_REG_LINE_NUM,
|
||||
LAST_FRAME_ST => MM2VS_REG_LAST_FRAME_ST,
|
||||
|
||||
INTERRUPT => SIG_MM2VS_INTERRUPT,
|
||||
FINISHED_PULSE => MM2VS_FINISHED_PULSE,
|
||||
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST
|
||||
);
|
||||
|
||||
|
||||
|
||||
mm2vs_fifo: entity work.axis_fifo_axi_2d_mmvs
|
||||
|
||||
generic map (
|
||||
FIFO_USE_BLOCKRAM => true, -- always use Block RAM
|
||||
FIFO_AWIDTH => MM2VS_FIFO_AWIDTH,
|
||||
FIFO_DWIDTH => MM2VS_VS2MM_DWIDTH,
|
||||
FIFO_TUSERWIDTH => 1
|
||||
)
|
||||
port map (
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_ACLK => memif_aclk,
|
||||
S_AXIS_ARESETN => memif_aresetn,
|
||||
S_AXIS_TVALID => MM2VS_AXIS_TVALID,
|
||||
S_AXIS_TDATA => MM2VS_AXIS_TDATA,
|
||||
S_AXIS_TLAST => MM2VS_AXIS_TLAST,
|
||||
S_AXIS_TREADY => MM2VS_AXIS_TREADY,
|
||||
S_AXIS_TUSER => MM2VS_AXIS_TUSER,
|
||||
S_NUM_FREE => MM2VS_NUM_FREE,
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_ACLK => mm2vs_aclk,
|
||||
M_AXIS_ARESETN => mm2vs_aresetn,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
M_NUM_AVAIL => open
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- VS2MM Section
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
VS2MM_GEN: if VS2MM_ENABLE generate
|
||||
|
||||
vs2mm_core: entity work.vs2mm_2d_core
|
||||
generic map (
|
||||
DWIDTH => MM2VS_VS2MM_DWIDTH,
|
||||
IDWIDTH => MM2VS_VS2MM_IDWIDTH,
|
||||
MAX_BURSTLEN => VS2MM_MAX_BURSTLEN,
|
||||
FIFO_AWIDTH => VS2MM_FIFO_AWIDTH
|
||||
)
|
||||
|
||||
port map (
|
||||
CLK => memif_aclk,
|
||||
RESETN => memif_aresetn,
|
||||
|
||||
S_AXIS_TVALID => VS2MM_AXIS_TVALID,
|
||||
S_AXIS_TDATA => VS2MM_AXIS_TDATA,
|
||||
S_AXIS_TLAST => VS2MM_AXIS_TLAST,
|
||||
S_AXIS_TREADY => VS2MM_AXIS_TREADY,
|
||||
S_AXIS_TUSER => VS2MM_AXIS_TUSER,
|
||||
S_AXIS_NUM_AVAIL => VS2MM_AXIS_NUM_AVAIL,
|
||||
|
||||
REG_CONTROL => VS2MM_REG_CONTROL,
|
||||
REG_STARTADDR => VS2MM_REG_STARTADDR,
|
||||
REG_HOR_BYTES => VS2MM_REG_HOR_BYTES,
|
||||
REG_STRIDE => VS2MM_REG_STRIDE,
|
||||
REG_VER_LINES => VS2MM_REG_VER_LINES,
|
||||
REG_INT_LINE => VS2MM_REG_INT_LINE,
|
||||
REG_FRAME_NUM => VS2MM_REG_FRAME_NUM,
|
||||
REG_LINE_NUM => VS2MM_REG_LINE_NUM,
|
||||
LAST_FRAME_ST => VS2MM_REG_LAST_FRAME_ST,
|
||||
|
||||
FINISHED_PULSE => VS2MM_FINISHED_PULSE,
|
||||
INTERRUPT => SIG_VS2MM_INTERRUPT,
|
||||
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
|
||||
|
||||
|
||||
vs2mm_fifo: entity work.axis_fifo_axi_2d_mmvs
|
||||
|
||||
generic map (
|
||||
FIFO_USE_BLOCKRAM => true, -- always use Block RAM
|
||||
FIFO_AWIDTH => VS2MM_FIFO_AWIDTH,
|
||||
FIFO_DWIDTH => MM2VS_VS2MM_DWIDTH,
|
||||
FIFO_TUSERWIDTH => 1
|
||||
)
|
||||
port map (
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_ACLK => vs2mm_aclk,
|
||||
S_AXIS_ARESETN => vs2mm_aresetn,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
S_NUM_FREE => open,
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_ACLK => memif_aclk,
|
||||
M_AXIS_ARESETN => memif_aresetn,
|
||||
M_AXIS_TVALID => VS2MM_AXIS_TVALID,
|
||||
M_AXIS_TDATA => VS2MM_AXIS_TDATA,
|
||||
M_AXIS_TLAST => VS2MM_AXIS_TLAST,
|
||||
M_AXIS_TREADY => VS2MM_AXIS_TREADY,
|
||||
M_AXIS_TUSER => VS2MM_AXIS_TUSER,
|
||||
M_NUM_AVAIL => VS2MM_AXIS_NUM_AVAIL
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
end;
|
||||
+304
@@ -0,0 +1,304 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axil_if_axi_2d_mmvs.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2014/2015/2017
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Entity section
|
||||
------------------------------------------------------------------------------
|
||||
entity axil_if_axi_2d_mmvs is
|
||||
generic
|
||||
(
|
||||
NUM_INTS : integer := 2; -- number of valid interrupt inputs (1 ... 32)
|
||||
|
||||
MM2VS_ENABLE : boolean := true;
|
||||
DEFAULT_MM2VS_REG_CONTROL : integer := 0;
|
||||
DEFAULT_MM2VS_REG_STARTADDR : std_logic_vector(31 downto 0) := x"00000000";
|
||||
DEFAULT_MM2VS_REG_HOR_BYTES : integer := 0;
|
||||
DEFAULT_MM2VS_REG_STRIDE : integer := 0;
|
||||
DEFAULT_MM2VS_REG_VER_LINES : integer := 0;
|
||||
DEFAULT_MM2VS_REG_INT_LINE : integer := 0;
|
||||
|
||||
VS2MM_ENABLE : boolean := true;
|
||||
DEFAULT_VS2MM_REG_CONTROL : integer := 0;
|
||||
DEFAULT_VS2MM_REG_STARTADDR : std_logic_vector(31 downto 0) := x"00000000";
|
||||
DEFAULT_VS2MM_REG_HOR_BYTES : integer := 0;
|
||||
DEFAULT_VS2MM_REG_STRIDE : integer := 0;
|
||||
DEFAULT_VS2MM_REG_VER_LINES : integer := 0;
|
||||
DEFAULT_VS2MM_REG_INT_LINE : integer := 0;
|
||||
|
||||
DEFAULT_REG_INT_ENABLE : integer := 0
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
S_AXIL_ACLK : in std_logic;
|
||||
S_AXIL_ARESETN : in std_logic;
|
||||
|
||||
-- AXI-Lite Slave Interface (from/to CPU)
|
||||
S_AXIL_AWADDR : in std_logic_vector(15 downto 0);
|
||||
S_AXIL_AWVALID : in std_logic := '0';
|
||||
S_AXIL_WDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIL_WSTRB : in std_logic_vector( 3 downto 0);
|
||||
S_AXIL_WVALID : in std_logic := '0';
|
||||
S_AXIL_BREADY : in std_logic := '1';
|
||||
S_AXIL_ARADDR : in std_logic_vector(15 downto 0);
|
||||
S_AXIL_ARVALID : in std_logic := '0';
|
||||
S_AXIL_RREADY : in std_logic := '1';
|
||||
S_AXIL_ARREADY : out std_logic;
|
||||
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
|
||||
S_AXIL_RRESP : out std_logic_vector( 1 downto 0);
|
||||
S_AXIL_RVALID : out std_logic;
|
||||
S_AXIL_WREADY : out std_logic;
|
||||
S_AXIL_BRESP : out std_logic_vector( 1 downto 0);
|
||||
S_AXIL_BVALID : out std_logic;
|
||||
S_AXIL_AWREADY : out std_logic;
|
||||
|
||||
-- User IO
|
||||
MM2VS_REG_CONTROL : out std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_STARTADDR : out std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_HOR_BYTES : out std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_STRIDE : out std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_VER_LINES : out std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_INT_LINE : out std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_FRAME_NUM : in std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_LINE_NUM : in std_logic_vector(31 downto 0);
|
||||
MM2VS_REG_LAST_FRAME_ST : in std_logic_vector(31 downto 0);
|
||||
|
||||
VS2MM_REG_CONTROL : out std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_STARTADDR : out std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_HOR_BYTES : out std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_STRIDE : out std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_VER_LINES : out std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_INT_LINE : out std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_FRAME_NUM : in std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_LINE_NUM : in std_logic_vector(31 downto 0);
|
||||
VS2MM_REG_LAST_FRAME_ST : in std_logic_vector(31 downto 0);
|
||||
|
||||
-- Interrupt Inputs (max. 32)
|
||||
INTERN_INTERRUPT_IN : in std_logic_vector(NUM_INTS-1 downto 0) := (others =>'0');
|
||||
INTERRUPTS : out std_logic_vector(1 downto 0)
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axil_if_axi_2d_mmvs is
|
||||
function BOOL_TO_INT(X : boolean) return integer is begin
|
||||
if X then return (1);
|
||||
else return (0);
|
||||
end if;
|
||||
end function;
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Register Adressing
|
||||
--------------------------------------------------------------
|
||||
constant REG_INT_ENABLE : integer := 0;
|
||||
constant REG_INT_STATUS : integer := 1;
|
||||
constant MM2VS_REGNUM_CONTROL : integer := 2;
|
||||
constant MM2VS_REGNUM_STARTADDR : integer := 3;
|
||||
constant MM2VS_REGNUM_HOR_BYTES : integer := 4;
|
||||
constant MM2VS_REGNUM_STRIDE : integer := 5;
|
||||
constant MM2VS_REGNUM_VER_LINES : integer := 6;
|
||||
constant MM2VS_REGNUM_INT_LINE : integer := 7;
|
||||
constant MM2VS_REGNUM_FRAME_NUM : integer := 8;
|
||||
constant MM2VS_REGNUM_LINE_NUM : integer := 9;
|
||||
constant MM2VS_REGNUM_LAST_FRAME_ST : integer := 10;
|
||||
|
||||
constant VS2MM_REGNUM_CONTROL : integer := 11;
|
||||
constant VS2MM_REGNUM_STARTADDR : integer := 12;
|
||||
constant VS2MM_REGNUM_HOR_BYTES : integer := 13;
|
||||
constant VS2MM_REGNUM_STRIDE : integer := 14;
|
||||
constant VS2MM_REGNUM_VER_LINES : integer := 15;
|
||||
constant VS2MM_REGNUM_INT_LINE : integer := 16;
|
||||
constant VS2MM_REGNUM_FRAME_NUM : integer := 17;
|
||||
constant VS2MM_REGNUM_LINE_NUM : integer := 18;
|
||||
constant VS2MM_REGNUM_LAST_FRAME_ST : integer := 19;
|
||||
|
||||
constant CONST_AXIL_ADDR_MAX : integer := 19; -- Max Address
|
||||
constant CONST_AXIL_ADDR_WIDTH : integer := 5; -- Bit Width needed for max. address
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Defintion of register width
|
||||
--------------------------------------------------------------
|
||||
|
||||
type T_REG_BIT_WIDTH is array (0 to CONST_AXIL_ADDR_MAX) of integer;
|
||||
constant CONST_REG_BIT_WIDTH : T_REG_BIT_WIDTH := (
|
||||
REG_INT_ENABLE => NUM_INTS,
|
||||
REG_INT_STATUS => NUM_INTS,
|
||||
MM2VS_REGNUM_CONTROL => 16*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_STARTADDR => 32*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_HOR_BYTES => 16*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_STRIDE => 24*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_VER_LINES => 16*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_INT_LINE => 16*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_FRAME_NUM => 32*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_LINE_NUM => 16*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
MM2VS_REGNUM_LAST_FRAME_ST => 32*BOOL_TO_INT(MM2VS_ENABLE),
|
||||
VS2MM_REGNUM_CONTROL => 16*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_STARTADDR => 32*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_HOR_BYTES => 16*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_STRIDE => 24*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_VER_LINES => 16*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_INT_LINE => 16*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_FRAME_NUM => 32*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_LINE_NUM => 16*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
VS2MM_REGNUM_LAST_FRAME_ST => 32*BOOL_TO_INT(VS2MM_ENABLE),
|
||||
others => 0);
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Defintion of Slave registers
|
||||
--------------------------------------------------------------
|
||||
type tregfile is array(0 to CONST_AXIL_ADDR_MAX) of std_logic_vector(31 downto 0);
|
||||
signal slvreg : tregfile;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- Constant or simple asynchronous Outputs
|
||||
-----------------------------------------------------------------
|
||||
S_AXIL_BRESP <= (others=>'0'); -- Never signal any write errors
|
||||
S_AXIL_RRESP <= (others=>'0'); -- Never signal any read errors
|
||||
S_AXIL_RVALID <= S_AXIL_ARVALID;
|
||||
S_AXIL_ARREADY <= '1';
|
||||
S_AXIL_AWREADY <= S_AXIL_WVALID and S_AXIL_AWVALID; -- if both, WVALID and AWVALID is asserted we accept the address and data at once
|
||||
S_AXIL_WREADY <= S_AXIL_WVALID and S_AXIL_AWVALID; -- see above
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- Write to registers
|
||||
--
|
||||
-- This could be caused by:
|
||||
-- 1. Write transaction from AXI lite interface
|
||||
-- 2. Interrupt signalling from interrupt source
|
||||
-- 3. Inputs values which should be reflected in the slave registers
|
||||
-----------------------------------------------------------------
|
||||
axil_wrregs_proc: process
|
||||
variable reg : integer;
|
||||
begin
|
||||
wait until rising_edge (S_AXIL_ACLK);
|
||||
|
||||
if S_AXIL_ARESETN = '0' then
|
||||
S_AXIL_BVALID <= '0';
|
||||
slvreg <= (others=> (others=>'0')); -- default assignment: all regs = 0;
|
||||
slvreg(REG_INT_ENABLE )(CONST_REG_BIT_WIDTH(REG_INT_ENABLE )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_REG_INT_ENABLE,(CONST_REG_BIT_WIDTH(REG_INT_ENABLE ))));
|
||||
|
||||
slvreg(MM2VS_REGNUM_CONTROL )(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_CONTROL )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_CONTROL ,(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_CONTROL ))));
|
||||
slvreg(MM2VS_REGNUM_STARTADDR)(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_STARTADDR)-1 downto 0) <= DEFAULT_MM2VS_REG_STARTADDR(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_STARTADDR)-1 downto 0);
|
||||
slvreg(MM2VS_REGNUM_HOR_BYTES)(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_HOR_BYTES)-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_HOR_BYTES ,(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_HOR_BYTES))));
|
||||
slvreg(MM2VS_REGNUM_STRIDE )(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_STRIDE )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_STRIDE ,(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_STRIDE ))));
|
||||
slvreg(MM2VS_REGNUM_VER_LINES)(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_VER_LINES)-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_VER_LINES ,(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_VER_LINES))));
|
||||
slvreg(MM2VS_REGNUM_INT_LINE )(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_INT_LINE )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_MM2VS_REG_INT_LINE ,(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_INT_LINE ))));
|
||||
|
||||
slvreg(VS2MM_REGNUM_CONTROL )(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_CONTROL )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_CONTROL ,(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_CONTROL ))));
|
||||
slvreg(VS2MM_REGNUM_STARTADDR)(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_STARTADDR)-1 downto 0) <= DEFAULT_VS2MM_REG_STARTADDR(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_STARTADDR)-1 downto 0);
|
||||
slvreg(VS2MM_REGNUM_HOR_BYTES)(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_HOR_BYTES)-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_HOR_BYTES ,(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_HOR_BYTES))));
|
||||
slvreg(VS2MM_REGNUM_STRIDE )(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_STRIDE )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_STRIDE ,(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_STRIDE ))));
|
||||
slvreg(VS2MM_REGNUM_VER_LINES)(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_VER_LINES)-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_VER_LINES ,(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_VER_LINES))));
|
||||
slvreg(VS2MM_REGNUM_INT_LINE )(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_INT_LINE )-1 downto 0) <= std_logic_vector(to_unsigned(DEFAULT_VS2MM_REG_INT_LINE ,(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_INT_LINE ))));
|
||||
else
|
||||
if S_AXIL_BREADY = '1' then -- if a previous write transaction response has been accepted BVALID should be deasserted
|
||||
S_AXIL_BVALID <= '0';
|
||||
end if;
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Write to registers from AXI lite Interface
|
||||
--------------------------------------------------------------
|
||||
reg := to_integer(unsigned(S_AXIL_AWADDR(CONST_AXIL_ADDR_WIDTH+1 downto 2)));
|
||||
|
||||
if S_AXIL_WVALID = '1' and S_AXIL_AWVALID = '1' then -- write
|
||||
S_AXIL_BVALID <= '1';
|
||||
if reg <= CONST_AXIL_ADDR_MAX then
|
||||
for i in 0 to 31 loop
|
||||
if (S_AXIL_WSTRB(i/8) = '1') and (i < CONST_REG_BIT_WIDTH(reg)) then
|
||||
slvreg(reg)(i) <= S_AXIL_WDATA(i);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Interrupt Register: Write if interrupt is active
|
||||
--------------------------------------------------------------
|
||||
for i in 0 to NUM_INTS-1 loop
|
||||
if INTERN_INTERRUPT_IN(i) = '1' then
|
||||
slvreg(REG_INT_STATUS)(i) <= '1' ;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Register Write from external connections
|
||||
--------------------------------------------------------------
|
||||
slvreg(MM2VS_REGNUM_FRAME_NUM) (CONST_REG_BIT_WIDTH(MM2VS_REGNUM_FRAME_NUM)-1 downto 0) <= MM2VS_REG_FRAME_NUM(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_FRAME_NUM)-1 downto 0);
|
||||
slvreg(MM2VS_REGNUM_LINE_NUM ) (CONST_REG_BIT_WIDTH(MM2VS_REGNUM_LINE_NUM )-1 downto 0) <= MM2VS_REG_LINE_NUM (CONST_REG_BIT_WIDTH(MM2VS_REGNUM_LINE_NUM )-1 downto 0);
|
||||
slvreg(MM2VS_REGNUM_LAST_FRAME_ST)(CONST_REG_BIT_WIDTH(MM2VS_REGNUM_LAST_FRAME_ST )-1 downto 0) <= MM2VS_REG_LAST_FRAME_ST (CONST_REG_BIT_WIDTH(MM2VS_REGNUM_LAST_FRAME_ST )-1 downto 0);
|
||||
slvreg(VS2MM_REGNUM_FRAME_NUM) (CONST_REG_BIT_WIDTH(VS2MM_REGNUM_FRAME_NUM)-1 downto 0) <= VS2MM_REG_FRAME_NUM(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_FRAME_NUM)-1 downto 0);
|
||||
slvreg(VS2MM_REGNUM_LINE_NUM ) (CONST_REG_BIT_WIDTH(VS2MM_REGNUM_LINE_NUM )-1 downto 0) <= VS2MM_REG_LINE_NUM (CONST_REG_BIT_WIDTH(VS2MM_REGNUM_LINE_NUM )-1 downto 0);
|
||||
slvreg(VS2MM_REGNUM_LAST_FRAME_ST)(CONST_REG_BIT_WIDTH(VS2MM_REGNUM_LAST_FRAME_ST )-1 downto 0) <= VS2MM_REG_LAST_FRAME_ST (CONST_REG_BIT_WIDTH(VS2MM_REGNUM_LAST_FRAME_ST )-1 downto 0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- Asynchronous Read from Registers (saves FFs for S_AXIL_RDATA)
|
||||
-----------------------------------------------------------------
|
||||
axil_readasync_proc: process (S_AXIL_ARADDR,slvreg)
|
||||
variable reg : integer;
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Register Read => AXI lite Interface
|
||||
--------------------------------------------------------------
|
||||
S_AXIL_RDATA <= (others=>'0'); -- default assignment
|
||||
|
||||
reg := to_integer(unsigned(S_AXIL_ARADDR(CONST_AXIL_ADDR_WIDTH+1 downto 2)));
|
||||
if reg <= CONST_AXIL_ADDR_MAX then
|
||||
for i in 0 to 31 loop
|
||||
if i < CONST_REG_BIT_WIDTH(reg) then
|
||||
S_AXIL_RDATA(i) <= slvreg(reg)(i);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
--------------------------------------------------------------
|
||||
-- Register Read => external connections
|
||||
--------------------------------------------------------------
|
||||
MM2VS_REG_CONTROL <= slvreg(MM2VS_REGNUM_CONTROL );
|
||||
MM2VS_REG_STARTADDR <= slvreg(MM2VS_REGNUM_STARTADDR);
|
||||
MM2VS_REG_HOR_BYTES <= slvreg(MM2VS_REGNUM_HOR_BYTES);
|
||||
MM2VS_REG_STRIDE <= slvreg(MM2VS_REGNUM_STRIDE );
|
||||
MM2VS_REG_VER_LINES <= slvreg(MM2VS_REGNUM_VER_LINES);
|
||||
MM2VS_REG_INT_LINE <= slvreg(MM2VS_REGNUM_INT_LINE );
|
||||
|
||||
VS2MM_REG_CONTROL <= slvreg(VS2MM_REGNUM_CONTROL );
|
||||
VS2MM_REG_STARTADDR <= slvreg(VS2MM_REGNUM_STARTADDR);
|
||||
VS2MM_REG_HOR_BYTES <= slvreg(VS2MM_REGNUM_HOR_BYTES);
|
||||
VS2MM_REG_STRIDE <= slvreg(VS2MM_REGNUM_STRIDE );
|
||||
VS2MM_REG_VER_LINES <= slvreg(VS2MM_REGNUM_VER_LINES);
|
||||
VS2MM_REG_INT_LINE <= slvreg(VS2MM_REGNUM_INT_LINE );
|
||||
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- Asynchronous Interrupt signalling (level high interrupt)
|
||||
-----------------------------------------------------------------
|
||||
axil_int_proc: process (slvreg)
|
||||
variable ints_masked : std_logic_vector(INTERRUPTS'range);
|
||||
begin
|
||||
|
||||
ints_masked := slvreg(REG_INT_STATUS)(INTERRUPTS'range) and slvreg(REG_INT_ENABLE)(INTERRUPTS'range);
|
||||
INTERRUPTS <= ints_masked;
|
||||
|
||||
end process;
|
||||
|
||||
end;
|
||||
+112
@@ -0,0 +1,112 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- axis_fifo_axi_2d_mmvs : AXI Stream FIFO
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
entity axis_fifo_axi_2d_mmvs is
|
||||
generic
|
||||
(
|
||||
FIFO_USE_BLOCKRAM : boolean := true;
|
||||
FIFO_AWIDTH : integer := 11;
|
||||
FIFO_DWIDTH : integer := 32;
|
||||
FIFO_TUSERWIDTH : integer := 1
|
||||
);
|
||||
port
|
||||
(
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_ACLK : in std_logic;
|
||||
S_AXIS_ARESETN : in std_logic := '1';
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
S_AXIS_TUSER : in std_logic_vector(FIFO_TUSERWIDTH-1 downto 0);
|
||||
S_NUM_FREE : out std_logic_vector(FIFO_AWIDTH-1 downto 0); -- Free Entries
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_ACLK : in std_logic;
|
||||
M_AXIS_ARESETN : in std_logic := '1';
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic;
|
||||
M_AXIS_TUSER : out std_logic_vector(FIFO_TUSERWIDTH-1 downto 0);
|
||||
M_NUM_AVAIL : out std_logic_vector(FIFO_AWIDTH-1 downto 0) -- Allocated Entries
|
||||
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_fifo_axi_2d_mmvs is
|
||||
|
||||
type T_AXIL_STATE is (IDLE,WAIT_BREADY,WAIT_RREADY);
|
||||
signal axil_state : T_AXIL_STATE := IDLE;
|
||||
|
||||
signal fifo_wrclk : std_logic;
|
||||
signal fifo_wrrst : std_logic;
|
||||
signal fifo_wren : std_logic;
|
||||
signal fifo_wrfull : std_logic;
|
||||
signal fifo_wrdat : std_logic_vector(FIFO_DWIDTH+FIFO_TUSERWIDTH downto 0);
|
||||
signal fifo_wrnum : std_logic_vector(FIFO_AWIDTH-1 downto 0);
|
||||
|
||||
signal fifo_rdclk : std_logic;
|
||||
signal fifo_rdrst : std_logic := '0';
|
||||
signal fifo_rden : std_logic;
|
||||
signal fifo_rdempty : std_logic;
|
||||
signal fifo_rddat : std_logic_vector(FIFO_DWIDTH+FIFO_TUSERWIDTH downto 0);
|
||||
signal fifo_rdnum : std_logic_vector(FIFO_AWIDTH-1 downto 0);
|
||||
|
||||
begin
|
||||
fifo_wrclk <= S_AXIS_ACLK;
|
||||
fifo_wrrst <= not S_AXIS_ARESETN;
|
||||
fifo_wren <= S_AXIS_TVALID;
|
||||
S_AXIS_TREADY <= not fifo_wrfull;
|
||||
fifo_wrdat <= S_AXIS_TUSER & S_AXIS_TLAST & S_AXIS_TDATA;
|
||||
S_NUM_FREE <= fifo_wrnum;
|
||||
|
||||
fifo_rdclk <= M_AXIS_ACLK;
|
||||
fifo_rdrst <= not M_AXIS_ARESETN;
|
||||
fifo_rden <= M_AXIS_TREADY;
|
||||
M_AXIS_TVALID <= not fifo_rdempty;
|
||||
M_AXIS_TDATA <= fifo_rddat(FIFO_DWIDTH-1 downto 0);
|
||||
M_AXIS_TUSER <= fifo_rddat(FIFO_DWIDTH+FIFO_TUSERWIDTH downto FIFO_DWIDTH+1);
|
||||
M_AXIS_TLAST <= fifo_rddat(FIFO_DWIDTH);
|
||||
M_NUM_AVAIL <= fifo_rdnum;
|
||||
|
||||
fifo : entity work.generic_fifo
|
||||
|
||||
generic map (
|
||||
USE_BLOCKRAM=> FIFO_USE_BLOCKRAM, -- Block RAM (1) or Distributed Memory (0)
|
||||
DW => FIFO_DWIDTH+FIFO_TUSERWIDTH+1, -- Data Width
|
||||
AW => FIFO_AWIDTH -- Address Width
|
||||
)
|
||||
port map (
|
||||
-- Write Port
|
||||
wrclk => fifo_wrclk, -- Clock
|
||||
wrrst => fifo_wrrst, -- Reset
|
||||
wrdat => fifo_wrdat, -- Data in
|
||||
wren => fifo_wren, -- Write enable
|
||||
wrfull => fifo_wrfull, -- Full indicator
|
||||
wrnum => fifo_wrnum,
|
||||
|
||||
-- Read Port
|
||||
rdclk => fifo_rdclk, -- Clock
|
||||
rdrst => fifo_rdrst, -- Reset
|
||||
rden => fifo_rden, -- Read enable
|
||||
rddat => fifo_rddat, -- Data out port
|
||||
rdempty => fifo_rdempty, -- Empty indicator
|
||||
rdnum => fifo_rdnum
|
||||
);
|
||||
|
||||
|
||||
end;
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- Dual-ported Synchronous Memory (Block Memory)
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2011
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity bmem_dp is
|
||||
|
||||
generic (
|
||||
DW : integer := 16; -- Data Width
|
||||
AW : integer := 10 -- Address Width
|
||||
);
|
||||
port (
|
||||
-- Port 1
|
||||
clk1 : in std_logic; -- Clock
|
||||
en1 : in std_logic; -- Enable
|
||||
a1 : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
d1 : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
we1 : in std_logic; -- Write enable
|
||||
q1 : out std_logic_vector(DW-1 downto 0); -- Data out port
|
||||
|
||||
-- Port 2
|
||||
clk2 : in std_logic; -- Clock
|
||||
en2 : in std_logic; -- Enable
|
||||
a2 : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
d2 : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
we2 : in std_logic; -- Write enable
|
||||
q2 : out std_logic_vector(DW-1 downto 0) -- Data out port
|
||||
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of bmem_dp is
|
||||
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
|
||||
shared variable mem : tmem := ((others=> (others=>'0')));
|
||||
|
||||
signal q1_sig : std_logic_vector(DW-1 downto 0) := (others=>'0');
|
||||
signal q2_sig : std_logic_vector(DW-1 downto 0) := (others=>'0');
|
||||
|
||||
begin
|
||||
q1 <= q1_sig;
|
||||
q2 <= q2_sig;
|
||||
|
||||
-- Port 1
|
||||
process (clk1)
|
||||
begin
|
||||
if (clk1'event and clk1 = '1') then
|
||||
if (en1 = '1') then
|
||||
if (we1 = '1') then
|
||||
mem(to_integer(unsigned(a1))) := d1;
|
||||
end if;
|
||||
q1_sig <= mem(to_integer(unsigned(a1)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Port 2
|
||||
process (clk2)
|
||||
begin
|
||||
if (clk2'event and clk2 = '1') then
|
||||
if (en2 = '1') then
|
||||
if (we2 = '1') then
|
||||
mem(to_integer(unsigned(a2))) := d2;
|
||||
end if;
|
||||
q2_sig <= mem(to_integer(unsigned(a2)));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- Dual-ported Asynchronous-Read Synchronous-Write Memory (Distributed Memory)
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2011
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dmem_dp is
|
||||
|
||||
generic (
|
||||
DW : integer := 16; -- Data Width
|
||||
AW : integer := 10 -- Address Width
|
||||
);
|
||||
port (
|
||||
-- Port 1
|
||||
clk1 : in std_logic; -- Clock
|
||||
en1 : in std_logic; -- Enable
|
||||
a1 : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
d1 : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
we1 : in std_logic; -- Write enable
|
||||
q1 : out std_logic_vector(DW-1 downto 0); -- Data out port
|
||||
|
||||
-- Port 2
|
||||
clk2 : in std_logic; -- Clock
|
||||
en2 : in std_logic; -- Enable
|
||||
a2 : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
d2 : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
we2 : in std_logic; -- Write enable
|
||||
q2 : out std_logic_vector(DW-1 downto 0) -- Data out port
|
||||
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of dmem_dp is
|
||||
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
|
||||
shared variable mem : tmem;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- Port 1
|
||||
process (clk1,a1)
|
||||
begin
|
||||
q1 <= mem(to_integer(unsigned(a1)));
|
||||
if (clk1'event and clk1 = '1') then
|
||||
if (en1 = '1') then
|
||||
if (we1 = '1') then
|
||||
mem(to_integer(unsigned(a1))) := d1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Port 2
|
||||
process (clk2,a2)
|
||||
begin
|
||||
q2 <= mem(to_integer(unsigned(a2)));
|
||||
if (clk2'event and clk2 = '1') then
|
||||
if (en2 = '1') then
|
||||
if (we2 = '1') then
|
||||
mem(to_integer(unsigned(a2))) := d2;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO incl. Clock Domain Crossing
|
||||
--
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity generic_fifo is
|
||||
|
||||
generic (
|
||||
USE_BLOCKRAM: boolean := true;
|
||||
DW : integer := 32; -- Data Width
|
||||
AW : integer := 10 -- Address Width
|
||||
);
|
||||
port (
|
||||
-- Write Port
|
||||
wrclk : in std_logic; -- Clock
|
||||
wrrst : in std_logic; -- Reset
|
||||
wrdat : in std_logic_vector(DW-1 downto 0); -- Data in
|
||||
wren : in std_logic; -- Write enable
|
||||
wrfull : out std_logic; -- Full indicator
|
||||
wrnum : out std_logic_vector(AW-1 downto 0); -- Free Entries
|
||||
|
||||
-- Read Port
|
||||
rdclk : in std_logic; -- Clock
|
||||
rdrst : in std_logic; -- Reset
|
||||
rden : in std_logic; -- Read enable
|
||||
rddat : out std_logic_vector(DW-1 downto 0); -- Data out port
|
||||
rdempty : out std_logic; -- Empty indicator
|
||||
rdnum : out std_logic_vector(AW-1 downto 0) -- Allocated Entries
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of generic_fifo is
|
||||
|
||||
|
||||
constant zero : std_logic_vector (DW-1 downto 0) := (others=>'0');
|
||||
|
||||
signal full : std_logic := '0';
|
||||
signal empty : std_logic := '1';
|
||||
|
||||
signal mem_wren : std_logic := '0';
|
||||
|
||||
signal wrrst_sync : std_logic := '0';
|
||||
signal rdrst_sync : std_logic := '0';
|
||||
|
||||
signal wp_bin : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal wp_bin_next : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal wp_gray : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal wp_gray_sync : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal wp_bin_sync : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal w_num_free : std_logic_vector (AW-1 downto 0) := (others=>'1');
|
||||
|
||||
signal rp_bin : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal rp_bin_reg : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal rp_bin_next : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal rp_gray : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal rp_gray_sync : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal rp_bin_sync : std_logic_vector (AW downto 0) := (others=>'0');
|
||||
signal r_num_avail : std_logic_vector (AW-1 downto 0) := (others=>'0');
|
||||
|
||||
signal rddat_dm : std_logic_vector(DW-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
bl_gen: if USE_BLOCKRAM generate
|
||||
fifomem : entity work.bmem_dp
|
||||
generic map(
|
||||
DW => DW, -- Data Width
|
||||
AW => AW -- Address Width
|
||||
)
|
||||
port map(
|
||||
-- Port 1
|
||||
clk1 => wrclk, -- Clock
|
||||
en1 => '1', -- Enable
|
||||
a1 => wp_bin(AW-1 downto 0), -- Address
|
||||
d1 => wrdat, -- Data in
|
||||
we1 => mem_wren, -- Write enable
|
||||
q1 => open, -- Data out port
|
||||
-- Port 2
|
||||
clk2 => rdclk, -- Clock
|
||||
en2 => '1', -- Enable
|
||||
a2 => rp_bin(AW-1 downto 0), -- Address
|
||||
d2 => zero, -- Data in
|
||||
we2 => '0', -- Write enable
|
||||
q2 => rddat -- Data out port
|
||||
);
|
||||
end generate;
|
||||
|
||||
dm_gen: if not USE_BLOCKRAM generate
|
||||
fifomem : entity work.dmem_dp
|
||||
generic map(
|
||||
DW => DW, -- Data Width
|
||||
AW => AW -- Address Width
|
||||
)
|
||||
port map(
|
||||
-- Port 1
|
||||
clk1 => wrclk, -- Clock
|
||||
en1 => '1', -- Enable
|
||||
a1 => wp_bin(AW-1 downto 0), -- Address
|
||||
d1 => wrdat, -- Data in
|
||||
we1 => mem_wren, -- Write enable
|
||||
q1 => open, -- Data out port
|
||||
-- Port 2
|
||||
clk2 => rdclk, -- Clock
|
||||
en2 => '1', -- Enable
|
||||
a2 => rp_bin(AW-1 downto 0), -- Address
|
||||
d2 => zero, -- Data in
|
||||
we2 => '0', -- Write enable
|
||||
q2 => rddat_dm -- Data out port
|
||||
);
|
||||
|
||||
process begin
|
||||
wait until rising_edge(rdclk);
|
||||
rddat <= rddat_dm;
|
||||
end process;
|
||||
end generate;
|
||||
----------------------------------------------
|
||||
-- FIFO Write Logic
|
||||
----------------------------------------------
|
||||
wp_gray <= '0' & wp_bin(AW downto 1) xor wp_bin; -- Gray Code conversion
|
||||
full <= '1' when (wp_bin(AW-1 downto 0) = rp_bin_sync(AW-1 downto 0)) and (wp_bin(AW) /= rp_bin_sync(AW)) else '0';
|
||||
wrfull <= full;
|
||||
wrnum <= w_num_free;
|
||||
mem_wren <= wren and (not full);
|
||||
|
||||
sync_wr : process begin
|
||||
wait until rising_edge(wrclk);
|
||||
rp_gray_sync <= rp_gray;
|
||||
rdrst_sync <= rdrst;
|
||||
end process;
|
||||
|
||||
fifo_fulln_wr : process begin
|
||||
wait until rising_edge(wrclk);
|
||||
if wp_bin = rp_bin_sync then
|
||||
w_num_free <= (others=>'1');
|
||||
else
|
||||
w_num_free <= std_logic_vector(unsigned(rp_bin_sync(AW-1 downto 0)) - unsigned(wp_bin(AW-1 downto 0)));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fifo_wr : process begin
|
||||
wait until rising_edge(wrclk);
|
||||
if wrrst = '1' or rdrst_sync = '1' then
|
||||
wp_bin <= (others=>'0');
|
||||
wp_bin_next <= std_logic_vector(to_unsigned(1,AW+1));
|
||||
else
|
||||
if wren = '1' and full = '0' then
|
||||
wp_bin <= wp_bin_next;
|
||||
wp_bin_next <= std_logic_vector(unsigned(wp_bin_next)+1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gray2bin_rp: process (rp_gray_sync)
|
||||
variable temp : std_logic_vector(AW downto 0);
|
||||
begin
|
||||
temp := rp_gray_sync;
|
||||
for i in AW-1 downto 0 loop
|
||||
temp(i) := rp_gray_sync(i) xor temp(i+1);
|
||||
end loop;
|
||||
rp_bin_sync <= temp;
|
||||
end process;
|
||||
|
||||
----------------------------------------------
|
||||
-- FIFO Read Logic
|
||||
----------------------------------------------
|
||||
rp_gray <= '0' & rp_bin(AW downto 1) xor rp_bin; -- Gray Code conversion
|
||||
empty <= '1' when rp_bin_reg = wp_bin_sync else '0';
|
||||
rdempty <= empty;
|
||||
rp_bin <= rp_bin_next when rden = '1' and empty = '0' else rp_bin_reg;
|
||||
rdnum <= r_num_avail;
|
||||
|
||||
|
||||
sync_rd : process begin
|
||||
wait until rising_edge(rdclk);
|
||||
wp_gray_sync <= wp_gray;
|
||||
wrrst_sync <= wrrst;
|
||||
end process;
|
||||
|
||||
fifo_fulln_rd : process begin
|
||||
wait until rising_edge(rdclk);
|
||||
if rp_bin_reg = wp_bin_sync then -- empty check -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16
|
||||
r_num_avail <= (others=>'0');
|
||||
elsif wp_bin_sync = (not rp_bin_reg(AW)) & rp_bin_reg(AW-1 downto 0) then --full check -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16
|
||||
r_num_avail <= (others=>'1');
|
||||
else
|
||||
r_num_avail <= std_logic_vector(unsigned(wp_bin_sync(AW-1 downto 0)) - unsigned(rp_bin_reg(AW-1 downto 0))); -- changed rp_bin to rp_bin_reg for timing improvement, WG 07.11.16
|
||||
end if;
|
||||
end process;
|
||||
|
||||
fifo_rd : process begin
|
||||
wait until rising_edge(rdclk);
|
||||
if rdrst = '1' or wrrst_sync = '1' then
|
||||
rp_bin_reg <= (others=>'0');
|
||||
rp_bin_next <= std_logic_vector(to_unsigned(1,AW+1));
|
||||
else
|
||||
rp_bin_reg <= rp_bin;
|
||||
if rden = '1' and empty = '0' then
|
||||
rp_bin_next <= std_logic_vector(unsigned(rp_bin_next)+1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
gray2bin_wp: process (wp_gray_sync)
|
||||
variable temp : std_logic_vector(AW downto 0);
|
||||
begin
|
||||
temp := wp_gray_sync;
|
||||
for i in AW-1 downto 0 loop
|
||||
temp(i) := wp_gray_sync(i) xor temp(i+1);
|
||||
end loop;
|
||||
wp_bin_sync <= temp;
|
||||
end process;
|
||||
|
||||
end;
|
||||
+359
@@ -0,0 +1,359 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- mm2vs_2d_core.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2014/2015
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity mm2vs_2d_core is
|
||||
generic
|
||||
(
|
||||
DWIDTH : integer := 32;
|
||||
IDWIDTH : integer := 1;
|
||||
MAX_BURSTLEN : integer := 16;
|
||||
MAX_PIPELINED_BURSTS : integer := 3;
|
||||
FIFO_AWIDTH : integer := 9
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic;
|
||||
|
||||
-- AXIS Initiator/Master Interface (IP)
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic := '0';
|
||||
M_AXIS_TUSER : out std_logic_vector(0 downto 0);
|
||||
M_AXIS_NUM_FREE : in std_logic_vector(FIFO_AWIDTH-1 downto 0):= (others=>'1'); -- Number of available entries in initiator
|
||||
|
||||
REG_CONTROL : in std_logic_vector(31 downto 0);
|
||||
REG_STARTADDR : in std_logic_vector(31 downto 0);
|
||||
REG_HOR_BYTES : in std_logic_vector(31 downto 0);
|
||||
REG_STRIDE : in std_logic_vector(31 downto 0);
|
||||
REG_VER_LINES : in std_logic_vector(31 downto 0);
|
||||
REG_INT_LINE : in std_logic_vector(31 downto 0);
|
||||
REG_FRAME_NUM : out std_logic_vector(31 downto 0);
|
||||
REG_LINE_NUM : out std_logic_vector(31 downto 0);
|
||||
LAST_FRAME_ST : out std_logic_vector(31 downto 0);
|
||||
|
||||
INTERRUPT : out std_logic;
|
||||
FINISHED_PULSE : out std_logic;
|
||||
|
||||
-- AXI Master Interface (Memory)
|
||||
M_AXI_ARREADY : in std_logic;
|
||||
M_AXI_ARVALID : out std_logic;
|
||||
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXI_ARID : out std_logic_vector(IDWIDTH-1 downto 0);
|
||||
M_AXI_ARLEN : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_ARSIZE : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_ARBURST : out std_logic_vector( 1 downto 0);
|
||||
M_AXI_ARPROT : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_ARCACHE : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_RREADY : out std_logic;
|
||||
M_AXI_RVALID : in std_logic;
|
||||
M_AXI_RDATA : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
M_AXI_RRESP : in std_logic_vector( 1 downto 0);
|
||||
M_AXI_RID : in std_logic_vector(IDWIDTH-1 downto 0);
|
||||
M_AXI_RLAST : in std_logic
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of mm2vs_2d_core is
|
||||
|
||||
-- Initiator AXI Master
|
||||
type T_MM2VS_FSM_STATE is (STARTUP,IDLE,CALC_FRAME_START_ADDR1,CALC_FRAME_START_ADDR2,CALC_FRAME_START_ADDR3,CALC_FRAME_START_ADDR4,REQ,WAIT_REQ_ACCEPT,WAIT_FRAME_FINISHED);
|
||||
signal mm2vs_fsm_state : T_MM2VS_FSM_STATE := IDLE;
|
||||
|
||||
signal mm2vs_lastgen_en : std_logic := '0';
|
||||
|
||||
begin
|
||||
------------------------------
|
||||
-- CONTROL-REGISTER
|
||||
------------------------------
|
||||
-- [0] run (if run_continously = 0 => toggle run to continue with next frame)
|
||||
-- [1] run_continously (1: do not stop if run is not toggled)
|
||||
-- [31:2] reserved
|
||||
|
||||
|
||||
M_AXI_ARSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
|
||||
M_AXI_ARBURST <= "01";
|
||||
M_AXI_ARPROT <= "000";
|
||||
-- M_AXI_ARCACHE <= "1111"; -- moved to process below (WG, Aug 16)
|
||||
M_AXI_ARID <= (others=>'0');
|
||||
|
||||
M_AXI_RREADY <= '1'; -- M_AXIS_TREADY;
|
||||
|
||||
------------------------------------------------
|
||||
-- AXIS Target Streaming Interface Connections
|
||||
------------------------------------------------
|
||||
-- All received data is accepted (= the FIFO ready signal is ignored)
|
||||
|
||||
M_AXIS_TVALID <= M_AXI_RVALID;
|
||||
M_AXIS_TDATA <= M_AXI_RDATA;
|
||||
M_AXIS_TLAST <= M_AXI_RLAST and mm2vs_lastgen_en;
|
||||
|
||||
-------------------------------------------
|
||||
-- Request and data handling state machine
|
||||
-------------------------------------------
|
||||
mm2vs_proc: process
|
||||
variable run : std_logic := '0';
|
||||
|
||||
variable addr : unsigned(31 downto 0);
|
||||
variable addr_frame_start : unsigned(31 downto 0);
|
||||
variable tmp36 : unsigned(35 downto 0);
|
||||
variable frame_size : unsigned(31 downto 0);
|
||||
variable buffered_frames : unsigned( 3 downto 0);
|
||||
variable curr_buffer : unsigned( 3 downto 0);
|
||||
variable last_buffer : unsigned( 3 downto 0);
|
||||
variable freezed_buffer : unsigned( 3 downto 0);
|
||||
variable freeze_active : boolean := false;
|
||||
variable last_freeze_ctrl : std_logic := '0';
|
||||
variable next_line_start : unsigned(31 downto 0);
|
||||
variable lastgen_bcnt : unsigned(15 downto 0);
|
||||
variable hor_beats : unsigned(15 downto 0);
|
||||
variable line_cnt : unsigned(15 downto 0);
|
||||
variable stride : unsigned(31 downto 0);
|
||||
variable h_req_cnt : unsigned(15 downto 0);
|
||||
variable h_data_cnt : unsigned(15 downto 0);
|
||||
|
||||
variable frame_cnt : unsigned(11 downto 0);
|
||||
variable frzd_frame_cnt : unsigned(11 downto 0);
|
||||
variable last_frame_cnt : unsigned(11 downto 0);
|
||||
|
||||
variable bursts_in_flight : unsigned( 4 downto 0);
|
||||
|
||||
variable start_delay_cnt : unsigned(27 downto 0);
|
||||
|
||||
variable burst_len : unsigned( 4 downto 0);
|
||||
variable burst_len_coded : unsigned( 4 downto 0);
|
||||
|
||||
variable bend : unsigned( 4 downto 0);
|
||||
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
|
||||
---------------------------------------------------
|
||||
-- Reset behaviour
|
||||
---------------------------------------------------
|
||||
if RESETN = '0' then
|
||||
M_AXI_ARVALID <= '0';
|
||||
M_AXI_ARADDR <= (others=>'0');
|
||||
M_AXI_ARLEN <= (others=>'0');
|
||||
M_AXIS_TUSER(0) <= '0'; -- SOF
|
||||
|
||||
INTERRUPT <= '0';
|
||||
FINISHED_PULSE <= '0';
|
||||
|
||||
bursts_in_flight := (others=>'0');
|
||||
|
||||
run := REG_CONTROL(0);
|
||||
|
||||
line_cnt := unsigned(REG_VER_LINES(line_cnt'range));
|
||||
frame_cnt := (others=>'0');
|
||||
buffered_frames := (others=>'0');
|
||||
curr_buffer := (others=>'0');
|
||||
freezed_buffer := (others=>'0');
|
||||
freeze_active := false;
|
||||
|
||||
if run = '1' then -- no transaction during initialization (i.e. when booting from SD card)
|
||||
start_delay_cnt := to_unsigned(150000000,28);
|
||||
mm2vs_fsm_state <= STARTUP;
|
||||
else
|
||||
mm2vs_fsm_state <= IDLE;
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
run := REG_CONTROL(0);
|
||||
|
||||
REG_FRAME_NUM <= x"00"&std_logic_vector(frzd_frame_cnt & last_frame_cnt);
|
||||
REG_FRAME_NUM (27 downto 24) <= std_logic_vector(freezed_buffer);
|
||||
REG_FRAME_NUM (31 downto 28) <= std_logic_vector(last_buffer);
|
||||
|
||||
REG_LINE_NUM <= x"0000"&std_logic_vector(line_cnt);
|
||||
|
||||
M_AXI_ARCACHE <= REG_CONTROL(15 downto 12);
|
||||
INTERRUPT <= '0'; -- de-assert IRQ line
|
||||
FINISHED_PULSE <= '0';
|
||||
|
||||
if (last_freeze_ctrl = '0' and REG_CONTROL(9) = '1') then -- rising edge on freeze control bit ?
|
||||
freezed_buffer := last_buffer;
|
||||
frzd_frame_cnt := last_frame_cnt;
|
||||
freeze_active := true;
|
||||
elsif (REG_CONTROL(9) = '0') then -- freeze control bit = zero ?
|
||||
freeze_active := false;
|
||||
end if;
|
||||
|
||||
last_freeze_ctrl := REG_CONTROL(9);
|
||||
|
||||
case mm2vs_fsm_state is
|
||||
|
||||
when STARTUP =>
|
||||
if start_delay_cnt = 0 then
|
||||
mm2vs_fsm_state <= IDLE;
|
||||
end if;
|
||||
|
||||
buffered_frames := (others=>'0');
|
||||
curr_buffer := (others=>'0');
|
||||
|
||||
start_delay_cnt := start_delay_cnt - 1;
|
||||
|
||||
when IDLE =>
|
||||
if run = '1' then
|
||||
bursts_in_flight := (others=>'0');
|
||||
|
||||
buffered_frames := unsigned(REG_CONTROL(7 downto 4));
|
||||
|
||||
-- calculate current buffer
|
||||
curr_buffer := curr_buffer+1;
|
||||
|
||||
if (curr_buffer > buffered_frames) then
|
||||
curr_buffer := (others=>'0');
|
||||
end if;
|
||||
|
||||
if (freeze_active and curr_buffer = freezed_buffer) then
|
||||
curr_buffer := curr_buffer+1;
|
||||
if (curr_buffer > buffered_frames) then
|
||||
curr_buffer := (others=>'0');
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
if DWIDTH = 32 then
|
||||
hor_beats := "00"&unsigned(REG_HOR_BYTES(15 downto 2));
|
||||
else
|
||||
hor_beats := "000"&unsigned(REG_HOR_BYTES(15 downto 3));
|
||||
end if;
|
||||
stride := unsigned(REG_STRIDE);
|
||||
if REG_STRIDE(23) = '0' then -- sign extension
|
||||
stride(31 downto 24) := (others=>'0');
|
||||
else
|
||||
stride(31 downto 24) := (others=>'1');
|
||||
end if;
|
||||
line_cnt := unsigned(REG_VER_LINES(line_cnt'range));
|
||||
frame_cnt := frame_cnt + 1;
|
||||
|
||||
h_req_cnt := hor_beats;
|
||||
h_data_cnt := hor_beats;
|
||||
|
||||
M_AXIS_TUSER(0) <= '1'; -- generate SOF
|
||||
|
||||
mm2vs_fsm_state <= CALC_FRAME_START_ADDR1;
|
||||
end if;
|
||||
|
||||
when CALC_FRAME_START_ADDR1 =>
|
||||
addr := unsigned(REG_STARTADDR(addr'range));
|
||||
frame_size := line_cnt * stride(15 downto 0);
|
||||
mm2vs_fsm_state <= CALC_FRAME_START_ADDR2;
|
||||
|
||||
when CALC_FRAME_START_ADDR2 =>
|
||||
tmp36 := frame_size*curr_buffer;
|
||||
mm2vs_fsm_state <= CALC_FRAME_START_ADDR3;
|
||||
|
||||
when CALC_FRAME_START_ADDR3 =>
|
||||
addr := addr + tmp36(31 downto 0);
|
||||
mm2vs_fsm_state <= CALC_FRAME_START_ADDR4;
|
||||
|
||||
when CALC_FRAME_START_ADDR4 =>
|
||||
addr_frame_start := addr;
|
||||
next_line_start := addr + stride;
|
||||
mm2vs_fsm_state <= REQ;
|
||||
|
||||
when REQ =>
|
||||
if (unsigned(M_AXIS_NUM_FREE) > MAX_BURSTLEN*(MAX_PIPELINED_BURSTS+1)) and (bursts_in_flight<=MAX_PIPELINED_BURSTS) then -- check if FIFO can deliver sufficient number of data to execute a complete burst
|
||||
M_AXI_ARADDR <= std_logic_vector(addr);
|
||||
M_AXI_ARVALID <= '1';
|
||||
|
||||
-- set burst length
|
||||
if h_req_cnt >= MAX_BURSTLEN then
|
||||
burst_len := to_unsigned(MAX_BURSTLEN,5);
|
||||
else
|
||||
burst_len := h_req_cnt(4 downto 0);
|
||||
end if;
|
||||
|
||||
bend := "0"&addr(5 downto 2) + burst_len - 1;
|
||||
|
||||
if addr(11 downto 6) = "111111" and bend(4) = '1' then -- 4k boundary crossing?
|
||||
burst_len := "0" & (not (addr(5 downto 2)) + 1);
|
||||
end if;
|
||||
|
||||
burst_len_coded := burst_len-1;
|
||||
M_AXI_ARLEN <= std_logic_vector(burst_len_coded(3 downto 0));
|
||||
h_req_cnt := h_req_cnt - burst_len;
|
||||
if h_req_cnt = 0 then
|
||||
h_req_cnt := hor_beats;
|
||||
line_cnt := line_cnt - 1;
|
||||
if line_cnt = unsigned(REG_INT_LINE(line_cnt'range)) then
|
||||
INTERRUPT <= '1';
|
||||
end if;
|
||||
addr := next_line_start;
|
||||
next_line_start := next_line_start + stride;
|
||||
else
|
||||
if DWIDTH = 32 then
|
||||
addr := addr + (burst_len&"00");
|
||||
else
|
||||
addr := addr + (burst_len&"000");
|
||||
end if;
|
||||
end if;
|
||||
|
||||
mm2vs_fsm_state <= WAIT_REQ_ACCEPT;
|
||||
end if;
|
||||
|
||||
|
||||
when WAIT_REQ_ACCEPT =>
|
||||
if M_AXI_ARREADY = '1' then -- has the currently requested burst been accepted ?
|
||||
bursts_in_flight := bursts_in_flight + 1;
|
||||
M_AXI_ARVALID <= '0'; -- and de-assert the valid signal
|
||||
if line_cnt = 0 then -- is this the last burst of the current frame ?
|
||||
mm2vs_fsm_state <= WAIT_FRAME_FINISHED; -- if yes, wait until all requested data have been transmitted
|
||||
else
|
||||
mm2vs_fsm_state <= REQ; -- if no, continue with next burst
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when WAIT_FRAME_FINISHED =>
|
||||
if bursts_in_flight <= 0 then
|
||||
FINISHED_PULSE <= '1';
|
||||
last_buffer := curr_buffer;
|
||||
last_frame_cnt := frame_cnt;
|
||||
LAST_FRAME_ST <= std_logic_vector(addr_frame_start);
|
||||
mm2vs_fsm_state <= IDLE;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
|
||||
|
||||
if M_AXI_RVALID = '1' then -- valid data transmission ?
|
||||
M_AXIS_TUSER(0) <= '0'; -- reset SOF (was set in FSM above)
|
||||
|
||||
h_data_cnt := h_data_cnt - 1;
|
||||
if h_data_cnt = 1 then
|
||||
mm2vs_lastgen_en <= '1';
|
||||
end if;
|
||||
if h_data_cnt = 0 then
|
||||
h_data_cnt := hor_beats;
|
||||
end if;
|
||||
|
||||
if M_AXI_RLAST = '1' then -- Burst finished ?
|
||||
mm2vs_lastgen_en <= '0';
|
||||
bursts_in_flight := bursts_in_flight - 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
+365
@@ -0,0 +1,365 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- vs2mm_2d_core.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2013/2014/2015
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity vs2mm_2d_core is
|
||||
generic
|
||||
(
|
||||
DWIDTH : integer := 32;
|
||||
IDWIDTH : integer := 1;
|
||||
MAX_BURSTLEN : integer := 16;
|
||||
FIFO_AWIDTH : integer := 9
|
||||
);
|
||||
|
||||
port
|
||||
(
|
||||
CLK : in std_logic;
|
||||
RESETN : in std_logic;
|
||||
|
||||
-- AXIS Initiator/Master Interface (IP)
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(DWIDTH-1 downto 0);
|
||||
S_AXIS_TLAST : in std_logic;
|
||||
S_AXIS_TREADY : out std_logic := '0';
|
||||
S_AXIS_TUSER : in std_logic_vector(0 downto 0);
|
||||
S_AXIS_NUM_AVAIL : in std_logic_vector(FIFO_AWIDTH-1 downto 0):= (others=>'1'); -- Number of available entries in initiator
|
||||
|
||||
REG_CONTROL : in std_logic_vector(31 downto 0);
|
||||
REG_STARTADDR : in std_logic_vector(31 downto 0);
|
||||
REG_HOR_BYTES : in std_logic_vector(31 downto 0);
|
||||
REG_STRIDE : in std_logic_vector(31 downto 0);
|
||||
REG_VER_LINES : in std_logic_vector(31 downto 0);
|
||||
REG_INT_LINE : in std_logic_vector(31 downto 0);
|
||||
REG_FRAME_NUM : out std_logic_vector(31 downto 0);
|
||||
REG_LINE_NUM : out std_logic_vector(31 downto 0);
|
||||
LAST_FRAME_ST : out std_logic_vector(31 downto 0);
|
||||
|
||||
INTERRUPT : out std_logic;
|
||||
FINISHED_PULSE : out std_logic;
|
||||
|
||||
-- AXI Master Interface (Memory)
|
||||
M_AXI_AWREADY : in std_logic;
|
||||
M_AXI_AWVALID : out std_logic;
|
||||
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXI_AWLEN : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_AWID : out std_logic_vector(IDWIDTH-1 downto 0);
|
||||
M_AXI_AWSIZE : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_AWBURST : out std_logic_vector( 1 downto 0);
|
||||
M_AXI_AWPROT : out std_logic_vector( 2 downto 0);
|
||||
M_AXI_AWCACHE : out std_logic_vector( 3 downto 0);
|
||||
M_AXI_WREADY : in std_logic;
|
||||
M_AXI_WVALID : out std_logic;
|
||||
M_AXI_WDATA : out std_logic_vector(DWIDTH-1 downto 0);
|
||||
M_AXI_WSTRB : out std_logic_vector(DWIDTH/8-1 downto 0);
|
||||
M_AXI_WLAST : out std_logic;
|
||||
M_AXI_WID : out std_logic_vector(IDWIDTH-1 downto 0);
|
||||
M_AXI_BREADY : out std_logic;
|
||||
M_AXI_BVALID : in std_logic;
|
||||
M_AXI_BID : in std_logic_vector(IDWIDTH-1 downto 0);
|
||||
M_AXI_BRESP : in std_logic_vector( 1 downto 0)
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of vs2mm_2d_core is
|
||||
|
||||
-- Initiator AXI Master
|
||||
type T_VS2MM_FSM_STATE is (STARTUP,IDLE,CALC_FRAME_START_ADDR1,CALC_FRAME_START_ADDR2,CALC_FRAME_START_ADDR3,CALC_FRAME_START_ADDR4,REQ,WAIT_REQ_ACCEPT,WAIT_BURST_FINISHED);
|
||||
signal vs2mm_fsm_state : T_VS2MM_FSM_STATE := STARTUP;
|
||||
|
||||
signal Flush_Until_SOF : std_logic;
|
||||
signal Flush_Always : std_logic;
|
||||
signal Wait_for_End_of_Burst : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
------------------------------
|
||||
-- CONTROL-REGISTER
|
||||
------------------------------
|
||||
-- [0] run (toggle to continue with next frame)
|
||||
-- [1] run_continously (1: do not stop if run bit is not toggled)
|
||||
-- [2] 1: wait for SOF at start of frame (i.e. stream re-synchronisation at frame start)
|
||||
-- [31:3] reserved
|
||||
|
||||
|
||||
M_AXI_AWSIZE <= "010" when DWIDTH=32 else "011"; -- Data width 32/64
|
||||
M_AXI_AWBURST <= "01";
|
||||
M_AXI_AWPROT <= "000";
|
||||
-- M_AXI_AWCACHE <= "1111"; -- moved to process below (WG, Aug 16)
|
||||
M_AXI_BREADY <= '1';
|
||||
M_AXI_WSTRB <= (others=>'1');
|
||||
M_AXI_AWID <= (others=>'0');
|
||||
M_AXI_WID <= (others=>'0');
|
||||
|
||||
------------------------------------------------
|
||||
-- AXIS Target Streaming Interface Connections
|
||||
------------------------------------------------
|
||||
|
||||
-- S_AXIS_TREADY <= '1' when (M_AXI_WREADY='1' and (vs2mm_fsm_state = WAIT_BURST_FINISHED)) or (Flush_Always='1') or (Flush_Until_SOF = '1' and S_AXIS_TUSER(0) = '0') else '0';
|
||||
-- M_AXI_WVALID <= '1' when S_AXIS_TVALID='1' and (vs2mm_fsm_state = WAIT_BURST_FINISHED) else '0';
|
||||
-- >>> replaced to improve timing
|
||||
S_AXIS_TREADY <= '1' when (vs2mm_fsm_state = STARTUP) or (M_AXI_WREADY='1' and Wait_for_End_of_Burst = '1') or (Flush_Always='1') or (Flush_Until_SOF = '1' and S_AXIS_TUSER(0) = '0') else '0';
|
||||
M_AXI_WVALID <= '1' when S_AXIS_TVALID='1' and Wait_for_End_of_Burst = '1' else '0';
|
||||
M_AXI_WDATA <= S_AXIS_TDATA;
|
||||
|
||||
-------------------------------------------
|
||||
-- Request and data handling state machine
|
||||
-------------------------------------------
|
||||
vs2mm_proc: process
|
||||
variable run : std_logic;
|
||||
variable no_flush_when_inactive : std_logic;
|
||||
variable wait_for_sof : std_logic;
|
||||
|
||||
variable addr : unsigned(31 downto 0);
|
||||
variable addr_frame_start : unsigned(31 downto 0);
|
||||
variable tmp36 : unsigned(35 downto 0);
|
||||
variable frame_size : unsigned(31 downto 0);
|
||||
variable buffered_frames : unsigned( 3 downto 0);
|
||||
variable curr_buffer : unsigned( 3 downto 0);
|
||||
variable last_buffer : unsigned( 3 downto 0);
|
||||
variable freezed_buffer : unsigned( 3 downto 0);
|
||||
variable freeze_active : boolean := false;
|
||||
variable last_freeze_ctrl : std_logic := '0';
|
||||
variable next_line_start : unsigned(31 downto 0);
|
||||
variable lastgen_bcnt : unsigned(15 downto 0);
|
||||
variable hor_beats : unsigned(15 downto 0);
|
||||
variable line_cnt : unsigned(15 downto 0);
|
||||
variable stride : unsigned(31 downto 0);
|
||||
variable h_req_cnt : unsigned(15 downto 0);
|
||||
variable h_data_cnt : unsigned( 4 downto 0);
|
||||
|
||||
variable frame_cnt : unsigned(11 downto 0);
|
||||
variable frzd_frame_cnt : unsigned(11 downto 0);
|
||||
variable last_frame_cnt : unsigned(11 downto 0);
|
||||
|
||||
variable start_delay_cnt : unsigned(27 downto 0);
|
||||
|
||||
variable burst_len : unsigned( 4 downto 0);
|
||||
variable burst_len_coded : unsigned( 4 downto 0);
|
||||
|
||||
variable bend : unsigned( 4 downto 0);
|
||||
|
||||
begin
|
||||
wait until rising_edge (CLK);
|
||||
|
||||
---------------------------------------------------
|
||||
-- Reset behaviour
|
||||
---------------------------------------------------
|
||||
if RESETN = '0' then
|
||||
M_AXI_AWVALID <= '0';
|
||||
M_AXI_AWADDR <= (others=>'0');
|
||||
M_AXI_AWLEN <= (others=>'0');
|
||||
M_AXI_WLAST <= '0';
|
||||
|
||||
Flush_Until_SOF <= '0';
|
||||
Flush_Always <= '0';
|
||||
Wait_for_End_of_Burst <= '0';
|
||||
|
||||
INTERRUPT <= '0';
|
||||
FINISHED_PULSE <= '0';
|
||||
|
||||
run := REG_CONTROL(0);
|
||||
no_flush_when_inactive := REG_CONTROL(8);
|
||||
|
||||
line_cnt := unsigned(REG_VER_LINES(line_cnt'range));
|
||||
frame_cnt := (others=>'0');
|
||||
buffered_frames := (others=>'0');
|
||||
curr_buffer := (others=>'0');
|
||||
freezed_buffer := (others=>'0');
|
||||
freeze_active := false;
|
||||
|
||||
if run = '1' then -- no transaction during initialization (i.e. when booting from SD card)
|
||||
start_delay_cnt := to_unsigned(150000000,28);
|
||||
vs2mm_fsm_state <= STARTUP;
|
||||
else
|
||||
vs2mm_fsm_state <= IDLE;
|
||||
end if;
|
||||
|
||||
else
|
||||
|
||||
run := REG_CONTROL(0);
|
||||
wait_for_sof := REG_CONTROL(1);
|
||||
Flush_Always <= not (run or no_flush_when_inactive);
|
||||
|
||||
REG_FRAME_NUM (23 downto 0) <= std_logic_vector(frzd_frame_cnt & last_frame_cnt);
|
||||
REG_FRAME_NUM (27 downto 24) <= std_logic_vector(freezed_buffer);
|
||||
REG_FRAME_NUM (31 downto 28) <= std_logic_vector(last_buffer);
|
||||
|
||||
REG_LINE_NUM <= x"0000"&std_logic_vector(line_cnt);
|
||||
|
||||
if (last_freeze_ctrl = '0' and REG_CONTROL(9) = '1') then -- rising edge on freeze control bit ?
|
||||
freezed_buffer := last_buffer;
|
||||
frzd_frame_cnt := last_frame_cnt;
|
||||
freeze_active := true;
|
||||
elsif (REG_CONTROL(9) = '0') then -- freeze control bit = zero ?
|
||||
freeze_active := false;
|
||||
end if;
|
||||
|
||||
last_freeze_ctrl := REG_CONTROL(9);
|
||||
|
||||
M_AXI_AWCACHE <= REG_CONTROL(15 downto 12);
|
||||
INTERRUPT <= '0'; -- de-assert IRQ line
|
||||
FINISHED_PULSE <= '0';
|
||||
|
||||
Wait_for_End_of_Burst <= '0';
|
||||
|
||||
case vs2mm_fsm_state is
|
||||
|
||||
when STARTUP =>
|
||||
if start_delay_cnt = 0 then
|
||||
vs2mm_fsm_state <= IDLE;
|
||||
end if;
|
||||
start_delay_cnt := start_delay_cnt - 1;
|
||||
buffered_frames := "0000";
|
||||
|
||||
when IDLE =>
|
||||
Flush_Until_SOF <= '0';
|
||||
if wait_for_sof = '1' and S_AXIS_TUSER(0) = '0' then
|
||||
Flush_Until_SOF <= '1';
|
||||
elsif run = '1' then
|
||||
|
||||
buffered_frames := unsigned(REG_CONTROL(7 downto 4));
|
||||
|
||||
-- calculate current buffer
|
||||
curr_buffer := curr_buffer+1;
|
||||
|
||||
if (curr_buffer > buffered_frames) then
|
||||
curr_buffer := (others=>'0');
|
||||
end if;
|
||||
|
||||
if (freeze_active and curr_buffer = freezed_buffer) then
|
||||
curr_buffer := curr_buffer+1;
|
||||
if (curr_buffer > buffered_frames) then
|
||||
curr_buffer := (others=>'0');
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if DWIDTH = 32 then
|
||||
hor_beats := "00"&unsigned(REG_HOR_BYTES(15 downto 2));
|
||||
else
|
||||
hor_beats := "000"&unsigned(REG_HOR_BYTES(15 downto 3));
|
||||
end if;
|
||||
stride := unsigned(REG_STRIDE);
|
||||
if REG_STRIDE(23) = '0' then -- sign extension
|
||||
stride(31 downto 24) := (others=>'0');
|
||||
else
|
||||
stride(31 downto 24) := (others=>'1');
|
||||
end if;
|
||||
line_cnt := unsigned(REG_VER_LINES(line_cnt'range));
|
||||
frame_cnt := frame_cnt + 1;
|
||||
|
||||
h_req_cnt := hor_beats;
|
||||
next_line_start := addr + stride;
|
||||
|
||||
vs2mm_fsm_state <= CALC_FRAME_START_ADDR1;
|
||||
end if;
|
||||
|
||||
when CALC_FRAME_START_ADDR1 =>
|
||||
addr := unsigned(REG_STARTADDR(addr'range));
|
||||
frame_size := line_cnt * stride(15 downto 0);
|
||||
vs2mm_fsm_state <= CALC_FRAME_START_ADDR2;
|
||||
|
||||
when CALC_FRAME_START_ADDR2 =>
|
||||
tmp36 := frame_size*curr_buffer;
|
||||
vs2mm_fsm_state <= CALC_FRAME_START_ADDR3;
|
||||
|
||||
when CALC_FRAME_START_ADDR3 =>
|
||||
addr := addr + tmp36(31 downto 0);
|
||||
vs2mm_fsm_state <= CALC_FRAME_START_ADDR4;
|
||||
|
||||
when CALC_FRAME_START_ADDR4 =>
|
||||
addr_frame_start := addr;
|
||||
next_line_start := addr + stride;
|
||||
vs2mm_fsm_state <= REQ;
|
||||
|
||||
when REQ =>
|
||||
if (unsigned(S_AXIS_NUM_AVAIL) >= MAX_BURSTLEN) then -- check if FIFO can deliver sufficient number of data to execute a complete burst
|
||||
M_AXI_AWADDR <= std_logic_vector(addr);
|
||||
M_AXI_AWVALID <= '1';
|
||||
|
||||
-- set burst length
|
||||
if h_req_cnt >= MAX_BURSTLEN then
|
||||
burst_len := to_unsigned(MAX_BURSTLEN,5);
|
||||
else
|
||||
burst_len := h_req_cnt(4 downto 0);
|
||||
end if;
|
||||
|
||||
bend := "0"&addr(5 downto 2) + burst_len - 1;
|
||||
|
||||
if addr(11 downto 6) = "111111" and bend(4) = '1' then -- 4k boundary crossing?
|
||||
burst_len := "0" & (not (addr(5 downto 2)) + 1);
|
||||
end if;
|
||||
|
||||
burst_len_coded := burst_len-1;
|
||||
M_AXI_AWLEN <= std_logic_vector(burst_len_coded(3 downto 0));
|
||||
h_req_cnt := h_req_cnt - burst_len;
|
||||
h_data_cnt := burst_len;
|
||||
if DWIDTH = 32 then
|
||||
addr := addr + (burst_len&"00");
|
||||
else
|
||||
addr := addr + (burst_len&"000");
|
||||
end if;
|
||||
|
||||
vs2mm_fsm_state <= WAIT_REQ_ACCEPT;
|
||||
end if;
|
||||
|
||||
|
||||
when WAIT_REQ_ACCEPT =>
|
||||
if M_AXI_AWREADY = '1' then -- has the currently requested burst been accepted ?
|
||||
M_AXI_AWVALID <= '0'; -- and de-assert the valid signal
|
||||
Wait_for_End_of_Burst <= '1';
|
||||
vs2mm_fsm_state <= WAIT_BURST_FINISHED; -- if yes, wait until all requested data have been transmitted
|
||||
end if;
|
||||
|
||||
when WAIT_BURST_FINISHED =>
|
||||
Wait_for_End_of_Burst <= '1';
|
||||
if M_AXI_WREADY = '1' then -- valid data transmission ?
|
||||
h_data_cnt := h_data_cnt - 1;
|
||||
|
||||
if h_data_cnt = 1 then
|
||||
M_AXI_WLAST <= '1';
|
||||
end if;
|
||||
|
||||
if h_data_cnt = 0 then -- burst finished
|
||||
Wait_for_End_of_Burst <= '0';
|
||||
vs2mm_fsm_state <= REQ;
|
||||
M_AXI_WLAST <= '0';
|
||||
if h_req_cnt = 0 then
|
||||
h_req_cnt := hor_beats;
|
||||
line_cnt := line_cnt - 1;
|
||||
if line_cnt = unsigned(REG_INT_LINE(line_cnt'range)) then
|
||||
INTERRUPT <= '1';
|
||||
end if;
|
||||
addr := next_line_start;
|
||||
next_line_start := next_line_start + stride;
|
||||
if line_cnt = 0 then
|
||||
FINISHED_PULSE <= '1';
|
||||
last_buffer := curr_buffer;
|
||||
last_frame_cnt := frame_cnt;
|
||||
LAST_FRAME_ST <= std_logic_vector(addr_frame_start);
|
||||
vs2mm_fsm_state <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
+5588
File diff suppressed because it is too large
Load Diff
+409
@@ -0,0 +1,409 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
|
||||
//--
|
||||
//-- This file contains confidential and proprietary information
|
||||
//-- of Xilinx, Inc. and is protected under U.S. and
|
||||
//-- international copyright and other intellectual property
|
||||
//-- laws.
|
||||
//--
|
||||
//-- DISCLAIMER
|
||||
//-- This disclaimer is not a license and does not grant any
|
||||
//-- rights to the materials distributed herewith. Except as
|
||||
//-- otherwise provided in a valid license issued to you by
|
||||
//-- Xilinx, and to the maximum extent permitted by applicable
|
||||
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
//-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
//-- including negligence, or under any other theory of
|
||||
//-- liability) for any loss or damage of any kind or nature
|
||||
//-- related to, arising under or in connection with these
|
||||
//-- materials, including for any direct, or any indirect,
|
||||
//-- special, incidental, or consequential loss or damage
|
||||
//-- (including loss of data, profits, goodwill, or any type of
|
||||
//-- loss or damage suffered as a result of any action brought
|
||||
//-- by a third party) even if such damage or loss was
|
||||
//-- reasonably foreseeable or Xilinx had been advised of the
|
||||
//-- possibility of the same.
|
||||
//--
|
||||
//-- CRITICAL APPLICATIONS
|
||||
//-- Xilinx products are not designed or intended to be fail-
|
||||
//-- safe, or for use in any application requiring fail-safe
|
||||
//-- performance, such as life-support or safety devices or
|
||||
//-- systems, Class III medical devices, nuclear facilities,
|
||||
//-- applications related to the deployment of airbags, or any
|
||||
//-- other applications that could lead to death, personal
|
||||
//-- injury, or severe property or environmental damage
|
||||
//-- (individually and collectively, "Critical
|
||||
//-- Applications"). Customer assumes the sole risk and
|
||||
//-- liability of any use of Xilinx products in Critical
|
||||
//-- Applications, subject only to applicable laws and
|
||||
//-- regulations governing limitations on product liability.
|
||||
//--
|
||||
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
//-- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: ACP Transaction Checker
|
||||
//
|
||||
// Check for optimized ACP transactions and flag if they are broken.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// atc
|
||||
// aw_atc
|
||||
// w_atc
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module processing_system7_v5_5_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
// Width of ARUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
// Width of WUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
// Width of RUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1
|
||||
// Width of BUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ACLK,
|
||||
input wire ARESETN,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output wire [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
|
||||
input wire [4-1:0] S_AXI_ARLEN,
|
||||
input wire [3-1:0] S_AXI_ARSIZE,
|
||||
input wire [2-1:0] S_AXI_ARBURST,
|
||||
input wire [2-1:0] S_AXI_ARLOCK,
|
||||
input wire [4-1:0] S_AXI_ARCACHE,
|
||||
input wire [3-1:0] S_AXI_ARPROT,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
|
||||
input wire S_AXI_ARVALID,
|
||||
output wire S_AXI_ARREADY,
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
|
||||
output wire [2-1:0] S_AXI_RRESP,
|
||||
output wire S_AXI_RLAST,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
|
||||
output wire S_AXI_RVALID,
|
||||
input wire S_AXI_RREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY,
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY,
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
|
||||
output wire [4-1:0] M_AXI_ARLEN,
|
||||
output wire [3-1:0] M_AXI_ARSIZE,
|
||||
output wire [2-1:0] M_AXI_ARBURST,
|
||||
output wire [2-1:0] M_AXI_ARLOCK,
|
||||
output wire [4-1:0] M_AXI_ARCACHE,
|
||||
output wire [3-1:0] M_AXI_ARPROT,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
|
||||
output wire M_AXI_ARVALID,
|
||||
input wire M_AXI_ARREADY,
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
|
||||
input wire [2-1:0] M_AXI_RRESP,
|
||||
input wire M_AXI_RLAST,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
|
||||
input wire M_AXI_RVALID,
|
||||
output wire M_AXI_RREADY,
|
||||
|
||||
output wire ERROR_TRIGGER,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam C_FIFO_DEPTH_LOG = 4;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Internal reset.
|
||||
reg ARESET;
|
||||
|
||||
// AW->W command queue signals.
|
||||
wire cmd_w_valid;
|
||||
wire cmd_w_check;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
|
||||
wire cmd_w_ready;
|
||||
|
||||
// W->B command queue signals.
|
||||
wire cmd_b_push;
|
||||
wire cmd_b_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
|
||||
wire cmd_b_full;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
|
||||
wire cmd_b_ready;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Internal Reset
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
always @ (posedge ACLK) begin
|
||||
ARESET <= !ARESETN;
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Write Channels (AW/W/B)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Write Address Channel.
|
||||
processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_addr_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
.S_AXI_AWID (S_AXI_AWID),
|
||||
.S_AXI_AWADDR (S_AXI_AWADDR),
|
||||
.S_AXI_AWLEN (S_AXI_AWLEN),
|
||||
.S_AXI_AWSIZE (S_AXI_AWSIZE),
|
||||
.S_AXI_AWBURST (S_AXI_AWBURST),
|
||||
.S_AXI_AWLOCK (S_AXI_AWLOCK),
|
||||
.S_AXI_AWCACHE (S_AXI_AWCACHE),
|
||||
.S_AXI_AWPROT (S_AXI_AWPROT),
|
||||
.S_AXI_AWUSER (S_AXI_AWUSER),
|
||||
.S_AXI_AWVALID (S_AXI_AWVALID),
|
||||
.S_AXI_AWREADY (S_AXI_AWREADY),
|
||||
|
||||
// Master Interface Write Address Port
|
||||
.M_AXI_AWID (M_AXI_AWID),
|
||||
.M_AXI_AWADDR (M_AXI_AWADDR),
|
||||
.M_AXI_AWLEN (M_AXI_AWLEN),
|
||||
.M_AXI_AWSIZE (M_AXI_AWSIZE),
|
||||
.M_AXI_AWBURST (M_AXI_AWBURST),
|
||||
.M_AXI_AWLOCK (M_AXI_AWLOCK),
|
||||
.M_AXI_AWCACHE (M_AXI_AWCACHE),
|
||||
.M_AXI_AWPROT (M_AXI_AWPROT),
|
||||
.M_AXI_AWUSER (M_AXI_AWUSER),
|
||||
.M_AXI_AWVALID (M_AXI_AWVALID),
|
||||
.M_AXI_AWREADY (M_AXI_AWREADY)
|
||||
);
|
||||
|
||||
// Write Data channel.
|
||||
processing_system7_v5_5_w_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
|
||||
) write_data_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
.S_AXI_WID (S_AXI_WID),
|
||||
.S_AXI_WDATA (S_AXI_WDATA),
|
||||
.S_AXI_WSTRB (S_AXI_WSTRB),
|
||||
.S_AXI_WLAST (S_AXI_WLAST),
|
||||
.S_AXI_WUSER (S_AXI_WUSER),
|
||||
.S_AXI_WVALID (S_AXI_WVALID),
|
||||
.S_AXI_WREADY (S_AXI_WREADY),
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
.M_AXI_WID (M_AXI_WID),
|
||||
.M_AXI_WDATA (M_AXI_WDATA),
|
||||
.M_AXI_WSTRB (M_AXI_WSTRB),
|
||||
.M_AXI_WLAST (M_AXI_WLAST),
|
||||
.M_AXI_WUSER (M_AXI_WUSER),
|
||||
.M_AXI_WVALID (M_AXI_WVALID),
|
||||
.M_AXI_WREADY (M_AXI_WREADY)
|
||||
);
|
||||
|
||||
// Write Response channel.
|
||||
processing_system7_v5_5_b_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_response_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
.S_AXI_BID (S_AXI_BID),
|
||||
.S_AXI_BRESP (S_AXI_BRESP),
|
||||
.S_AXI_BUSER (S_AXI_BUSER),
|
||||
.S_AXI_BVALID (S_AXI_BVALID),
|
||||
.S_AXI_BREADY (S_AXI_BREADY),
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
.M_AXI_BID (M_AXI_BID),
|
||||
.M_AXI_BRESP (M_AXI_BRESP),
|
||||
.M_AXI_BUSER (M_AXI_BUSER),
|
||||
.M_AXI_BVALID (M_AXI_BVALID),
|
||||
.M_AXI_BREADY (M_AXI_BREADY),
|
||||
|
||||
// Trigger detection
|
||||
.ERROR_TRIGGER (ERROR_TRIGGER),
|
||||
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
|
||||
);
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Read Channels (AR/R)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Read Address Port
|
||||
assign M_AXI_ARID = S_AXI_ARID;
|
||||
assign M_AXI_ARADDR = S_AXI_ARADDR;
|
||||
assign M_AXI_ARLEN = S_AXI_ARLEN;
|
||||
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
|
||||
assign M_AXI_ARBURST = S_AXI_ARBURST;
|
||||
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
|
||||
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
|
||||
assign M_AXI_ARPROT = S_AXI_ARPROT;
|
||||
assign M_AXI_ARUSER = S_AXI_ARUSER;
|
||||
assign M_AXI_ARVALID = S_AXI_ARVALID;
|
||||
assign S_AXI_ARREADY = M_AXI_ARREADY;
|
||||
|
||||
// Read Data Port
|
||||
assign S_AXI_RID = M_AXI_RID;
|
||||
assign S_AXI_RDATA = M_AXI_RDATA;
|
||||
assign S_AXI_RRESP = M_AXI_RRESP;
|
||||
assign S_AXI_RLAST = M_AXI_RLAST;
|
||||
assign S_AXI_RUSER = M_AXI_RUSER;
|
||||
assign S_AXI_RVALID = M_AXI_RVALID;
|
||||
assign M_AXI_RREADY = S_AXI_RREADY;
|
||||
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user