Matthias Biermann
61 lines
1.3 KiB
VHDL
61 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity spi2display_tb is
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end;
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architecture rtl of spi2display_tb is
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constant EXT_CLOCK_FREQ : integer := 125000000;
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constant SCK_FREQ : integer := 1000000;
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constant CPOL : std_logic := '0';
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constant CPHA : std_logic := '0';
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constant clk_half_period : time := 1 sec / EXT_CLOCK_FREQ / 2;
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal sck : std_logic;
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signal mosi : std_logic;
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signal ssel : std_logic;
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begin
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clk_proc: process (clk)
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begin
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clk <= not clk after clk_half_period;
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end process;
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stim: process
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begin
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reset <= '0' after 100 * clk_half_period;
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-- wait for 45 us;
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-- wait until rising_edge(clk);
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-- reset <= '1';
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-- wait for 1 us;
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-- wait until rising_edge(clk);
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-- reset <= '0';
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wait;
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end process;
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dut: entity work.spi2display
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generic map (
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-- CPOL => CPOL,
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-- CPHA => CPHA,
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CLOCK_FREQ => EXT_CLOCK_FREQ,
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SCK_FREQ => SCK_FREQ
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)
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port map (
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clk => clk,
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reset => reset,
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mosi => mosi,
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sck => sck,
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ssel => ssel
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);
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end;
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