Sebastian Meyer
82 lines
2.3 KiB
VHDL
82 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axis_audio_bitcrusher_tb is
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end;
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architecture rtl of axis_audio_bitcrusher_tb is
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constant EXT_CLOCK_FREQ : integer := 125000000;
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constant SCK_FREQ : integer := 1000000;
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constant has_last : boolean := true;
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constant bit_reduction : integer := 8;
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constant clk_half_period : time := 1 sec / EXT_CLOCK_FREQ / 2;
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signal axis_clk : std_logic := '0';
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signal axis_reset : std_logic := '1';
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signal s_axis_data : std_logic_vector(15 downto 0) := (others=>'0') ;
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signal s_axis_valid : std_logic := '0';
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signal s_axis_tlast : std_logic := '0';
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signal s_axis_ready : std_logic;
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signal m_axis_data : std_logic_vector(15 downto 0) := (others=>'0') ;
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signal m_axis_valid : std_logic;
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signal m_axis_tlast : std_logic;
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signal m_axis_ready : std_logic := '0';
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begin
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clk_proc: process (axis_clk)
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begin
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axis_clk <= not axis_clk after clk_half_period;
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end process;
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stim: process
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begin
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axis_reset <= '0' after 100 * clk_half_period;
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wait until axis_reset = '0';
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wait until rising_edge(axis_clk);
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s_axis_data <= x"1234";
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s_axis_valid <= '1';
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s_axis_tlast <= '1';
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loop
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wait until rising_edge(axis_clk);
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if s_axis_ready = '1' then
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s_axis_valid <= '0';
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s_axis_tlast <= '0';
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s_axis_data <= (others=>'0');
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elsif m_axis_valid = '1' and m_axis_tlast = '1' then
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exit;
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end if;
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end loop;
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wait;
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end process;
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dut: entity work.axis_audio_bitcrusher
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generic map (
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BIT_REDUCTION => bit_reduction,
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HAS_LAST => has_last
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)
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port map (
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AXIS_ACLK => axis_clk,
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AXIS_ARESETN => axis_reset,
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-- AXI Streaming Target Port
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S_AXIS_TVALID => s_axis_valid ,
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S_AXIS_TDATA => s_axis_data,
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S_AXIS_TLAST => s_axis_tlast,
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S_AXIS_TREADY => s_axis_ready,
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-- AXI Streaming Initiator Port
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M_AXIS_TVALID => m_axis_valid ,
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M_AXIS_TDATA => m_axis_data,
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M_AXIS_TLAST => m_axis_tlast,
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M_AXIS_TREADY => m_axis_ready
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);
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end architecture; |