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erster Durchlauf vom Bitcrsuher funktioniert

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This commit is contained in:
Sebastian Meyer
2024-10-24 21:25:37 +02:00
parent 0456ad3421
commit 3b9ef06996
3 changed files with 44 additions and 42 deletions
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Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.xpr
+11 -8
View File
@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="3"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -116,9 +116,16 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../axis_audio_bitcrusher_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axis_audio_bitcrusher"/>
<Option Name="TopModule" Val="axis_audio_bitcrusher_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
@@ -159,9 +166,7 @@
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -170,9 +175,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
Milestone2/axis_audio_bitcrusher.vhd
+12 -15
View File
@@ -1,10 +1,9 @@
library ieee;
use ieee.std_logic_1164.all
use ieee.numeric_std.all
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axis_audio_bitcrusher is
generic
(
generic(
BIT_REDUCTION : integer := 14;
HAS_LAST : boolean := false
);
@@ -28,8 +27,6 @@ entity axis_audio_bitcrusher is
end;
architecture rtl of axis_audio_bitcrusher is
begin
-- Steuersignale zwischen Steuerwerk und Rechenwerk
signal RegInputEn : std_logic := '0';
signal RegOutputEn : std_logic := '0';
@@ -46,7 +43,7 @@ begin
-- Register fuer die Inputdaten
RegInput: process
begin
wait until rising_edge(clk);
wait until rising_edge(AXIS_ACLK);
if RegInputEn = '1' then
caculatorInput <= S_AXIS_TDATA;
end if;
@@ -55,27 +52,27 @@ begin
-- Kombinatorik fuer Bitcrusherberechnung
Bitcrusher: process (caculatorInput)
begin
calculatorOutput <= caculatorInput(16 downto BIT_REDUCTION) & (others => '0'); -- Setze die Bits 0 bis (x-1) auf Null
caculatorOutput <= caculatorInput(15 downto BIT_REDUCTION + 1) & (BIT_REDUCTION downto 0 => '0');
end process;
-- Register fuer die Outputdaten
RegOutput: process
begin
wait until rising_edge(clk);
wait until rising_edge(AXIS_ACLK);
if RegOutputEn = '1' then
M_AXIS_TDATA <= caculatorOutput;
end if;
end process;
-- Prozesse fuer endlichen Automaten
Transition: process(state, reset, M_AXIS_TREADY, S_AXIS_TVALID, S_AXIS_TLAST)
Transition: process(state, AXIS_ARESETN, M_AXIS_TREADY, S_AXIS_TVALID, S_AXIS_TLAST)
begin
-- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
state_next <= S_ERROR;
-- Berechnung des Folgezustandes und der Mealy-Ausgaenge
case state is
when S_INPUT =>
if HAS_LAST = '1' then
if HAS_LAST = true then
if S_AXIS_TLAST = '1' then
safeTLast <= '1';
end if;
@@ -88,7 +85,7 @@ begin
when S_CALCULATE =>
state_next <= S_OUTPUT;
when S_OUTPUT =>
if HAS_LAST = '1' then
if HAS_LAST = true then
if safeTLast = '1' then
M_AXIS_TLAST <= '1';
end if;
@@ -99,7 +96,7 @@ begin
state_next <= S_OUTPUT;
end if;
when S_ERROR =>
if reset = '1' then
if AXIS_ARESETN = '1' then
state_next <= S_OUTPUT;
else
state_next <= S_ERROR;
@@ -110,7 +107,7 @@ begin
-- Register fuer Zustand und Ausgaenge
Reg: process
begin
wait until rising_edge(clk);
wait until rising_edge(AXIS_ACLK);
-- Zustandswechsel
state <= state_next;
-- Berechnung der Moore-Ausgaenge, die nur vom Zustand abhaengen
Milestone2/axis_audio_bitcrusher_tb.vhd
+21 -19
View File
@@ -10,7 +10,7 @@ architecture rtl of axis_audio_bitcrusher_tb is
constant EXT_CLOCK_FREQ : integer := 125000000;
constant SCK_FREQ : integer := 1000000;
constant has_last : boolean := true;
constant bit_reduction : integer := 14;
constant bit_reduction : integer := 8;
constant clk_half_period : time := 1 sec / EXT_CLOCK_FREQ / 2;
@@ -30,9 +30,9 @@ architecture rtl of axis_audio_bitcrusher_tb is
begin
clk_proc: process (clk)
clk_proc: process (axis_clk)
begin
clk <= not clk after clk_half_period;
axis_clk <= not axis_clk after clk_half_period;
end process;
stim: process
@@ -40,18 +40,18 @@ begin
axis_reset <= '0' after 100 * clk_half_period;
wait until axis_reset = '0';
wait until rising_edge(clk);
wait until rising_edge(axis_clk);
s_axis_data <= x"1234";
s_axis_valid <= '1';
s_axis_tlast <= '1';
loop
wait until rising_edge(clk);
wait until rising_edge(axis_clk);
if s_axis_ready = '1' then
s_axis_valid <= '0';
s_axis_tlast <= '0';
s_data <= (others=>'0');
if m_axis_valid and m_axis_tlast then
s_axis_data <= (others=>'0');
elsif m_axis_valid = '1' and m_axis_tlast = '1' then
exit;
end if;
end loop;
@@ -60,21 +60,23 @@ begin
end process;
dut: entity work.axis_audio_bitcrusher
dut: entity work.axis_audio_bitcrusher
generic map (
BIT_REDUCTION => bit_reduction;
HAS_LAST => has_last;
);
BIT_REDUCTION => bit_reduction,
HAS_LAST => has_last
)
port map (
AXIS_ACLK => axis_clk,
AXIS_ARESETN => axis_reset,
-- AXI Streaming Target Port
S_AXIS_TVALID => s_axis_data ;
S_AXIS_TDATA => s_axis_valid;
S_AXIS_TLAST => s_axis_tlast;
S_AXIS_TREADY => s_axis_ready;
S_AXIS_TVALID => s_axis_valid ,
S_AXIS_TDATA => s_axis_data,
S_AXIS_TLAST => s_axis_tlast,
S_AXIS_TREADY => s_axis_ready,
-- AXI Streaming Initiator Port
M_AXIS_TVALID => m_axis_data ;
M_AXIS_TDATA => m_axis_valid;
M_AXIS_TLAST => m_axis_tlast;
M_AXIS_TREADY => m_axis_ready;
M_AXIS_TVALID => m_axis_valid ,
M_AXIS_TDATA => m_axis_data,
M_AXIS_TLAST => m_axis_tlast,
M_AXIS_TREADY => m_axis_ready
);
end architecture;