AXI Schreiben
This commit is contained in:
Matthias Biermann
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axi_crc_dma_sim_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738469743"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738469743"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738469743"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738469743"/>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1739031653"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739031654"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1739031653"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739031654"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axi_crc_dma_sim_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 05:15:42 2025
|
||||
--Date : Sat Feb 8 17:20:53 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1_wrapper.bd
|
||||
--Design : axi_crc_dma_sim_1_wrapper
|
||||
|
||||
+1
-1
@@ -664,7 +664,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 02 02:02:02 UTC 2025</spirit:value>
|
||||
<spirit:value>Sat Feb 08 16:18:54 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+5
-5
@@ -581,7 +581,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:be22c7e7</spirit:value>
|
||||
<spirit:value>9:dc1943c5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -597,11 +597,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 02 02:12:31 UTC 2025</spirit:value>
|
||||
<spirit:value>Sat Feb 08 16:20:53 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:be22c7e7</spirit:value>
|
||||
<spirit:value>9:dc1943c5</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -983,7 +983,7 @@
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>REVISION_NO</spirit:name>
|
||||
<spirit:displayName>Revision No</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">8</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.REVISION_NO">20</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
@@ -1039,7 +1039,7 @@
|
||||
<spirit:parameter>
|
||||
<spirit:name>REVISION_NO</spirit:name>
|
||||
<spirit:displayName>Revision No</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">8</spirit:value>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REVISION_NO">20</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
|
||||
+1
-1
@@ -149,7 +149,7 @@ BEGIN
|
||||
STIM_FILENAME => "../../axi_crc_dma_sim.mem",
|
||||
HAS_FINISHED_OUT => false,
|
||||
HAS_INTERRUPT_IN => true,
|
||||
REVISION_NO => 8
|
||||
REVISION_NO => 20
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt_in => interrupt_in,
|
||||
|
||||
+1
-1
@@ -461,7 +461,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 02 04:07:29 UTC 2025</spirit:value>
|
||||
<spirit:value>Sat Feb 08 10:24:50 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
|
||||
+4
-1
@@ -1504,7 +1504,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Feb 02 04:15:43 UTC 2025</spirit:value>
|
||||
<spirit:value>Sat Feb 08 16:08:04 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -2331,6 +2331,9 @@
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 05:15:42 2025
|
||||
--Date : Sat Feb 8 17:20:53 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1.bd
|
||||
--Design : axi_crc_dma_sim_1
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Feb 2 05:15:42 2025
|
||||
--Date : Sat Feb 8 17:20:53 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_sim_1.bd
|
||||
--Design : axi_crc_dma_sim_1
|
||||
|
||||
+56
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="axi_crc_dma_syn_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739031745"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739031745"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739031745"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739031745"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\axi_crc_dma_syn_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axi_crc_dma_syn_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axi_crc_dma_syn_1_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\axi_crc_dma_syn_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="axi_crc_dma_syn_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\axi_crc_dma_syn_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\axi_crc_dma_syn_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
|
||||
|
||||
################################################################################
|
||||
+92
@@ -0,0 +1,92 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sat Feb 8 17:22:17 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target axi_crc_dma_syn_1_wrapper.bd
|
||||
--Design : axi_crc_dma_syn_1_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity axi_crc_dma_syn_1_wrapper is
|
||||
port (
|
||||
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_cas_n : inout STD_LOGIC;
|
||||
DDR_ck_n : inout STD_LOGIC;
|
||||
DDR_ck_p : inout STD_LOGIC;
|
||||
DDR_cke : inout STD_LOGIC;
|
||||
DDR_cs_n : inout STD_LOGIC;
|
||||
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_odt : inout STD_LOGIC;
|
||||
DDR_ras_n : inout STD_LOGIC;
|
||||
DDR_reset_n : inout STD_LOGIC;
|
||||
DDR_we_n : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrn : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrp : inout STD_LOGIC;
|
||||
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
FIXED_IO_ps_clk : inout STD_LOGIC;
|
||||
FIXED_IO_ps_porb : inout STD_LOGIC;
|
||||
FIXED_IO_ps_srstb : inout STD_LOGIC
|
||||
);
|
||||
end axi_crc_dma_syn_1_wrapper;
|
||||
|
||||
architecture STRUCTURE of axi_crc_dma_syn_1_wrapper is
|
||||
component axi_crc_dma_syn_1 is
|
||||
port (
|
||||
DDR_cas_n : inout STD_LOGIC;
|
||||
DDR_cke : inout STD_LOGIC;
|
||||
DDR_ck_n : inout STD_LOGIC;
|
||||
DDR_ck_p : inout STD_LOGIC;
|
||||
DDR_cs_n : inout STD_LOGIC;
|
||||
DDR_reset_n : inout STD_LOGIC;
|
||||
DDR_odt : inout STD_LOGIC;
|
||||
DDR_ras_n : inout STD_LOGIC;
|
||||
DDR_we_n : inout STD_LOGIC;
|
||||
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
FIXED_IO_ddr_vrn : inout STD_LOGIC;
|
||||
FIXED_IO_ddr_vrp : inout STD_LOGIC;
|
||||
FIXED_IO_ps_srstb : inout STD_LOGIC;
|
||||
FIXED_IO_ps_clk : inout STD_LOGIC;
|
||||
FIXED_IO_ps_porb : inout STD_LOGIC
|
||||
);
|
||||
end component axi_crc_dma_syn_1;
|
||||
begin
|
||||
axi_crc_dma_syn_1_i: component axi_crc_dma_syn_1
|
||||
port map (
|
||||
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
|
||||
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
|
||||
DDR_cas_n => DDR_cas_n,
|
||||
DDR_ck_n => DDR_ck_n,
|
||||
DDR_ck_p => DDR_ck_p,
|
||||
DDR_cke => DDR_cke,
|
||||
DDR_cs_n => DDR_cs_n,
|
||||
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
|
||||
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
|
||||
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
|
||||
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
|
||||
DDR_odt => DDR_odt,
|
||||
DDR_ras_n => DDR_ras_n,
|
||||
DDR_reset_n => DDR_reset_n,
|
||||
DDR_we_n => DDR_we_n,
|
||||
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
|
||||
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
|
||||
);
|
||||
end STRUCTURE;
|
||||
+4638
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
+12770
File diff suppressed because it is too large
Load Diff
+89
@@ -0,0 +1,89 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:14:23 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_auto_pc_0 -prefix
|
||||
// axi_crc_dma_syn_1_auto_pc_0_ axi_crc_dma_syn_1_auto_pc_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */
|
||||
/* synthesis syn_force_seq_prim="aclk" */;
|
||||
input aclk /* synthesis syn_isclock = 1 */;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+573
@@ -0,0 +1,573 @@
|
||||
#ifndef IP_AXI_CRC_DMA_SYN_1_AUTO_PC_0_H_
|
||||
#define IP_AXI_CRC_DMA_SYN_1_AUTO_PC_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "axi_crc_dma_syn_1_auto_pc_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport axi_crc_dma_syn_1_auto_pc_0 : public axi_crc_dma_syn_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport axi_crc_dma_syn_1_auto_pc_0 : public axi_crc_dma_syn_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport axi_crc_dma_syn_1_auto_pc_0 : public axi_crc_dma_syn_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport axi_crc_dma_syn_1_auto_pc_0 : public axi_crc_dma_syn_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport axi_crc_dma_syn_1_auto_pc_0 : public axi_crc_dma_syn_1_auto_pc_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_auto_pc_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > aclk;
|
||||
sc_core::sc_in< bool > aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_wid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
|
||||
sc_core::sc_out< bool > m_axi_awvalid;
|
||||
sc_core::sc_in< bool > m_axi_awready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
|
||||
sc_core::sc_out< bool > m_axi_wvalid;
|
||||
sc_core::sc_in< bool > m_axi_wready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
|
||||
sc_core::sc_in< bool > m_axi_bvalid;
|
||||
sc_core::sc_out< bool > m_axi_bready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
|
||||
sc_core::sc_out< bool > m_axi_arvalid;
|
||||
sc_core::sc_in< bool > m_axi_arready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
|
||||
sc_core::sc_in< bool > m_axi_rvalid;
|
||||
sc_core::sc_out< bool > m_axi_rready;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,12,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_awlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_awlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_awlock_converter;
|
||||
sc_signal< bool > m_s_axi_awlock_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_s_axi_arlen_converter;
|
||||
sc_signal< sc_bv<8> > m_s_axi_arlen_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_s_axi_arlock_converter;
|
||||
sc_signal< bool > m_s_axi_arlock_converter_signal;
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_AXI_CRC_DMA_SYN_1_AUTO_PC_0_H_
|
||||
+354
@@ -0,0 +1,354 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module axi_crc_dma_syn_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
|
||||
HREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
|
||||
_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_28_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_AXI_CRC_DMA_SYN_1_AUTO_PC_0_SC_H_
|
||||
#define IP_AXI_CRC_DMA_SYN_1_AUTO_PC_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_protocol_converter;
|
||||
|
||||
class DllExport axi_crc_dma_syn_1_auto_pc_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_auto_pc_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_protocol_converter* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
axi_crc_dma_syn_1_auto_pc_0_sc(const axi_crc_dma_syn_1_auto_pc_0_sc&);
|
||||
const axi_crc_dma_syn_1_auto_pc_0_sc& operator=(const axi_crc_dma_syn_1_auto_pc_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_AXI_CRC_DMA_SYN_1_AUTO_PC_0_SC_H_
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: axi_crc_dma_syn_1_auto_pc_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module axi_crc_dma_syn_1_auto_pc_0 (
|
||||
input bit_as_bool aclk,
|
||||
input bit_as_bool aresetn,
|
||||
input bit [11 : 0] s_axi_awid,
|
||||
input bit [31 : 0] s_axi_awaddr,
|
||||
input bit [3 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit [1 : 0] s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit [3 : 0] s_axi_awqos,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [11 : 0] s_axi_wid,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [11 : 0] s_axi_bid,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [11 : 0] s_axi_arid,
|
||||
input bit [31 : 0] s_axi_araddr,
|
||||
input bit [3 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit [1 : 0] s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit [3 : 0] s_axi_arqos,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [11 : 0] s_axi_rid,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit [31 : 0] m_axi_awaddr,
|
||||
output bit [2 : 0] m_axi_awprot,
|
||||
output bit_as_bool m_axi_awvalid,
|
||||
input bit_as_bool m_axi_awready,
|
||||
output bit [31 : 0] m_axi_wdata,
|
||||
output bit [3 : 0] m_axi_wstrb,
|
||||
output bit_as_bool m_axi_wvalid,
|
||||
input bit_as_bool m_axi_wready,
|
||||
input bit [1 : 0] m_axi_bresp,
|
||||
input bit_as_bool m_axi_bvalid,
|
||||
output bit_as_bool m_axi_bready,
|
||||
output bit [31 : 0] m_axi_araddr,
|
||||
output bit [2 : 0] m_axi_arprot,
|
||||
output bit_as_bool m_axi_arvalid,
|
||||
input bit_as_bool m_axi_arready,
|
||||
input bit [31 : 0] m_axi_rdata,
|
||||
input bit [1 : 0] m_axi_rresp,
|
||||
input bit_as_bool m_axi_rvalid,
|
||||
output bit_as_bool m_axi_rready
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module axi_crc_dma_syn_1_auto_pc_0 (aclk,aresetn,s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awvalid,s_axi_awready,s_axi_wid,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arvalid,s_axi_arready,s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr,m_axi_awprot,m_axi_awvalid,m_axi_awready,m_axi_wdata,m_axi_wstrb,m_axi_wvalid,m_axi_wready,m_axi_bresp,m_axi_bvalid,m_axi_bready,m_axi_araddr,m_axi_arprot,m_axi_arvalid,m_axi_arready,m_axi_rdata,m_axi_rresp,m_axi_rvalid,m_axi_rready)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit aclk;
|
||||
input bit aresetn;
|
||||
input bit [11 : 0] s_axi_awid;
|
||||
input bit [31 : 0] s_axi_awaddr;
|
||||
input bit [3 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit [1 : 0] s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit [3 : 0] s_axi_awqos;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [11 : 0] s_axi_wid;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [11 : 0] s_axi_arid;
|
||||
input bit [31 : 0] s_axi_araddr;
|
||||
input bit [3 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit [1 : 0] s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit [3 : 0] s_axi_arqos;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
output wire m_axi_awvalid;
|
||||
input bit m_axi_awready;
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
output wire m_axi_wvalid;
|
||||
input bit m_axi_wready;
|
||||
input bit [1 : 0] m_axi_bresp;
|
||||
input bit m_axi_bvalid;
|
||||
output wire m_axi_bready;
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
output wire m_axi_arvalid;
|
||||
input bit m_axi_arready;
|
||||
input bit [31 : 0] m_axi_rdata;
|
||||
input bit [1 : 0] m_axi_rresp;
|
||||
input bit m_axi_rvalid;
|
||||
output wire m_axi_rready;
|
||||
endmodule
|
||||
`endif
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
#ifndef _axi_protocol_converter_
|
||||
#define _axi_protocol_converter_
|
||||
#include <xtlm.h>
|
||||
#include <utils/xtlm_aximm_passthru_module.h>
|
||||
#include <systemc>
|
||||
|
||||
class axi_protocol_converter:public sc_module{
|
||||
public:
|
||||
axi_protocol_converter(sc_core::sc_module_name module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_protocol_converter();
|
||||
SC_HAS_PROCESS(axi_protocol_converter);
|
||||
xtlm::xtlm_aximm_target_socket* target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* initiator_wr_socket;
|
||||
sc_in<bool> aclk;
|
||||
sc_in<bool> aresetn;
|
||||
private:
|
||||
xtlm::xtlm_aximm_passthru_module *P1;
|
||||
xtlm::xtlm_aximm_passthru_module *P2;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
+356
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 28
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_28_axi_protocol_converter,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "axi_crc_dma_syn_1_auto_pc_0,axi_protocol_converter_v2_1_28_axi_protocol_converter,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=28,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
|
||||
_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module axi_crc_dma_syn_1_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
|
||||
HREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ\
|
||||
_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_28_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+1644
File diff suppressed because it is too large
Load Diff
+1644
File diff suppressed because it is too large
Load Diff
+830
@@ -0,0 +1,830 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>RESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">RESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3206ef0f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_crc</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d5f8737e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Feb 08 13:29:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d5f8737e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d5f8737e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axi_crc_dma_syn_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Feb 07 15:16:13 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3206ef0f</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>axi_crc_dma_syn_1_axis_crc_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Feb 07 15:16:13 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d5f8737e</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>RESETN</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>initial_value</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>polynomial</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
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|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
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|
||||
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||||
</spirit:wireTypeDefs>
|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
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|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
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<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
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<spirit:name>axi_crc_dma_syn_1_axis_crc_0_0_stub.vhdl</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
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<spirit:file>
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||||
<spirit:name>sim/axi_crc_dma_syn_1_axis_crc_0_0.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/axi_crc_dma_syn_1_axis_crc_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
|
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</spirit:fileSet>
|
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</spirit:fileSets>
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<spirit:description>xilinx.com:module_ref:axis_crc:1.0</spirit:description>
|
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<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_crc_dma_syn_1_axis_crc_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_crc_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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</xilinx:configElementInfos>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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||||
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+6956
File diff suppressed because it is too large
Load Diff
+35
@@ -0,0 +1,35 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:17:41 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_axis_crc_0_0 -prefix
|
||||
// axi_crc_dma_syn_1_axis_crc_0_0_ axi_crc_dma_syn_1_axis_crc_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_axis_crc_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_crc,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_axis_crc_0_0(CLK, RESETN, initial_value, polynomial,
|
||||
S_AXIS_TVALID, S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA,
|
||||
M_AXIS_TLAST, M_AXIS_TREADY)
|
||||
/* synthesis syn_black_box black_box_pad_pin="RESETN,initial_value[31:0],polynomial[31:0],S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY" */
|
||||
/* synthesis syn_force_seq_prim="CLK" */;
|
||||
input CLK /* synthesis syn_isclock = 1 */;
|
||||
input RESETN;
|
||||
input [31:0]initial_value;
|
||||
input [31:0]polynomial;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
endmodule
|
||||
+8
-8
@@ -53,7 +53,7 @@ LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axis_crc_sim_1_axis_crc_0_0 IS
|
||||
ENTITY axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
@@ -68,11 +68,11 @@ ENTITY axis_crc_sim_1_axis_crc_0_0 IS
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axis_crc_sim_1_axis_crc_0_0;
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0;
|
||||
|
||||
ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axis_crc_sim_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
@@ -91,19 +91,19 @@ ARCHITECTURE axis_crc_sim_1_axis_crc_0_0_arch OF axis_crc_sim_1_axis_crc_0_0 IS
|
||||
END COMPONENT axis_crc;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_crc
|
||||
@@ -121,4 +121,4 @@ BEGIN
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axis_crc_sim_1_axis_crc_0_0_arch;
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0_arch;
|
||||
+132
@@ -0,0 +1,132 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_crc:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_crc_0_0_arch OF axi_crc_dma_syn_1_axis_crc_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_crc IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
initial_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_crc;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "axis_crc,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_crc_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_axis_crc_0_0,axis_crc,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_crc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axis_crc_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_crc
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_crc_0_0_arch;
|
||||
+2851
File diff suppressed because it is too large
Load Diff
+359
@@ -0,0 +1,359 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_dma_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_dma_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_dma_0_0_arch OF axi_crc_dma_syn_1_axis_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_dma IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_dma;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH" &
|
||||
"READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ" &
|
||||
"_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_dma
|
||||
GENERIC MAP (
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
FIFO_AWIDTH => 8,
|
||||
polynomial_default => X"04C11DB7",
|
||||
initial_value_default => X"00000000"
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
INTERRUPT => INTERRUPT,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
FIFO_NUM_FREE => FIFO_NUM_FREE,
|
||||
FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_dma_0_0_arch;
|
||||
+367
@@ -0,0 +1,367 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_dma:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_dma_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_dma_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_dma_0_0_arch OF axi_crc_dma_syn_1_axis_dma_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_dma IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
polynomial_default : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
initial_value_default : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
INTERRUPT : OUT STD_LOGIC;
|
||||
initial_value : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
polynomial : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
FIFO_NUM_FREE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
FIFO_NUM_AVAIL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_dma;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "axis_dma,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_dma_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_dma_0_0,axis_dma,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_axis_dma_0_0,axis_dma,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_dma,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,FIFO_AWIDTH=8,polynomial_default=0x04C11DB7,initial_value_default=0x00000000}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF axi_crc_dma_syn_1_axis_dma_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS:M_AXI:S_AXIL, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF INTERRUPT: SIGNAL IS "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, PORTWIDTH 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF INTERRUPT: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_TH" &
|
||||
"READS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, NUM_READ" &
|
||||
"_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_dma
|
||||
GENERIC MAP (
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
FIFO_AWIDTH => 8,
|
||||
polynomial_default => X"04C11DB7",
|
||||
initial_value_default => X"00000000"
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
INTERRUPT => INTERRUPT,
|
||||
initial_value => initial_value,
|
||||
polynomial => polynomial,
|
||||
FIFO_NUM_FREE => FIFO_NUM_FREE,
|
||||
FIFO_NUM_AVAIL => FIFO_NUM_AVAIL,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_dma_0_0_arch;
|
||||
+2150
File diff suppressed because it is too large
Load Diff
+2134
File diff suppressed because it is too large
Load Diff
+41
@@ -0,0 +1,41 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:13:59 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_axis_fifo_0_0 -prefix
|
||||
// axi_crc_dma_syn_1_axis_fifo_0_0_ axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_fifo,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_axis_fifo_0_0(S_AXIS_ACLK, S_AXIS_ARESETN, S_AXIS_TVALID,
|
||||
S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, S_AXIS_TUSER, S_NUM_FREE, M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY, M_AXIS_TUSER,
|
||||
M_NUM_AVAIL)
|
||||
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_ARESETN,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,S_AXIS_TUSER[0:0],S_NUM_FREE[7:0],M_AXIS_ARESETN,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY,M_AXIS_TUSER[0:0],M_NUM_AVAIL[7:0]" */
|
||||
/* synthesis syn_force_seq_prim="S_AXIS_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="M_AXIS_ACLK" */;
|
||||
input S_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXIS_ARESETN;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
input [0:0]S_AXIS_TUSER;
|
||||
output [7:0]S_NUM_FREE;
|
||||
input M_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input M_AXIS_ARESETN;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
output [0:0]M_AXIS_TUSER;
|
||||
output [7:0]M_NUM_AVAIL;
|
||||
endmodule
|
||||
+186
@@ -0,0 +1,186 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axis_fifo:1.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_fifo_0_0 IS
|
||||
PORT (
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_fifo_0_0_arch OF axi_crc_dma_syn_1_axis_fifo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_fifo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_fifo IS
|
||||
GENERIC (
|
||||
FIFO_HAS_AXIL_IF : BOOLEAN;
|
||||
FIFO_USE_BLOCKRAM : BOOLEAN;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
FIFO_DWIDTH : INTEGER;
|
||||
FIFO_TUSERWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
S_AXI_ACLK : IN STD_LOGIC;
|
||||
S_AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_fifo;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_fifo
|
||||
GENERIC MAP (
|
||||
FIFO_HAS_AXIL_IF => false,
|
||||
FIFO_USE_BLOCKRAM => true,
|
||||
FIFO_AWIDTH => 8,
|
||||
FIFO_DWIDTH => 32,
|
||||
FIFO_TUSERWIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
S_AXI_ACLK => '0',
|
||||
S_AXI_ARESETN => '0',
|
||||
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_AWVALID => '0',
|
||||
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_WVALID => '0',
|
||||
S_AXI_BREADY => '0',
|
||||
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_ARVALID => '0',
|
||||
S_AXI_RREADY => '0',
|
||||
S_AXIS_ACLK => S_AXIS_ACLK,
|
||||
S_AXIS_ARESETN => S_AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
S_NUM_FREE => S_NUM_FREE,
|
||||
M_AXIS_ACLK => M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN => M_AXIS_ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
M_NUM_AVAIL => M_NUM_AVAIL
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_0_0_arch;
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axis_fifo:1.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_fifo_0_0 IS
|
||||
PORT (
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_0_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_fifo_0_0_arch OF axi_crc_dma_syn_1_axis_fifo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_fifo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_fifo IS
|
||||
GENERIC (
|
||||
FIFO_HAS_AXIL_IF : BOOLEAN;
|
||||
FIFO_USE_BLOCKRAM : BOOLEAN;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
FIFO_DWIDTH : INTEGER;
|
||||
FIFO_TUSERWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
S_AXI_ACLK : IN STD_LOGIC;
|
||||
S_AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_fifo;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_fifo_0_0_arch: ARCHITECTURE IS "axis_fifo,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_fifo_0_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_fifo_0_0,axis_fifo,{}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_fifo
|
||||
GENERIC MAP (
|
||||
FIFO_HAS_AXIL_IF => false,
|
||||
FIFO_USE_BLOCKRAM => true,
|
||||
FIFO_AWIDTH => 8,
|
||||
FIFO_DWIDTH => 32,
|
||||
FIFO_TUSERWIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
S_AXI_ACLK => '0',
|
||||
S_AXI_ARESETN => '0',
|
||||
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_AWVALID => '0',
|
||||
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_WVALID => '0',
|
||||
S_AXI_BREADY => '0',
|
||||
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_ARVALID => '0',
|
||||
S_AXI_RREADY => '0',
|
||||
S_AXIS_ACLK => S_AXIS_ACLK,
|
||||
S_AXIS_ARESETN => S_AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
S_NUM_FREE => S_NUM_FREE,
|
||||
M_AXIS_ACLK => M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN => M_AXIS_ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
M_NUM_AVAIL => M_NUM_AVAIL
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_0_0_arch;
|
||||
+2150
File diff suppressed because it is too large
Load Diff
+2134
File diff suppressed because it is too large
Load Diff
+41
@@ -0,0 +1,41 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:13:59 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_axis_fifo_1_0 -prefix
|
||||
// axi_crc_dma_syn_1_axis_fifo_1_0_ axi_crc_dma_syn_1_axis_fifo_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_axis_fifo_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axis_fifo,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_axis_fifo_1_0(S_AXIS_ACLK, S_AXIS_ARESETN, S_AXIS_TVALID,
|
||||
S_AXIS_TDATA, S_AXIS_TLAST, S_AXIS_TREADY, S_AXIS_TUSER, S_NUM_FREE, M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY, M_AXIS_TUSER,
|
||||
M_NUM_AVAIL)
|
||||
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_ARESETN,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TLAST,S_AXIS_TREADY,S_AXIS_TUSER[0:0],S_NUM_FREE[7:0],M_AXIS_ARESETN,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TLAST,M_AXIS_TREADY,M_AXIS_TUSER[0:0],M_NUM_AVAIL[7:0]" */
|
||||
/* synthesis syn_force_seq_prim="S_AXIS_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="M_AXIS_ACLK" */;
|
||||
input S_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXIS_ARESETN;
|
||||
input S_AXIS_TVALID;
|
||||
input [31:0]S_AXIS_TDATA;
|
||||
input S_AXIS_TLAST;
|
||||
output S_AXIS_TREADY;
|
||||
input [0:0]S_AXIS_TUSER;
|
||||
output [7:0]S_NUM_FREE;
|
||||
input M_AXIS_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input M_AXIS_ARESETN;
|
||||
output M_AXIS_TVALID;
|
||||
output [31:0]M_AXIS_TDATA;
|
||||
output M_AXIS_TLAST;
|
||||
input M_AXIS_TREADY;
|
||||
output [0:0]M_AXIS_TUSER;
|
||||
output [7:0]M_NUM_AVAIL;
|
||||
endmodule
|
||||
+186
@@ -0,0 +1,186 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axis_fifo:1.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_fifo_1_0 IS
|
||||
PORT (
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_1_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_fifo_1_0_arch OF axi_crc_dma_syn_1_axis_fifo_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_fifo_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_fifo IS
|
||||
GENERIC (
|
||||
FIFO_HAS_AXIL_IF : BOOLEAN;
|
||||
FIFO_USE_BLOCKRAM : BOOLEAN;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
FIFO_DWIDTH : INTEGER;
|
||||
FIFO_TUSERWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
S_AXI_ACLK : IN STD_LOGIC;
|
||||
S_AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_fifo;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_fifo
|
||||
GENERIC MAP (
|
||||
FIFO_HAS_AXIL_IF => false,
|
||||
FIFO_USE_BLOCKRAM => true,
|
||||
FIFO_AWIDTH => 8,
|
||||
FIFO_DWIDTH => 32,
|
||||
FIFO_TUSERWIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
S_AXI_ACLK => '0',
|
||||
S_AXI_ARESETN => '0',
|
||||
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_AWVALID => '0',
|
||||
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_WVALID => '0',
|
||||
S_AXI_BREADY => '0',
|
||||
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_ARVALID => '0',
|
||||
S_AXI_RREADY => '0',
|
||||
S_AXIS_ACLK => S_AXIS_ACLK,
|
||||
S_AXIS_ARESETN => S_AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
S_NUM_FREE => S_NUM_FREE,
|
||||
M_AXIS_ACLK => M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN => M_AXIS_ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
M_NUM_AVAIL => M_NUM_AVAIL
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_1_0_arch;
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: Gehrke:user:axis_fifo:1.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_axis_fifo_1_0 IS
|
||||
PORT (
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_1_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_axis_fifo_1_0_arch OF axi_crc_dma_syn_1_axis_fifo_1_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_axis_fifo_1_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_fifo IS
|
||||
GENERIC (
|
||||
FIFO_HAS_AXIL_IF : BOOLEAN;
|
||||
FIFO_USE_BLOCKRAM : BOOLEAN;
|
||||
FIFO_AWIDTH : INTEGER;
|
||||
FIFO_DWIDTH : INTEGER;
|
||||
FIFO_TUSERWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
S_AXI_ACLK : IN STD_LOGIC;
|
||||
S_AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
S_AXIS_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_NUM_FREE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC;
|
||||
M_AXIS_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_NUM_AVAIL : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axis_fifo;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_axis_fifo_1_0_arch: ARCHITECTURE IS "axis_fifo,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_axis_fifo_1_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_axis_fifo_1_0,axis_fifo,{}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_clock, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET M_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_clock, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET S_AXIS_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_signal_clock CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_ARESETN: SIGNAL IS "XIL_INTERFACENAME S_AXIS_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXIS_signal_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_fifo
|
||||
GENERIC MAP (
|
||||
FIFO_HAS_AXIL_IF => false,
|
||||
FIFO_USE_BLOCKRAM => true,
|
||||
FIFO_AWIDTH => 8,
|
||||
FIFO_DWIDTH => 32,
|
||||
FIFO_TUSERWIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
S_AXI_ACLK => '0',
|
||||
S_AXI_ARESETN => '0',
|
||||
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_AWVALID => '0',
|
||||
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
S_AXI_WVALID => '0',
|
||||
S_AXI_BREADY => '0',
|
||||
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
S_AXI_ARVALID => '0',
|
||||
S_AXI_RREADY => '0',
|
||||
S_AXIS_ACLK => S_AXIS_ACLK,
|
||||
S_AXIS_ARESETN => S_AXIS_ARESETN,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
S_AXIS_TUSER => S_AXIS_TUSER,
|
||||
S_NUM_FREE => S_NUM_FREE,
|
||||
M_AXIS_ACLK => M_AXIS_ACLK,
|
||||
M_AXIS_ARESETN => M_AXIS_ARESETN,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY,
|
||||
M_AXIS_TUSER => M_AXIS_TUSER,
|
||||
M_NUM_AVAIL => M_NUM_AVAIL
|
||||
);
|
||||
END axi_crc_dma_syn_1_axis_fifo_1_0_arch;
|
||||
+710
@@ -0,0 +1,710 @@
|
||||
############################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2006 www.xilinx.com
|
||||
############################################################################
|
||||
## File name : ps7_constraints.xdc
|
||||
##
|
||||
## Details : Constraints file
|
||||
## FPGA family: zynq
|
||||
## FPGA: xc7z020clg400-1
|
||||
## Device Size: xc7z020
|
||||
## Package: clg400
|
||||
## Speedgrade: -1
|
||||
##
|
||||
##
|
||||
############################################################################
|
||||
############################################################################
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
create_clock -name clk_fpga_0 -period "10" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_2 -period "5" [get_pins "PS7_i/FCLKCLK[2]"]
|
||||
set_input_jitter clk_fpga_2 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_1 -period "8" [get_pins "PS7_i/FCLKCLK[1]"]
|
||||
set_input_jitter clk_fpga_1 0.24
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_3 -period "14.999" [get_pins "PS7_i/FCLKCLK[3]"]
|
||||
set_input_jitter clk_fpga_3 0.44997
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
|
||||
############################################################################
|
||||
# I/O STANDARDS and Location Constraints #
|
||||
############################################################################
|
||||
|
||||
# Enet 0 / mdio / MIO[53]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
|
||||
set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
|
||||
set_property slew "slow" [get_ports "MIO[53]"]
|
||||
set_property drive "8" [get_ports "MIO[53]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[53]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
|
||||
# Enet 0 / mdc / MIO[52]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
|
||||
set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
|
||||
set_property slew "slow" [get_ports "MIO[52]"]
|
||||
set_property drive "8" [get_ports "MIO[52]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[52]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
|
||||
# GPIO / gpio[51] / MIO[51]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
|
||||
set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
|
||||
set_property slew "slow" [get_ports "MIO[51]"]
|
||||
set_property drive "8" [get_ports "MIO[51]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[51]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
|
||||
# GPIO / gpio[50] / MIO[50]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
|
||||
set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
|
||||
set_property slew "slow" [get_ports "MIO[50]"]
|
||||
set_property drive "8" [get_ports "MIO[50]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[50]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
|
||||
# UART 1 / rx / MIO[49]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
|
||||
set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
|
||||
set_property slew "slow" [get_ports "MIO[49]"]
|
||||
set_property drive "8" [get_ports "MIO[49]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[49]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
|
||||
# UART 1 / tx / MIO[48]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
|
||||
set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
|
||||
set_property slew "slow" [get_ports "MIO[48]"]
|
||||
set_property drive "8" [get_ports "MIO[48]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[48]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
|
||||
# SD 0 / cd / MIO[47]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
|
||||
set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
|
||||
set_property slew "slow" [get_ports "MIO[47]"]
|
||||
set_property drive "8" [get_ports "MIO[47]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[47]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
|
||||
# USB Reset / reset / MIO[46]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
|
||||
set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
|
||||
set_property slew "slow" [get_ports "MIO[46]"]
|
||||
set_property drive "8" [get_ports "MIO[46]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[46]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[46]"]
|
||||
# SD 0 / data[3] / MIO[45]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
|
||||
set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
|
||||
set_property slew "slow" [get_ports "MIO[45]"]
|
||||
set_property drive "8" [get_ports "MIO[45]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[45]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
|
||||
# SD 0 / data[2] / MIO[44]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
|
||||
set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
|
||||
set_property slew "slow" [get_ports "MIO[44]"]
|
||||
set_property drive "8" [get_ports "MIO[44]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[44]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
|
||||
# SD 0 / data[1] / MIO[43]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
|
||||
set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
|
||||
set_property slew "slow" [get_ports "MIO[43]"]
|
||||
set_property drive "8" [get_ports "MIO[43]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[43]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
|
||||
# SD 0 / data[0] / MIO[42]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
|
||||
set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
|
||||
set_property slew "slow" [get_ports "MIO[42]"]
|
||||
set_property drive "8" [get_ports "MIO[42]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[42]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
|
||||
# SD 0 / cmd / MIO[41]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
|
||||
set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
|
||||
set_property slew "slow" [get_ports "MIO[41]"]
|
||||
set_property drive "8" [get_ports "MIO[41]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[41]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
|
||||
# SD 0 / clk / MIO[40]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
|
||||
set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
|
||||
set_property slew "slow" [get_ports "MIO[40]"]
|
||||
set_property drive "8" [get_ports "MIO[40]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[40]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
|
||||
# USB 0 / data[7] / MIO[39]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
|
||||
set_property slew "fast" [get_ports "MIO[39]"]
|
||||
set_property drive "8" [get_ports "MIO[39]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[39]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
|
||||
# USB 0 / data[6] / MIO[38]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
|
||||
set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
|
||||
set_property slew "fast" [get_ports "MIO[38]"]
|
||||
set_property drive "8" [get_ports "MIO[38]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[38]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
|
||||
# USB 0 / data[5] / MIO[37]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
|
||||
set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
|
||||
set_property slew "fast" [get_ports "MIO[37]"]
|
||||
set_property drive "8" [get_ports "MIO[37]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[37]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
|
||||
# USB 0 / clk / MIO[36]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
|
||||
set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
|
||||
set_property slew "fast" [get_ports "MIO[36]"]
|
||||
set_property drive "8" [get_ports "MIO[36]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[36]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
|
||||
# USB 0 / data[3] / MIO[35]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
|
||||
set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
|
||||
set_property slew "fast" [get_ports "MIO[35]"]
|
||||
set_property drive "8" [get_ports "MIO[35]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[35]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
|
||||
# USB 0 / data[2] / MIO[34]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
|
||||
set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
|
||||
set_property slew "fast" [get_ports "MIO[34]"]
|
||||
set_property drive "8" [get_ports "MIO[34]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[34]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
|
||||
# USB 0 / data[1] / MIO[33]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
|
||||
set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
|
||||
set_property slew "fast" [get_ports "MIO[33]"]
|
||||
set_property drive "8" [get_ports "MIO[33]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[33]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
|
||||
# USB 0 / data[0] / MIO[32]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
|
||||
set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
|
||||
set_property slew "fast" [get_ports "MIO[32]"]
|
||||
set_property drive "8" [get_ports "MIO[32]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[32]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
|
||||
# USB 0 / nxt / MIO[31]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
|
||||
set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
|
||||
set_property slew "fast" [get_ports "MIO[31]"]
|
||||
set_property drive "8" [get_ports "MIO[31]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[31]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
|
||||
# USB 0 / stp / MIO[30]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
|
||||
set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
|
||||
set_property slew "fast" [get_ports "MIO[30]"]
|
||||
set_property drive "8" [get_ports "MIO[30]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[30]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
|
||||
# USB 0 / dir / MIO[29]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
|
||||
set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
|
||||
set_property slew "fast" [get_ports "MIO[29]"]
|
||||
set_property drive "8" [get_ports "MIO[29]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[29]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
|
||||
# USB 0 / data[4] / MIO[28]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
|
||||
set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
|
||||
set_property slew "fast" [get_ports "MIO[28]"]
|
||||
set_property drive "8" [get_ports "MIO[28]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
|
||||
# Enet 0 / rx_ctl / MIO[27]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
|
||||
set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
|
||||
set_property slew "fast" [get_ports "MIO[27]"]
|
||||
set_property drive "8" [get_ports "MIO[27]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[27]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
|
||||
# Enet 0 / rxd[3] / MIO[26]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
|
||||
set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
|
||||
set_property slew "fast" [get_ports "MIO[26]"]
|
||||
set_property drive "8" [get_ports "MIO[26]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[26]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
|
||||
# Enet 0 / rxd[2] / MIO[25]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
|
||||
set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
|
||||
set_property slew "fast" [get_ports "MIO[25]"]
|
||||
set_property drive "8" [get_ports "MIO[25]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[25]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
|
||||
# Enet 0 / rxd[1] / MIO[24]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
|
||||
set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
|
||||
set_property slew "fast" [get_ports "MIO[24]"]
|
||||
set_property drive "8" [get_ports "MIO[24]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[24]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
|
||||
# Enet 0 / rxd[0] / MIO[23]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
|
||||
set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
|
||||
set_property slew "fast" [get_ports "MIO[23]"]
|
||||
set_property drive "8" [get_ports "MIO[23]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[23]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
|
||||
# Enet 0 / rx_clk / MIO[22]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
|
||||
set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
|
||||
set_property slew "fast" [get_ports "MIO[22]"]
|
||||
set_property drive "8" [get_ports "MIO[22]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[22]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
|
||||
# Enet 0 / tx_ctl / MIO[21]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
|
||||
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
|
||||
set_property slew "fast" [get_ports "MIO[21]"]
|
||||
set_property drive "8" [get_ports "MIO[21]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[21]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
|
||||
# Enet 0 / txd[3] / MIO[20]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
|
||||
set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
|
||||
set_property slew "fast" [get_ports "MIO[20]"]
|
||||
set_property drive "8" [get_ports "MIO[20]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[20]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
|
||||
# Enet 0 / txd[2] / MIO[19]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
|
||||
set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
|
||||
set_property slew "fast" [get_ports "MIO[19]"]
|
||||
set_property drive "8" [get_ports "MIO[19]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[19]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
|
||||
# Enet 0 / txd[1] / MIO[18]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
|
||||
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
|
||||
set_property slew "fast" [get_ports "MIO[18]"]
|
||||
set_property drive "8" [get_ports "MIO[18]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[18]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
|
||||
# Enet 0 / txd[0] / MIO[17]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
|
||||
set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
|
||||
set_property slew "fast" [get_ports "MIO[17]"]
|
||||
set_property drive "8" [get_ports "MIO[17]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[17]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
|
||||
# Enet 0 / tx_clk / MIO[16]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
|
||||
set_property slew "fast" [get_ports "MIO[16]"]
|
||||
set_property drive "8" [get_ports "MIO[16]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[16]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
|
||||
# I2C 0 / sda / MIO[15]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
|
||||
set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
|
||||
set_property slew "slow" [get_ports "MIO[15]"]
|
||||
set_property drive "8" [get_ports "MIO[15]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
|
||||
# I2C 0 / scl / MIO[14]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
|
||||
set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
|
||||
set_property slew "slow" [get_ports "MIO[14]"]
|
||||
set_property drive "8" [get_ports "MIO[14]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
|
||||
# I2C 1 / sda / MIO[13]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
|
||||
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
|
||||
set_property slew "slow" [get_ports "MIO[13]"]
|
||||
set_property drive "8" [get_ports "MIO[13]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
|
||||
# I2C 1 / scl / MIO[12]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
|
||||
set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
|
||||
set_property slew "slow" [get_ports "MIO[12]"]
|
||||
set_property drive "8" [get_ports "MIO[12]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
|
||||
# UART 0 / tx / MIO[11]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
|
||||
set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
|
||||
set_property slew "slow" [get_ports "MIO[11]"]
|
||||
set_property drive "8" [get_ports "MIO[11]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[11]"]
|
||||
# UART 0 / rx / MIO[10]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
|
||||
set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
|
||||
set_property slew "slow" [get_ports "MIO[10]"]
|
||||
set_property drive "8" [get_ports "MIO[10]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[10]"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[10]"]
|
||||
# GPIO / gpio[9] / MIO[9]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
|
||||
set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
|
||||
set_property slew "slow" [get_ports "MIO[9]"]
|
||||
set_property drive "8" [get_ports "MIO[9]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
|
||||
# Quad SPI Flash / qspi_fbclk / MIO[8]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
|
||||
set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
|
||||
set_property slew "slow" [get_ports "MIO[8]"]
|
||||
set_property drive "8" [get_ports "MIO[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
|
||||
# GPIO / gpio[7] / MIO[7]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
|
||||
set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
|
||||
set_property slew "slow" [get_ports "MIO[7]"]
|
||||
set_property drive "8" [get_ports "MIO[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
|
||||
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
|
||||
set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
|
||||
set_property slew "slow" [get_ports "MIO[6]"]
|
||||
set_property drive "8" [get_ports "MIO[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
|
||||
# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
|
||||
set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
|
||||
set_property slew "slow" [get_ports "MIO[5]"]
|
||||
set_property drive "8" [get_ports "MIO[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
|
||||
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
|
||||
set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
|
||||
set_property slew "slow" [get_ports "MIO[4]"]
|
||||
set_property drive "8" [get_ports "MIO[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
|
||||
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
|
||||
set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
|
||||
set_property slew "slow" [get_ports "MIO[3]"]
|
||||
set_property drive "8" [get_ports "MIO[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
|
||||
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
|
||||
set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
|
||||
set_property slew "slow" [get_ports "MIO[2]"]
|
||||
set_property drive "8" [get_ports "MIO[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
|
||||
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
|
||||
set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
|
||||
set_property slew "slow" [get_ports "MIO[1]"]
|
||||
set_property drive "8" [get_ports "MIO[1]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
|
||||
# GPIO / gpio[0] / MIO[0]
|
||||
set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
|
||||
set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
|
||||
set_property slew "slow" [get_ports "MIO[0]"]
|
||||
set_property drive "8" [get_ports "MIO[0]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"]
|
||||
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRP"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"]
|
||||
set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRN"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_WEB"]
|
||||
set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
|
||||
set_property slew "SLOW" [get_ports "DDR_WEB"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"]
|
||||
set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_ODT"]
|
||||
set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
|
||||
set_property slew "SLOW" [get_ports "DDR_ODT"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"]
|
||||
set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
|
||||
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"]
|
||||
set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"]
|
||||
set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"]
|
||||
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"]
|
||||
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"]
|
||||
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"]
|
||||
set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"]
|
||||
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"]
|
||||
set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"]
|
||||
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"]
|
||||
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"]
|
||||
set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"]
|
||||
set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"]
|
||||
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"]
|
||||
set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"]
|
||||
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"]
|
||||
set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"]
|
||||
set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"]
|
||||
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"]
|
||||
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"]
|
||||
set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"]
|
||||
set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"]
|
||||
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"]
|
||||
set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"]
|
||||
set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"]
|
||||
set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"]
|
||||
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"]
|
||||
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"]
|
||||
set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"]
|
||||
set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"]
|
||||
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"]
|
||||
set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"]
|
||||
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"]
|
||||
set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"]
|
||||
set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"]
|
||||
set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"]
|
||||
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"]
|
||||
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"]
|
||||
set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"]
|
||||
set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
|
||||
set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"]
|
||||
set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CS_n"]
|
||||
set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CKE"]
|
||||
set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CKE"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
|
||||
set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"]
|
||||
set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
|
||||
set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"]
|
||||
set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"]
|
||||
set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"]
|
||||
set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"]
|
||||
set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"]
|
||||
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"]
|
||||
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"]
|
||||
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"]
|
||||
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"]
|
||||
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"]
|
||||
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"]
|
||||
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"]
|
||||
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"]
|
||||
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"]
|
||||
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"]
|
||||
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"]
|
||||
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
||||
set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"]
|
||||
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
|
||||
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
|
||||
set_property slew "fast" [get_ports "PS_PORB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
||||
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
|
||||
set_property slew "fast" [get_ports "PS_SRSTB"]
|
||||
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
|
||||
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
|
||||
set_property slew "fast" [get_ports "PS_CLK"]
|
||||
|
||||
+41279
File diff suppressed because it is too large
Load Diff
+6384
File diff suppressed because it is too large
Load Diff
+167
@@ -0,0 +1,167 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sat Feb 8 16:59:22 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_processing_system7_0_0/axi_crc_dma_syn_1_processing_system7_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_processing_system7_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
|
||||
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
|
||||
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, S_AXI_HP0_BVALID,
|
||||
S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, S_AXI_HP0_RRESP,
|
||||
S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, S_AXI_HP0_WCOUNT,
|
||||
S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, S_AXI_HP0_ARVALID,
|
||||
S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, S_AXI_HP0_RREADY,
|
||||
S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, S_AXI_HP0_ARBURST,
|
||||
S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, S_AXI_HP0_AWLOCK,
|
||||
S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, S_AXI_HP0_AWADDR,
|
||||
S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, S_AXI_HP0_AWLEN,
|
||||
S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, S_AXI_HP0_WDATA,
|
||||
S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, MIO,
|
||||
DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB,
|
||||
DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK,
|
||||
PS_PORB)
|
||||
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[31:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[31:0],S_AXI_HP0_WSTRB[3:0],IRQ_F2P[0:0],FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */
|
||||
/* synthesis syn_force_seq_prim="M_AXI_GP0_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="S_AXI_HP0_ACLK" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK0" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK1" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK2" */
|
||||
/* synthesis syn_force_seq_prim="FCLK_CLK3" */;
|
||||
input SDIO0_WP;
|
||||
output TTC0_WAVE0_OUT;
|
||||
output TTC0_WAVE1_OUT;
|
||||
output TTC0_WAVE2_OUT;
|
||||
output [1:0]USB0_PORT_INDCTL;
|
||||
output USB0_VBUS_PWRSELECT;
|
||||
input USB0_VBUS_PWRFAULT;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11:0]M_AXI_GP0_ARID;
|
||||
output [11:0]M_AXI_GP0_AWID;
|
||||
output [11:0]M_AXI_GP0_WID;
|
||||
output [1:0]M_AXI_GP0_ARBURST;
|
||||
output [1:0]M_AXI_GP0_ARLOCK;
|
||||
output [2:0]M_AXI_GP0_ARSIZE;
|
||||
output [1:0]M_AXI_GP0_AWBURST;
|
||||
output [1:0]M_AXI_GP0_AWLOCK;
|
||||
output [2:0]M_AXI_GP0_AWSIZE;
|
||||
output [2:0]M_AXI_GP0_ARPROT;
|
||||
output [2:0]M_AXI_GP0_AWPROT;
|
||||
output [31:0]M_AXI_GP0_ARADDR;
|
||||
output [31:0]M_AXI_GP0_AWADDR;
|
||||
output [31:0]M_AXI_GP0_WDATA;
|
||||
output [3:0]M_AXI_GP0_ARCACHE;
|
||||
output [3:0]M_AXI_GP0_ARLEN;
|
||||
output [3:0]M_AXI_GP0_ARQOS;
|
||||
output [3:0]M_AXI_GP0_AWCACHE;
|
||||
output [3:0]M_AXI_GP0_AWLEN;
|
||||
output [3:0]M_AXI_GP0_AWQOS;
|
||||
output [3:0]M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11:0]M_AXI_GP0_BID;
|
||||
input [11:0]M_AXI_GP0_RID;
|
||||
input [1:0]M_AXI_GP0_BRESP;
|
||||
input [1:0]M_AXI_GP0_RRESP;
|
||||
input [31:0]M_AXI_GP0_RDATA;
|
||||
output S_AXI_HP0_ARREADY;
|
||||
output S_AXI_HP0_AWREADY;
|
||||
output S_AXI_HP0_BVALID;
|
||||
output S_AXI_HP0_RLAST;
|
||||
output S_AXI_HP0_RVALID;
|
||||
output S_AXI_HP0_WREADY;
|
||||
output [1:0]S_AXI_HP0_BRESP;
|
||||
output [1:0]S_AXI_HP0_RRESP;
|
||||
output [5:0]S_AXI_HP0_BID;
|
||||
output [5:0]S_AXI_HP0_RID;
|
||||
output [31:0]S_AXI_HP0_RDATA;
|
||||
output [7:0]S_AXI_HP0_RCOUNT;
|
||||
output [7:0]S_AXI_HP0_WCOUNT;
|
||||
output [2:0]S_AXI_HP0_RACOUNT;
|
||||
output [5:0]S_AXI_HP0_WACOUNT;
|
||||
input S_AXI_HP0_ACLK /* synthesis syn_isclock = 1 */;
|
||||
input S_AXI_HP0_ARVALID;
|
||||
input S_AXI_HP0_AWVALID;
|
||||
input S_AXI_HP0_BREADY;
|
||||
input S_AXI_HP0_RDISSUECAP1_EN;
|
||||
input S_AXI_HP0_RREADY;
|
||||
input S_AXI_HP0_WLAST;
|
||||
input S_AXI_HP0_WRISSUECAP1_EN;
|
||||
input S_AXI_HP0_WVALID;
|
||||
input [1:0]S_AXI_HP0_ARBURST;
|
||||
input [1:0]S_AXI_HP0_ARLOCK;
|
||||
input [2:0]S_AXI_HP0_ARSIZE;
|
||||
input [1:0]S_AXI_HP0_AWBURST;
|
||||
input [1:0]S_AXI_HP0_AWLOCK;
|
||||
input [2:0]S_AXI_HP0_AWSIZE;
|
||||
input [2:0]S_AXI_HP0_ARPROT;
|
||||
input [2:0]S_AXI_HP0_AWPROT;
|
||||
input [31:0]S_AXI_HP0_ARADDR;
|
||||
input [31:0]S_AXI_HP0_AWADDR;
|
||||
input [3:0]S_AXI_HP0_ARCACHE;
|
||||
input [3:0]S_AXI_HP0_ARLEN;
|
||||
input [3:0]S_AXI_HP0_ARQOS;
|
||||
input [3:0]S_AXI_HP0_AWCACHE;
|
||||
input [3:0]S_AXI_HP0_AWLEN;
|
||||
input [3:0]S_AXI_HP0_AWQOS;
|
||||
input [5:0]S_AXI_HP0_ARID;
|
||||
input [5:0]S_AXI_HP0_AWID;
|
||||
input [5:0]S_AXI_HP0_WID;
|
||||
input [31:0]S_AXI_HP0_WDATA;
|
||||
input [3:0]S_AXI_HP0_WSTRB;
|
||||
input [0:0]IRQ_F2P;
|
||||
output FCLK_CLK0 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK1 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK2 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_CLK3 /* synthesis syn_isclock = 1 */;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53:0]MIO;
|
||||
inout DDR_CAS_n;
|
||||
inout DDR_CKE;
|
||||
inout DDR_Clk_n;
|
||||
inout DDR_Clk;
|
||||
inout DDR_CS_n;
|
||||
inout DDR_DRSTB;
|
||||
inout DDR_ODT;
|
||||
inout DDR_RAS_n;
|
||||
inout DDR_WEB;
|
||||
inout [2:0]DDR_BankAddr;
|
||||
inout [14:0]DDR_Addr;
|
||||
inout DDR_VRN;
|
||||
inout DDR_VRP;
|
||||
inout [3:0]DDR_DM;
|
||||
inout [31:0]DDR_DQ;
|
||||
inout [3:0]DDR_DQS_n;
|
||||
inout [3:0]DDR_DQS;
|
||||
inout PS_SRSTB;
|
||||
inout PS_CLK;
|
||||
inout PS_PORB;
|
||||
endmodule
|
||||
+3934
File diff suppressed because it is too large
Load Diff
+12628
File diff suppressed because it is too large
Load Diff
+117
@@ -0,0 +1,117 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 125000000
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 66666672
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+859
@@ -0,0 +1,859 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x000003FF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x000003FF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8008000 0x00000001 0x00000001
|
||||
mask_write 0XF8008014 0x00000001 0x00000001
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8008000 0x00000001 0x00000001
|
||||
mask_write 0XF8008014 0x00000001 0x00000001
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF8000138 0x00000011 0x00000001
|
||||
mask_write 0XF8000140 0x03F03F71 0x00100801
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000150 0x00003F33 0x00001401
|
||||
mask_write 0XF8000154 0x00003F33 0x00000A03
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF8000180 0x03F03F30 0x00200400
|
||||
mask_write 0XF8000190 0x03F03F30 0x00100500
|
||||
mask_write 0XF80001A0 0x03F03F30 0x00100F00
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000080
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000777
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00027000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00026C00
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00028800
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF8006158 0x000FFFFF 0x0000007A
|
||||
mask_write 0XF800615C 0x000FFFFF 0x0000007C
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000073
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F1
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F0
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F7
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000BA
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000BC
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000B3
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000081
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000260
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000600
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000724 0x00003FFF 0x00001600
|
||||
mask_write 0XF8000728 0x00003FFF 0x000016E1
|
||||
mask_write 0XF800072C 0x00003FFF 0x000016E0
|
||||
mask_write 0XF8000730 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000734 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000738 0x00003FFF 0x00001640
|
||||
mask_write 0XF800073C 0x00003FFF 0x00001640
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001302
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001302
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001303
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001303
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001303
|
||||
mask_write 0XF8000770 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000774 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000778 0x00003FFF 0x00001304
|
||||
mask_write 0XF800077C 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000780 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000784 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000788 0x00003FFF 0x00001304
|
||||
mask_write 0XF800078C 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000790 0x00003FFF 0x00001305
|
||||
mask_write 0XF8000794 0x00003FFF 0x00001304
|
||||
mask_write 0XF8000798 0x00003FFF 0x00001304
|
||||
mask_write 0XF800079C 0x00003FFF 0x00001304
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007BC 0x00003F01 0x00001201
|
||||
mask_write 0XF80007C0 0x00003FFF 0x000012E0
|
||||
mask_write 0XF80007C4 0x00003FFF 0x000012E1
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001280
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001280
|
||||
mask_write 0XF8000830 0x003F003F 0x002F0037
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000180
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000180
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE0001034 0x000000FF 0x00000006
|
||||
mask_write 0XE0001018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0001000 0x000001FF 0x00000017
|
||||
mask_write 0XE0001004 0x00000FFF 0x00000020
|
||||
mask_write 0XE0000034 0x000000FF 0x00000006
|
||||
mask_write 0XE0000018 0x0000FFFF 0x0000007C
|
||||
mask_write 0XE0000000 0x000001FF 0x00000017
|
||||
mask_write 0XE0000004 0x00000FFF 0x00000020
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
mask_write 0XE000A244 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
mask_write 0XE000A248 0x003FFFFF 0x00004000
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
|
||||
mask_delay 0XF8F00200 1
|
||||
mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8008000 0x00000001 0x00000001
|
||||
mask_write 0XF8008014 0x00000001 0x00000001
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 667000000
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+12641
File diff suppressed because it is too large
Load Diff
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010-2020 <Xilinx Inc.>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 125000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 50000000
|
||||
#define UART_FREQ 100000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 100000000
|
||||
#define FPGA1_FREQ 125000000
|
||||
#define FPGA2_FREQ 200000000
|
||||
#define FPGA3_FREQ 66666672
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="667" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="4" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="125" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="65" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 14 .. 15" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="MIO 12 .. 13" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="fast" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="5" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 47" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="EMIO" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 10 .. 11" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.221" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.222" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.217" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.244" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="18.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="22.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="27.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="22.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="29.4" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.050" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="-0.044" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.035" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="22.8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="27.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="22.9" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="29.4" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3 (Low Voltage)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 46" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="100.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="125.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="200.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="66.666672" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
+918
@@ -0,0 +1,918 @@
|
||||
#ifndef IP_AXI_CRC_DMA_SYN_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
#define IP_AXI_CRC_DMA_SYN_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "axi_crc_dma_syn_1_processing_system7_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport axi_crc_dma_syn_1_processing_system7_0_0 : public axi_crc_dma_syn_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport axi_crc_dma_syn_1_processing_system7_0_0 : public axi_crc_dma_syn_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout< bool > DDR_CAS_n;
|
||||
sc_core::sc_inout< bool > DDR_CKE;
|
||||
sc_core::sc_inout< bool > DDR_Clk_n;
|
||||
sc_core::sc_inout< bool > DDR_Clk;
|
||||
sc_core::sc_inout< bool > DDR_CS_n;
|
||||
sc_core::sc_inout< bool > DDR_DRSTB;
|
||||
sc_core::sc_inout< bool > DDR_ODT;
|
||||
sc_core::sc_inout< bool > DDR_RAS_n;
|
||||
sc_core::sc_inout< bool > DDR_WEB;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout< bool > DDR_VRN;
|
||||
sc_core::sc_inout< bool > DDR_VRP;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout< bool > PS_SRSTB;
|
||||
sc_core::sc_inout< bool > PS_CLK;
|
||||
sc_core::sc_inout< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport axi_crc_dma_syn_1_processing_system7_0_0 : public axi_crc_dma_syn_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport axi_crc_dma_syn_1_processing_system7_0_0 : public axi_crc_dma_syn_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_initiator_stub.h"
|
||||
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport axi_crc_dma_syn_1_processing_system7_0_0 : public axi_crc_dma_syn_1_processing_system7_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_processing_system7_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > SDIO0_WP;
|
||||
sc_core::sc_out< bool > TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out< bool > TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_BREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_RREADY;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WLAST;
|
||||
sc_core::sc_out< bool > M_AXI_GP0_WVALID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ACLK;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_BVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RLAST;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_RVALID;
|
||||
sc_core::sc_in< bool > M_AXI_GP0_WREADY;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_ARREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_AWREADY;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_BVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RLAST;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_RVALID;
|
||||
sc_core::sc_out< bool > S_AXI_HP0_WREADY;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_BRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > S_AXI_HP0_RRESP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_BID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_RID;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > S_AXI_HP0_RDATA;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out< sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_ARVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_AWVALID;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_BREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_RREADY;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WLAST;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in< bool > S_AXI_HP0_WVALID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_ARLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWBURST;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > S_AXI_HP0_AWLOCK;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWSIZE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_ARPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > S_AXI_HP0_AWPROT;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_ARADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_AWADDR;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_ARQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWCACHE;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWLEN;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_AWQOS;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_ARID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_AWID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<6> > S_AXI_HP0_WID;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > S_AXI_HP0_WDATA;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > S_AXI_HP0_WSTRB;
|
||||
sc_core::sc_in< sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out< bool > FCLK_CLK0;
|
||||
sc_core::sc_out< bool > FCLK_CLK1;
|
||||
sc_core::sc_out< bool > FCLK_CLK2;
|
||||
sc_core::sc_out< bool > FCLK_CLK3;
|
||||
sc_core::sc_out< bool > FCLK_RESET0_N;
|
||||
sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_out< bool > DDR_CAS_n;
|
||||
sc_core::sc_out< bool > DDR_CKE;
|
||||
sc_core::sc_out< bool > DDR_Clk_n;
|
||||
sc_core::sc_out< bool > DDR_Clk;
|
||||
sc_core::sc_out< bool > DDR_CS_n;
|
||||
sc_core::sc_out< bool > DDR_DRSTB;
|
||||
sc_core::sc_out< bool > DDR_ODT;
|
||||
sc_core::sc_out< bool > DDR_RAS_n;
|
||||
sc_core::sc_out< bool > DDR_WEB;
|
||||
sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_out< bool > DDR_VRN;
|
||||
sc_core::sc_out< bool > DDR_VRP;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_out< bool > PS_SRSTB;
|
||||
sc_core::sc_out< bool > PS_CLK;
|
||||
sc_core::sc_out< bool > PS_PORB;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
|
||||
xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
|
||||
xtlm::xaximm_pin2xtlm_t<32,32,6,1,1,1,1,1>* mp_S_AXI_HP0_transactor;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_ARLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_ARLOCK_converter_signal;
|
||||
xsc::common::vectorN2scalar_converter<2>* mp_S_AXI_HP0_AWLOCK_converter;
|
||||
sc_signal< bool > m_S_AXI_HP0_AWLOCK_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_ARLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_ARLEN_converter_signal;
|
||||
xsc::common::vector2vector_converter<4,8>* mp_S_AXI_HP0_AWLEN_converter;
|
||||
sc_signal< sc_bv<8> > m_S_AXI_HP0_AWLEN_converter_signal;
|
||||
sc_signal< bool > m_S_AXI_HP0_transactor_rst_signal;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_initiator_stub * M_AXI_GP0_transactor_initiator_wr_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_HP0_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_AXI_CRC_DMA_SYN_1_PROCESSING_SYSTEM7_0_0_H_
|
||||
+1403
File diff suppressed because it is too large
Load Diff
+690
@@ -0,0 +1,690 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi_crc_dma_syn_1_processing_system7_0_0 (
|
||||
SDIO0_WP,
|
||||
TTC0_WAVE0_OUT,
|
||||
TTC0_WAVE1_OUT,
|
||||
TTC0_WAVE2_OUT,
|
||||
USB0_PORT_INDCTL,
|
||||
USB0_VBUS_PWRSELECT,
|
||||
USB0_VBUS_PWRFAULT,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
S_AXI_HP0_ARREADY,
|
||||
S_AXI_HP0_AWREADY,
|
||||
S_AXI_HP0_BVALID,
|
||||
S_AXI_HP0_RLAST,
|
||||
S_AXI_HP0_RVALID,
|
||||
S_AXI_HP0_WREADY,
|
||||
S_AXI_HP0_BRESP,
|
||||
S_AXI_HP0_RRESP,
|
||||
S_AXI_HP0_BID,
|
||||
S_AXI_HP0_RID,
|
||||
S_AXI_HP0_RDATA,
|
||||
S_AXI_HP0_RCOUNT,
|
||||
S_AXI_HP0_WCOUNT,
|
||||
S_AXI_HP0_RACOUNT,
|
||||
S_AXI_HP0_WACOUNT,
|
||||
S_AXI_HP0_ACLK,
|
||||
S_AXI_HP0_ARVALID,
|
||||
S_AXI_HP0_AWVALID,
|
||||
S_AXI_HP0_BREADY,
|
||||
S_AXI_HP0_RDISSUECAP1_EN,
|
||||
S_AXI_HP0_RREADY,
|
||||
S_AXI_HP0_WLAST,
|
||||
S_AXI_HP0_WRISSUECAP1_EN,
|
||||
S_AXI_HP0_WVALID,
|
||||
S_AXI_HP0_ARBURST,
|
||||
S_AXI_HP0_ARLOCK,
|
||||
S_AXI_HP0_ARSIZE,
|
||||
S_AXI_HP0_AWBURST,
|
||||
S_AXI_HP0_AWLOCK,
|
||||
S_AXI_HP0_AWSIZE,
|
||||
S_AXI_HP0_ARPROT,
|
||||
S_AXI_HP0_AWPROT,
|
||||
S_AXI_HP0_ARADDR,
|
||||
S_AXI_HP0_AWADDR,
|
||||
S_AXI_HP0_ARCACHE,
|
||||
S_AXI_HP0_ARLEN,
|
||||
S_AXI_HP0_ARQOS,
|
||||
S_AXI_HP0_AWCACHE,
|
||||
S_AXI_HP0_AWLEN,
|
||||
S_AXI_HP0_AWQOS,
|
||||
S_AXI_HP0_ARID,
|
||||
S_AXI_HP0_AWID,
|
||||
S_AXI_HP0_WID,
|
||||
S_AXI_HP0_WDATA,
|
||||
S_AXI_HP0_WSTRB,
|
||||
IRQ_F2P,
|
||||
FCLK_CLK0,
|
||||
FCLK_CLK1,
|
||||
FCLK_CLK2,
|
||||
FCLK_CLK3,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input SDIO0_WP;
|
||||
output TTC0_WAVE0_OUT;
|
||||
output TTC0_WAVE1_OUT;
|
||||
output TTC0_WAVE2_OUT;
|
||||
output [1 : 0] USB0_PORT_INDCTL;
|
||||
output USB0_VBUS_PWRSELECT;
|
||||
input USB0_VBUS_PWRFAULT;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
output S_AXI_HP0_ARREADY;
|
||||
output S_AXI_HP0_AWREADY;
|
||||
output S_AXI_HP0_BVALID;
|
||||
output S_AXI_HP0_RLAST;
|
||||
output S_AXI_HP0_RVALID;
|
||||
output S_AXI_HP0_WREADY;
|
||||
output [1 : 0] S_AXI_HP0_BRESP;
|
||||
output [1 : 0] S_AXI_HP0_RRESP;
|
||||
output [5 : 0] S_AXI_HP0_BID;
|
||||
output [5 : 0] S_AXI_HP0_RID;
|
||||
output [31 : 0] S_AXI_HP0_RDATA;
|
||||
output [7 : 0] S_AXI_HP0_RCOUNT;
|
||||
output [7 : 0] S_AXI_HP0_WCOUNT;
|
||||
output [2 : 0] S_AXI_HP0_RACOUNT;
|
||||
output [5 : 0] S_AXI_HP0_WACOUNT;
|
||||
input S_AXI_HP0_ACLK;
|
||||
input S_AXI_HP0_ARVALID;
|
||||
input S_AXI_HP0_AWVALID;
|
||||
input S_AXI_HP0_BREADY;
|
||||
input S_AXI_HP0_RDISSUECAP1_EN;
|
||||
input S_AXI_HP0_RREADY;
|
||||
input S_AXI_HP0_WLAST;
|
||||
input S_AXI_HP0_WRISSUECAP1_EN;
|
||||
input S_AXI_HP0_WVALID;
|
||||
input [1 : 0] S_AXI_HP0_ARBURST;
|
||||
input [1 : 0] S_AXI_HP0_ARLOCK;
|
||||
input [2 : 0] S_AXI_HP0_ARSIZE;
|
||||
input [1 : 0] S_AXI_HP0_AWBURST;
|
||||
input [1 : 0] S_AXI_HP0_AWLOCK;
|
||||
input [2 : 0] S_AXI_HP0_AWSIZE;
|
||||
input [2 : 0] S_AXI_HP0_ARPROT;
|
||||
input [2 : 0] S_AXI_HP0_AWPROT;
|
||||
input [31 : 0] S_AXI_HP0_ARADDR;
|
||||
input [31 : 0] S_AXI_HP0_AWADDR;
|
||||
input [3 : 0] S_AXI_HP0_ARCACHE;
|
||||
input [3 : 0] S_AXI_HP0_ARLEN;
|
||||
input [3 : 0] S_AXI_HP0_ARQOS;
|
||||
input [3 : 0] S_AXI_HP0_AWCACHE;
|
||||
input [3 : 0] S_AXI_HP0_AWLEN;
|
||||
input [3 : 0] S_AXI_HP0_AWQOS;
|
||||
input [5 : 0] S_AXI_HP0_ARID;
|
||||
input [5 : 0] S_AXI_HP0_AWID;
|
||||
input [5 : 0] S_AXI_HP0_WID;
|
||||
input [31 : 0] S_AXI_HP0_WDATA;
|
||||
input [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input [0 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_CLK2;
|
||||
output FCLK_CLK3;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_16 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(1),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(32),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(100.0),
|
||||
.C_FCLK_CLK1_FREQ(125.0),
|
||||
.C_FCLK_CLK2_FREQ(200.0),
|
||||
.C_FCLK_CLK3_FREQ(66.666672),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
|
||||
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
|
||||
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
|
||||
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
|
||||
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
|
||||
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
|
||||
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
|
||||
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
|
||||
.S_AXI_HP0_BID(S_AXI_HP0_BID),
|
||||
.S_AXI_HP0_RID(S_AXI_HP0_RID),
|
||||
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
|
||||
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
|
||||
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
|
||||
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
|
||||
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
|
||||
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
|
||||
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
|
||||
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
|
||||
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
|
||||
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
|
||||
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
|
||||
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
|
||||
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
|
||||
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
|
||||
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
|
||||
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
|
||||
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
|
||||
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
|
||||
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
|
||||
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
|
||||
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
|
||||
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
|
||||
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
|
||||
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
|
||||
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
|
||||
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
|
||||
.S_AXI_HP0_WID(S_AXI_HP0_WID),
|
||||
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
|
||||
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(FCLK_CLK1),
|
||||
|
||||
.FCLK_CLK2(FCLK_CLK2),
|
||||
|
||||
.FCLK_CLK3(FCLK_CLK3),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
#ifndef IP_AXI_CRC_DMA_SYN_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
#define IP_AXI_CRC_DMA_SYN_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class processing_system7_v5_5_tlm;
|
||||
|
||||
class DllExport axi_crc_dma_syn_1_processing_system7_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~axi_crc_dma_syn_1_processing_system7_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
processing_system7_v5_5_tlm* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
axi_crc_dma_syn_1_processing_system7_0_0_sc(const axi_crc_dma_syn_1_processing_system7_0_0_sc&);
|
||||
const axi_crc_dma_syn_1_processing_system7_0_0_sc& operator=(const axi_crc_dma_syn_1_processing_system7_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_AXI_CRC_DMA_SYN_1_PROCESSING_SYSTEM7_0_0_SC_H_
|
||||
+315
@@ -0,0 +1,315 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: axi_crc_dma_syn_1_processing_system7_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module axi_crc_dma_syn_1_processing_system7_0_0 (
|
||||
input bit_as_bool SDIO0_WP,
|
||||
output bit_as_bool TTC0_WAVE0_OUT,
|
||||
output bit_as_bool TTC0_WAVE1_OUT,
|
||||
output bit_as_bool TTC0_WAVE2_OUT,
|
||||
output bit [1 : 0] USB0_PORT_INDCTL,
|
||||
output bit_as_bool USB0_VBUS_PWRSELECT,
|
||||
input bit_as_bool USB0_VBUS_PWRFAULT,
|
||||
output bit_as_bool M_AXI_GP0_ARVALID,
|
||||
output bit_as_bool M_AXI_GP0_AWVALID,
|
||||
output bit_as_bool M_AXI_GP0_BREADY,
|
||||
output bit_as_bool M_AXI_GP0_RREADY,
|
||||
output bit_as_bool M_AXI_GP0_WLAST,
|
||||
output bit_as_bool M_AXI_GP0_WVALID,
|
||||
output bit [11 : 0] M_AXI_GP0_ARID,
|
||||
output bit [11 : 0] M_AXI_GP0_AWID,
|
||||
output bit [11 : 0] M_AXI_GP0_WID,
|
||||
output bit [1 : 0] M_AXI_GP0_ARBURST,
|
||||
output bit [1 : 0] M_AXI_GP0_ARLOCK,
|
||||
output bit [2 : 0] M_AXI_GP0_ARSIZE,
|
||||
output bit [1 : 0] M_AXI_GP0_AWBURST,
|
||||
output bit [1 : 0] M_AXI_GP0_AWLOCK,
|
||||
output bit [2 : 0] M_AXI_GP0_AWSIZE,
|
||||
output bit [2 : 0] M_AXI_GP0_ARPROT,
|
||||
output bit [2 : 0] M_AXI_GP0_AWPROT,
|
||||
output bit [31 : 0] M_AXI_GP0_ARADDR,
|
||||
output bit [31 : 0] M_AXI_GP0_AWADDR,
|
||||
output bit [31 : 0] M_AXI_GP0_WDATA,
|
||||
output bit [3 : 0] M_AXI_GP0_ARCACHE,
|
||||
output bit [3 : 0] M_AXI_GP0_ARLEN,
|
||||
output bit [3 : 0] M_AXI_GP0_ARQOS,
|
||||
output bit [3 : 0] M_AXI_GP0_AWCACHE,
|
||||
output bit [3 : 0] M_AXI_GP0_AWLEN,
|
||||
output bit [3 : 0] M_AXI_GP0_AWQOS,
|
||||
output bit [3 : 0] M_AXI_GP0_WSTRB,
|
||||
input bit_as_bool M_AXI_GP0_ACLK,
|
||||
input bit_as_bool M_AXI_GP0_ARREADY,
|
||||
input bit_as_bool M_AXI_GP0_AWREADY,
|
||||
input bit_as_bool M_AXI_GP0_BVALID,
|
||||
input bit_as_bool M_AXI_GP0_RLAST,
|
||||
input bit_as_bool M_AXI_GP0_RVALID,
|
||||
input bit_as_bool M_AXI_GP0_WREADY,
|
||||
input bit [11 : 0] M_AXI_GP0_BID,
|
||||
input bit [11 : 0] M_AXI_GP0_RID,
|
||||
input bit [1 : 0] M_AXI_GP0_BRESP,
|
||||
input bit [1 : 0] M_AXI_GP0_RRESP,
|
||||
input bit [31 : 0] M_AXI_GP0_RDATA,
|
||||
output bit_as_bool S_AXI_HP0_ARREADY,
|
||||
output bit_as_bool S_AXI_HP0_AWREADY,
|
||||
output bit_as_bool S_AXI_HP0_BVALID,
|
||||
output bit_as_bool S_AXI_HP0_RLAST,
|
||||
output bit_as_bool S_AXI_HP0_RVALID,
|
||||
output bit_as_bool S_AXI_HP0_WREADY,
|
||||
output bit [1 : 0] S_AXI_HP0_BRESP,
|
||||
output bit [1 : 0] S_AXI_HP0_RRESP,
|
||||
output bit [5 : 0] S_AXI_HP0_BID,
|
||||
output bit [5 : 0] S_AXI_HP0_RID,
|
||||
output bit [31 : 0] S_AXI_HP0_RDATA,
|
||||
output bit [7 : 0] S_AXI_HP0_RCOUNT,
|
||||
output bit [7 : 0] S_AXI_HP0_WCOUNT,
|
||||
output bit [2 : 0] S_AXI_HP0_RACOUNT,
|
||||
output bit [5 : 0] S_AXI_HP0_WACOUNT,
|
||||
input bit_as_bool S_AXI_HP0_ACLK,
|
||||
input bit_as_bool S_AXI_HP0_ARVALID,
|
||||
input bit_as_bool S_AXI_HP0_AWVALID,
|
||||
input bit_as_bool S_AXI_HP0_BREADY,
|
||||
input bit_as_bool S_AXI_HP0_RDISSUECAP1_EN,
|
||||
input bit_as_bool S_AXI_HP0_RREADY,
|
||||
input bit_as_bool S_AXI_HP0_WLAST,
|
||||
input bit_as_bool S_AXI_HP0_WRISSUECAP1_EN,
|
||||
input bit_as_bool S_AXI_HP0_WVALID,
|
||||
input bit [1 : 0] S_AXI_HP0_ARBURST,
|
||||
input bit [1 : 0] S_AXI_HP0_ARLOCK,
|
||||
input bit [2 : 0] S_AXI_HP0_ARSIZE,
|
||||
input bit [1 : 0] S_AXI_HP0_AWBURST,
|
||||
input bit [1 : 0] S_AXI_HP0_AWLOCK,
|
||||
input bit [2 : 0] S_AXI_HP0_AWSIZE,
|
||||
input bit [2 : 0] S_AXI_HP0_ARPROT,
|
||||
input bit [2 : 0] S_AXI_HP0_AWPROT,
|
||||
input bit [31 : 0] S_AXI_HP0_ARADDR,
|
||||
input bit [31 : 0] S_AXI_HP0_AWADDR,
|
||||
input bit [3 : 0] S_AXI_HP0_ARCACHE,
|
||||
input bit [3 : 0] S_AXI_HP0_ARLEN,
|
||||
input bit [3 : 0] S_AXI_HP0_ARQOS,
|
||||
input bit [3 : 0] S_AXI_HP0_AWCACHE,
|
||||
input bit [3 : 0] S_AXI_HP0_AWLEN,
|
||||
input bit [3 : 0] S_AXI_HP0_AWQOS,
|
||||
input bit [5 : 0] S_AXI_HP0_ARID,
|
||||
input bit [5 : 0] S_AXI_HP0_AWID,
|
||||
input bit [5 : 0] S_AXI_HP0_WID,
|
||||
input bit [31 : 0] S_AXI_HP0_WDATA,
|
||||
input bit [3 : 0] S_AXI_HP0_WSTRB,
|
||||
input bit [0 : 0] IRQ_F2P,
|
||||
output bit_as_bool FCLK_CLK0,
|
||||
output bit_as_bool FCLK_CLK1,
|
||||
output bit_as_bool FCLK_CLK2,
|
||||
output bit_as_bool FCLK_CLK3,
|
||||
output bit_as_bool FCLK_RESET0_N,
|
||||
output bit [53 : 0] MIO,
|
||||
output bit_as_bool DDR_CAS_n,
|
||||
output bit_as_bool DDR_CKE,
|
||||
output bit_as_bool DDR_Clk_n,
|
||||
output bit_as_bool DDR_Clk,
|
||||
output bit_as_bool DDR_CS_n,
|
||||
output bit_as_bool DDR_DRSTB,
|
||||
output bit_as_bool DDR_ODT,
|
||||
output bit_as_bool DDR_RAS_n,
|
||||
output bit_as_bool DDR_WEB,
|
||||
output bit [2 : 0] DDR_BankAddr,
|
||||
output bit [14 : 0] DDR_Addr,
|
||||
output bit_as_bool DDR_VRN,
|
||||
output bit_as_bool DDR_VRP,
|
||||
output bit [3 : 0] DDR_DM,
|
||||
output bit [31 : 0] DDR_DQ,
|
||||
output bit [3 : 0] DDR_DQS_n,
|
||||
output bit [3 : 0] DDR_DQS,
|
||||
output bit_as_bool PS_SRSTB,
|
||||
output bit_as_bool PS_CLK,
|
||||
output bit_as_bool PS_PORB
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module axi_crc_dma_syn_1_processing_system7_0_0 (SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL,USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID,M_AXI_GP0_AWID,M_AXI_GP0_WID,M_AXI_GP0_ARBURST,M_AXI_GP0_ARLOCK,M_AXI_GP0_ARSIZE,M_AXI_GP0_AWBURST,M_AXI_GP0_AWLOCK,M_AXI_GP0_AWSIZE,M_AXI_GP0_ARPROT,M_AXI_GP0_AWPROT,M_AXI_GP0_ARADDR,M_AXI_GP0_AWADDR,M_AXI_GP0_WDATA,M_AXI_GP0_ARCACHE,M_AXI_GP0_ARLEN,M_AXI_GP0_ARQOS,M_AXI_GP0_AWCACHE,M_AXI_GP0_AWLEN,M_AXI_GP0_AWQOS,M_AXI_GP0_WSTRB,M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID,M_AXI_GP0_RID,M_AXI_GP0_BRESP,M_AXI_GP0_RRESP,M_AXI_GP0_RDATA,S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP,S_AXI_HP0_RRESP,S_AXI_HP0_BID,S_AXI_HP0_RID,S_AXI_HP0_RDATA,S_AXI_HP0_RCOUNT,S_AXI_HP0_WCOUNT,S_AXI_HP0_RACOUNT,S_AXI_HP0_WACOUNT,S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST,S_AXI_HP0_ARLOCK,S_AXI_HP0_ARSIZE,S_AXI_HP0_AWBURST,S_AXI_HP0_AWLOCK,S_AXI_HP0_AWSIZE,S_AXI_HP0_ARPROT,S_AXI_HP0_AWPROT,S_AXI_HP0_ARADDR,S_AXI_HP0_AWADDR,S_AXI_HP0_ARCACHE,S_AXI_HP0_ARLEN,S_AXI_HP0_ARQOS,S_AXI_HP0_AWCACHE,S_AXI_HP0_AWLEN,S_AXI_HP0_AWQOS,S_AXI_HP0_ARID,S_AXI_HP0_AWID,S_AXI_HP0_WID,S_AXI_HP0_WDATA,S_AXI_HP0_WSTRB,IRQ_F2P,FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit SDIO0_WP;
|
||||
output wire TTC0_WAVE0_OUT;
|
||||
output wire TTC0_WAVE1_OUT;
|
||||
output wire TTC0_WAVE2_OUT;
|
||||
output wire [1 : 0] USB0_PORT_INDCTL;
|
||||
output wire USB0_VBUS_PWRSELECT;
|
||||
input bit USB0_VBUS_PWRFAULT;
|
||||
output wire M_AXI_GP0_ARVALID;
|
||||
output wire M_AXI_GP0_AWVALID;
|
||||
output wire M_AXI_GP0_BREADY;
|
||||
output wire M_AXI_GP0_RREADY;
|
||||
output wire M_AXI_GP0_WLAST;
|
||||
output wire M_AXI_GP0_WVALID;
|
||||
output wire [11 : 0] M_AXI_GP0_ARID;
|
||||
output wire [11 : 0] M_AXI_GP0_AWID;
|
||||
output wire [11 : 0] M_AXI_GP0_WID;
|
||||
output wire [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output wire [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output wire [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output wire [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output wire [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output wire [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output wire [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output wire [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output wire [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output wire [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output wire [31 : 0] M_AXI_GP0_WDATA;
|
||||
output wire [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output wire [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output wire [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output wire [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output wire [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output wire [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input bit M_AXI_GP0_ACLK;
|
||||
input bit M_AXI_GP0_ARREADY;
|
||||
input bit M_AXI_GP0_AWREADY;
|
||||
input bit M_AXI_GP0_BVALID;
|
||||
input bit M_AXI_GP0_RLAST;
|
||||
input bit M_AXI_GP0_RVALID;
|
||||
input bit M_AXI_GP0_WREADY;
|
||||
input bit [11 : 0] M_AXI_GP0_BID;
|
||||
input bit [11 : 0] M_AXI_GP0_RID;
|
||||
input bit [1 : 0] M_AXI_GP0_BRESP;
|
||||
input bit [1 : 0] M_AXI_GP0_RRESP;
|
||||
input bit [31 : 0] M_AXI_GP0_RDATA;
|
||||
output wire S_AXI_HP0_ARREADY;
|
||||
output wire S_AXI_HP0_AWREADY;
|
||||
output wire S_AXI_HP0_BVALID;
|
||||
output wire S_AXI_HP0_RLAST;
|
||||
output wire S_AXI_HP0_RVALID;
|
||||
output wire S_AXI_HP0_WREADY;
|
||||
output wire [1 : 0] S_AXI_HP0_BRESP;
|
||||
output wire [1 : 0] S_AXI_HP0_RRESP;
|
||||
output wire [5 : 0] S_AXI_HP0_BID;
|
||||
output wire [5 : 0] S_AXI_HP0_RID;
|
||||
output wire [31 : 0] S_AXI_HP0_RDATA;
|
||||
output wire [7 : 0] S_AXI_HP0_RCOUNT;
|
||||
output wire [7 : 0] S_AXI_HP0_WCOUNT;
|
||||
output wire [2 : 0] S_AXI_HP0_RACOUNT;
|
||||
output wire [5 : 0] S_AXI_HP0_WACOUNT;
|
||||
input bit S_AXI_HP0_ACLK;
|
||||
input bit S_AXI_HP0_ARVALID;
|
||||
input bit S_AXI_HP0_AWVALID;
|
||||
input bit S_AXI_HP0_BREADY;
|
||||
input bit S_AXI_HP0_RDISSUECAP1_EN;
|
||||
input bit S_AXI_HP0_RREADY;
|
||||
input bit S_AXI_HP0_WLAST;
|
||||
input bit S_AXI_HP0_WRISSUECAP1_EN;
|
||||
input bit S_AXI_HP0_WVALID;
|
||||
input bit [1 : 0] S_AXI_HP0_ARBURST;
|
||||
input bit [1 : 0] S_AXI_HP0_ARLOCK;
|
||||
input bit [2 : 0] S_AXI_HP0_ARSIZE;
|
||||
input bit [1 : 0] S_AXI_HP0_AWBURST;
|
||||
input bit [1 : 0] S_AXI_HP0_AWLOCK;
|
||||
input bit [2 : 0] S_AXI_HP0_AWSIZE;
|
||||
input bit [2 : 0] S_AXI_HP0_ARPROT;
|
||||
input bit [2 : 0] S_AXI_HP0_AWPROT;
|
||||
input bit [31 : 0] S_AXI_HP0_ARADDR;
|
||||
input bit [31 : 0] S_AXI_HP0_AWADDR;
|
||||
input bit [3 : 0] S_AXI_HP0_ARCACHE;
|
||||
input bit [3 : 0] S_AXI_HP0_ARLEN;
|
||||
input bit [3 : 0] S_AXI_HP0_ARQOS;
|
||||
input bit [3 : 0] S_AXI_HP0_AWCACHE;
|
||||
input bit [3 : 0] S_AXI_HP0_AWLEN;
|
||||
input bit [3 : 0] S_AXI_HP0_AWQOS;
|
||||
input bit [5 : 0] S_AXI_HP0_ARID;
|
||||
input bit [5 : 0] S_AXI_HP0_AWID;
|
||||
input bit [5 : 0] S_AXI_HP0_WID;
|
||||
input bit [31 : 0] S_AXI_HP0_WDATA;
|
||||
input bit [3 : 0] S_AXI_HP0_WSTRB;
|
||||
input bit [0 : 0] IRQ_F2P;
|
||||
output wire FCLK_CLK0;
|
||||
output wire FCLK_CLK1;
|
||||
output wire FCLK_CLK2;
|
||||
output wire FCLK_CLK3;
|
||||
output wire FCLK_RESET0_N;
|
||||
inout wire [53 : 0] MIO;
|
||||
inout wire DDR_CAS_n;
|
||||
inout wire DDR_CKE;
|
||||
inout wire DDR_Clk_n;
|
||||
inout wire DDR_Clk;
|
||||
inout wire DDR_CS_n;
|
||||
inout wire DDR_DRSTB;
|
||||
inout wire DDR_ODT;
|
||||
inout wire DDR_RAS_n;
|
||||
inout wire DDR_WEB;
|
||||
inout wire [2 : 0] DDR_BankAddr;
|
||||
inout wire [14 : 0] DDR_Addr;
|
||||
inout wire DDR_VRN;
|
||||
inout wire DDR_VRP;
|
||||
inout wire [3 : 0] DDR_DM;
|
||||
inout wire [31 : 0] DDR_DQ;
|
||||
inout wire [3 : 0] DDR_DQS_n;
|
||||
inout wire [3 : 0] DDR_DQS;
|
||||
inout wire PS_SRSTB;
|
||||
inout wire PS_CLK;
|
||||
inout wire PS_PORB;
|
||||
endmodule
|
||||
`endif
|
||||
+170
@@ -0,0 +1,170 @@
|
||||
// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#ifndef _B_TRANSPORT_CONVERTER_H_
|
||||
#define _B_TRANSPORT_CONVERTER_H_
|
||||
|
||||
#include <systemc>
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
class b_transport_converter: public sc_core::sc_module
|
||||
{
|
||||
enum TLM_IF_TYPE
|
||||
{
|
||||
B_TRANSPORT = 0,
|
||||
NB_TRANSPORT,
|
||||
TRANSPORT_DBG,
|
||||
DMI_IF,
|
||||
INVALID_IF
|
||||
};
|
||||
typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(b_transport_converter);
|
||||
b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
|
||||
sc_module(name)
|
||||
{
|
||||
target_socket.register_b_transport(
|
||||
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
|
||||
initiator_socket.register_nb_transport_bw(
|
||||
this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
|
||||
|
||||
}
|
||||
|
||||
//simple tlm target/initiator socket...
|
||||
tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
|
||||
tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
|
||||
|
||||
|
||||
public:
|
||||
void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
|
||||
{
|
||||
tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
|
||||
switch(get_tlm_if_type(payload.get_address()))
|
||||
{
|
||||
case B_TRANSPORT:
|
||||
initiator_socket->b_transport(payload, time);
|
||||
break;
|
||||
|
||||
case NB_TRANSPORT:
|
||||
initiator_socket->nb_transport_fw(payload, phase, time);
|
||||
wait(resp_complete_event); //! Wait for the response to complete
|
||||
break;
|
||||
|
||||
case TRANSPORT_DBG:
|
||||
initiator_socket->transport_dbg(payload);
|
||||
break;
|
||||
|
||||
case DMI_IF:
|
||||
break;
|
||||
|
||||
default:
|
||||
SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
|
||||
}
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum
|
||||
nb_transport_bw(tlm::tlm_generic_payload& payload,
|
||||
tlm::tlm_phase& phase, sc_core::sc_time& time)
|
||||
{
|
||||
if(phase == tlm::BEGIN_RESP) {
|
||||
resp_complete_event.notify();
|
||||
phase = tlm::END_RESP;
|
||||
return tlm::TLM_UPDATED;
|
||||
}
|
||||
return tlm::TLM_ACCEPTED;
|
||||
}
|
||||
|
||||
private:
|
||||
TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
|
||||
{
|
||||
//check for b_transport addresses
|
||||
for(auto& addr_range: m_b_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return B_TRANSPORT;
|
||||
}
|
||||
}
|
||||
|
||||
//check for nb_transport addresses
|
||||
for(auto& addr_range: m_nb_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return NB_TRANSPORT;
|
||||
}
|
||||
}
|
||||
//check for dbg_transport addresses
|
||||
for(auto& addr_range: m_dbg_transport_addr_list) {
|
||||
if(address >= addr_range.first && address < addr_range.second) {
|
||||
return TRANSPORT_DBG;
|
||||
}
|
||||
}
|
||||
|
||||
//By default return NB_TRANSPORT
|
||||
return NB_TRANSPORT;
|
||||
}
|
||||
|
||||
//Start and End Address List for each of interfaces...
|
||||
static addr_range_list m_b_transport_addr_list;
|
||||
static addr_range_list m_nb_transport_addr_list;
|
||||
static addr_range_list m_dbg_transport_addr_list;
|
||||
|
||||
//event to notify completion of transaction
|
||||
sc_core::sc_event resp_complete_event;
|
||||
};
|
||||
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
|
||||
template<int IN_WIDTH, int OUT_WIDTH>
|
||||
typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
|
||||
|
||||
|
||||
#endif /* _B_TRANSPORT_CONVERTER_H_ */
|
||||
|
||||
+251
@@ -0,0 +1,251 @@
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
#ifndef __PS7_H__
|
||||
#define __PS7_H__
|
||||
|
||||
#include "systemc.h"
|
||||
#include "xtlm.h"
|
||||
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
|
||||
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "genattr.h"
|
||||
#include "xilinx-zynq.h"
|
||||
#include "b_transport_converter.h"
|
||||
#include "utils/xtlm_aximm_fifo.h"
|
||||
|
||||
/***************************************************************************************
|
||||
*
|
||||
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
|
||||
* calls to xTLM sockets bn_transport_x() calls..
|
||||
*
|
||||
* This is Only specific to remote-port so not creating seperate header for it.
|
||||
*
|
||||
***************************************************************************************/
|
||||
template <int IN_WIDTH, int OUT_WIDTH>
|
||||
class rptlm2xtlm_converter : public sc_module{
|
||||
public:
|
||||
tlm::tlm_target_socket<IN_WIDTH> target_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket rd_socket;
|
||||
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
|
||||
void registerUserExtensionHandlerCallback(
|
||||
void (*callback)(xtlm::aximm_payload*,
|
||||
const tlm::tlm_generic_payload*));
|
||||
|
||||
private:
|
||||
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
|
||||
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
|
||||
};
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with tlm2xtlm bridge
|
||||
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
|
||||
*
|
||||
* caller: tlm2xtlm bridge
|
||||
* purpose: To get master id and other parameters out of genattr_extension
|
||||
* and use master id to AxUSER PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
|
||||
|
||||
/***************************************************************************************
|
||||
* Global method, get registered with xtlm2tlm bridge
|
||||
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
|
||||
*
|
||||
* caller: xtlm2tlm bridge
|
||||
* purpose: To create and add master id and other parameters to genattr_extension.
|
||||
* Master id red from AxID PIN of xtlm payload.
|
||||
*
|
||||
*
|
||||
***************************************************************************************/
|
||||
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// //
|
||||
// File: processing_system7_tlm.h //
|
||||
// //
|
||||
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
|
||||
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
|
||||
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
|
||||
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
|
||||
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
|
||||
// it fill the the gap between input/output ports of vivado generated wrapper to //
|
||||
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
|
||||
// based on IP configuration in vivado. //
|
||||
// //
|
||||
// //
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
class processing_system7_v5_5_tlm : public sc_core::sc_module {
|
||||
|
||||
public:
|
||||
// Non-AXI ports are declared here
|
||||
sc_core::sc_in<bool> SDIO0_WP;
|
||||
sc_core::sc_out<bool> TTC0_WAVE0_OUT;
|
||||
sc_core::sc_out<bool> TTC0_WAVE1_OUT;
|
||||
sc_core::sc_out<bool> TTC0_WAVE2_OUT;
|
||||
sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
|
||||
sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
|
||||
sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
|
||||
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
|
||||
sc_core::sc_out<sc_dt::sc_bv<8> > S_AXI_HP0_RCOUNT;
|
||||
sc_core::sc_out<sc_dt::sc_bv<8> > S_AXI_HP0_WCOUNT;
|
||||
sc_core::sc_out<sc_dt::sc_bv<3> > S_AXI_HP0_RACOUNT;
|
||||
sc_core::sc_out<sc_dt::sc_bv<6> > S_AXI_HP0_WACOUNT;
|
||||
sc_core::sc_in<bool> S_AXI_HP0_ACLK;
|
||||
sc_core::sc_in<bool> S_AXI_HP0_RDISSUECAP1_EN;
|
||||
sc_core::sc_in<bool> S_AXI_HP0_WRISSUECAP1_EN;
|
||||
sc_core::sc_in<sc_dt::sc_bv<1> > IRQ_F2P;
|
||||
sc_core::sc_out<bool> FCLK_CLK0;
|
||||
sc_core::sc_out<bool> FCLK_CLK1;
|
||||
sc_core::sc_out<bool> FCLK_CLK2;
|
||||
sc_core::sc_out<bool> FCLK_CLK3;
|
||||
sc_core::sc_out<bool> FCLK_RESET0_N;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
|
||||
sc_core::sc_inout<bool> DDR_CAS_n;
|
||||
sc_core::sc_inout<bool> DDR_CKE;
|
||||
sc_core::sc_inout<bool> DDR_Clk_n;
|
||||
sc_core::sc_inout<bool> DDR_Clk;
|
||||
sc_core::sc_inout<bool> DDR_CS_n;
|
||||
sc_core::sc_inout<bool> DDR_DRSTB;
|
||||
sc_core::sc_inout<bool> DDR_ODT;
|
||||
sc_core::sc_inout<bool> DDR_RAS_n;
|
||||
sc_core::sc_inout<bool> DDR_WEB;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
|
||||
sc_core::sc_inout<bool> DDR_VRN;
|
||||
sc_core::sc_inout<bool> DDR_VRP;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
|
||||
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
|
||||
sc_core::sc_inout<bool> PS_SRSTB;
|
||||
sc_core::sc_inout<bool> PS_CLK;
|
||||
sc_core::sc_inout<bool> PS_PORB;
|
||||
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
|
||||
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_rd_socket;
|
||||
|
||||
//constructor having three paramters
|
||||
// 1. module name in sc_module_name objec,
|
||||
// 2. reference to map object of name and integer value pairs
|
||||
// 3. reference to map object of name and string value pairs
|
||||
// All the model parameters (integer and string) which are configuration parameters
|
||||
// of Processing System 7 IP propogated from Vivado
|
||||
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
|
||||
xsc::common_cpp::properties&);
|
||||
|
||||
~processing_system7_v5_5_tlm();
|
||||
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
|
||||
|
||||
private:
|
||||
|
||||
//zynq tlm wrapper provided by Edgar
|
||||
//module with interfaces of standard tlm
|
||||
//and input/output ports at signal level
|
||||
xilinx_zynq* m_zynq_tlm_model;
|
||||
|
||||
// Xtlm2tlm_t Bridges
|
||||
// Converts Xtlm transactions to tlm transactions
|
||||
// Bridge's Xtlm wr/rd target sockets binds with
|
||||
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
|
||||
// socket with xilinx_zynq's target socket
|
||||
xtlm::xaximm_xtlm2tlm_t<32,32> S_AXI_HP0_xtlm_brdg;
|
||||
xtlm::xtlm_aximm_fifo *S_AXI_HP0_buff;
|
||||
|
||||
// This Bridges converts b_transport to nb_transports and also
|
||||
// Converts tlm transactions to xtlm transactions.
|
||||
// Bridge's tlm simple target socket binds with
|
||||
// simple initiator socket of xilinx_zynqmp and xtlm
|
||||
// socket with xilinx_zynq's simple target socket
|
||||
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
|
||||
|
||||
// sc_clocks for generating pl clocks
|
||||
// output pins FCLK_CLK0..3 are drived by these clocks
|
||||
sc_core::sc_clock FCLK_CLK0_clk;
|
||||
sc_core::sc_clock FCLK_CLK1_clk;
|
||||
sc_core::sc_clock FCLK_CLK2_clk;
|
||||
sc_core::sc_clock FCLK_CLK3_clk;
|
||||
|
||||
|
||||
//Method which is sentive to FCLK_CLK0_clk sc_clock object
|
||||
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
|
||||
void trigger_FCLK_CLK0_pin();
|
||||
//Method which is sentive to FCLK_CLK1_clk sc_clock object
|
||||
//FCLK_CLK1 pin written based on FCLK_CLK1_clk clock value
|
||||
void trigger_FCLK_CLK1_pin();
|
||||
//Method which is sentive to FCLK_CLK2_clk sc_clock object
|
||||
//FCLK_CLK2 pin written based on FCLK_CLK2_clk clock value
|
||||
void trigger_FCLK_CLK2_pin();
|
||||
//Method which is sentive to FCLK_CLK3_clk sc_clock object
|
||||
//FCLK_CLK3 pin written based on FCLK_CLK3_clk clock value
|
||||
void trigger_FCLK_CLK3_pin();
|
||||
|
||||
void IRQ_F2P_method();
|
||||
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
|
||||
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
|
||||
void FCLK_RESET0_N_trigger();
|
||||
|
||||
sc_signal<bool> qemu_rst;
|
||||
void start_of_simulation();
|
||||
|
||||
xsc::common_cpp::properties prop;
|
||||
|
||||
};
|
||||
#endif
|
||||
+104
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
|
||||
*
|
||||
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
|
||||
*
|
||||
* Copyright (c) 2016, Xilinx Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "systemc.h"
|
||||
|
||||
#include "tlm_utils/simple_initiator_socket.h"
|
||||
#include "tlm_utils/simple_target_socket.h"
|
||||
#include "tlm_utils/tlm_quantumkeeper.h"
|
||||
|
||||
#include "remote-port-tlm.h"
|
||||
#include "remote-port-tlm-memory-master.h"
|
||||
#include "remote-port-tlm-memory-slave.h"
|
||||
#include "remote-port-tlm-wires.h"
|
||||
|
||||
class xilinx_zynq
|
||||
: public remoteport_tlm
|
||||
{
|
||||
private:
|
||||
remoteport_tlm_memory_master rp_m_axi_gp0;
|
||||
remoteport_tlm_memory_master rp_m_axi_gp1;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_gp0;
|
||||
remoteport_tlm_memory_slave rp_s_axi_gp1;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp0;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp1;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp2;
|
||||
remoteport_tlm_memory_slave rp_s_axi_hp3;
|
||||
|
||||
remoteport_tlm_memory_slave rp_s_axi_acp;
|
||||
|
||||
remoteport_tlm_wires rp_wires_in;
|
||||
remoteport_tlm_wires rp_wires_out;
|
||||
remoteport_tlm_wires rp_irq_out;
|
||||
|
||||
public:
|
||||
/*
|
||||
* M_AXI_GP 0 - 1.
|
||||
* These sockets represent the High speed PS to PL interfaces.
|
||||
* These are AXI Slave ports on the PS side and AXI Master ports
|
||||
* on the PL side.
|
||||
*
|
||||
* Used to transfer data from the PS to the PL.
|
||||
*/
|
||||
tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
|
||||
|
||||
/*
|
||||
* S_AXI_GP0 - 1.
|
||||
* These sockets represent the High speed IO Coherent PL to PS
|
||||
* interfaces.
|
||||
*
|
||||
* HP0 - 3.
|
||||
* These sockets represent the High performance dataflow PL to PS interfaces.
|
||||
*
|
||||
* ACP
|
||||
* Accelerator Coherency Port, used to transfered coherent data to
|
||||
* the PS via the Cortex-A9 subsystem.
|
||||
*
|
||||
* These are AXI Master ports on the PS side and AXI Slave ports
|
||||
* on the PL side.
|
||||
*
|
||||
* Used to transfer data from the PL to the PS.
|
||||
*/
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
|
||||
tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
|
||||
|
||||
/* PL (fabric) to PS interrupt signals. */
|
||||
sc_vector<sc_signal<bool> > pl2ps_irq;
|
||||
|
||||
/* PS to PL Interrupt signals. */
|
||||
sc_vector<sc_signal<bool> > ps2pl_irq;
|
||||
|
||||
/* FPGA out resets. */
|
||||
sc_vector<sc_signal<bool> > ps2pl_rst;
|
||||
|
||||
xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
|
||||
//xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
|
||||
// Iremoteport_tlm_sync *sync = NULL);
|
||||
};
|
||||
+1160
File diff suppressed because it is too large
Load Diff
+49
@@ -0,0 +1,49 @@
|
||||
|
||||
# file: axi_crc_dma_syn_1_rst_ps7_0_100M_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
+978
@@ -0,0 +1,978 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>axi_crc_dma_syn_1_rst_ps7_0_100M_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>clock</spirit:name>
|
||||
<spirit:displayName>Clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_reset</spirit:name>
|
||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:presence>required</xilinx:presence>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>aux_reset</spirit:name>
|
||||
<spirit:displayName>aux_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>dbg_reset</spirit:name>
|
||||
<spirit:displayName>DBG_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>mb_rst</spirit:name>
|
||||
<spirit:displayName>MB_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:displayName>bus_struct_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>interconnect_low_rst</spirit:name>
|
||||
<spirit:displayName>interconnect_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_high_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_high_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_low_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
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||||
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|
||||
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||||
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|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
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|
||||
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||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
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<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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<spirit:fileType>vhdlSource</spirit:fileType>
|
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<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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|
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<spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
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</spirit:file>
|
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|
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<spirit:name>axi_crc_dma_syn_1_rst_ps7_0_100M_0.xdc</spirit:name>
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<spirit:userFileType>xdc</spirit:userFileType>
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</spirit:file>
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<spirit:description>Processor Reset System</spirit:description>
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<spirit:parameters>
|
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<spirit:parameter>
|
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<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
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<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
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<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
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</spirit:parameter>
|
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<spirit:parameter>
|
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<spirit:name>C_NUM_PERP_RST</spirit:name>
|
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<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
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</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
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</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
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<spirit:displayName>Ext Rst Width</spirit:displayName>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
|
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_crc_dma_syn_1_rst_ps7_0_100M_0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
|
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<spirit:name>USE_BOARD_FLOW</spirit:name>
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<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
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<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:displayName>Processor System Reset</xilinx:displayName>
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|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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|
||||
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|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name slowest_sync_clk [get_ports slowest_sync_clk]
|
||||
|
||||
|
||||
+980
@@ -0,0 +1,980 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:13:54 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top axi_crc_dma_syn_1_rst_ps7_0_100M_0 -prefix
|
||||
// axi_crc_dma_syn_1_rst_ps7_0_100M_0_ axi_crc_dma_syn_1_rst_ps7_0_100M_0_sim_netlist.v
|
||||
// Design : axi_crc_dma_syn_1_rst_ps7_0_100M_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "axi_crc_dma_syn_1_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input slowest_sync_clk;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input ext_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
|
||||
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;
|
||||
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *)
|
||||
(* C_AUX_RST_WIDTH = "4" *)
|
||||
(* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *)
|
||||
(* C_FAMILY = "zynq" *)
|
||||
(* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_ARESETN = "1" *)
|
||||
(* C_NUM_PERP_RST = "1" *)
|
||||
axi_crc_dma_syn_1_rst_ps7_0_100M_0_proc_sys_reset U0
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.interconnect_aresetn(interconnect_aresetn),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.mb_reset(mb_reset),
|
||||
.peripheral_aresetn(peripheral_aresetn),
|
||||
.peripheral_reset(peripheral_reset),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0_cdc_sync
|
||||
(lpf_asr_reg,
|
||||
scndry_out,
|
||||
lpf_asr,
|
||||
p_1_in,
|
||||
p_2_in,
|
||||
asr_lpf,
|
||||
aux_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_asr_reg;
|
||||
output scndry_out;
|
||||
input lpf_asr;
|
||||
input p_1_in;
|
||||
input p_2_in;
|
||||
input [0:0]asr_lpf;
|
||||
input aux_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire asr_d1;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_asr_reg;
|
||||
wire p_1_in;
|
||||
wire p_2_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(asr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
|
||||
(.I0(aux_reset_in),
|
||||
.O(asr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_asr_i_1
|
||||
(.I0(lpf_asr),
|
||||
.I1(p_1_in),
|
||||
.I2(p_2_in),
|
||||
.I3(scndry_out),
|
||||
.I4(asr_lpf),
|
||||
.O(lpf_asr_reg));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "cdc_sync" *)
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0_cdc_sync_0
|
||||
(lpf_exr_reg,
|
||||
scndry_out,
|
||||
lpf_exr,
|
||||
p_1_in4_in,
|
||||
p_2_in3_in,
|
||||
exr_lpf,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
slowest_sync_clk);
|
||||
output lpf_exr_reg;
|
||||
output scndry_out;
|
||||
input lpf_exr;
|
||||
input p_1_in4_in;
|
||||
input p_2_in3_in;
|
||||
input [0:0]exr_lpf;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
|
||||
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
|
||||
wire Q;
|
||||
wire exr_d1;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_exr;
|
||||
wire lpf_exr_reg;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in3_in;
|
||||
wire scndry_out;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(exr_d1),
|
||||
.Q(Q),
|
||||
.R(1'b0));
|
||||
LUT2 #(
|
||||
.INIT(4'hB))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
|
||||
(.I0(mb_debug_sys_rst),
|
||||
.I1(ext_reset_in),
|
||||
.O(exr_d1));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Q),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
|
||||
.Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.R(1'b0));
|
||||
(* ASYNC_REG *)
|
||||
(* XILINX_LEGACY_PRIM = "FDR" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
|
||||
.Q(scndry_out),
|
||||
.R(1'b0));
|
||||
LUT5 #(
|
||||
.INIT(32'hEAAAAAA8))
|
||||
lpf_exr_i_1
|
||||
(.I0(lpf_exr),
|
||||
.I1(p_1_in4_in),
|
||||
.I2(p_2_in3_in),
|
||||
.I3(scndry_out),
|
||||
.I4(exr_lpf),
|
||||
.O(lpf_exr_reg));
|
||||
endmodule
|
||||
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0_lpf
|
||||
(lpf_int,
|
||||
slowest_sync_clk,
|
||||
dcm_locked,
|
||||
mb_debug_sys_rst,
|
||||
ext_reset_in,
|
||||
aux_reset_in);
|
||||
output lpf_int;
|
||||
input slowest_sync_clk;
|
||||
input dcm_locked;
|
||||
input mb_debug_sys_rst;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
|
||||
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
|
||||
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
|
||||
wire Q;
|
||||
wire [0:0]asr_lpf;
|
||||
wire aux_reset_in;
|
||||
wire dcm_locked;
|
||||
wire [0:0]exr_lpf;
|
||||
wire ext_reset_in;
|
||||
wire lpf_asr;
|
||||
wire lpf_exr;
|
||||
wire lpf_int;
|
||||
wire lpf_int0__0;
|
||||
wire mb_debug_sys_rst;
|
||||
wire p_1_in;
|
||||
wire p_1_in4_in;
|
||||
wire p_2_in;
|
||||
wire p_2_in3_in;
|
||||
wire p_3_in1_in;
|
||||
wire p_3_in6_in;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
axi_crc_dma_syn_1_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
|
||||
(.asr_lpf(asr_lpf),
|
||||
.aux_reset_in(aux_reset_in),
|
||||
.lpf_asr(lpf_asr),
|
||||
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.p_1_in(p_1_in),
|
||||
.p_2_in(p_2_in),
|
||||
.scndry_out(p_3_in1_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
axi_crc_dma_syn_1_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
|
||||
(.exr_lpf(exr_lpf),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_exr(lpf_exr),
|
||||
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.p_1_in4_in(p_1_in4_in),
|
||||
.p_2_in3_in(p_2_in3_in),
|
||||
.scndry_out(p_3_in6_in),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[1].asr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in1_in),
|
||||
.Q(p_2_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[2].asr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in),
|
||||
.Q(p_1_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\AUX_LPF[3].asr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in),
|
||||
.Q(asr_lpf),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[1].exr_lpf_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_in6_in),
|
||||
.Q(p_2_in3_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[2].exr_lpf_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_2_in3_in),
|
||||
.Q(p_1_in4_in),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\EXT_LPF[3].exr_lpf_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_1_in4_in),
|
||||
.Q(exr_lpf),
|
||||
.R(1'b0));
|
||||
(* XILINX_LEGACY_PRIM = "SRL16" *)
|
||||
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
(* srl_name = "U0/\\EXT_LPF/POR_SRL_I " *)
|
||||
SRL16E #(
|
||||
.INIT(16'hFFFF))
|
||||
POR_SRL_I
|
||||
(.A0(1'b1),
|
||||
.A1(1'b1),
|
||||
.A2(1'b1),
|
||||
.A3(1'b1),
|
||||
.CE(1'b1),
|
||||
.CLK(slowest_sync_clk),
|
||||
.D(1'b0),
|
||||
.Q(Q));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_asr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
|
||||
.Q(lpf_asr),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_exr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
|
||||
.Q(lpf_exr),
|
||||
.R(1'b0));
|
||||
LUT4 #(
|
||||
.INIT(16'hFFFD))
|
||||
lpf_int0
|
||||
(.I0(dcm_locked),
|
||||
.I1(lpf_exr),
|
||||
.I2(lpf_asr),
|
||||
.I3(Q),
|
||||
.O(lpf_int0__0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
lpf_int_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(lpf_int0__0),
|
||||
.Q(lpf_int),
|
||||
.R(1'b0));
|
||||
endmodule
|
||||
|
||||
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
|
||||
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
|
||||
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0_proc_sys_reset
|
||||
(slowest_sync_clk,
|
||||
ext_reset_in,
|
||||
aux_reset_in,
|
||||
mb_debug_sys_rst,
|
||||
dcm_locked,
|
||||
mb_reset,
|
||||
bus_struct_reset,
|
||||
peripheral_reset,
|
||||
interconnect_aresetn,
|
||||
peripheral_aresetn);
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
|
||||
wire Bsr_out;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire SEQ_n_3;
|
||||
wire SEQ_n_4;
|
||||
wire aux_reset_in;
|
||||
wire [0:0]bus_struct_reset;
|
||||
wire dcm_locked;
|
||||
wire ext_reset_in;
|
||||
wire [0:0]interconnect_aresetn;
|
||||
wire lpf_int;
|
||||
wire mb_debug_sys_rst;
|
||||
wire mb_reset;
|
||||
wire [0:0]peripheral_aresetn;
|
||||
wire [0:0]peripheral_reset;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_3),
|
||||
.Q(interconnect_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b0),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(SEQ_n_4),
|
||||
.Q(peripheral_aresetn),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\BSR_OUT_DFF[0].FDRE_BSR
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Bsr_out),
|
||||
.Q(bus_struct_reset),
|
||||
.R(1'b0));
|
||||
axi_crc_dma_syn_1_rst_ps7_0_100M_0_lpf EXT_LPF
|
||||
(.aux_reset_in(aux_reset_in),
|
||||
.dcm_locked(dcm_locked),
|
||||
.ext_reset_in(ext_reset_in),
|
||||
.lpf_int(lpf_int),
|
||||
.mb_debug_sys_rst(mb_debug_sys_rst),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
FDRE_inst
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(MB_out),
|
||||
.Q(mb_reset),
|
||||
.R(1'b0));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
FDRE #(
|
||||
.INIT(1'b1),
|
||||
.IS_C_INVERTED(1'b0),
|
||||
.IS_D_INVERTED(1'b0),
|
||||
.IS_R_INVERTED(1'b0))
|
||||
\PR_OUT_DFF[0].FDRE_PER
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Pr_out),
|
||||
.Q(peripheral_reset),
|
||||
.R(1'b0));
|
||||
axi_crc_dma_syn_1_rst_ps7_0_100M_0_sequence_psr SEQ
|
||||
(.Bsr_out(Bsr_out),
|
||||
.MB_out(MB_out),
|
||||
.Pr_out(Pr_out),
|
||||
.bsr_reg_0(SEQ_n_3),
|
||||
.lpf_int(lpf_int),
|
||||
.pr_reg_0(SEQ_n_4),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
endmodule
|
||||
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0_sequence_psr
|
||||
(MB_out,
|
||||
Bsr_out,
|
||||
Pr_out,
|
||||
bsr_reg_0,
|
||||
pr_reg_0,
|
||||
lpf_int,
|
||||
slowest_sync_clk);
|
||||
output MB_out;
|
||||
output Bsr_out;
|
||||
output Pr_out;
|
||||
output bsr_reg_0;
|
||||
output pr_reg_0;
|
||||
input lpf_int;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire Bsr_out;
|
||||
wire Core_i_1_n_0;
|
||||
wire MB_out;
|
||||
wire Pr_out;
|
||||
wire \bsr_dec_reg_n_0_[0] ;
|
||||
wire \bsr_dec_reg_n_0_[2] ;
|
||||
wire bsr_i_1_n_0;
|
||||
wire bsr_reg_0;
|
||||
wire \core_dec[0]_i_1_n_0 ;
|
||||
wire \core_dec[2]_i_1_n_0 ;
|
||||
wire \core_dec_reg_n_0_[0] ;
|
||||
wire \core_dec_reg_n_0_[1] ;
|
||||
wire from_sys_i_1_n_0;
|
||||
wire lpf_int;
|
||||
wire p_0_in;
|
||||
wire [2:0]p_3_out;
|
||||
wire [2:0]p_5_out;
|
||||
wire pr_dec0__0;
|
||||
wire \pr_dec_reg_n_0_[0] ;
|
||||
wire \pr_dec_reg_n_0_[2] ;
|
||||
wire pr_i_1_n_0;
|
||||
wire pr_reg_0;
|
||||
wire seq_clr;
|
||||
wire [5:0]seq_cnt;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
|
||||
(.I0(Bsr_out),
|
||||
.O(bsr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
|
||||
(.I0(Pr_out),
|
||||
.O(pr_reg_0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
Core_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(p_0_in),
|
||||
.O(Core_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
Core_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(Core_i_1_n_0),
|
||||
.Q(MB_out),
|
||||
.S(lpf_int));
|
||||
axi_crc_dma_syn_1_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
|
||||
(.Q(seq_cnt),
|
||||
.seq_clr(seq_clr),
|
||||
.seq_cnt_en(seq_cnt_en),
|
||||
.slowest_sync_clk(slowest_sync_clk));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h0090))
|
||||
\bsr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(p_5_out[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\bsr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\bsr_dec_reg_n_0_[0] ),
|
||||
.O(p_5_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[0]),
|
||||
.Q(\bsr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\bsr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_5_out[2]),
|
||||
.Q(\bsr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair4" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
bsr_i_1
|
||||
(.I0(Bsr_out),
|
||||
.I1(\bsr_dec_reg_n_0_[2] ),
|
||||
.O(bsr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
bsr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(bsr_i_1_n_0),
|
||||
.Q(Bsr_out),
|
||||
.S(lpf_int));
|
||||
(* SOFT_HLUTNM = "soft_lutpair2" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h9000))
|
||||
\core_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[4]),
|
||||
.I2(seq_cnt[3]),
|
||||
.I3(seq_cnt[5]),
|
||||
.O(\core_dec[0]_i_1_n_0 ));
|
||||
(* SOFT_HLUTNM = "soft_lutpair6" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\core_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\core_dec_reg_n_0_[0] ),
|
||||
.O(\core_dec[2]_i_1_n_0 ));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[0]_i_1_n_0 ),
|
||||
.Q(\core_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_dec0__0),
|
||||
.Q(\core_dec_reg_n_0_[1] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\core_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(\core_dec[2]_i_1_n_0 ),
|
||||
.Q(p_0_in),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair3" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
from_sys_i_1
|
||||
(.I0(MB_out),
|
||||
.I1(seq_cnt_en),
|
||||
.O(from_sys_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b0))
|
||||
from_sys_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(from_sys_i_1_n_0),
|
||||
.Q(seq_cnt_en),
|
||||
.S(lpf_int));
|
||||
LUT4 #(
|
||||
.INIT(16'h0018))
|
||||
pr_dec0
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[0]),
|
||||
.I2(seq_cnt[2]),
|
||||
.I3(seq_cnt[1]),
|
||||
.O(pr_dec0__0));
|
||||
LUT4 #(
|
||||
.INIT(16'h0480))
|
||||
\pr_dec[0]_i_1
|
||||
(.I0(seq_cnt_en),
|
||||
.I1(seq_cnt[3]),
|
||||
.I2(seq_cnt[5]),
|
||||
.I3(seq_cnt[4]),
|
||||
.O(p_3_out[0]));
|
||||
LUT2 #(
|
||||
.INIT(4'h8))
|
||||
\pr_dec[2]_i_1
|
||||
(.I0(\core_dec_reg_n_0_[1] ),
|
||||
.I1(\pr_dec_reg_n_0_[0] ),
|
||||
.O(p_3_out[2]));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[0]),
|
||||
.Q(\pr_dec_reg_n_0_[0] ),
|
||||
.R(1'b0));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
\pr_dec_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(p_3_out[2]),
|
||||
.Q(\pr_dec_reg_n_0_[2] ),
|
||||
.R(1'b0));
|
||||
(* SOFT_HLUTNM = "soft_lutpair5" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h2))
|
||||
pr_i_1
|
||||
(.I0(Pr_out),
|
||||
.I1(\pr_dec_reg_n_0_[2] ),
|
||||
.O(pr_i_1_n_0));
|
||||
FDSE #(
|
||||
.INIT(1'b1))
|
||||
pr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(pr_i_1_n_0),
|
||||
.Q(Pr_out),
|
||||
.S(lpf_int));
|
||||
FDRE #(
|
||||
.INIT(1'b0))
|
||||
seq_clr_reg
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(1'b1),
|
||||
.D(1'b1),
|
||||
.Q(seq_clr),
|
||||
.R(lpf_int));
|
||||
endmodule
|
||||
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0_upcnt_n
|
||||
(Q,
|
||||
seq_clr,
|
||||
seq_cnt_en,
|
||||
slowest_sync_clk);
|
||||
output [5:0]Q;
|
||||
input seq_clr;
|
||||
input seq_cnt_en;
|
||||
input slowest_sync_clk;
|
||||
|
||||
wire [5:0]Q;
|
||||
wire clear;
|
||||
wire [5:0]q_int0;
|
||||
wire seq_clr;
|
||||
wire seq_cnt_en;
|
||||
wire slowest_sync_clk;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[0]_i_1
|
||||
(.I0(Q[0]),
|
||||
.O(q_int0[0]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT2 #(
|
||||
.INIT(4'h6))
|
||||
\q_int[1]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.O(q_int0[1]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair1" *)
|
||||
LUT3 #(
|
||||
.INIT(8'h78))
|
||||
\q_int[2]_i_1
|
||||
(.I0(Q[0]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[2]),
|
||||
.O(q_int0[2]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT4 #(
|
||||
.INIT(16'h7F80))
|
||||
\q_int[3]_i_1
|
||||
(.I0(Q[1]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[2]),
|
||||
.I3(Q[3]),
|
||||
.O(q_int0[3]));
|
||||
(* SOFT_HLUTNM = "soft_lutpair0" *)
|
||||
LUT5 #(
|
||||
.INIT(32'h7FFF8000))
|
||||
\q_int[4]_i_1
|
||||
(.I0(Q[2]),
|
||||
.I1(Q[0]),
|
||||
.I2(Q[1]),
|
||||
.I3(Q[3]),
|
||||
.I4(Q[4]),
|
||||
.O(q_int0[4]));
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\q_int[5]_i_1
|
||||
(.I0(seq_clr),
|
||||
.O(clear));
|
||||
LUT6 #(
|
||||
.INIT(64'h7FFFFFFF80000000))
|
||||
\q_int[5]_i_2
|
||||
(.I0(Q[3]),
|
||||
.I1(Q[1]),
|
||||
.I2(Q[0]),
|
||||
.I3(Q[2]),
|
||||
.I4(Q[4]),
|
||||
.I5(Q[5]),
|
||||
.O(q_int0[5]));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[0]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[0]),
|
||||
.Q(Q[0]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[1]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[1]),
|
||||
.Q(Q[1]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[2]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[2]),
|
||||
.Q(Q[2]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[3]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[3]),
|
||||
.Q(Q[3]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[4]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[4]),
|
||||
.Q(Q[4]),
|
||||
.R(clear));
|
||||
FDRE #(
|
||||
.INIT(1'b1))
|
||||
\q_int_reg[5]
|
||||
(.C(slowest_sync_clk),
|
||||
.CE(seq_cnt_en),
|
||||
.D(q_int0[5]),
|
||||
.Q(Q[5]),
|
||||
.R(clear));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Feb 7 16:13:54 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top axi_crc_dma_syn_1_rst_ps7_0_100M_0 -prefix
|
||||
// axi_crc_dma_syn_1_rst_ps7_0_100M_0_ axi_crc_dma_syn_1_rst_ps7_0_100M_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_rst_ps7_0_100M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "proc_sys_reset,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
|
||||
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
|
||||
interconnect_aresetn, peripheral_aresetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */
|
||||
/* synthesis syn_force_seq_prim="slowest_sync_clk" */;
|
||||
input slowest_sync_clk /* synthesis syn_isclock = 1 */;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
endmodule
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_rst_ps7_0_100M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END axi_crc_dma_syn_1_rst_ps7_0_100M_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch OF axi_crc_dma_syn_1_rst_ps7_0_100M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY axi_crc_dma_syn_1_rst_ps7_0_100M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END axi_crc_dma_syn_1_rst_ps7_0_100M_0;
|
||||
|
||||
ARCHITECTURE axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch OF axi_crc_dma_syn_1_rst_ps7_0_100M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "axi_crc_dma_syn_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "axi_crc_dma_syn_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN axi_crc_dma_syn_1_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END axi_crc_dma_syn_1_rst_ps7_0_100M_0_arch;
|
||||
+38102
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name clk [get_ports clk]
|
||||
|
||||
|
||||
+73660
File diff suppressed because one or more lines are too long
+91
@@ -0,0 +1,91 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sat Feb 8 17:01:56 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/aci_crc_dma/aci_crc_dma.gen/sources_1/bd/axi_crc_dma_syn_1/ip/axi_crc_dma_syn_1_system_ila_0_0/axi_crc_dma_syn_1_system_ila_0_0_stub.v
|
||||
// Design : axi_crc_dma_syn_1_system_ila_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "bd_2505,Vivado 2023.1" *)
|
||||
module axi_crc_dma_syn_1_system_ila_0_0(clk, probe0, probe1, SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awprot, SLOT_0_AXI_awvalid, SLOT_0_AXI_awready, SLOT_0_AXI_wdata,
|
||||
SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid, SLOT_0_AXI_wready, SLOT_0_AXI_bresp,
|
||||
SLOT_0_AXI_bvalid, SLOT_0_AXI_bready, SLOT_0_AXI_araddr, SLOT_0_AXI_arprot,
|
||||
SLOT_0_AXI_arvalid, SLOT_0_AXI_arready, SLOT_0_AXI_rdata, SLOT_0_AXI_rresp,
|
||||
SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, SLOT_1_AXI_awid, SLOT_1_AXI_awaddr,
|
||||
SLOT_1_AXI_awlen, SLOT_1_AXI_awsize, SLOT_1_AXI_awburst, SLOT_1_AXI_awcache,
|
||||
SLOT_1_AXI_awprot, SLOT_1_AXI_awvalid, SLOT_1_AXI_awready, SLOT_1_AXI_wid,
|
||||
SLOT_1_AXI_wdata, SLOT_1_AXI_wstrb, SLOT_1_AXI_wlast, SLOT_1_AXI_wvalid,
|
||||
SLOT_1_AXI_wready, SLOT_1_AXI_bid, SLOT_1_AXI_bresp, SLOT_1_AXI_bvalid,
|
||||
SLOT_1_AXI_bready, SLOT_1_AXI_arid, SLOT_1_AXI_araddr, SLOT_1_AXI_arlen,
|
||||
SLOT_1_AXI_arsize, SLOT_1_AXI_arburst, SLOT_1_AXI_arcache, SLOT_1_AXI_arprot,
|
||||
SLOT_1_AXI_arvalid, SLOT_1_AXI_arready, SLOT_1_AXI_rid, SLOT_1_AXI_rdata,
|
||||
SLOT_1_AXI_rresp, SLOT_1_AXI_rlast, SLOT_1_AXI_rvalid, SLOT_1_AXI_rready, resetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="probe0[0:0],probe1[0:0],SLOT_0_AXI_awaddr[7:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[7:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_AXI_awid[0:0],SLOT_1_AXI_awaddr[31:0],SLOT_1_AXI_awlen[3:0],SLOT_1_AXI_awsize[2:0],SLOT_1_AXI_awburst[1:0],SLOT_1_AXI_awcache[3:0],SLOT_1_AXI_awprot[2:0],SLOT_1_AXI_awvalid,SLOT_1_AXI_awready,SLOT_1_AXI_wid[0:0],SLOT_1_AXI_wdata[31:0],SLOT_1_AXI_wstrb[3:0],SLOT_1_AXI_wlast,SLOT_1_AXI_wvalid,SLOT_1_AXI_wready,SLOT_1_AXI_bid[0:0],SLOT_1_AXI_bresp[1:0],SLOT_1_AXI_bvalid,SLOT_1_AXI_bready,SLOT_1_AXI_arid[0:0],SLOT_1_AXI_araddr[31:0],SLOT_1_AXI_arlen[3:0],SLOT_1_AXI_arsize[2:0],SLOT_1_AXI_arburst[1:0],SLOT_1_AXI_arcache[3:0],SLOT_1_AXI_arprot[2:0],SLOT_1_AXI_arvalid,SLOT_1_AXI_arready,SLOT_1_AXI_rid[0:0],SLOT_1_AXI_rdata[31:0],SLOT_1_AXI_rresp[1:0],SLOT_1_AXI_rlast,SLOT_1_AXI_rvalid,SLOT_1_AXI_rready,resetn" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [7:0]SLOT_0_AXI_awaddr;
|
||||
input [2:0]SLOT_0_AXI_awprot;
|
||||
input SLOT_0_AXI_awvalid;
|
||||
input SLOT_0_AXI_awready;
|
||||
input [31:0]SLOT_0_AXI_wdata;
|
||||
input [3:0]SLOT_0_AXI_wstrb;
|
||||
input SLOT_0_AXI_wvalid;
|
||||
input SLOT_0_AXI_wready;
|
||||
input [1:0]SLOT_0_AXI_bresp;
|
||||
input SLOT_0_AXI_bvalid;
|
||||
input SLOT_0_AXI_bready;
|
||||
input [7:0]SLOT_0_AXI_araddr;
|
||||
input [2:0]SLOT_0_AXI_arprot;
|
||||
input SLOT_0_AXI_arvalid;
|
||||
input SLOT_0_AXI_arready;
|
||||
input [31:0]SLOT_0_AXI_rdata;
|
||||
input [1:0]SLOT_0_AXI_rresp;
|
||||
input SLOT_0_AXI_rvalid;
|
||||
input SLOT_0_AXI_rready;
|
||||
input [0:0]SLOT_1_AXI_awid;
|
||||
input [31:0]SLOT_1_AXI_awaddr;
|
||||
input [3:0]SLOT_1_AXI_awlen;
|
||||
input [2:0]SLOT_1_AXI_awsize;
|
||||
input [1:0]SLOT_1_AXI_awburst;
|
||||
input [3:0]SLOT_1_AXI_awcache;
|
||||
input [2:0]SLOT_1_AXI_awprot;
|
||||
input SLOT_1_AXI_awvalid;
|
||||
input SLOT_1_AXI_awready;
|
||||
input [0:0]SLOT_1_AXI_wid;
|
||||
input [31:0]SLOT_1_AXI_wdata;
|
||||
input [3:0]SLOT_1_AXI_wstrb;
|
||||
input SLOT_1_AXI_wlast;
|
||||
input SLOT_1_AXI_wvalid;
|
||||
input SLOT_1_AXI_wready;
|
||||
input [0:0]SLOT_1_AXI_bid;
|
||||
input [1:0]SLOT_1_AXI_bresp;
|
||||
input SLOT_1_AXI_bvalid;
|
||||
input SLOT_1_AXI_bready;
|
||||
input [0:0]SLOT_1_AXI_arid;
|
||||
input [31:0]SLOT_1_AXI_araddr;
|
||||
input [3:0]SLOT_1_AXI_arlen;
|
||||
input [2:0]SLOT_1_AXI_arsize;
|
||||
input [1:0]SLOT_1_AXI_arburst;
|
||||
input [3:0]SLOT_1_AXI_arcache;
|
||||
input [2:0]SLOT_1_AXI_arprot;
|
||||
input SLOT_1_AXI_arvalid;
|
||||
input SLOT_1_AXI_arready;
|
||||
input [0:0]SLOT_1_AXI_rid;
|
||||
input [31:0]SLOT_1_AXI_rdata;
|
||||
input [1:0]SLOT_1_AXI_rresp;
|
||||
input SLOT_1_AXI_rlast;
|
||||
input SLOT_1_AXI_rvalid;
|
||||
input SLOT_1_AXI_rready;
|
||||
input resetn;
|
||||
endmodule
|
||||
+1492
File diff suppressed because it is too large
Load Diff
+50
@@ -0,0 +1,50 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_2505" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1739031744"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1739031744"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1739031744"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1739031744"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_2505.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_2505.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_2505.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_2505_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\axi_crc_dma_syn_1_system_ila_0_0.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\axi_crc_dma_syn_1_system_ila_0_0.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Command: generate_target bd_2505_wrapper.bd
|
||||
--Design : bd_2505_wrapper
|
||||
--Purpose: IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity bd_2505_wrapper is
|
||||
port (
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_arready : in STD_LOGIC;
|
||||
SLOT_1_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_awready : in STD_LOGIC;
|
||||
SLOT_1_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_bready : in STD_LOGIC;
|
||||
SLOT_1_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_rlast : in STD_LOGIC;
|
||||
SLOT_1_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_wlast : in STD_LOGIC;
|
||||
SLOT_1_AXI_wready : in STD_LOGIC;
|
||||
SLOT_1_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_wvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end bd_2505_wrapper;
|
||||
|
||||
architecture STRUCTURE of bd_2505_wrapper is
|
||||
component bd_2505 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
resetn : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_arready : in STD_LOGIC;
|
||||
SLOT_1_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_awready : in STD_LOGIC;
|
||||
SLOT_1_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_1_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_bready : in STD_LOGIC;
|
||||
SLOT_1_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_rlast : in STD_LOGIC;
|
||||
SLOT_1_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_1_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_1_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_1_AXI_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
SLOT_1_AXI_wlast : in STD_LOGIC;
|
||||
SLOT_1_AXI_wready : in STD_LOGIC;
|
||||
SLOT_1_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_1_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 )
|
||||
);
|
||||
end component bd_2505;
|
||||
begin
|
||||
bd_2505_i: component bd_2505
|
||||
port map (
|
||||
SLOT_0_AXI_araddr(7 downto 0) => SLOT_0_AXI_araddr(7 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => SLOT_0_AXI_arprot(2 downto 0),
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_awaddr(7 downto 0) => SLOT_0_AXI_awaddr(7 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => SLOT_0_AXI_awprot(2 downto 0),
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_bready => SLOT_0_AXI_bready,
|
||||
SLOT_0_AXI_bresp(1 downto 0) => SLOT_0_AXI_bresp(1 downto 0),
|
||||
SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
|
||||
SLOT_0_AXI_rdata(31 downto 0) => SLOT_0_AXI_rdata(31 downto 0),
|
||||
SLOT_0_AXI_rready => SLOT_0_AXI_rready,
|
||||
SLOT_0_AXI_rresp(1 downto 0) => SLOT_0_AXI_rresp(1 downto 0),
|
||||
SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
|
||||
SLOT_0_AXI_wdata(31 downto 0) => SLOT_0_AXI_wdata(31 downto 0),
|
||||
SLOT_0_AXI_wready => SLOT_0_AXI_wready,
|
||||
SLOT_0_AXI_wstrb(3 downto 0) => SLOT_0_AXI_wstrb(3 downto 0),
|
||||
SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
|
||||
SLOT_1_AXI_araddr(31 downto 0) => SLOT_1_AXI_araddr(31 downto 0),
|
||||
SLOT_1_AXI_arburst(1 downto 0) => SLOT_1_AXI_arburst(1 downto 0),
|
||||
SLOT_1_AXI_arcache(3 downto 0) => SLOT_1_AXI_arcache(3 downto 0),
|
||||
SLOT_1_AXI_arid(0) => SLOT_1_AXI_arid(0),
|
||||
SLOT_1_AXI_arlen(3 downto 0) => SLOT_1_AXI_arlen(3 downto 0),
|
||||
SLOT_1_AXI_arprot(2 downto 0) => SLOT_1_AXI_arprot(2 downto 0),
|
||||
SLOT_1_AXI_arready => SLOT_1_AXI_arready,
|
||||
SLOT_1_AXI_arsize(2 downto 0) => SLOT_1_AXI_arsize(2 downto 0),
|
||||
SLOT_1_AXI_arvalid => SLOT_1_AXI_arvalid,
|
||||
SLOT_1_AXI_awaddr(31 downto 0) => SLOT_1_AXI_awaddr(31 downto 0),
|
||||
SLOT_1_AXI_awburst(1 downto 0) => SLOT_1_AXI_awburst(1 downto 0),
|
||||
SLOT_1_AXI_awcache(3 downto 0) => SLOT_1_AXI_awcache(3 downto 0),
|
||||
SLOT_1_AXI_awid(0) => SLOT_1_AXI_awid(0),
|
||||
SLOT_1_AXI_awlen(3 downto 0) => SLOT_1_AXI_awlen(3 downto 0),
|
||||
SLOT_1_AXI_awprot(2 downto 0) => SLOT_1_AXI_awprot(2 downto 0),
|
||||
SLOT_1_AXI_awready => SLOT_1_AXI_awready,
|
||||
SLOT_1_AXI_awsize(2 downto 0) => SLOT_1_AXI_awsize(2 downto 0),
|
||||
SLOT_1_AXI_awvalid => SLOT_1_AXI_awvalid,
|
||||
SLOT_1_AXI_bid(0) => SLOT_1_AXI_bid(0),
|
||||
SLOT_1_AXI_bready => SLOT_1_AXI_bready,
|
||||
SLOT_1_AXI_bresp(1 downto 0) => SLOT_1_AXI_bresp(1 downto 0),
|
||||
SLOT_1_AXI_bvalid => SLOT_1_AXI_bvalid,
|
||||
SLOT_1_AXI_rdata(31 downto 0) => SLOT_1_AXI_rdata(31 downto 0),
|
||||
SLOT_1_AXI_rid(0) => SLOT_1_AXI_rid(0),
|
||||
SLOT_1_AXI_rlast => SLOT_1_AXI_rlast,
|
||||
SLOT_1_AXI_rready => SLOT_1_AXI_rready,
|
||||
SLOT_1_AXI_rresp(1 downto 0) => SLOT_1_AXI_rresp(1 downto 0),
|
||||
SLOT_1_AXI_rvalid => SLOT_1_AXI_rvalid,
|
||||
SLOT_1_AXI_wdata(31 downto 0) => SLOT_1_AXI_wdata(31 downto 0),
|
||||
SLOT_1_AXI_wid(0) => SLOT_1_AXI_wid(0),
|
||||
SLOT_1_AXI_wlast => SLOT_1_AXI_wlast,
|
||||
SLOT_1_AXI_wready => SLOT_1_AXI_wready,
|
||||
SLOT_1_AXI_wstrb(3 downto 0) => SLOT_1_AXI_wstrb(3 downto 0),
|
||||
SLOT_1_AXI_wvalid => SLOT_1_AXI_wvalid,
|
||||
clk => clk,
|
||||
probe0(0) => probe0(0),
|
||||
probe1(0) => probe1(0),
|
||||
resetn => resetn
|
||||
);
|
||||
end STRUCTURE;
|
||||
+6348
File diff suppressed because it is too large
Load Diff
+75036
File diff suppressed because it is too large
Load Diff
+69
@@ -0,0 +1,69 @@
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for ILA core
|
||||
|
||||
|
||||
|
||||
create_clock -name ILA_CLK -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+103
@@ -0,0 +1,103 @@
|
||||
##
|
||||
## ARM and HALT transfer false paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Register False Paths
|
||||
##
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
|
||||
#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
|
||||
|
||||
##
|
||||
## ILA Capture Block False Paths
|
||||
##
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Capture State to XSDB register False Paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
|
||||
|
||||
|
||||
##
|
||||
## Waivers
|
||||
##
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
|
||||
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY bd_2505_ila_lib_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
|
||||
|
||||
probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe26 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe28 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe30 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe32 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe33 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe34 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe35 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe36 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe37 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe38 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe39 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe40 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe41 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe42 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe43 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe44 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe45 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe46 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe47 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe48 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe49 : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
|
||||
);
|
||||
END bd_2505_ila_lib_0;
|
||||
|
||||
ARCHITECTURE bd_2505_ila_lib_0_arch OF bd_2505_ila_lib_0 IS
|
||||
BEGIN
|
||||
END bd_2505_ila_lib_0_arch;
|
||||
+8435
File diff suppressed because it is too large
Load Diff
+3134
File diff suppressed because it is too large
Load Diff
+114004
File diff suppressed because it is too large
Load Diff
+4954
File diff suppressed because it is too large
Load Diff
+4396
File diff suppressed because it is too large
Load Diff
+4456
File diff suppressed because it is too large
Load Diff
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_2505_slot_1_b_0",
|
||||
"cell_name": "slot_1_b",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_2505_slot_1_b_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
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"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+5065
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_2505_slot_1_b_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_2505_slot_1_b_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_2505_slot_1_b_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
|
||||
=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
|
||||
2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
|
||||
TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_2505_slot_1_b_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_2505_slot_1_ar_0",
|
||||
"cell_name": "slot_1_ar",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_2505_slot_1_ar_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+5065
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_2505_slot_1_ar_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_2505_slot_1_ar_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_2505_slot_1_ar_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDT\
|
||||
H=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN\
|
||||
62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WI\
|
||||
DTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_2505_slot_1_ar_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+308
@@ -0,0 +1,308 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_2505_slot_1_r_0",
|
||||
"cell_name": "slot_1_r",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_2505_slot_1_r_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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}
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}
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+5066
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Reference in New Issue
Block a user