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CRC Testbench + axr_crc architecture

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This commit is contained in:
Matthias Biermann
2025-01-26 14:17:13 +01:00
parent 4e34f728b4
commit 8a141b47ff
11 changed files with 479 additions and 261 deletions
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ES_Grobkonzept.pdf
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Hardware/CRC.vhd
+63 -63
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@@ -1,63 +1,63 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CRC is
generic (
crcLength : positive;
inDataLength : positive
);
port (
CLK : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
initialValue : in std_logic_vector(crcLength-1 downto 0);
polynomial : in std_logic_vector(crcLength-1 downto 0);
-- Datensignale
inData : in std_logic_vector(inDataLength-1 downto 0);
checksum : out std_logic_vector(crcLength-1 downto 0)
);
end CRC;
architecture rtl of CRC is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (inData, checksum_i)
variable mix: std_logic_vector(crcLength-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in inData'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & inData(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (CLK)
begin
if rising_edge(CLK) then
if reset = '1' then
checksum_i <= initialValue;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity crc is
generic (
crcLength : positive;
inDataLength : positive
);
port (
clk : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
initialValue : in std_logic_vector(crcLength-1 downto 0);
polynomial : in std_logic_vector(crcLength-1 downto 0);
-- Datensignale
inData : in std_logic_vector(inDataLength-1 downto 0);
checksum : out std_logic_vector(crcLength-1 downto 0)
);
end crc;
architecture Behavioral of crc is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (inData, checksum_i)
variable mix: std_logic_vector(crcLength-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in inData'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & inData(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
checksum_i <= initialValue;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end Behavioral;
Hardware/axi_crc/axi_crc.srcs/sources_1/new/axi_crc.vhd → Hardware/axi_crc.vhd
+29 -4
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@@ -5,8 +5,7 @@ use IEEE.NUMERIC_STD.ALL;
entity axi_crc is
generic (
DATA_WIDTH : integer := 32; -- Datenwortbreite
ID_WIDTH : integer := 4; -- AXI ID Wortbreite
ID_WIDTH : integer := 4; -- AXI ID Wortbreite
ID_WIDTH : integer := 4 -- AXI ID Wortbreite
);
port (
CLK : in std_logic;
@@ -67,14 +66,40 @@ entity axi_crc is
S_AXIL_RDATA : out std_logic_vector(31 downto 0);
S_AXIL_RVALID : out std_logic;
S_AXIL_RREADY : in std_logic;
S_AXIL_RRESP : out std_logic_vector(1 downto 0);
S_AXIL_RRESP : out std_logic_vector(1 downto 0)
);
end axi_crc;
architecture rtl of axi_crc is
-- AXIL Registers
-- signal
begin
----------------------------------------------------------------------------
-- AXIL Interface
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- AXI Master Interface to Memory
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CRC Calculation component
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Main control state machine
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Block RAM Memory
----------------------------------------------------------------------------
end Behavioral;
Hardware/axi_crc/.gitignore
+89
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@@ -0,0 +1,89 @@
# Created by https://www.toptal.com/developers/gitignore/api/vivado
# Edit at https://www.toptal.com/developers/gitignore?templates=vivado
### Vivado ###
#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########
#Exclude all
*
!*/
!.gitignore
###########################################################################
## VIVADO
#Source files:
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.sv
!*.bd
!*.edif
#IP files
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#.xcix: Core container file
#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41)
!*.xcix
#*.dcp(checkpoint files)
!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#System Generator
!*.mdl
!*.slx
!*.bxml
#Simulation logic analyzer
!*.wcfg
!*.coe
#MIG
!*.prj
!*.mem
#Project files
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#Constraint files
#Do NOT ignore *.xdc files
!*.xdc
#TCL - files
!*.tcl
#Journal - files
!*.jou
#Reports
!*.rpt
!*.txt
!*.vdi
#C-files
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
# End of https://www.toptal.com/developers/gitignore/api/vivado
# Vidado project directories which are not needed
.Xil/
*.cache/
*.hw/
*.ip_user_files/
*.runs/
*.sim/
# design checkpoint file
*.dcp
# ignore Vivado log files
*.log
*.jou
vivado_pid*.str
# DO NOT ignore images as bitmap files
!*.bmp
Hardware/axi_crc/axi_crc.cache/wt/project.wpc
+1 -1
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@@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
6d6f64655f636f756e7465727c4755494d6f6465:2
eof:
Hardware/axi_crc/axi_crc.srcs/sources_1/new/crc.vhd
-63
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@@ -1,63 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity crc is
generic (
crcLength : positive;
inDataLength : positive
);
port (
clk : in std_logic;
-- Kontrollsignale
reset : in std_logic;
enable : in std_logic;
initialValue : in std_logic_vector(crcLength-1 downto 0);
polynomial : in std_logic_vector(crcLength-1 downto 0);
-- Datensignale
inData : in std_logic_vector(inDataLength-1 downto 0);
checksum : out std_logic_vector(crcLength-1 downto 0)
);
end crc;
architecture Behavioral of crc is
-- Interne Signale fuer CRC Pruefsumme
signal checksum_i : std_logic_vector(crcLength-1 downto 0);
signal nextChecksum : std_logic_vector(crcLength-1 downto 0);
begin
-- Kombinatorik fuer CRC-Berechnung
ProcNextCRC: process (inData, checksum_i)
variable mix: std_logic_vector(crcLength-1 downto 0);
variable MSB : std_logic;
begin
mix := checksum_i;
for i in inData'range loop
-- Pruefen ob MSB gesetzt ist
MSB := mix(mix'length-1);
-- neues Bit reinschieben
mix := mix(mix'length-2 downto 0) & inData(i);
-- XOR Verknuepfung
if MSB = '1' then
mix := mix XOR polynomial;
end if;
end loop;
nextChecksum <= mix;
end process;
-- Register zum Speichern der CRC-Pruefsumme
Reg: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
checksum_i <= initialValue;
elsif enable = '1' then
checksum_i <= nextChecksum;
end if;
end if;
end process;
checksum <= checksum_i;
end Behavioral;
Hardware/axi_crc/axi_crc.xpr
+13 -17
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="9"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -91,22 +91,15 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/axi_crc.vhd">
<File Path="$PPRDIR/../crc.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/crc.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_crc"/>
<Option Name="TopModule" Val="crc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
@@ -117,9 +110,16 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../crc_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_crc"/>
<Option Name="TopModule" Val="CRC_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
@@ -160,9 +160,7 @@
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -171,9 +169,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
Hardware/crc_tb.vhd
+132
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@@ -0,0 +1,132 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CRC_tb is
end;
architecture testbench of CRC_tb is
constant CLK_PERIOD : time := 8 ns;
constant crcLength : positive := 32;
constant inDataLength : positive := 8;
signal CLK : std_logic := '0';
signal reset : std_logic;
signal enable : std_logic;
signal initialValue : std_logic_vector(crcLength-1 downto 0) := x"00000000";
signal polynomial : std_logic_vector(crcLength-1 downto 0) := x"04C11DB7";
signal inData : std_logic_vector(inDataLength-1 downto 0);
signal checksum : std_logic_vector(crcLength-1 downto 0);
type testdaten_t is array (natural range<>, natural range<>) of std_logic_vector(inDataLength-1 downto 0);
type checksums_t is array (natural range<>) of std_logic_vector(crcLength-1 downto 0);
type pruefsummen_t is array (natural range<>, natural range<>, natural range<>) of std_logic_vector(crcLength-1 downto 0);
-- Testdaten fuer die CRC-Pruefsummen
constant testdaten : testdaten_t := (
(x"11", x"22", x"33", x"44", x"55", x"66", x"77", x"88"), -- Test 3.0
(x"99", x"AA", x"BB", x"CC", x"DD", x"EE", x"FF", x"11"), -- Test 3.1
(x"12", x"23", x"45", x"67", x"89", x"AB", x"CD", x"DE") -- Test 3.2
);
-- Generatorpolynome
constant polynomials : checksums_t := (
x"04C11DB7", -- Test 3.0
x"1EDC6F41", -- Test 3.1
x"A833982B" -- Test 3.2
);
constant initialValues : checksums_t := (
x"00000000",
x"FFFFFFFF"
);
-- CRC Pruefsummen der Testdaten, berechnet mit crc.c
constant pruefsummen : pruefsummen_t := (
((x"2320fd3f", x"4a244666"),(x"0011be5f", x"aea35591"),(x"a0e0fa80", x"03bc523e")),
((x"51f76195", x"38f3dacc"),(x"5f023f32", x"f1b0d4fc"),(x"73b55630", x"d0e9fe8e")),
((x"9f40b766", x"f6440c3f"),(x"ef3b8a49", x"41896187"),(x"1bfa029d", x"b8a6aa23"))
);
begin
clk_proc: process
begin
wait for CLK_PERIOD / 2;
CLK <= not CLK;
end process;
Stim: process
begin
enable <= '0';
reset <= '0';
wait until rising_edge(CLK);
-- Testen des Resets
report "Test 1: Testen des Resets";
reset <= '1';
wait until rising_edge(CLK);
reset <= '0';
wait until rising_edge(CLK);
assert checksum = initialValue report "Fehler beim Reset" severity failure;
-- Testen des Enable
report "Test 2: Testen des Enable";
inData <= (inDataLength-1 downto 8 =>'0') & x"a4";
wait until rising_edge(CLK);
assert checksum = initialValue report "Fehler. Pruefsumme wird ohne enable-Signal berechnet" severity failure;
enable <= '1';
wait until rising_edge(CLK);
enable <= '0';
wait until rising_edge(CLK);
assert checksum /= initialValue report "Fehler. Pruefsumme wird trotz enable Signal nicht berechnet" severity error;
wait until rising_edge(CLK);
report "Test 3: Berechnen von CRC-Pruefsummen";
for testfall in testdaten'range(1) loop
for polynom in polynomials'range loop
for initialwert in initialValues'range loop
polynomial <= polynomials(polynom);
initialValue <= initialValues(initialwert);
reset <= '1'; -- Zuruecksetzen
wait until rising_edge(CLK);
reset <= '0';
report "Beginn Test 3." & natural'image(testfall);
enable <= '1';
for byte in testdaten'range(2) loop
inData <= testdaten(testfall, byte);
wait until rising_edge(CLK);
end loop;
enable <= '0';
wait until rising_edge(CLK);
assert checksum = pruefsummen(testfall, polynom, initialwert) report "Falscher Wert fuer CRC-Pruefsumme" severity failure;
report "Test 3." & natural'image(testfall) &"."& natural'image(polynom) &"."& natural'image(initialwert) & ": Ohne Fehler.";
end loop;
end loop;
end loop;
report "ALLE TESTFAELLE ABGESCHLOSSEN";
wait;
end process;
uut: entity work.CRC
generic map (
crcLength => crcLength,
inDataLength => inDataLength
)
port map (
CLK => CLK,
reset => reset,
polynomial => polynomial,
initialValue => initialValue,
enable => enable,
inData => inData,
checksum => checksum
);
end architecture;
Konzept/ES_Grobkonzept.pdf
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Konzept/crc-axi Architecture Blockschaltplan.pdf
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Software/CRC_Test/crc.c
+152 -113
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@@ -1,114 +1,153 @@
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
// Berechnen einer 8 Bit CRC-Pruefsumme
uint8_t crc8(uint8_t* data, size_t size);
// Berechnen einer 32 Bit CRC-Pruefsumme
uint32_t crc32(uint8_t* inBytes, size_t size, uint32_t polynomial);
// Check einer 32 Bit CRC-Pruefsumme
int checkCrc32(uint8_t* data, size_t size, uint32_t crc, uint32_t polynomial);
int main()
{
char msg[] = "Hello World!\0\0\0\0";
uint32_t crc = crc32((uint8_t*) msg, strlen(msg)+4, 0x4C11DB7);
printf("CRC32 of '%s': 0x%08x\n\n", msg, crc);
int crcValid = checkCrc32((uint8_t*) msg, strlen(msg), crc, 0x4C11DB7);
// String einlesen und CRC32 ausgeben
// char input[1024];
// printf("String eingeben:\n");
// while (1)
// {
// // Liest eine Zeile von stdin ein und speichert sie in 'eingabe'
// if (fgets(input, sizeof(input), stdin) != NULL) {
// // Entfernt das Newline-Zeichen, das fgets hinzufügt
// size_t laenge = strlen(input);
// if (laenge > 0 && input[laenge - 1] == '\n') {
// input[laenge - 1] = '\0';
// }
// }
// crc = crc32((uint8_t*) input, strlen(input));
// printf("'%s' -> 0x%08x\n\n", input, crc);
// }
return 0;
}
uint8_t crc8(uint8_t* inBytes, size_t size)
{
uint8_t crc = 0x0; // initial value
uint8_t polynomial = 0x7;
for (size_t i = 0; i < size; i++) {
for (int bit = 7; bit >= 0; bit--) {
// get next bit
uint8_t inBit = (inBytes[i] & (1<<bit)) ? 1 : 0;
// check if MSB is set
uint8_t MSB_high = crc & 0x80;
// input Bit reinschieben
crc = (uint8_t) (crc << 1);
crc ^= inBit;
if (MSB_high) {
crc ^= polynomial;
}
// for (int in = 0; in < 8; in++) {
// printf("%d", !!((crc << in) & 0x80));
// }
// printf("\n");
}
}
return crc;
}
uint32_t crc32(uint8_t* inBytes, size_t size, uint32_t polynomial)
{
uint32_t crc = 0x0; // initial value
for (size_t i = 0; i < size; i++) {
for (int bit = 7; bit >= 0; bit--) {
// get next bit
uint8_t inBit = (inBytes[i] & (1<<bit)) ? 1 : 0;
// check if MSB is set
uint32_t MSB_high = crc & 0x80000000;
// input Bit reinschieben
crc <<= 1;
crc ^= inBit;
if (MSB_high) {
crc ^= polynomial;
}
// for (int in = 0; in < 8; in++) {
// printf("%d", !!((crc << in) & 0x80));
// }
// printf("\n");
}
// printf("0x%x\n", crc);
}
return crc;
}
int checkCrc32(uint8_t* data, size_t size, uint32_t crc, uint32_t polynomial)
{
// Daten und CRC zusammenhaengend in den HEAP Speicher kopieren
uint8_t *dataCrc = malloc(size + 4);
memcpy_s(dataCrc, size+4, data, size);
for (uint32_t i = 0; i < 4; i++) {
dataCrc[size+i] = (crc >> (24 - 8 * i)) & 0xFF; // Extract the MSB first
}
// CRC von Daten mit CRC-Pruefsumme berechnen
// Bei validen Daten bzw. Pruefsumme kommt Null heraus
if (crc32(dataCrc, size+4, polynomial) == 0) return 1;
else return 0;
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
// Berechnen einer 8 Bit CRC-Pruefsumme
uint8_t crc8(uint8_t* data, size_t size);
// Berechnen einer 32 Bit CRC-Pruefsumme
uint32_t crc32(uint8_t* inBytes, size_t size, uint32_t polynomial, uint32_t initialValue);
// Check einer 32 Bit CRC-Pruefsumme
int checkCrc32(uint8_t* data, size_t size, uint32_t crc, uint32_t polynomial);
// Berechnung der Pruefsummen fuer crc_tb
void calc_testcases();
int main()
{
// Testweise Pruefsumme berechnen und ausgeben
char msg[] = "Hello World!\0\0\0\0";
uint32_t crc = crc32((uint8_t*) msg, strlen(msg)+4, 0x4C11DB7, 0x0);
printf("CRC32 of '%s': 0x%08x\n\n", msg, crc);
int crcValid = checkCrc32((uint8_t*) msg, strlen(msg), crc, 0x4C11DB7);
calc_testcases();
// String einlesen und CRC32 ausgeben
// char input[1024];
// printf("String eingeben:\n");
// while (1)
// {
// // Liest eine Zeile von stdin ein und speichert sie in 'eingabe'
// if (fgets(input, sizeof(input), stdin) != NULL) {
// // Entfernt das Newline-Zeichen, das fgets hinzufügt
// size_t laenge = strlen(input);
// if (laenge > 0 && input[laenge - 1] == '\n') {
// input[laenge - 1] = '\0';
// }
// }
// crc = crc32((uint8_t*) input, strlen(input));
// printf("'%s' -> 0x%08x\n\n", input, crc);
// }
return 0;
}
// Berechnung der Pruefsummen fuer crc_tb
void calc_testcases()
{
// CRC-Pruefsummen fuer Testbench crc_tb berechnen
uint8_t testcases[11][11] = {
{8, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88}, // CRC_tb
{8, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF, 0x11}, // CRC_tb
{8, 0x12, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xDE}, // CRC_tb
};
uint32_t testPolynomials[3] = {
0x4C11DB7,
0x1EDC6F41,
0xA833982B,
};
uint32_t initalValues[2] = {
0x0,
0xFFFFFFFF,
};
for (int testcase = 0; testcase < 3; testcase++) {
for (int polynomial = 0; polynomial < 3; polynomial++) {
for (int intialValue = 0; intialValue < 2; intialValue++) {
uint32_t checksum;
checksum = crc32(testcases[testcase]+1, testcases[testcase][0], testPolynomials[polynomial], initalValues[intialValue]);
printf("Testfall %d, polynom %d, iV %d: x\"%08x\"\n", testcase, polynomial, intialValue, checksum);
}
}
}
}
uint8_t crc8(uint8_t* inBytes, size_t size)
{
uint8_t crc = 0x0; // initial value
uint8_t polynomial = 0x7;
for (size_t i = 0; i < size; i++) {
for (int bit = 7; bit >= 0; bit--) {
// get next bit
uint8_t inBit = (inBytes[i] & (1<<bit)) ? 1 : 0;
// check if MSB is set
uint8_t MSB_high = crc & 0x80;
// input Bit reinschieben
crc = (uint8_t) (crc << 1);
crc ^= inBit;
if (MSB_high) {
crc ^= polynomial;
}
// for (int in = 0; in < 8; in++) {
// printf("%d", !!((crc << in) & 0x80));
// }
// printf("\n");
}
}
return crc;
}
uint32_t crc32(uint8_t* inBytes, size_t size, uint32_t polynomial, uint32_t initialValue)
{
uint32_t crc = initialValue;
for (size_t i = 0; i < size; i++) {
for (int bit = 7; bit >= 0; bit--) {
// get next bit
uint8_t inBit = (inBytes[i] & (1<<bit)) ? 1 : 0;
// check if MSB is set
uint32_t MSB_high = crc & 0x80000000;
// input Bit reinschieben
crc <<= 1;
crc ^= inBit;
if (MSB_high) {
crc ^= polynomial;
}
// for (int in = 0; in < 8; in++) {
// printf("%d", !!((crc << in) & 0x80));
// }
// printf("\n");
}
// printf("0x%x\n", crc);
}
return crc;
}
int checkCrc32(uint8_t* data, size_t size, uint32_t crc, uint32_t polynomial)
{
// Daten und CRC zusammenhaengend in den HEAP Speicher kopieren
uint8_t *dataCrc = malloc(size + 4);
memcpy_s(dataCrc, size+4, data, size);
for (uint32_t i = 0; i < 4; i++) {
dataCrc[size+i] = (crc >> (24 - 8 * i)) & 0xFF; // Extract the MSB first
}
// CRC von Daten mit CRC-Pruefsumme berechnen
// Bei validen Daten bzw. Pruefsumme kommt Null heraus
if (crc32(dataCrc, size+4, polynomial, 0x0) == 0) return 1;
else return 0;
}