Matthias Biermann 0b52a30c62 axi_master schreiben

2025-01-30 11:49:12 +01:00

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CRC_Test

CRC timing test + entity of axi_crc component

2025-01-25 11:53:10 +01:00

Milestone4

axi_master schreiben

2025-01-30 11:49:12 +01:00

stm2mem

ram + axi_master angefanen

2025-01-28 22:42:52 +01:00