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M3: add local gitignore files for vivado projects

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This commit is contained in:
Matthias Biermann
2024-11-26 15:05:14 +01:00
parent 4d3ff4ccb6
commit 024ab68201
178 changed files with 4687 additions and 729524 deletions
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.gitignore
+13 -13
View File
@@ -5,17 +5,17 @@
work/
*.wlf
# Vidado project directories which are not needed
.Xil/
*.cache/
*.hw/
*.ip_user_files/
*.runs/
*.sim/
# design checkpoint file
*.dcp
# # Vidado project directories which are not needed
# .Xil/
# *.cache/
# *.hw/
# *.ip_user_files/
# *.runs/
# *.sim/
# # design checkpoint file
# *.dcp
# ignore Vivado log files
*.log
*.jou
vivado_pid*.str
# # ignore Vivado log files
# *.log
# *.jou
# vivado_pid*.str
Milestone1/es-milestone1/.gitignore
+41
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@@ -0,0 +1,41 @@
# Ignore everything
*
# Allow whitelisting subdirectories
!*/
# Don\'t ignore the block design and block design hdl wrapper files
!/bd/*/*.bd
!/bd/*/hdl/*.sv
!/bd/*/hdl/*.v
!/bd/*/hdl/*.vhd
!/bd/*/hdl/*.vhdl
# Don\'t ignore the constraint files
!/constraints/**/*.xdc
# Don\'t ignore the synthesis files
!/hdl/**/*.sv
!/hdl/**/*.v
!/hdl/**/*.vh
!/hdl/**/*.vhd
!/hdl/**/*.vhdl
# Don\'t ignore the HLS source and testbench files
!/hsl/*/sources/*.cpp
!/hsl/*/sources/*.hpp
!/hsl/*/testbench/*.cpp
# Don\'t ignore the IP defintion files
!/ip/*/*.xci
# Don\'t ignore the HLS IP defintion files
!/ip/hls_ip/**
# Don\'t ignore the output files
!/output/**/*.bit
!/output/**/*.xsa
!/output/**/*.dcp
# Don\'t ignore the project files
!/project/*.xpr
# Don\'t ignore the simulation files
!/sim/**/*.sv
!/sim/**/*.v
!/sim/**/*.vh
!/sim/**/*.vhd
!/sim/**/*.vhdl
!/sim/**/*.wav
# Don\'t ignore this file
!.gitignore
Milestone2/VivadoProjekt/axis_audio_bitcrusher/.gitignore
+41
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@@ -0,0 +1,41 @@
# Ignore everything
*
# Allow whitelisting subdirectories
!*/
# Don\'t ignore the block design and block design hdl wrapper files
!/bd/*/*.bd
!/bd/*/hdl/*.sv
!/bd/*/hdl/*.v
!/bd/*/hdl/*.vhd
!/bd/*/hdl/*.vhdl
# Don\'t ignore the constraint files
!/constraints/**/*.xdc
# Don\'t ignore the synthesis files
!/hdl/**/*.sv
!/hdl/**/*.v
!/hdl/**/*.vh
!/hdl/**/*.vhd
!/hdl/**/*.vhdl
# Don\'t ignore the HLS source and testbench files
!/hsl/*/sources/*.cpp
!/hsl/*/sources/*.hpp
!/hsl/*/testbench/*.cpp
# Don\'t ignore the IP defintion files
!/ip/*/*.xci
# Don\'t ignore the HLS IP defintion files
!/ip/hls_ip/**
# Don\'t ignore the output files
!/output/**/*.bit
!/output/**/*.xsa
!/output/**/*.dcp
# Don\'t ignore the project files
!/project/*.xpr
# Don\'t ignore the simulation files
!/sim/**/*.sv
!/sim/**/*.v
!/sim/**/*.vh
!/sim/**/*.vhd
!/sim/**/*.vhdl
!/sim/**/*.wav
# Don\'t ignore this file
!.gitignore
Milestone3/es-milestone3/.gitignore
+41
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@@ -0,0 +1,41 @@
# Ignore everything
*
# Allow whitelisting subdirectories
!*/
# Don\'t ignore the block design and block design hdl wrapper files
!/bd/*/*.bd
!/bd/*/hdl/*.sv
!/bd/*/hdl/*.v
!/bd/*/hdl/*.vhd
!/bd/*/hdl/*.vhdl
# Don\'t ignore the constraint files
!/constraints/**/*.xdc
# Don\'t ignore the synthesis files
!/hdl/**/*.sv
!/hdl/**/*.v
!/hdl/**/*.vh
!/hdl/**/*.vhd
!/hdl/**/*.vhdl
# Don\'t ignore the HLS source and testbench files
!/hsl/*/sources/*.cpp
!/hsl/*/sources/*.hpp
!/hsl/*/testbench/*.cpp
# Don\'t ignore the IP defintion files
!/ip/*/*.xci
# Don\'t ignore the HLS IP defintion files
!/ip/hls_ip/**
# Don\'t ignore the output files
!/output/**/*.bit
!/output/**/*.xsa
!/output/**/*.dcp
# Don\'t ignore the project files
!/project/*.xpr
# Don\'t ignore the simulation files
!/sim/**/*.sv
!/sim/**/*.v
!/sim/**/*.vh
!/sim/**/*.vhd
!/sim/**/*.vhdl
!/sim/**/*.wav
# Don\'t ignore this file
!.gitignore
Milestone3/es-milestone3/design_1_wrapper_behav.wcfg
-85
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@@ -1,85 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="design_1_wrapper_behav.wdb" id="1">
<top_modules>
<top_module name="design_1_wrapper" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="230,762.430 ns"></ZoomStartTime>
<ZoomEndTime time="230,867.515 ns"></ZoomEndTime>
<Cursor1Time time="230,850.000 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="262"></NameColumnWidth>
<ValueColumnWidth column_width="118"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="10" />
<wvobject fp_name="/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL_ACLK" type="logic">
<obj_property name="ElementShortName">M_AXIL_ACLK</obj_property>
<obj_property name="ObjectShortName">M_AXIL_ACLK</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/clk_rst_generator_0/rst_n" type="logic">
<obj_property name="ElementShortName">rst_n</obj_property>
<obj_property name="ObjectShortName">rst_n</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL" type="protoinst">
<obj_property name="ElementShortName">M_AXIL</obj_property>
<obj_property name="ObjectShortName">M_AXIL</obj_property>
<obj_property name="children_use_element_short_name">true</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="EnumTransactionColorTable">0=blank 1=#D399FF 2=pink</obj_property>
<obj_property name="EnumTransactionValueTable">0=blank;1=Read;2=Write;3=Read/Write</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">turquoise</obj_property>
<obj_property name="Render_Data">/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL.readWriteSummary</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="CellHeight">36</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS" type="protoinst">
<obj_property name="children_use_element_short_name">true</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#00E600</obj_property>
<obj_property name="Render_Data">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.streamWaveData</obj_property>
<obj_property name="Number_Overlay">2</obj_property>
<obj_property name="Overlay_Object_0">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.linkStarve</obj_property>
<obj_property name="Overlay_Color_0">#99E600</obj_property>
<obj_property name="Overlay_Object_1">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.linkStall</obj_property>
<obj_property name="Overlay_Color_1">#E64C00</obj_property>
<obj_property name="Detail_Data">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.streamTooltipData</obj_property>
<obj_property name="ElementShortName">M_AXIS</obj_property>
<obj_property name="ObjectShortName">M_AXIS</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axis_audio_mono2ster_0/S_AXIS" type="protoinst">
<obj_property name="ElementShortName">S_AXIS</obj_property>
<obj_property name="ObjectShortName">S_AXIS</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider52">
<obj_property name="label">Interne Signale</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/ip_active" type="logic">
<obj_property name="ElementShortName">ip_active</obj_property>
<obj_property name="ObjectShortName">ip_active</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/c0" type="array">
<obj_property name="ElementShortName">c0[7:0]</obj_property>
<obj_property name="ObjectShortName">c0[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/c1" type="array">
<obj_property name="ElementShortName">c1[7:0]</obj_property>
<obj_property name="ObjectShortName">c1[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/c2" type="array">
<obj_property name="ElementShortName">c2[7:0]</obj_property>
<obj_property name="ObjectShortName">c2[7:0]</obj_property>
</wvobject>
</wave_config>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim.bxml
+4 -28
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@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="af_sim" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1732621923"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732621924"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732621923"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732621924"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1732629775"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1732629775"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732629775"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1732629660"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\af_sim.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
@@ -27,30 +27,6 @@
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\af_sim.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="af_sim.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\af_sim.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\af_sim.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/hdl/af_sim_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 12:52:03 2024
--Date : Tue Nov 26 15:03:40 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target af_sim_wrapper.bd
--Design : af_sim_wrapper
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/hw_handoff/af_sim.hwh
-523
View File
@@ -1,523 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Nov 26 12:52:03 2024" VIVADOVERSION="2023.1">
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="af_sim" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS/>
<EXTERNALINTERFACES/>
<MODULES>
<MODULE COREREVISION="2" FULLNAME="/axis_audio_master_si_0" HWVERSION="1.0" INSTANCE="axis_audio_master_si_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_master_simmodel" VLNV="xilinx.com:user:axis_audio_master_simmodel:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="CLOCK_CYCLES_PER_SAMPLE" VALUE="5"/>
<PARAMETER NAME="FILE_NAME" VALUE="../../../../HaveANiceDay"/>
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_master_si_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="S_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="WAV_HEADER"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="3" FULLNAME="/axis_audio_mono2ster_0" HWVERSION="1.0" INSTANCE="axis_audio_mono2ster_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_mono2stereo" VLNV="xilinx.com:user:axis_audio_mono2stereo:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_mono2ster_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="M_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="M_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="M_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="S_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="axis_prog_audio_filt_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="18" FULLNAME="/axis_audio_slave_sim_0" HWVERSION="1.0" INSTANCE="axis_audio_slave_sim_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_slave_simmodel" VLNV="xilinx.com:user:axis_audio_slave_simmodel:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="FILE_NAME" VALUE="../../../../sim_out"/>
<PARAMETER NAME="RANDOM_TREADY" VALUE="true"/>
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_slave_sim_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_M_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="M_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="FINISHED" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="stop_simulation"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="351" NAME="WAV_HEADER" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_WAV_HEADER">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="WAV_HEADER"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axis_audio_mono2ster_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="4" FULLNAME="/axis_audio_stereo2mo_0" HWVERSION="1.0" INSTANCE="axis_audio_stereo2mo_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_audio_stereo2mono" VLNV="xilinx.com:user:axis_audio_stereo2mono:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_audio_stereo2mo_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXIS_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_master_si_0_M_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="M_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="S_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="S_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="S_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="axis_audio_master_si_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="0"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="1" FULLNAME="/axis_prog_audio_filt_0" HWVERSION="1.0" INSTANCE="axis_prog_audio_filt_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_prog_audio_filter3" VLNV="xilinx.com:module_ref:axis_prog_audio_filter3:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="COEFF_0" VALUE="16"/>
<PARAMETER NAME="COEFF_1" VALUE="32"/>
<PARAMETER NAME="COEFF_2" VALUE="16"/>
<PARAMETER NAME="SHIFT" VALUE="6"/>
<PARAMETER NAME="RUN_AFTER_RESET" VALUE="true"/>
<PARAMETER NAME="HAS_LAST" VALUE="false"/>
<PARAMETER NAME="Component_Name" VALUE="af_sim_axis_prog_audio_filt_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="AXI_ACLK" SIGIS="clk" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="AXI_ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="clk_rst_generator_0_rst_n">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="S_AXIL_AWADDR" RIGHT="0" SIGIS="undef"/>
<PORT DIR="I" NAME="S_AXIL_AWVALID" SIGIS="undef"/>
<PORT DIR="O" NAME="S_AXIL_AWREADY" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S_AXIL_WDATA" RIGHT="0" SIGIS="undef"/>
<PORT DIR="I" NAME="S_AXIL_WVALID" SIGIS="undef"/>
<PORT DIR="O" NAME="S_AXIL_WREADY" SIGIS="undef"/>
<PORT DIR="I" LEFT="3" NAME="S_AXIL_WSTRB" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" NAME="S_AXIL_BVALID" SIGIS="undef"/>
<PORT DIR="I" NAME="S_AXIL_BREADY" SIGIS="undef"/>
<PORT DIR="O" LEFT="1" NAME="S_AXIL_BRESP" RIGHT="0" SIGIS="undef"/>
<PORT DIR="I" LEFT="7" NAME="S_AXIL_ARADDR" RIGHT="0" SIGIS="undef"/>
<PORT DIR="I" NAME="S_AXIL_ARVALID" SIGIS="undef"/>
<PORT DIR="O" NAME="S_AXIL_ARREADY" SIGIS="undef"/>
<PORT DIR="O" LEFT="31" NAME="S_AXIL_RDATA" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" NAME="S_AXIL_RVALID" SIGIS="undef"/>
<PORT DIR="I" NAME="S_AXIL_RREADY" SIGIS="undef"/>
<PORT DIR="O" LEFT="1" NAME="S_AXIL_RRESP" RIGHT="0" SIGIS="undef"/>
<PORT DIR="I" NAME="S_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="15" NAME="S_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXIS_TLAST" SIGIS="undef"/>
<PORT DIR="O" NAME="S_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_stereo2mo_0_M_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="M_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXIS_TVALID" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TVALID"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="M_AXIS_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TDATA">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXIS_TLAST" SIGIS="undef"/>
<PORT DIR="I" NAME="M_AXIS_TREADY" SIGIS="undef" SIGNAME="axis_audio_mono2ster_0_S_AXIS_TREADY">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="S_AXIS_TREADY"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axis_prog_audio_filt_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="M_AXIS_TDATA"/>
<PORTMAP LOGICAL="TLAST" PHYSICAL="M_AXIS_TLAST"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="M_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="M_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="axis_audio_stereo2mo_0_M_AXIS" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="HAS_TREADY" VALUE="1"/>
<PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
<PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
<PARAMETER NAME="HAS_TLAST" VALUE="1"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="TDATA" PHYSICAL="S_AXIS_TDATA"/>
<PORTMAP LOGICAL="TLAST" PHYSICAL="S_AXIS_TLAST"/>
<PORTMAP LOGICAL="TVALID" PHYSICAL="S_AXIS_TVALID"/>
<PORTMAP LOGICAL="TREADY" PHYSICAL="S_AXIS_TREADY"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="__NOC__" DATAWIDTH="32" NAME="S_AXIL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
<PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="8"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="0"/>
<PARAMETER NAME="HAS_LOCK" VALUE="0"/>
<PARAMETER NAME="HAS_PROT" VALUE="0"/>
<PARAMETER NAME="HAS_CACHE" VALUE="0"/>
<PARAMETER NAME="HAS_QOS" VALUE="0"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXIL_AWADDR"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXIL_AWVALID"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXIL_AWREADY"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXIL_WDATA"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXIL_WSTRB"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXIL_WVALID"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXIL_WREADY"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXIL_BRESP"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXIL_BVALID"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXIL_BREADY"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXIL_ARADDR"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXIL_ARVALID"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXIL_ARREADY"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXIL_RDATA"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXIL_RRESP"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXIL_RVALID"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXIL_RREADY"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="7" FULLNAME="/clk_rst_generator_0" HWVERSION="1.0" INSTANCE="clk_rst_generator_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_rst_generator" VLNV="wg:user:clk_rst_generator:1.0">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="CLOCK_PERIOD" VALUE="8000"/>
<PARAMETER NAME="HAS_CLK_INPUT" VALUE="false"/>
<PARAMETER NAME="HAS_RESET_INPUT" VALUE="false"/>
<PARAMETER NAME="HAS_STOP_INPUT" VALUE="true"/>
<PARAMETER NAME="Component_Name" VALUE="af_sim_clk_rst_generator_0_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
</PARAMETERS>
<PORTS>
<PORT DIR="O" NAME="clk" SIGIS="undef" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ACLK"/>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="AXIS_ACLK"/>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="AXIS_ACLK"/>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ACLK"/>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ACLK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="rst_n" SIGIS="undef" SIGNAME="clk_rst_generator_0_rst_n">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_master_si_0" PORT="ARESETN"/>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="ARESETN"/>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ARESETN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="stop_simulation" SIGIS="undef" SIGNAME="axis_audio_slave_sim_0_FINISHED">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_slave_sim_0" PORT="FINISHED"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES/>
</MODULE>
</MODULES>
</EDKSYSTEM>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0/af_sim_axis_audio_master_si_0_0.xml
+6 -68
View File
@@ -269,47 +269,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_audio_master_simmodel</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9805a313</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_axis_audio_master_si_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9805a313</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>ACLK</spirit:name>
@@ -318,7 +277,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -330,7 +289,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -342,7 +301,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -358,7 +317,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -370,7 +329,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -389,7 +348,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -415,27 +374,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/45f9/wav_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/45f9/axis_audio_master_simmodel.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/af_sim_axis_audio_master_si_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_audio_master_simmodel</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_master_si_0_0/sim/af_sim_axis_audio_master_si_0_0.vhd
-108
View File
@@ -1,108 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_master_simmodel:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY af_sim_axis_audio_master_si_0_0 IS
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
);
END af_sim_axis_audio_master_si_0_0;
ARCHITECTURE af_sim_axis_audio_master_si_0_0_arch OF af_sim_axis_audio_master_si_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_master_si_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_master_simmodel IS
GENERIC (
CLOCK_CYCLES_PER_SAMPLE : INTEGER;
FILE_NAME : STRING
);
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
WAV_HEADER : OUT STD_LOGIC_VECTOR(351 DOWNTO 0)
);
END COMPONENT axis_audio_master_simmodel;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF M_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
BEGIN
U0 : axis_audio_master_simmodel
GENERIC MAP (
CLOCK_CYCLES_PER_SAMPLE => 5,
FILE_NAME => "../../../../HaveANiceDay"
)
PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY,
WAV_HEADER => WAV_HEADER
);
END af_sim_axis_audio_master_si_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0/af_sim_axis_audio_mono2ster_0_0.xml
+9 -67
View File
@@ -410,47 +410,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2720fb8a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_axis_audio_mono2ster_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2720fb8a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>AXIS_ACLK</spirit:name>
@@ -459,7 +418,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -471,7 +430,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -487,7 +446,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -502,7 +461,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -524,7 +483,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -536,7 +495,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -552,7 +511,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -564,7 +523,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -583,7 +542,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -600,23 +559,6 @@
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/af_sim_axis_audio_mono2ster_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_audio_mono2stereo</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_mono2ster_0_0/sim/af_sim_axis_audio_mono2ster_0_0.vhd
-114
View File
@@ -1,114 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY af_sim_axis_audio_mono2ster_0_0 IS
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC
);
END af_sim_axis_audio_mono2ster_0_0;
ARCHITECTURE af_sim_axis_audio_mono2ster_0_0_arch OF af_sim_axis_audio_mono2ster_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_mono2stereo IS
GENERIC (
HAS_LAST : BOOLEAN
);
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_audio_mono2stereo;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_mono2stereo
GENERIC MAP (
HAS_LAST => false
)
PORT MAP (
AXIS_ACLK => AXIS_ACLK,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY
);
END af_sim_axis_audio_mono2ster_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0/af_sim_axis_audio_slave_sim_0_0.xml
+7 -69
View File
@@ -269,47 +269,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_audio_slave_simmodel</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:794188b3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_axis_audio_slave_sim_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:794188b3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>ACLK</spirit:name>
@@ -318,7 +277,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -330,7 +289,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -342,7 +301,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -358,7 +317,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -373,7 +332,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -385,7 +344,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -401,7 +360,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -427,27 +386,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/efba/wav_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/efba/axis_audio_slave_simmodel.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/af_sim_axis_audio_slave_sim_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_audio_slave_simmodel</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_slave_sim_0_0/sim/af_sim_axis_audio_slave_sim_0_0.vhd
-111
View File
@@ -1,111 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_slave_simmodel:1.0
-- IP Revision: 18
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY af_sim_axis_audio_slave_sim_0_0 IS
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
FINISHED : OUT STD_LOGIC;
WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
);
END af_sim_axis_audio_slave_sim_0_0;
ARCHITECTURE af_sim_axis_audio_slave_sim_0_0_arch OF af_sim_axis_audio_slave_sim_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_slave_sim_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_slave_simmodel IS
GENERIC (
FILE_NAME : STRING;
RANDOM_TREADY : BOOLEAN
);
PORT (
ACLK : IN STD_LOGIC;
ARESETN : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
FINISHED : OUT STD_LOGIC;
WAV_HEADER : IN STD_LOGIC_VECTOR(351 DOWNTO 0)
);
END COMPONENT axis_audio_slave_simmodel;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF ACLK: SIGNAL IS "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF ARESETN: SIGNAL IS "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_slave_simmodel
GENERIC MAP (
FILE_NAME => "../../../../sim_out",
RANDOM_TREADY => true
)
PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TREADY => S_AXIS_TREADY,
FINISHED => FINISHED,
WAV_HEADER => WAV_HEADER
);
END af_sim_axis_audio_slave_sim_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_stereo2mo_0_0/af_sim_axis_audio_stereo2mo_0_0.xml
+9 -67
View File
@@ -410,47 +410,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a5608c2f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_axis_audio_stereo2mo_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a5608c2f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>AXIS_ACLK</spirit:name>
@@ -459,7 +418,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -471,7 +430,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -487,7 +446,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -502,7 +461,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -524,7 +483,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -536,7 +495,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -552,7 +511,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -564,7 +523,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -583,7 +542,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -600,23 +559,6 @@
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/af_sim_axis_audio_stereo2mo_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_audio_stereo2mono</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_audio_stereo2mo_0_0/sim/af_sim_axis_audio_stereo2mo_0_0.vhd
-114
View File
@@ -1,114 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY af_sim_axis_audio_stereo2mo_0_0 IS
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC
);
END af_sim_axis_audio_stereo2mo_0_0;
ARCHITECTURE af_sim_axis_audio_stereo2mo_0_0_arch OF af_sim_axis_audio_stereo2mo_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_stereo2mono IS
GENERIC (
HAS_LAST : BOOLEAN
);
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_audio_stereo2mono;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_stereo2mono
GENERIC MAP (
HAS_LAST => false
)
PORT MAP (
AXIS_ACLK => AXIS_ACLK,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY
);
END af_sim_axis_audio_stereo2mo_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xml
+27 -71
View File
@@ -882,40 +882,6 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_prog_audio_filter3</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:08ca8409</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_axis_prog_audio_filt_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:52:03 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:08ca8409</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>AXI_ACLK</spirit:name>
@@ -924,7 +890,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -936,7 +902,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -952,7 +918,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -967,7 +933,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -982,7 +948,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -998,7 +964,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1013,7 +979,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1028,7 +994,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1044,7 +1010,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1059,7 +1025,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1071,7 +1037,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1090,7 +1056,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1106,7 +1072,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1121,7 +1087,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1136,7 +1102,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1152,7 +1118,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1164,7 +1130,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1176,7 +1142,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1195,7 +1161,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1207,7 +1173,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1223,7 +1189,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1238,7 +1204,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1253,7 +1219,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1265,7 +1231,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1281,7 +1247,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1293,7 +1259,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1305,7 +1271,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1354,16 +1320,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/af_sim_axis_prog_audio_filt_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axis_prog_audio_filter3:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/sim/af_sim_axis_prog_audio_filt_0_0.vhd
-204
View File
@@ -1,204 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY af_sim_axis_prog_audio_filt_0_0 IS
PORT (
AXI_ACLK : IN STD_LOGIC;
AXI_ARESETN : IN STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END af_sim_axis_prog_audio_filt_0_0;
ARCHITECTURE af_sim_axis_prog_audio_filt_0_0_arch OF af_sim_axis_prog_audio_filt_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_axis_prog_audio_filt_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_prog_audio_filter3 IS
GENERIC (
COEFF_0 : INTEGER;
COEFF_1 : INTEGER;
COEFF_2 : INTEGER;
SHIFT : INTEGER;
RUN_AFTER_RESET : BOOLEAN;
HAS_LAST : BOOLEAN
);
PORT (
AXI_ACLK : IN STD_LOGIC;
AXI_ARESETN : IN STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_prog_audio_filter3;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
"ITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_prog_audio_filter3
GENERIC MAP (
COEFF_0 => 16,
COEFF_1 => 32,
COEFF_2 => 16,
SHIFT => 6,
RUN_AFTER_RESET => true,
HAS_LAST => false
)
PORT MAP (
AXI_ACLK => AXI_ACLK,
AXI_ARESETN => AXI_ARESETN,
S_AXIL_AWADDR => S_AXIL_AWADDR,
S_AXIL_AWVALID => S_AXIL_AWVALID,
S_AXIL_AWREADY => S_AXIL_AWREADY,
S_AXIL_WDATA => S_AXIL_WDATA,
S_AXIL_WVALID => S_AXIL_WVALID,
S_AXIL_WREADY => S_AXIL_WREADY,
S_AXIL_WSTRB => S_AXIL_WSTRB,
S_AXIL_BVALID => S_AXIL_BVALID,
S_AXIL_BREADY => S_AXIL_BREADY,
S_AXIL_BRESP => S_AXIL_BRESP,
S_AXIL_ARADDR => S_AXIL_ARADDR,
S_AXIL_ARVALID => S_AXIL_ARVALID,
S_AXIL_ARREADY => S_AXIL_ARREADY,
S_AXIL_RDATA => S_AXIL_RDATA,
S_AXIL_RVALID => S_AXIL_RVALID,
S_AXIL_RREADY => S_AXIL_RREADY,
S_AXIL_RRESP => S_AXIL_RRESP,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
END af_sim_axis_prog_audio_filt_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0/af_sim_clk_rst_generator_0_0.xml
+5 -63
View File
@@ -5,47 +5,6 @@
<spirit:name>af_sim_clk_rst_generator_0_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>clk_rst_generator</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7ea0028a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_clk_rst_generator_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 11:27:33 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7ea0028a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk_in</spirit:name>
@@ -54,7 +13,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -76,7 +35,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -98,7 +57,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -110,7 +69,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -122,7 +81,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -161,23 +120,6 @@
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/af_sim_clk_rst_generator_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>clk_rst_generator</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_clk_rst_generator_0_0/sim/af_sim_clk_rst_generator_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:clk_rst_generator:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY af_sim_clk_rst_generator_0_0 IS
PORT (
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END af_sim_clk_rst_generator_0_0;
ARCHITECTURE af_sim_clk_rst_generator_0_0_arch OF af_sim_clk_rst_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF af_sim_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clk_rst_generator IS
GENERIC (
CLOCK_PERIOD : INTEGER;
HAS_CLK_INPUT : BOOLEAN;
HAS_RESET_INPUT : BOOLEAN;
HAS_STOP_INPUT : BOOLEAN
);
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END COMPONENT clk_rst_generator;
BEGIN
U0 : clk_rst_generator
GENERIC MAP (
CLOCK_PERIOD => 8000,
HAS_CLK_INPUT => false,
HAS_RESET_INPUT => false,
HAS_STOP_INPUT => true
)
PORT MAP (
clk_in => '1',
rst_in => '0',
clk => clk,
rst_n => rst_n,
stop_simulation => stop_simulation
);
END af_sim_clk_rst_generator_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/45f9/axis_audio_master_simmodel.vhd
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------------------------------------------------------------------------------
-- axis_audio_master_simmodel.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
----------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wav_pkg.all;
entity axis_audio_master_simmodel is
generic
(
CLOCK_CYCLES_PER_SAMPLE : integer := 2083;
FILE_NAME : string := string'("tst")
);
port
(
ACLK : in std_logic;
ARESETN : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TREADY : in std_logic;
WAV_HEADER : out std_logic_vector(44*8-1 downto 0)
);
end entity axis_audio_master_simmodel;
architecture sim of axis_audio_master_simmodel is
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
signal local_clk : std_logic;
begin
-- synthesis translate_off
-- translate off
local_clk <= ACLK;
-- uint32_t xorshift32() {
-- static uint32_t x = 314159265;
-- x ^= x << 13;
-- x ^= x >> 17;
-- x ^= x << 5;
-- return x;
-- }
process
variable r : unsigned (31 downto 0);
begin
wait until rising_edge(local_clk);
r := rnd;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd <= r;
end process;
process
variable file_num : integer := 0;
variable num_samples : integer;
variable sample : std_logic_vector(31 downto 0);
variable delay_cnt : integer;
variable tvalid_cnt : integer := 31415;
file f : WAV_FILE_TYPE;
variable header : WAV_HEADER_TYPE;
variable file_status : file_open_status;
variable ok : boolean;
variable cyccnt : integer;
begin
wait until rising_edge (local_clk);
if (ARESETN = '0') then
M_AXIS_TVALID <= '0';
M_AXIS_TDATA <= (others=>'0');
file_num := 0;
tvalid_cnt := to_integer(rnd and x"0000001F");
else
M_AXIS_TVALID <= '0';
-- Start-Up delay
for i in 0 to 100 loop
wait until rising_edge (local_clk);
end loop;
M_AXIS_TVALID <= '0';
-- Create filename and try to open the file
file_open ( file_status, f, FILE_NAME & ".wav", read_mode);
-- File open succeeded ?
if file_status /= open_ok then
assert false report "AXIS_AUDIO_MASTER_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
else
read_wav_header(ok,num_samples,header,f);
assert ok report "AXIS_AUDIO_MASTER_SIMMODEL: Input is not in WAV format." severity failure;
for i in 0 to 43 loop
WAV_HEADER(8*(i+1)-1 downto 8*i) <= std_logic_vector(to_unsigned(header(i),8));
end loop;
if ok then
for s in 0 to num_samples-1 loop -- sample loop
M_AXIS_TDATA ( 7 downto 0) <= std_logic_vector(to_unsigned(wavget8(f),8));
M_AXIS_TDATA (15 downto 8) <= std_logic_vector(to_unsigned(wavget8(f),8));
M_AXIS_TDATA (23 downto 16) <= std_logic_vector(to_unsigned(wavget8(f),8));
M_AXIS_TDATA (31 downto 24) <= std_logic_vector(to_unsigned(wavget8(f),8));
M_AXIS_TVALID <= '1';
-- wait until data has been acknowledged
wait until rising_edge (local_clk);
cyccnt := CLOCK_CYCLES_PER_SAMPLE;
while M_AXIS_TREADY = '0' loop
wait until rising_edge (local_clk);
cyccnt := cyccnt - 1;
end loop;
M_AXIS_TVALID <= '0';
while cyccnt > 0 loop
wait until rising_edge (local_clk);
cyccnt := cyccnt - 1;
end loop;
end loop; -- sample loop
file_close(f);
end if; -- if ok
end if; -- if open_status ok
M_AXIS_TVALID <= '0';
-- wait until reset is activated
while ARESETN = '1' loop
wait until rising_edge (local_clk);
end loop;
end if;
end process;
-- synthesis translate_on
-- translate on
end sim;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/45f9/wav_pkg.vhd
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use std.textio.all;
package wav_pkg is
type WAV_FILE_TYPE is file of character;
type WAV_HEADER_TYPE is array (0 to 43) of integer;
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE );
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer;
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
end;
package body wav_pkg is
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE ) is
begin
write(f, character'val(value));
end wavput8;
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
begin
for i in 0 to 43 loop
wavput8(header(i),f);
end loop;
end write_wav_header;
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
variable chr : character;
begin
read (f,chr);
return character'pos(chr);
end wavget8;
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
variable chr : character;
variable val : integer;
begin
success := true;
for i in 0 to 43 loop
header(i) := wavget8(f);
end loop;
numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then -- check for 'RIFF'
numsamples := 0;
success := false;
end if;
if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then -- check for 'WAVE'
numsamples := 0;
success := false;
end if;
end read_wav_header;
end package body;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd
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--------------------------------------------------------------------------
--
-- AXI Stream Audio Mono to Stereo
--
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity axis_audio_mono2stereo is
generic
(
HAS_LAST : boolean := false
);
port
(
AXIS_ACLK : in std_logic;
-- AXI Streaming Target Port
S_AXIS_TVALID : in std_logic;
S_AXIS_TDATA : in std_logic_vector(15 downto 0);
S_AXIS_TLAST : in std_logic := '0';
S_AXIS_TREADY : out std_logic;
-- AXI Streaming Initiator Port
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
);
end;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of axis_audio_mono2stereo is
begin
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
M_AXIS_TLAST <= S_AXIS_TLAST;
M_AXIS_TDATA (31 downto 16) <= S_AXIS_TDATA;
M_AXIS_TDATA (15 downto 0) <= S_AXIS_TDATA;
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/9a97/sources_1/new/clk_rst_generator.vhd
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------------------------------------------------------------------------------
-- clk_rst_generator.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_rst_generator is
generic
(
CLOCK_PERIOD : integer := 10000;
HAS_CLK_INPUT : boolean := true;
HAS_RESET_INPUT : boolean := true;
HAS_STOP_INPUT : boolean := true
);
port
(
clk_in : in std_logic := '1';
rst_in : in std_logic := '0';
clk : out std_logic;
rst_n : out std_logic;
stop_simulation : in std_logic := '0'
);
end;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of clk_rst_generator is
signal clk_sim : std_logic := '1';
signal clk_in_sig : std_logic := '1';
signal clk_sig : std_logic := '1';
signal rst_sig : std_logic := '0';
signal rst_in_sync : std_logic := '0';
begin
clk <= clk_sig;
rst_n <= not rst_sig;
---------------------------------------------------------------
---------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------
---------------------------------------------------------------
clk_sig <= clk_in_sig and clk_sim;
-- Dies ist kein gated Clock!
-- Fuer die Synthese ist clk_sim konstant '1'
-- somit wird die UND-Verknuepfung 'wegoptimiert'
-- und was übrig bleibt, ist ein 'Draht'
-- synthesis translate_off
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
-- synthesis translate_on
process (clk_in) begin
clk_in_sig <= clk_in;
-- synthesis translate_off
clk_in_sig <= '1';
-- synthesis translate_on
end process;
---------------------------------------------------------------
---------------------------------------------------------------
-- RESET GENERATION
---------------------------------------------------------------
---------------------------------------------------------------
process
variable rescnt : unsigned (6 downto 0) := (others=>'1');
begin
wait until rising_edge(clk_sig);
rst_in_sync <= rst_in;
if rst_in_sync = '1' then
rescnt := (others=>'1');
end if;
if rescnt = 0 then
rst_sig <= '0';
else
rescnt := rescnt - 1;
rst_sig <= '1';
end if;
end process;
---------------------------------------------------------------
---------------------------------------------------------------
-- STOP SIMULATION INPUT (simulation only)
---------------------------------------------------------------
---------------------------------------------------------------
-- synthesis translate_off
process (stop_simulation) begin
if stop_simulation = '1' then
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
end if;
end process;
-- synthesis translate_on
end rtl;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd
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--------------------------------------------------------------------------
--
-- AXI Stream Audio Stereo to Mono
--
-- Prof. Dr.-Ing. W. Gehrke (c) 2020/2021
--
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axis_audio_stereo2mono is
generic
(
HAS_LAST : boolean := false
);
port
(
AXIS_ACLK : in std_logic;
-- AXI Streaming Target Port
S_AXIS_TVALID : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic := '0';
S_AXIS_TREADY : out std_logic;
-- AXI Streaming Initiator Port
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(15 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
);
end;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture rtl of axis_audio_stereo2mono is
signal m_valid_sig : std_logic := '0';
begin
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
process begin
wait until rising_edge(AXIS_ACLK);
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
M_AXIS_TDATA <= std_logic_vector(signed(S_AXIS_TDATA(31)&S_AXIS_TDATA(31 downto 17))+signed(S_AXIS_TDATA(15)&S_AXIS_TDATA(15 downto 1)));
M_AXIS_TVALID <= S_AXIS_TVALID;
m_valid_sig <= S_AXIS_TVALID;
M_AXIS_TLAST <= S_AXIS_TLAST;
end if;
end process;
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/efba/axis_audio_slave_simmodel.vhd
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------------------------------------------------------------------------------
-- axis_audio_slave_simmodel.vhd - entity/architecture pair
------------------------------------------------------------------------------
----------------------------------------------------------
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
----------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wav_pkg.all;
entity axis_audio_slave_simmodel is
generic
(
FILE_NAME : string := string'("tst_out");
RANDOM_TREADY : boolean := true
);
port
(
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TVALID : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TREADY : out std_logic;
FINISHED : out std_logic;
WAV_HEADER : in std_logic_vector(11*32-1 downto 0)
);
end entity;
architecture sim of axis_audio_slave_simmodel is
signal rnd : unsigned (31 downto 0) := x"ABBAABBA";
signal local_clk : std_logic;
begin
-- synthesis translate_off
-- translate off
local_clk <= ACLK;
-- uint32_t xorshift32() {
-- static uint32_t x = 314159265;
-- x ^= x << 13;
-- x ^= x >> 17;
-- x ^= x << 5;
-- return x;
-- }
process
variable r : unsigned (31 downto 0);
begin
wait until rising_edge(local_clk);
r := rnd;
r := r xor (r(18 downto 0)& x"000"&"0");
r := r xor (x"0000"&"0"&r(31 downto 17));
r := r xor (r(26 downto 0)& "00000");
rnd <= r;
end process;
process
variable num_samples : integer;
variable delay_cnt : integer;
variable tready_cnt : integer := 31415;
file f : WAV_FILE_TYPE;
variable header : WAV_HEADER_TYPE;
variable file_status : file_open_status;
begin
wait until rising_edge (local_clk);
if (ARESETN = '0') then
tready_cnt := to_integer(rnd and x"0000001F");
FINISHED <= '0';
else
S_AXIS_TREADY <= '1';
FINISHED <= '0';
-- Create filename and try to open the file
file_open ( file_status, f, FILE_NAME & ".wav", write_mode);
-- File open succeeded ?
if file_status /= open_ok then
assert false report "AXIS_AUDIO_SLAVE_SIMMODEL: Cannot open input file." & FILE_NAME & ".wav" severity failure;
else
wait until S_AXIS_TVALID = '1';
for i in 0 to 43 loop
header(i) := to_integer(unsigned(WAV_HEADER(8*(i+1)-1 downto 8*i)));
end loop;
write_wav_header(header,f);
num_samples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
for s in 0 to num_samples-1 loop -- sample loop
S_AXIS_TREADY <= '1';
wait until rising_edge(local_clk);
while S_AXIS_TVALID /= '1' loop
wait until rising_edge(local_clk);
end loop;
wavput8 (to_integer(unsigned(S_AXIS_TDATA( 7 downto 0))),f);
wavput8 (to_integer(unsigned(S_AXIS_TDATA(15 downto 8))),f);
wavput8 (to_integer(unsigned(S_AXIS_TDATA(23 downto 16))),f);
wavput8 (to_integer(unsigned(S_AXIS_TDATA(31 downto 24))),f);
tready_cnt := tready_cnt - 1;
if RANDOM_TREADY and tready_cnt <= 0 then
-- random TREADY delay
delay_cnt := to_integer(rnd and x"00000007");
while delay_cnt > 0 loop
S_AXIS_TREADY <= '0';
delay_cnt := delay_cnt - 1;
wait until rising_edge (local_clk);
tready_cnt := to_integer(rnd and x"0000001F");
end loop;
end if;
end loop; -- sample loop
file_close(f);
FINISHED <= '1';
end if; -- if open_status ok
-- wait until reset is activated
while ARESETN = '1' loop
wait until rising_edge (local_clk);
end loop;
end if;
end process;
-- synthesis translate_on
-- translate on
end sim;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ipshared/efba/wav_pkg.vhd
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use std.textio.all;
package wav_pkg is
type WAV_FILE_TYPE is file of character;
type WAV_HEADER_TYPE is array (0 to 43) of integer;
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE );
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer;
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE );
end;
package body wav_pkg is
procedure wavput8 (value : in integer; file f : WAV_FILE_TYPE ) is
begin
write(f, character'val(value));
end wavput8;
procedure write_wav_header (header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
begin
for i in 0 to 43 loop
wavput8(header(i),f);
end loop;
end write_wav_header;
impure function wavget8 (file f : WAV_FILE_TYPE ) return integer is
variable chr : character;
begin
read (f,chr);
return character'pos(chr);
end wavget8;
procedure read_wav_header (success : inout boolean; numsamples : inout integer; header : inout WAV_HEADER_TYPE; file f : WAV_FILE_TYPE ) is
variable chr : character;
variable val : integer;
begin
success := true;
for i in 0 to 43 loop
header(i) := wavget8(f);
end loop;
numsamples := header(43)*4194304+header(42)*16384+header(41)*64+header(40)/4;
if header(0) /= 16#52# or header(1) /= 16#49# or header(2) /= 16#46# or header(3) /= 16#46# then -- check for 'RIFF'
numsamples := 0;
success := false;
end if;
if header(8) /= 16#57# or header(9) /= 16#41# or header(10) /= 16#56# or header(11) /= 16#45# then -- check for 'WAVE'
numsamples := 0;
success := false;
end if;
end read_wav_header;
end package body;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.protoinst
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{
"version": "1.0",
"modules": {
"af_sim": {
"proto_instances": {
"/axis_audio_master_si_0/M_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "ACLK"},
"ARESETN": { "actual": "ARESETN"},
"TDATA": { "actual": "M_AXIS_TDATA"},
"TREADY": { "actual": "M_AXIS_TREADY"},
"TVALID": { "actual": "M_AXIS_TVALID"}
}
},
"/axis_audio_mono2ster_0/M_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "AXIS_ACLK"},
"TDATA": { "actual": "M_AXIS_TDATA"},
"TREADY": { "actual": "M_AXIS_TREADY"},
"TVALID": { "actual": "M_AXIS_TVALID"}
}
},
"/axis_audio_mono2ster_0/S_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "AXIS_ACLK"},
"TDATA": { "actual": "S_AXIS_TDATA"},
"TREADY": { "actual": "S_AXIS_TREADY"},
"TVALID": { "actual": "S_AXIS_TVALID"}
}
},
"/axis_audio_slave_sim_0/S_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "ACLK"},
"ARESETN": { "actual": "ARESETN"},
"TDATA": { "actual": "S_AXIS_TDATA"},
"TREADY": { "actual": "S_AXIS_TREADY"},
"TVALID": { "actual": "S_AXIS_TVALID"}
}
},
"/axis_audio_stereo2mo_0/M_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "AXIS_ACLK"},
"TDATA": { "actual": "M_AXIS_TDATA"},
"TREADY": { "actual": "M_AXIS_TREADY"},
"TVALID": { "actual": "M_AXIS_TVALID"}
}
},
"/axis_audio_stereo2mo_0/S_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"ACLK": { "actual": "AXIS_ACLK"},
"TDATA": { "actual": "S_AXIS_TDATA"},
"TREADY": { "actual": "S_AXIS_TREADY"},
"TVALID": { "actual": "S_AXIS_TVALID"}
}
},
"/axis_prog_audio_filt_0/M_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"TDATA": { "actual": "M_AXIS_TDATA"},
"TLAST": { "actual": "M_AXIS_TLAST"},
"TREADY": { "actual": "M_AXIS_TREADY"},
"TVALID": { "actual": "M_AXIS_TVALID"}
}
},
"/axis_prog_audio_filt_0/S_AXIS": {
"interface": "xilinx.com:interface:axis:1.0",
"ports": {
"TDATA": { "actual": "S_AXIS_TDATA"},
"TLAST": { "actual": "S_AXIS_TLAST"},
"TREADY": { "actual": "S_AXIS_TREADY"},
"TVALID": { "actual": "S_AXIS_TVALID"}
}
}
}
}
}
}
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 12:52:03 2024
--Date : Tue Nov 26 15:03:40 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target af_sim.bd
--Design : af_sim
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.hwdef
BIN
View File
Binary file not shown.
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 12:52:03 2024
--Date : Tue Nov 26 15:03:40 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target af_sim.bd
--Design : af_sim
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml
+5 -50
View File
@@ -2,55 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732628584"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732628584"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732628584"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732628584"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="design_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="design_1.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\design_1.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\design_1.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1732629660"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1732629660"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732629660"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1732629660"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
+1 -1
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 14:42:59 2024
--Date : Tue Nov 26 15:02:11 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
-4867
View File
File diff suppressed because it is too large Load Diff
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/constrs_1/new/axil_master_with_rom.xdc
View File
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/constrs_1/new/axil_master_with_rom_clocks.xdc
View File
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/constrs_1/new/axil_master_with_rom_ooc.xdc
-1
View File
@@ -1 +0,0 @@
create_clock -period 10.000 -name M_AXIL_ACLK -waveform {0.000 5.000} [get_ports M_AXIL_ACLK]
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
+23 -244
View File
@@ -565,115 +565,6 @@
</spirit:addressSpace>
</spirit:addressSpaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axil_master_with_rom</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:315e6bc8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axil_master_with_rom</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:45b54a85</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:48:16 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:45b54a85</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:45b54a85</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axil_master_with_rom_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:315e6bc8</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axil_master_with_rom_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:45b54a85</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>interrupt_in</spirit:name>
@@ -682,8 +573,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -705,8 +595,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -725,8 +614,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -738,8 +626,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -754,8 +641,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -770,8 +656,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -787,8 +672,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -804,8 +688,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -817,8 +700,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -830,8 +712,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -850,8 +731,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -870,8 +750,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -886,8 +765,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -902,8 +780,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -919,8 +796,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -936,8 +812,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -949,8 +824,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -965,8 +839,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -982,8 +855,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -999,8 +871,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1012,8 +883,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1025,8 +895,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1045,8 +914,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1080,95 +948,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/d271/sources_1/new/axilm_rom.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/d271/sources_1/new/axil_master_with_rom.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constrs_1/new/axil_master_with_rom.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/axil_master_with_rom_clocks.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/axil_master_with_rom_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/d271/sources_1/new/axilm_rom.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/d271/sources_1/new/axil_master_with_rom.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_sim_netlist.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:41:13 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axil_master_with_rom_0_0 -prefix
// design_1_axil_master_with_rom_0_0_ design_1_axil_master_with_rom_0_0_stub.v
// Design : design_1_axil_master_with_rom_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axil_master_with_rom,Vivado 2023.1" *)
module design_1_axil_master_with_rom_0_0(interrupt_in, M_AXIL_ACLK, M_AXIL_ARESETN,
M_AXIL_ARREADY, M_AXIL_ARVALID, M_AXIL_ARADDR, M_AXIL_ARPROT, M_AXIL_RREADY, M_AXIL_RVALID,
M_AXIL_RDATA, M_AXIL_RRESP, M_AXIL_AWREADY, M_AXIL_AWVALID, M_AXIL_AWADDR, M_AXIL_AWPROT,
M_AXIL_WREADY, M_AXIL_WVALID, M_AXIL_WDATA, M_AXIL_WSTRB, M_AXIL_BREADY, M_AXIL_BVALID,
M_AXIL_BRESP)
/* synthesis syn_black_box black_box_pad_pin="interrupt_in,M_AXIL_ARESETN,M_AXIL_ARREADY,M_AXIL_ARVALID,M_AXIL_ARADDR[31:0],M_AXIL_ARPROT[2:0],M_AXIL_RREADY,M_AXIL_RVALID,M_AXIL_RDATA[31:0],M_AXIL_RRESP[1:0],M_AXIL_AWREADY,M_AXIL_AWVALID,M_AXIL_AWADDR[31:0],M_AXIL_AWPROT[2:0],M_AXIL_WREADY,M_AXIL_WVALID,M_AXIL_WDATA[31:0],M_AXIL_WSTRB[3:0],M_AXIL_BREADY,M_AXIL_BVALID,M_AXIL_BRESP[1:0]" */
/* synthesis syn_force_seq_prim="M_AXIL_ACLK" */;
input interrupt_in;
input M_AXIL_ACLK /* synthesis syn_isclock = 1 */;
input M_AXIL_ARESETN;
input M_AXIL_ARREADY;
output M_AXIL_ARVALID;
output [31:0]M_AXIL_ARADDR;
output [2:0]M_AXIL_ARPROT;
output M_AXIL_RREADY;
input M_AXIL_RVALID;
input [31:0]M_AXIL_RDATA;
input [1:0]M_AXIL_RRESP;
input M_AXIL_AWREADY;
output M_AXIL_AWVALID;
output [31:0]M_AXIL_AWADDR;
output [2:0]M_AXIL_AWPROT;
input M_AXIL_WREADY;
output M_AXIL_WVALID;
output [31:0]M_AXIL_WDATA;
output [3:0]M_AXIL_WSTRB;
output M_AXIL_BREADY;
input M_AXIL_BVALID;
input [1:0]M_AXIL_BRESP;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:41:13 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_axil_master_with_rom_0_0 -prefix
-- design_1_axil_master_with_rom_0_0_ design_1_axil_master_with_rom_0_0_stub.vhdl
-- Design : design_1_axil_master_with_rom_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axil_master_with_rom_0_0 is
Port (
interrupt_in : in STD_LOGIC;
M_AXIL_ACLK : in STD_LOGIC;
M_AXIL_ARESETN : in STD_LOGIC;
M_AXIL_ARREADY : in STD_LOGIC;
M_AXIL_ARVALID : out STD_LOGIC;
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_RREADY : out STD_LOGIC;
M_AXIL_RVALID : in STD_LOGIC;
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXIL_AWREADY : in STD_LOGIC;
M_AXIL_AWVALID : out STD_LOGIC;
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_WREADY : in STD_LOGIC;
M_AXIL_WVALID : out STD_LOGIC;
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIL_BREADY : out STD_LOGIC;
M_AXIL_BVALID : in STD_LOGIC;
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end design_1_axil_master_with_rom_0_0;
architecture stub of design_1_axil_master_with_rom_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "interrupt_in,M_AXIL_ACLK,M_AXIL_ARESETN,M_AXIL_ARREADY,M_AXIL_ARVALID,M_AXIL_ARADDR[31:0],M_AXIL_ARPROT[2:0],M_AXIL_RREADY,M_AXIL_RVALID,M_AXIL_RDATA[31:0],M_AXIL_RRESP[1:0],M_AXIL_AWREADY,M_AXIL_AWVALID,M_AXIL_AWADDR[31:0],M_AXIL_AWPROT[2:0],M_AXIL_WREADY,M_AXIL_WVALID,M_AXIL_WDATA[31:0],M_AXIL_WSTRB[3:0],M_AXIL_BREADY,M_AXIL_BVALID,M_AXIL_BRESP[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axil_master_with_rom,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/sim/design_1_axil_master_with_rom_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:axil_master_with_rom:1.0
-- IP Revision: 17
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axil_master_with_rom_0_0 IS
PORT (
interrupt_in : IN STD_LOGIC;
M_AXIL_ACLK : IN STD_LOGIC;
M_AXIL_ARESETN : IN STD_LOGIC;
M_AXIL_ARREADY : IN STD_LOGIC;
M_AXIL_ARVALID : OUT STD_LOGIC;
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_RREADY : OUT STD_LOGIC;
M_AXIL_RVALID : IN STD_LOGIC;
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXIL_AWREADY : IN STD_LOGIC;
M_AXIL_AWVALID : OUT STD_LOGIC;
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_WREADY : IN STD_LOGIC;
M_AXIL_WVALID : OUT STD_LOGIC;
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIL_BREADY : OUT STD_LOGIC;
M_AXIL_BVALID : IN STD_LOGIC;
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END design_1_axil_master_with_rom_0_0;
ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axil_master_with_rom IS
GENERIC (
STIM_FILENAME : STRING;
HAS_FINISHED_OUT : BOOLEAN;
HAS_INTERRUPT_IN : BOOLEAN
);
PORT (
interrupt_in : IN STD_LOGIC;
finished_o : OUT STD_LOGIC;
M_AXIL_ACLK : IN STD_LOGIC;
M_AXIL_ARESETN : IN STD_LOGIC;
M_AXIL_ARREADY : IN STD_LOGIC;
M_AXIL_ARVALID : OUT STD_LOGIC;
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_RREADY : OUT STD_LOGIC;
M_AXIL_RVALID : IN STD_LOGIC;
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXIL_AWREADY : IN STD_LOGIC;
M_AXIL_AWVALID : OUT STD_LOGIC;
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_WREADY : IN STD_LOGIC;
M_AXIL_WVALID : OUT STD_LOGIC;
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIL_BREADY : OUT STD_LOGIC;
M_AXIL_BVALID : IN STD_LOGIC;
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axil_master_with_rom;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
"SERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
BEGIN
U0 : axil_master_with_rom
GENERIC MAP (
STIM_FILENAME => "../../stimuli.mem",
HAS_FINISHED_OUT => false,
HAS_INTERRUPT_IN => true
)
PORT MAP (
interrupt_in => interrupt_in,
M_AXIL_ACLK => M_AXIL_ACLK,
M_AXIL_ARESETN => M_AXIL_ARESETN,
M_AXIL_ARREADY => M_AXIL_ARREADY,
M_AXIL_ARVALID => M_AXIL_ARVALID,
M_AXIL_ARADDR => M_AXIL_ARADDR,
M_AXIL_ARPROT => M_AXIL_ARPROT,
M_AXIL_RREADY => M_AXIL_RREADY,
M_AXIL_RVALID => M_AXIL_RVALID,
M_AXIL_RDATA => M_AXIL_RDATA,
M_AXIL_RRESP => M_AXIL_RRESP,
M_AXIL_AWREADY => M_AXIL_AWREADY,
M_AXIL_AWVALID => M_AXIL_AWVALID,
M_AXIL_AWADDR => M_AXIL_AWADDR,
M_AXIL_AWPROT => M_AXIL_AWPROT,
M_AXIL_WREADY => M_AXIL_WREADY,
M_AXIL_WVALID => M_AXIL_WVALID,
M_AXIL_WDATA => M_AXIL_WDATA,
M_AXIL_WSTRB => M_AXIL_WSTRB,
M_AXIL_BREADY => M_AXIL_BREADY,
M_AXIL_BVALID => M_AXIL_BVALID,
M_AXIL_BRESP => M_AXIL_BRESP
);
END design_1_axil_master_with_rom_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/synth/design_1_axil_master_with_rom_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:axil_master_with_rom:1.0
-- IP Revision: 17
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axil_master_with_rom_0_0 IS
PORT (
interrupt_in : IN STD_LOGIC;
M_AXIL_ACLK : IN STD_LOGIC;
M_AXIL_ARESETN : IN STD_LOGIC;
M_AXIL_ARREADY : IN STD_LOGIC;
M_AXIL_ARVALID : OUT STD_LOGIC;
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_RREADY : OUT STD_LOGIC;
M_AXIL_RVALID : IN STD_LOGIC;
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXIL_AWREADY : IN STD_LOGIC;
M_AXIL_AWVALID : OUT STD_LOGIC;
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_WREADY : IN STD_LOGIC;
M_AXIL_WVALID : OUT STD_LOGIC;
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIL_BREADY : OUT STD_LOGIC;
M_AXIL_BVALID : IN STD_LOGIC;
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END design_1_axil_master_with_rom_0_0;
ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axil_master_with_rom IS
GENERIC (
STIM_FILENAME : STRING;
HAS_FINISHED_OUT : BOOLEAN;
HAS_INTERRUPT_IN : BOOLEAN
);
PORT (
interrupt_in : IN STD_LOGIC;
finished_o : OUT STD_LOGIC;
M_AXIL_ACLK : IN STD_LOGIC;
M_AXIL_ARESETN : IN STD_LOGIC;
M_AXIL_ARREADY : IN STD_LOGIC;
M_AXIL_ARVALID : OUT STD_LOGIC;
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_RREADY : OUT STD_LOGIC;
M_AXIL_RVALID : IN STD_LOGIC;
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXIL_AWREADY : IN STD_LOGIC;
M_AXIL_AWVALID : OUT STD_LOGIC;
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXIL_WREADY : IN STD_LOGIC;
M_AXIL_WVALID : OUT STD_LOGIC;
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIL_BREADY : OUT STD_LOGIC;
M_AXIL_BVALID : IN STD_LOGIC;
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axil_master_with_rom;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "axil_master_with_rom,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axil_master_with_rom_0_0_arch : ARCHITECTURE IS "design_1_axil_master_with_rom_0_0,axil_master_with_rom,{}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "package_project";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
"SERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
BEGIN
U0 : axil_master_with_rom
GENERIC MAP (
STIM_FILENAME => "../../stimuli.mem",
HAS_FINISHED_OUT => false,
HAS_INTERRUPT_IN => true
)
PORT MAP (
interrupt_in => interrupt_in,
M_AXIL_ACLK => M_AXIL_ACLK,
M_AXIL_ARESETN => M_AXIL_ARESETN,
M_AXIL_ARREADY => M_AXIL_ARREADY,
M_AXIL_ARVALID => M_AXIL_ARVALID,
M_AXIL_ARADDR => M_AXIL_ARADDR,
M_AXIL_ARPROT => M_AXIL_ARPROT,
M_AXIL_RREADY => M_AXIL_RREADY,
M_AXIL_RVALID => M_AXIL_RVALID,
M_AXIL_RDATA => M_AXIL_RDATA,
M_AXIL_RRESP => M_AXIL_RRESP,
M_AXIL_AWREADY => M_AXIL_AWREADY,
M_AXIL_AWVALID => M_AXIL_AWVALID,
M_AXIL_AWADDR => M_AXIL_AWADDR,
M_AXIL_AWPROT => M_AXIL_AWPROT,
M_AXIL_WREADY => M_AXIL_WREADY,
M_AXIL_WVALID => M_AXIL_WVALID,
M_AXIL_WDATA => M_AXIL_WDATA,
M_AXIL_WSTRB => M_AXIL_WSTRB,
M_AXIL_BREADY => M_AXIL_BREADY,
M_AXIL_BVALID => M_AXIL_BVALID,
M_AXIL_BRESP => M_AXIL_BRESP
);
END design_1_axil_master_with_rom_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/constrs_1/new/axis_audio_mono2stereo.xdc
View File
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/constrs_1/new/axis_audio_mono2stereo_clocks.xdc
View File
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/constrs_1/new/axis_audio_mono2stereo_ooc.xdc
-1
View File
@@ -1 +0,0 @@
create_clock -period 10.000 [get_ports AXIS_ACLK]
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml
+9 -208
View File
@@ -410,115 +410,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:27d6e957</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2c94a4ed</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:48:42 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2c94a4ed</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2c94a4ed</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axis_audio_mono2ster_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:27d6e957</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axis_audio_mono2ster_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2c94a4ed</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>AXIS_ACLK</spirit:name>
@@ -527,8 +418,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -540,8 +430,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -557,8 +446,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -573,8 +461,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -596,8 +483,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -609,8 +495,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -626,8 +511,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -639,8 +523,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -659,8 +542,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -677,87 +559,6 @@
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constrs_1/new/axis_audio_mono2stereo.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/axis_audio_mono2stereo_clocks.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/axis_audio_mono2stereo_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>design_1_axis_audio_mono2ster_0_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_audio_mono2ster_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_audio_mono2ster_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_audio_mono2ster_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_audio_mono2ster_0_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/design_1_axis_audio_mono2ster_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/design_1_axis_audio_mono2ster_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>axis_audio_mono2stereo</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_sim_netlist.v
-172
View File
@@ -1,172 +0,0 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:37 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
// design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_sim_netlist.v
// Design : design_1_axis_audio_mono2ster_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* HAS_LAST = "FALSE" *)
module design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TLAST,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TREADY);
input AXIS_ACLK;
input S_AXIS_TVALID;
input [15:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [31:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
wire \<const0> ;
wire M_AXIS_TREADY;
wire [15:0]S_AXIS_TDATA;
wire S_AXIS_TVALID;
assign M_AXIS_TDATA[31:16] = S_AXIS_TDATA;
assign M_AXIS_TDATA[15:0] = S_AXIS_TDATA;
assign M_AXIS_TLAST = \<const0> ;
assign M_AXIS_TVALID = S_AXIS_TVALID;
assign S_AXIS_TREADY = M_AXIS_TREADY;
GND GND
(.G(\<const0> ));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_axis_audio_mono2ster_0_0
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TREADY);
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [15:0]S_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [31:0]M_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
wire [31:0]M_AXIS_TDATA;
wire M_AXIS_TREADY;
wire M_AXIS_TVALID;
wire [15:0]S_AXIS_TDATA;
wire S_AXIS_TREADY;
wire S_AXIS_TVALID;
wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
(* HAS_LAST = "FALSE" *)
design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo U0
(.AXIS_ACLK(1'b0),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TLAST(1'b0),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TVALID(S_AXIS_TVALID));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_sim_netlist.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:37 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
-- design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_sim_netlist.vhdl
-- Design : design_1_axis_audio_mono2ster_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
attribute HAS_LAST : string;
attribute HAS_LAST of design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo : entity is "FALSE";
end design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo;
architecture STRUCTURE of design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo is
signal \<const0>\ : STD_LOGIC;
signal \^m_axis_tready\ : STD_LOGIC;
signal \^s_axis_tdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^s_axis_tvalid\ : STD_LOGIC;
begin
M_AXIS_TDATA(31 downto 16) <= \^s_axis_tdata\(15 downto 0);
M_AXIS_TDATA(15 downto 0) <= \^s_axis_tdata\(15 downto 0);
M_AXIS_TLAST <= \<const0>\;
M_AXIS_TVALID <= \^s_axis_tvalid\;
S_AXIS_TREADY <= \^m_axis_tready\;
\^m_axis_tready\ <= M_AXIS_TREADY;
\^s_axis_tdata\(15 downto 0) <= S_AXIS_TDATA(15 downto 0);
\^s_axis_tvalid\ <= S_AXIS_TVALID;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_mono2ster_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_axis_audio_mono2ster_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_axis_audio_mono2ster_0_0 : entity is "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_axis_audio_mono2ster_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of design_1_axis_audio_mono2ster_0_0 : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of design_1_axis_audio_mono2ster_0_0 : entity is "axis_audio_mono2stereo,Vivado 2023.1";
end design_1_axis_audio_mono2ster_0_0;
architecture STRUCTURE of design_1_axis_audio_mono2ster_0_0 is
signal NLW_U0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
attribute HAS_LAST : string;
attribute HAS_LAST of U0 : label is "FALSE";
attribute x_interface_info : string;
attribute x_interface_info of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
attribute x_interface_info of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
attribute x_interface_parameter of M_AXIS_TVALID : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
attribute x_interface_info of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
attribute x_interface_parameter of S_AXIS_TVALID : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
attribute x_interface_info of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
begin
U0: entity work.design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
port map (
AXIS_ACLK => '0',
M_AXIS_TDATA(31 downto 0) => M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => NLW_U0_M_AXIS_TLAST_UNCONNECTED,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
S_AXIS_TDATA(15 downto 0) => S_AXIS_TDATA(15 downto 0),
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TVALID => S_AXIS_TVALID
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:37 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
// design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_stub.v
// Design : design_1_axis_audio_mono2ster_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
module design_1_axis_audio_mono2ster_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA,
S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
/* synthesis syn_black_box black_box_pad_pin="AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY" */;
input AXIS_ACLK;
input S_AXIS_TVALID;
input [15:0]S_AXIS_TDATA;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [31:0]M_AXIS_TDATA;
input M_AXIS_TREADY;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:37 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
-- design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_stub.vhdl
-- Design : design_1_axis_audio_mono2ster_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axis_audio_mono2ster_0_0 is
Port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end design_1_axis_audio_mono2ster_0_0;
architecture stub of design_1_axis_audio_mono2ster_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_audio_mono2stereo,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/sim/design_1_axis_audio_mono2ster_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_audio_mono2ster_0_0 IS
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC
);
END design_1_axis_audio_mono2ster_0_0;
ARCHITECTURE design_1_axis_audio_mono2ster_0_0_arch OF design_1_axis_audio_mono2ster_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_mono2stereo IS
GENERIC (
HAS_LAST : BOOLEAN
);
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_audio_mono2stereo;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_mono2stereo
GENERIC MAP (
HAS_LAST => false
)
PORT MAP (
AXIS_ACLK => AXIS_ACLK,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY
);
END design_1_axis_audio_mono2ster_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/synth/design_1_axis_audio_mono2ster_0_0.vhd
-122
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@@ -1,122 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_audio_mono2ster_0_0 IS
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC
);
END design_1_axis_audio_mono2ster_0_0;
ARCHITECTURE design_1_axis_audio_mono2ster_0_0_arch OF design_1_axis_audio_mono2ster_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_mono2stereo IS
GENERIC (
HAS_LAST : BOOLEAN
);
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_audio_mono2stereo;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "axis_audio_mono2stereo,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_audio_mono2ster_0_0_arch : ARCHITECTURE IS "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_mono2stereo,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HAS_LAST=false}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "package_project";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_mono2stereo
GENERIC MAP (
HAS_LAST => false
)
PORT MAP (
AXIS_ACLK => AXIS_ACLK,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY
);
END design_1_axis_audio_mono2ster_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/constrs_1/new/axis_audio_stereo2mono.xdc
View File
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/constrs_1/new/axis_audio_stereo2mono_clocks.xdc
View File
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/constrs_1/new/axis_audio_stereo2mono_ooc.xdc
-1
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@@ -1 +0,0 @@
create_clock -period 10.000 [get_ports AXIS_ACLK]
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml
+9 -208
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@@ -410,115 +410,6 @@
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
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<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
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<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
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<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
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<spirit:value>9:fcf1b95b</spirit:value>
</spirit:parameter>
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</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:49:04 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fcf1b95b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fcf1b95b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axis_audio_stereo2mo_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e1ff5562</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axis_audio_stereo2mo_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fcf1b95b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>AXIS_ACLK</spirit:name>
@@ -527,8 +418,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -540,8 +430,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -557,8 +446,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -573,8 +461,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -596,8 +483,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -609,8 +495,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -626,8 +511,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -639,8 +523,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -659,8 +542,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -677,87 +559,6 @@
</spirit:modelParameter>
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</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
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<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constrs_1/new/axis_audio_stereo2mono.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
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<spirit:name>constrs_1/new/axis_audio_stereo2mono_clocks.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/axis_audio_stereo2mono_ooc.xdc</spirit:name>
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<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
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<spirit:name>../../ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd</spirit:name>
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<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_audio_stereo2mo_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:description>axis_audio_stereo2mono</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_sim_netlist.v
-439
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@@ -1,439 +0,0 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:47 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
// design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_sim_netlist.v
// Design : design_1_axis_audio_stereo2mo_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* HAS_LAST = "FALSE" *)
module design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TLAST,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TREADY);
input AXIS_ACLK;
input S_AXIS_TVALID;
input [31:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [15:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
wire \<const0> ;
wire AXIS_ACLK;
wire [15:0]M_AXIS_TDATA;
wire \M_AXIS_TDATA[11]_i_2_n_0 ;
wire \M_AXIS_TDATA[11]_i_3_n_0 ;
wire \M_AXIS_TDATA[11]_i_4_n_0 ;
wire \M_AXIS_TDATA[11]_i_5_n_0 ;
wire \M_AXIS_TDATA[15]_i_2_n_0 ;
wire \M_AXIS_TDATA[15]_i_3_n_0 ;
wire \M_AXIS_TDATA[15]_i_4_n_0 ;
wire \M_AXIS_TDATA[15]_i_5_n_0 ;
wire \M_AXIS_TDATA[3]_i_2_n_0 ;
wire \M_AXIS_TDATA[3]_i_3_n_0 ;
wire \M_AXIS_TDATA[3]_i_4_n_0 ;
wire \M_AXIS_TDATA[3]_i_5_n_0 ;
wire \M_AXIS_TDATA[7]_i_2_n_0 ;
wire \M_AXIS_TDATA[7]_i_3_n_0 ;
wire \M_AXIS_TDATA[7]_i_4_n_0 ;
wire \M_AXIS_TDATA[7]_i_5_n_0 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_0 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_3 ;
wire \M_AXIS_TDATA_reg[15]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[15]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[15]_i_1_n_3 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_0 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_3 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_0 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_3 ;
wire M_AXIS_TREADY;
wire M_AXIS_TVALID;
wire [31:0]S_AXIS_TDATA;
wire S_AXIS_TREADY;
wire S_AXIS_TVALID;
wire [15:0]p_0_in;
wire [3:3]\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED ;
assign M_AXIS_TLAST = \<const0> ;
GND GND
(.G(\<const0> ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_2
(.I0(S_AXIS_TDATA[28]),
.I1(S_AXIS_TDATA[12]),
.O(\M_AXIS_TDATA[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_3
(.I0(S_AXIS_TDATA[27]),
.I1(S_AXIS_TDATA[11]),
.O(\M_AXIS_TDATA[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_4
(.I0(S_AXIS_TDATA[26]),
.I1(S_AXIS_TDATA[10]),
.O(\M_AXIS_TDATA[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_5
(.I0(S_AXIS_TDATA[25]),
.I1(S_AXIS_TDATA[9]),
.O(\M_AXIS_TDATA[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\M_AXIS_TDATA[15]_i_2
(.I0(S_AXIS_TDATA[31]),
.O(\M_AXIS_TDATA[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[15]_i_3
(.I0(S_AXIS_TDATA[31]),
.I1(S_AXIS_TDATA[15]),
.O(\M_AXIS_TDATA[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[15]_i_4
(.I0(S_AXIS_TDATA[30]),
.I1(S_AXIS_TDATA[14]),
.O(\M_AXIS_TDATA[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[15]_i_5
(.I0(S_AXIS_TDATA[29]),
.I1(S_AXIS_TDATA[13]),
.O(\M_AXIS_TDATA[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_2
(.I0(S_AXIS_TDATA[20]),
.I1(S_AXIS_TDATA[4]),
.O(\M_AXIS_TDATA[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_3
(.I0(S_AXIS_TDATA[19]),
.I1(S_AXIS_TDATA[3]),
.O(\M_AXIS_TDATA[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_4
(.I0(S_AXIS_TDATA[18]),
.I1(S_AXIS_TDATA[2]),
.O(\M_AXIS_TDATA[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_5
(.I0(S_AXIS_TDATA[17]),
.I1(S_AXIS_TDATA[1]),
.O(\M_AXIS_TDATA[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_2
(.I0(S_AXIS_TDATA[24]),
.I1(S_AXIS_TDATA[8]),
.O(\M_AXIS_TDATA[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_3
(.I0(S_AXIS_TDATA[23]),
.I1(S_AXIS_TDATA[7]),
.O(\M_AXIS_TDATA[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_4
(.I0(S_AXIS_TDATA[22]),
.I1(S_AXIS_TDATA[6]),
.O(\M_AXIS_TDATA[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_5
(.I0(S_AXIS_TDATA[21]),
.I1(S_AXIS_TDATA[5]),
.O(\M_AXIS_TDATA[7]_i_5_n_0 ));
FDRE \M_AXIS_TDATA_reg[0]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[0]),
.Q(M_AXIS_TDATA[0]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[10]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[10]),
.Q(M_AXIS_TDATA[10]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[11]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[11]),
.Q(M_AXIS_TDATA[11]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[11]_i_1
(.CI(\M_AXIS_TDATA_reg[7]_i_1_n_0 ),
.CO({\M_AXIS_TDATA_reg[11]_i_1_n_0 ,\M_AXIS_TDATA_reg[11]_i_1_n_1 ,\M_AXIS_TDATA_reg[11]_i_1_n_2 ,\M_AXIS_TDATA_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(S_AXIS_TDATA[28:25]),
.O(p_0_in[11:8]),
.S({\M_AXIS_TDATA[11]_i_2_n_0 ,\M_AXIS_TDATA[11]_i_3_n_0 ,\M_AXIS_TDATA[11]_i_4_n_0 ,\M_AXIS_TDATA[11]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[12]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[12]),
.Q(M_AXIS_TDATA[12]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[13]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[13]),
.Q(M_AXIS_TDATA[13]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[14]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[14]),
.Q(M_AXIS_TDATA[14]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[15]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[15]),
.Q(M_AXIS_TDATA[15]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[15]_i_1
(.CI(\M_AXIS_TDATA_reg[11]_i_1_n_0 ),
.CO({\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED [3],\M_AXIS_TDATA_reg[15]_i_1_n_1 ,\M_AXIS_TDATA_reg[15]_i_1_n_2 ,\M_AXIS_TDATA_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\M_AXIS_TDATA[15]_i_2_n_0 ,S_AXIS_TDATA[30:29]}),
.O(p_0_in[15:12]),
.S({1'b1,\M_AXIS_TDATA[15]_i_3_n_0 ,\M_AXIS_TDATA[15]_i_4_n_0 ,\M_AXIS_TDATA[15]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[1]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[1]),
.Q(M_AXIS_TDATA[1]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[2]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[2]),
.Q(M_AXIS_TDATA[2]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[3]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[3]),
.Q(M_AXIS_TDATA[3]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[3]_i_1
(.CI(1'b0),
.CO({\M_AXIS_TDATA_reg[3]_i_1_n_0 ,\M_AXIS_TDATA_reg[3]_i_1_n_1 ,\M_AXIS_TDATA_reg[3]_i_1_n_2 ,\M_AXIS_TDATA_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(S_AXIS_TDATA[20:17]),
.O(p_0_in[3:0]),
.S({\M_AXIS_TDATA[3]_i_2_n_0 ,\M_AXIS_TDATA[3]_i_3_n_0 ,\M_AXIS_TDATA[3]_i_4_n_0 ,\M_AXIS_TDATA[3]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[4]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[4]),
.Q(M_AXIS_TDATA[4]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[5]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[5]),
.Q(M_AXIS_TDATA[5]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[6]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[6]),
.Q(M_AXIS_TDATA[6]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[7]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[7]),
.Q(M_AXIS_TDATA[7]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[7]_i_1
(.CI(\M_AXIS_TDATA_reg[3]_i_1_n_0 ),
.CO({\M_AXIS_TDATA_reg[7]_i_1_n_0 ,\M_AXIS_TDATA_reg[7]_i_1_n_1 ,\M_AXIS_TDATA_reg[7]_i_1_n_2 ,\M_AXIS_TDATA_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(S_AXIS_TDATA[24:21]),
.O(p_0_in[7:4]),
.S({\M_AXIS_TDATA[7]_i_2_n_0 ,\M_AXIS_TDATA[7]_i_3_n_0 ,\M_AXIS_TDATA[7]_i_4_n_0 ,\M_AXIS_TDATA[7]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[8]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[8]),
.Q(M_AXIS_TDATA[8]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[9]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[9]),
.Q(M_AXIS_TDATA[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
M_AXIS_TVALID_reg
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(S_AXIS_TVALID),
.Q(M_AXIS_TVALID),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
S_AXIS_TREADY_INST_0
(.I0(M_AXIS_TREADY),
.I1(M_AXIS_TVALID),
.O(S_AXIS_TREADY));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_axis_audio_stereo2mo_0_0
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TREADY);
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [31:0]S_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [15:0]M_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
wire AXIS_ACLK;
wire [15:0]M_AXIS_TDATA;
wire M_AXIS_TREADY;
wire M_AXIS_TVALID;
wire [31:0]S_AXIS_TDATA;
wire S_AXIS_TREADY;
wire S_AXIS_TVALID;
wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
(* HAS_LAST = "FALSE" *)
design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono U0
(.AXIS_ACLK(AXIS_ACLK),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.S_AXIS_TDATA({S_AXIS_TDATA[31:17],1'b0,S_AXIS_TDATA[15:1],1'b0}),
.S_AXIS_TLAST(1'b0),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TVALID(S_AXIS_TVALID));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_sim_netlist.vhdl
-491
View File
@@ -1,491 +0,0 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:47 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
-- design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_sim_netlist.vhdl
-- Design : design_1_axis_audio_stereo2mo_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
attribute HAS_LAST : string;
attribute HAS_LAST of design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono : entity is "FALSE";
end design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono;
architecture STRUCTURE of design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono is
signal \<const0>\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \^m_axis_tvalid\ : STD_LOGIC;
signal \^s_axis_tready\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
M_AXIS_TLAST <= \<const0>\;
M_AXIS_TVALID <= \^m_axis_tvalid\;
S_AXIS_TREADY <= \^s_axis_tready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\M_AXIS_TDATA[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(28),
I1 => S_AXIS_TDATA(12),
O => \M_AXIS_TDATA[11]_i_2_n_0\
);
\M_AXIS_TDATA[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(27),
I1 => S_AXIS_TDATA(11),
O => \M_AXIS_TDATA[11]_i_3_n_0\
);
\M_AXIS_TDATA[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(26),
I1 => S_AXIS_TDATA(10),
O => \M_AXIS_TDATA[11]_i_4_n_0\
);
\M_AXIS_TDATA[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(25),
I1 => S_AXIS_TDATA(9),
O => \M_AXIS_TDATA[11]_i_5_n_0\
);
\M_AXIS_TDATA[15]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => S_AXIS_TDATA(31),
O => \M_AXIS_TDATA[15]_i_2_n_0\
);
\M_AXIS_TDATA[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(31),
I1 => S_AXIS_TDATA(15),
O => \M_AXIS_TDATA[15]_i_3_n_0\
);
\M_AXIS_TDATA[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(30),
I1 => S_AXIS_TDATA(14),
O => \M_AXIS_TDATA[15]_i_4_n_0\
);
\M_AXIS_TDATA[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(29),
I1 => S_AXIS_TDATA(13),
O => \M_AXIS_TDATA[15]_i_5_n_0\
);
\M_AXIS_TDATA[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(20),
I1 => S_AXIS_TDATA(4),
O => \M_AXIS_TDATA[3]_i_2_n_0\
);
\M_AXIS_TDATA[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(19),
I1 => S_AXIS_TDATA(3),
O => \M_AXIS_TDATA[3]_i_3_n_0\
);
\M_AXIS_TDATA[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(18),
I1 => S_AXIS_TDATA(2),
O => \M_AXIS_TDATA[3]_i_4_n_0\
);
\M_AXIS_TDATA[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(17),
I1 => S_AXIS_TDATA(1),
O => \M_AXIS_TDATA[3]_i_5_n_0\
);
\M_AXIS_TDATA[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(24),
I1 => S_AXIS_TDATA(8),
O => \M_AXIS_TDATA[7]_i_2_n_0\
);
\M_AXIS_TDATA[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(23),
I1 => S_AXIS_TDATA(7),
O => \M_AXIS_TDATA[7]_i_3_n_0\
);
\M_AXIS_TDATA[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(22),
I1 => S_AXIS_TDATA(6),
O => \M_AXIS_TDATA[7]_i_4_n_0\
);
\M_AXIS_TDATA[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(21),
I1 => S_AXIS_TDATA(5),
O => \M_AXIS_TDATA[7]_i_5_n_0\
);
\M_AXIS_TDATA_reg[0]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(0),
Q => M_AXIS_TDATA(0),
R => '0'
);
\M_AXIS_TDATA_reg[10]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(10),
Q => M_AXIS_TDATA(10),
R => '0'
);
\M_AXIS_TDATA_reg[11]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(11),
Q => M_AXIS_TDATA(11),
R => '0'
);
\M_AXIS_TDATA_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \M_AXIS_TDATA_reg[7]_i_1_n_0\,
CO(3) => \M_AXIS_TDATA_reg[11]_i_1_n_0\,
CO(2) => \M_AXIS_TDATA_reg[11]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[11]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => S_AXIS_TDATA(28 downto 25),
O(3 downto 0) => p_0_in(11 downto 8),
S(3) => \M_AXIS_TDATA[11]_i_2_n_0\,
S(2) => \M_AXIS_TDATA[11]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[11]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[11]_i_5_n_0\
);
\M_AXIS_TDATA_reg[12]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(12),
Q => M_AXIS_TDATA(12),
R => '0'
);
\M_AXIS_TDATA_reg[13]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(13),
Q => M_AXIS_TDATA(13),
R => '0'
);
\M_AXIS_TDATA_reg[14]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(14),
Q => M_AXIS_TDATA(14),
R => '0'
);
\M_AXIS_TDATA_reg[15]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(15),
Q => M_AXIS_TDATA(15),
R => '0'
);
\M_AXIS_TDATA_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \M_AXIS_TDATA_reg[11]_i_1_n_0\,
CO(3) => \NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \M_AXIS_TDATA_reg[15]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[15]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \M_AXIS_TDATA[15]_i_2_n_0\,
DI(1 downto 0) => S_AXIS_TDATA(30 downto 29),
O(3 downto 0) => p_0_in(15 downto 12),
S(3) => '1',
S(2) => \M_AXIS_TDATA[15]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[15]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[15]_i_5_n_0\
);
\M_AXIS_TDATA_reg[1]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(1),
Q => M_AXIS_TDATA(1),
R => '0'
);
\M_AXIS_TDATA_reg[2]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(2),
Q => M_AXIS_TDATA(2),
R => '0'
);
\M_AXIS_TDATA_reg[3]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(3),
Q => M_AXIS_TDATA(3),
R => '0'
);
\M_AXIS_TDATA_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \M_AXIS_TDATA_reg[3]_i_1_n_0\,
CO(2) => \M_AXIS_TDATA_reg[3]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[3]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => S_AXIS_TDATA(20 downto 17),
O(3 downto 0) => p_0_in(3 downto 0),
S(3) => \M_AXIS_TDATA[3]_i_2_n_0\,
S(2) => \M_AXIS_TDATA[3]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[3]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[3]_i_5_n_0\
);
\M_AXIS_TDATA_reg[4]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(4),
Q => M_AXIS_TDATA(4),
R => '0'
);
\M_AXIS_TDATA_reg[5]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(5),
Q => M_AXIS_TDATA(5),
R => '0'
);
\M_AXIS_TDATA_reg[6]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(6),
Q => M_AXIS_TDATA(6),
R => '0'
);
\M_AXIS_TDATA_reg[7]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(7),
Q => M_AXIS_TDATA(7),
R => '0'
);
\M_AXIS_TDATA_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \M_AXIS_TDATA_reg[3]_i_1_n_0\,
CO(3) => \M_AXIS_TDATA_reg[7]_i_1_n_0\,
CO(2) => \M_AXIS_TDATA_reg[7]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[7]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => S_AXIS_TDATA(24 downto 21),
O(3 downto 0) => p_0_in(7 downto 4),
S(3) => \M_AXIS_TDATA[7]_i_2_n_0\,
S(2) => \M_AXIS_TDATA[7]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[7]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[7]_i_5_n_0\
);
\M_AXIS_TDATA_reg[8]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(8),
Q => M_AXIS_TDATA(8),
R => '0'
);
\M_AXIS_TDATA_reg[9]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(9),
Q => M_AXIS_TDATA(9),
R => '0'
);
M_AXIS_TVALID_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => S_AXIS_TVALID,
Q => \^m_axis_tvalid\,
R => '0'
);
S_AXIS_TREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => M_AXIS_TREADY,
I1 => \^m_axis_tvalid\,
O => \^s_axis_tready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_stereo2mo_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_axis_audio_stereo2mo_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_axis_audio_stereo2mo_0_0 : entity is "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_axis_audio_stereo2mo_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of design_1_axis_audio_stereo2mo_0_0 : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of design_1_axis_audio_stereo2mo_0_0 : entity is "axis_audio_stereo2mono,Vivado 2023.1";
end design_1_axis_audio_stereo2mo_0_0;
architecture STRUCTURE of design_1_axis_audio_stereo2mo_0_0 is
signal NLW_U0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
attribute HAS_LAST : string;
attribute HAS_LAST of U0 : label is "FALSE";
attribute x_interface_info : string;
attribute x_interface_info of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
attribute x_interface_info of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
attribute x_interface_parameter of M_AXIS_TVALID : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
attribute x_interface_info of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
attribute x_interface_parameter of S_AXIS_TVALID : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
attribute x_interface_info of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
begin
U0: entity work.design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
port map (
AXIS_ACLK => AXIS_ACLK,
M_AXIS_TDATA(15 downto 0) => M_AXIS_TDATA(15 downto 0),
M_AXIS_TLAST => NLW_U0_M_AXIS_TLAST_UNCONNECTED,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
S_AXIS_TDATA(31 downto 17) => S_AXIS_TDATA(31 downto 17),
S_AXIS_TDATA(16) => '0',
S_AXIS_TDATA(15 downto 1) => S_AXIS_TDATA(15 downto 1),
S_AXIS_TDATA(0) => '0',
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TVALID => S_AXIS_TVALID
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:47 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
// design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_stub.v
// Design : design_1_axis_audio_stereo2mo_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
module design_1_axis_audio_stereo2mo_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA,
S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY" */
/* synthesis syn_force_seq_prim="AXIS_ACLK" */;
input AXIS_ACLK /* synthesis syn_isclock = 1 */;
input S_AXIS_TVALID;
input [31:0]S_AXIS_TDATA;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [15:0]M_AXIS_TDATA;
input M_AXIS_TREADY;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:47 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
-- design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_stub.vhdl
-- Design : design_1_axis_audio_stereo2mo_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axis_audio_stereo2mo_0_0 is
Port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end design_1_axis_audio_stereo2mo_0_0;
architecture stub of design_1_axis_audio_stereo2mo_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_audio_stereo2mono,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/sim/design_1_axis_audio_stereo2mo_0_0.vhd
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-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_audio_stereo2mo_0_0 IS
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC
);
END design_1_axis_audio_stereo2mo_0_0;
ARCHITECTURE design_1_axis_audio_stereo2mo_0_0_arch OF design_1_axis_audio_stereo2mo_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_stereo2mono IS
GENERIC (
HAS_LAST : BOOLEAN
);
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_audio_stereo2mono;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_stereo2mono
GENERIC MAP (
HAS_LAST => false
)
PORT MAP (
AXIS_ACLK => AXIS_ACLK,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY
);
END design_1_axis_audio_stereo2mo_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/synth/design_1_axis_audio_stereo2mo_0_0.vhd
-122
View File
@@ -1,122 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_audio_stereo2mo_0_0 IS
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC
);
END design_1_axis_audio_stereo2mo_0_0;
ARCHITECTURE design_1_axis_audio_stereo2mo_0_0_arch OF design_1_axis_audio_stereo2mo_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_audio_stereo2mono IS
GENERIC (
HAS_LAST : BOOLEAN
);
PORT (
AXIS_ACLK : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_audio_stereo2mono;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "axis_audio_stereo2mono,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_audio_stereo2mo_0_0_arch : ARCHITECTURE IS "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_stereo2mono,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HAS_LAST=false}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "package_project";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_audio_stereo2mono
GENERIC MAP (
HAS_LAST => false
)
PORT MAP (
AXIS_ACLK => AXIS_ACLK,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TREADY => M_AXIS_TREADY
);
END design_1_axis_audio_stereo2mo_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml
+27 -203
View File
@@ -882,101 +882,6 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_prog_audio_filter3</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:15e36279</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axis_prog_audio_filter3</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 13:45:05 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axis_prog_audio_filt_0_1</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 13:43:04 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:15e36279</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_axis_prog_audio_filt_0_1</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 13:43:04 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>AXI_ACLK</spirit:name>
@@ -985,8 +890,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -998,8 +902,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1015,8 +918,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1031,8 +933,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1047,8 +948,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1064,8 +964,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1080,8 +979,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1096,8 +994,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1113,8 +1010,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1129,8 +1025,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1142,8 +1037,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1162,8 +1056,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1179,8 +1072,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1195,8 +1087,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1211,8 +1102,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1228,8 +1118,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1241,8 +1130,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1254,8 +1142,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1274,8 +1161,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1287,8 +1173,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1304,8 +1189,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1320,8 +1204,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1336,8 +1219,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1349,8 +1231,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1366,8 +1247,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1379,8 +1259,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1392,8 +1271,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1442,60 +1320,6 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>design_1_axis_prog_audio_filt_0_1.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_prog_audio_filt_0_1_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_prog_audio_filt_0_1_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_prog_audio_filt_0_1_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_axis_prog_audio_filt_0_1_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/design_1_axis_prog_audio_filt_0_1.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/design_1_axis_prog_audio_filt_0_1.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axis_prog_audio_filter3:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_sim_netlist.v
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_sim_netlist.vhdl
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Tue Nov 26 14:45:05 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v
// Design : design_1_axis_prog_audio_filt_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_prog_audio_filter3,Vivado 2023.1" *)
module design_1_axis_prog_audio_filt_0_1(AXI_ACLK, AXI_ARESETN, S_AXIL_AWADDR,
S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB,
S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY,
S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP, S_AXIS_TVALID, S_AXIS_TDATA,
S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY)
/* synthesis syn_black_box black_box_pad_pin="AXI_ARESETN,S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY" */
/* synthesis syn_force_seq_prim="AXI_ACLK" */;
input AXI_ACLK /* synthesis syn_isclock = 1 */;
input AXI_ARESETN;
input [7:0]S_AXIL_AWADDR;
input S_AXIL_AWVALID;
output S_AXIL_AWREADY;
input [31:0]S_AXIL_WDATA;
input S_AXIL_WVALID;
output S_AXIL_WREADY;
input [3:0]S_AXIL_WSTRB;
output S_AXIL_BVALID;
input S_AXIL_BREADY;
output [1:0]S_AXIL_BRESP;
input [7:0]S_AXIL_ARADDR;
input S_AXIL_ARVALID;
output S_AXIL_ARREADY;
output [31:0]S_AXIL_RDATA;
output S_AXIL_RVALID;
input S_AXIL_RREADY;
output [1:0]S_AXIL_RRESP;
input S_AXIS_TVALID;
input [15:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [15:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.vhdl
-57
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@@ -1,57 +0,0 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Tue Nov 26 14:45:05 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.vhdl
-- Design : design_1_axis_prog_audio_filt_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axis_prog_audio_filt_0_1 is
Port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end design_1_axis_prog_audio_filt_0_1;
architecture stub of design_1_axis_prog_audio_filt_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "AXI_ACLK,AXI_ARESETN,S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_prog_audio_filter3,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/sim/design_1_axis_prog_audio_filt_0_1.vhd
-204
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@@ -1,204 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_prog_audio_filt_0_1 IS
PORT (
AXI_ACLK : IN STD_LOGIC;
AXI_ARESETN : IN STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END design_1_axis_prog_audio_filt_0_1;
ARCHITECTURE design_1_axis_prog_audio_filt_0_1_arch OF design_1_axis_prog_audio_filt_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axis_prog_audio_filter3 IS
GENERIC (
COEFF_0 : INTEGER;
COEFF_1 : INTEGER;
COEFF_2 : INTEGER;
SHIFT : INTEGER;
RUN_AFTER_RESET : BOOLEAN;
HAS_LAST : BOOLEAN
);
PORT (
AXI_ACLK : IN STD_LOGIC;
AXI_ARESETN : IN STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_prog_audio_filter3;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
"ITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_prog_audio_filter3
GENERIC MAP (
COEFF_0 => 42,
COEFF_1 => 42,
COEFF_2 => 42,
SHIFT => 7,
RUN_AFTER_RESET => true,
HAS_LAST => false
)
PORT MAP (
AXI_ACLK => AXI_ACLK,
AXI_ARESETN => AXI_ARESETN,
S_AXIL_AWADDR => S_AXIL_AWADDR,
S_AXIL_AWVALID => S_AXIL_AWVALID,
S_AXIL_AWREADY => S_AXIL_AWREADY,
S_AXIL_WDATA => S_AXIL_WDATA,
S_AXIL_WVALID => S_AXIL_WVALID,
S_AXIL_WREADY => S_AXIL_WREADY,
S_AXIL_WSTRB => S_AXIL_WSTRB,
S_AXIL_BVALID => S_AXIL_BVALID,
S_AXIL_BREADY => S_AXIL_BREADY,
S_AXIL_BRESP => S_AXIL_BRESP,
S_AXIL_ARADDR => S_AXIL_ARADDR,
S_AXIL_ARVALID => S_AXIL_ARVALID,
S_AXIL_ARREADY => S_AXIL_ARREADY,
S_AXIL_RDATA => S_AXIL_RDATA,
S_AXIL_RVALID => S_AXIL_RVALID,
S_AXIL_RREADY => S_AXIL_RREADY,
S_AXIL_RRESP => S_AXIL_RRESP,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
END design_1_axis_prog_audio_filt_0_1_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/synth/design_1_axis_prog_audio_filt_0_1.vhd
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@@ -1,212 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axis_prog_audio_filt_0_1 IS
PORT (
AXI_ACLK : IN STD_LOGIC;
AXI_ARESETN : IN STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END design_1_axis_prog_audio_filt_0_1;
ARCHITECTURE design_1_axis_prog_audio_filt_0_1_arch OF design_1_axis_prog_audio_filt_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axis_prog_audio_filter3 IS
GENERIC (
COEFF_0 : INTEGER;
COEFF_1 : INTEGER;
COEFF_2 : INTEGER;
SHIFT : INTEGER;
RUN_AFTER_RESET : BOOLEAN;
HAS_LAST : BOOLEAN
);
PORT (
AXI_ACLK : IN STD_LOGIC;
AXI_ARESETN : IN STD_LOGIC;
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_AWVALID : IN STD_LOGIC;
S_AXIL_AWREADY : OUT STD_LOGIC;
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_WVALID : IN STD_LOGIC;
S_AXIL_WREADY : OUT STD_LOGIC;
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIL_BVALID : OUT STD_LOGIC;
S_AXIL_BREADY : IN STD_LOGIC;
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXIL_ARVALID : IN STD_LOGIC;
S_AXIL_ARREADY : OUT STD_LOGIC;
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIL_RVALID : OUT STD_LOGIC;
S_AXIL_RREADY : IN STD_LOGIC;
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC
);
END COMPONENT axis_prog_audio_filter3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "axis_prog_audio_filter3,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_prog_audio_filt_0_1_arch : ARCHITECTURE IS "design_1_axis_prog_audio_filt_0_1,axis_prog_audio_filter3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "design_1_axis_prog_audio_filt_0_1,axis_prog_audio_filter3,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_prog_audio_filter3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,COEFF_0=42,COEFF_1=42,COEFF_2=42,SHIFT=7,RUN_AFTER_RESET=true,HAS_LAST=false}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
"ITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
BEGIN
U0 : axis_prog_audio_filter3
GENERIC MAP (
COEFF_0 => 42,
COEFF_1 => 42,
COEFF_2 => 42,
SHIFT => 7,
RUN_AFTER_RESET => true,
HAS_LAST => false
)
PORT MAP (
AXI_ACLK => AXI_ACLK,
AXI_ARESETN => AXI_ARESETN,
S_AXIL_AWADDR => S_AXIL_AWADDR,
S_AXIL_AWVALID => S_AXIL_AWVALID,
S_AXIL_AWREADY => S_AXIL_AWREADY,
S_AXIL_WDATA => S_AXIL_WDATA,
S_AXIL_WVALID => S_AXIL_WVALID,
S_AXIL_WREADY => S_AXIL_WREADY,
S_AXIL_WSTRB => S_AXIL_WSTRB,
S_AXIL_BVALID => S_AXIL_BVALID,
S_AXIL_BREADY => S_AXIL_BREADY,
S_AXIL_BRESP => S_AXIL_BRESP,
S_AXIL_ARADDR => S_AXIL_ARADDR,
S_AXIL_ARVALID => S_AXIL_ARVALID,
S_AXIL_ARREADY => S_AXIL_ARREADY,
S_AXIL_RDATA => S_AXIL_RDATA,
S_AXIL_RVALID => S_AXIL_RVALID,
S_AXIL_RREADY => S_AXIL_RREADY,
S_AXIL_RRESP => S_AXIL_RRESP,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
END design_1_axis_prog_audio_filt_0_1_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator.xdc
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_clocks.xdc
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/constrs_1/new/clk_rst_generator_ooc.xdc
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create_clock -period 10.000 -name clk_in -waveform {0.000 5.000} [get_ports clk_in]
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
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@@ -5,115 +5,6 @@
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<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
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<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5839f862</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_clk_rst_generator_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a3a4ca5c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>design_1_clk_rst_generator_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5839f862</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk_in</spirit:name>
@@ -122,8 +13,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -145,8 +35,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -168,8 +57,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -181,8 +69,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -194,8 +81,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -234,86 +120,6 @@
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>constrs_1/new/clk_rst_generator.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/clk_rst_generator_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>constrs_1/new/clk_rst_generator_clocks.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>design_1_clk_rst_generator_0_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_clk_rst_generator_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_clk_rst_generator_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_clk_rst_generator_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_clk_rst_generator_0_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/design_1_clk_rst_generator_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/design_1_clk_rst_generator_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>clk_rst_generator</spirit:description>
<spirit:parameters>
<spirit:parameter>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.v
-375
View File
@@ -1,375 +0,0 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:45 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_clk_rst_generator_0_0 -prefix
// design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_sim_netlist.v
// Design : design_1_clk_rst_generator_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CLOCK_PERIOD = "10000" *) (* HAS_CLK_INPUT = "TRUE" *) (* HAS_RESET_INPUT = "TRUE" *)
(* HAS_STOP_INPUT = "TRUE" *)
module design_1_clk_rst_generator_0_0_clk_rst_generator
(clk_in,
rst_in,
clk,
rst_n,
stop_simulation);
input clk_in;
input rst_in;
output clk;
output rst_n;
input stop_simulation;
wire [4:0]L;
wire clk_in;
wire [6:0]rescnt;
wire \rescnt[3]_i_5_n_0 ;
wire \rescnt[3]_i_6_n_0 ;
wire \rescnt[3]_i_7_n_0 ;
wire \rescnt[3]_i_8_n_0 ;
wire \rescnt[6]_i_4_n_0 ;
wire \rescnt[6]_i_5_n_0 ;
wire \rescnt[6]_i_6_n_0 ;
wire [6:0]rescnt_reg;
wire \rescnt_reg[3]_i_1_n_0 ;
wire \rescnt_reg[3]_i_1_n_1 ;
wire \rescnt_reg[3]_i_1_n_2 ;
wire \rescnt_reg[3]_i_1_n_3 ;
wire \rescnt_reg[6]_i_1_n_2 ;
wire \rescnt_reg[6]_i_1_n_3 ;
wire rst_in;
wire rst_in_sync;
wire rst_n;
wire rst_sig;
wire rst_sig_i_1_n_0;
wire rst_sig_i_2_n_0;
wire rst_sig_reg_n_0;
wire [3:2]\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED ;
assign clk = clk_in;
LUT2 #(
.INIT(4'hE))
\rescnt[3]_i_2
(.I0(rst_in_sync),
.I1(rescnt_reg[2]),
.O(L[2]));
LUT5 #(
.INIT(32'h00000001))
\rescnt[3]_i_3
(.I0(rescnt_reg[6]),
.I1(rescnt_reg[4]),
.I2(rst_in_sync),
.I3(rescnt_reg[5]),
.I4(rst_sig_i_2_n_0),
.O(rst_sig));
LUT2 #(
.INIT(4'hE))
\rescnt[3]_i_4
(.I0(rst_in_sync),
.I1(rescnt_reg[0]),
.O(L[0]));
LUT3 #(
.INIT(8'hF9))
\rescnt[3]_i_5
(.I0(rescnt_reg[2]),
.I1(rescnt_reg[3]),
.I2(rst_in_sync),
.O(\rescnt[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h000000000001FFFE))
\rescnt[3]_i_6
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rescnt_reg[4]),
.I3(rescnt_reg[6]),
.I4(rescnt_reg[2]),
.I5(rst_in_sync),
.O(\rescnt[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000000000001FFFE))
\rescnt[3]_i_7
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rescnt_reg[4]),
.I3(rescnt_reg[6]),
.I4(rescnt_reg[1]),
.I5(rst_in_sync),
.O(\rescnt[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0055005500550056))
\rescnt[3]_i_8
(.I0(rescnt_reg[0]),
.I1(rst_sig_i_2_n_0),
.I2(rescnt_reg[5]),
.I3(rst_in_sync),
.I4(rescnt_reg[4]),
.I5(rescnt_reg[6]),
.O(\rescnt[3]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\rescnt[6]_i_2
(.I0(rst_in_sync),
.I1(rescnt_reg[4]),
.O(L[4]));
LUT2 #(
.INIT(4'hE))
\rescnt[6]_i_3
(.I0(rst_in_sync),
.I1(rescnt_reg[3]),
.O(L[3]));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_4
(.I0(rescnt_reg[5]),
.I1(rescnt_reg[6]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_4_n_0 ));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_5
(.I0(rescnt_reg[4]),
.I1(rescnt_reg[5]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_5_n_0 ));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_6
(.I0(rescnt_reg[3]),
.I1(rescnt_reg[4]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_6_n_0 ));
FDRE #(
.INIT(1'b1))
\rescnt_reg[0]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[0]),
.Q(rescnt_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[1]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[1]),
.Q(rescnt_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[2]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[2]),
.Q(rescnt_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[3]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[3]),
.Q(rescnt_reg[3]),
.R(1'b0));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \rescnt_reg[3]_i_1
(.CI(1'b0),
.CO({\rescnt_reg[3]_i_1_n_0 ,\rescnt_reg[3]_i_1_n_1 ,\rescnt_reg[3]_i_1_n_2 ,\rescnt_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({L[2],rst_sig,rst_sig_i_1_n_0,L[0]}),
.O(rescnt[3:0]),
.S({\rescnt[3]_i_5_n_0 ,\rescnt[3]_i_6_n_0 ,\rescnt[3]_i_7_n_0 ,\rescnt[3]_i_8_n_0 }));
FDRE #(
.INIT(1'b1))
\rescnt_reg[4]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[4]),
.Q(rescnt_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[5]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[5]),
.Q(rescnt_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[6]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[6]),
.Q(rescnt_reg[6]),
.R(1'b0));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \rescnt_reg[6]_i_1
(.CI(\rescnt_reg[3]_i_1_n_0 ),
.CO({\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED [3:2],\rescnt_reg[6]_i_1_n_2 ,\rescnt_reg[6]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,L[4:3]}),
.O({\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED [3],rescnt[6:4]}),
.S({1'b0,\rescnt[6]_i_4_n_0 ,\rescnt[6]_i_5_n_0 ,\rescnt[6]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
rst_in_sync_reg
(.C(clk_in),
.CE(1'b1),
.D(rst_in),
.Q(rst_in_sync),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_n_INST_0
(.I0(rst_sig_reg_n_0),
.O(rst_n));
LUT5 #(
.INIT(32'hFFFFFFFE))
rst_sig_i_1
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rst_in_sync),
.I3(rescnt_reg[4]),
.I4(rescnt_reg[6]),
.O(rst_sig_i_1_n_0));
LUT5 #(
.INIT(32'hFFFFFFFE))
rst_sig_i_2
(.I0(rescnt_reg[2]),
.I1(rescnt_reg[3]),
.I2(rst_in_sync),
.I3(rescnt_reg[0]),
.I4(rescnt_reg[1]),
.O(rst_sig_i_2_n_0));
FDRE #(
.INIT(1'b0))
rst_sig_reg
(.C(clk_in),
.CE(1'b1),
.D(rst_sig_i_1_n_0),
.Q(rst_sig_reg_n_0),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_clk_rst_generator_0_0,clk_rst_generator,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_clk_rst_generator_0_0
(clk_in,
rst_in,
clk,
rst_n,
stop_simulation);
input clk_in;
input rst_in;
output clk;
output rst_n;
input stop_simulation;
wire clk;
wire clk_in;
wire rst_in;
wire rst_n;
(* CLOCK_PERIOD = "10000" *)
(* HAS_CLK_INPUT = "TRUE" *)
(* HAS_RESET_INPUT = "TRUE" *)
(* HAS_STOP_INPUT = "TRUE" *)
design_1_clk_rst_generator_0_0_clk_rst_generator U0
(.clk(clk),
.clk_in(clk_in),
.rst_in(rst_in),
.rst_n(rst_n),
.stop_simulation(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.vhdl
-402
View File
@@ -1,402 +0,0 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:45 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_clk_rst_generator_0_0 -prefix
-- design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_sim_netlist.vhdl
-- Design : design_1_clk_rst_generator_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_clk_rst_generator_0_0_clk_rst_generator is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
attribute CLOCK_PERIOD : integer;
attribute CLOCK_PERIOD of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is 10000;
attribute HAS_CLK_INPUT : string;
attribute HAS_CLK_INPUT of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
attribute HAS_RESET_INPUT : string;
attribute HAS_RESET_INPUT of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
attribute HAS_STOP_INPUT : string;
attribute HAS_STOP_INPUT of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
end design_1_clk_rst_generator_0_0_clk_rst_generator;
architecture STRUCTURE of design_1_clk_rst_generator_0_0_clk_rst_generator is
signal L : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^clk_in\ : STD_LOGIC;
signal rescnt : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \rescnt[3]_i_5_n_0\ : STD_LOGIC;
signal \rescnt[3]_i_6_n_0\ : STD_LOGIC;
signal \rescnt[3]_i_7_n_0\ : STD_LOGIC;
signal \rescnt[3]_i_8_n_0\ : STD_LOGIC;
signal \rescnt[6]_i_4_n_0\ : STD_LOGIC;
signal \rescnt[6]_i_5_n_0\ : STD_LOGIC;
signal \rescnt[6]_i_6_n_0\ : STD_LOGIC;
signal rescnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \rescnt_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rescnt_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rescnt_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rescnt_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rescnt_reg[6]_i_1_n_2\ : STD_LOGIC;
signal \rescnt_reg[6]_i_1_n_3\ : STD_LOGIC;
signal rst_in_sync : STD_LOGIC;
signal rst_sig : STD_LOGIC;
signal rst_sig_i_1_n_0 : STD_LOGIC;
signal rst_sig_i_2_n_0 : STD_LOGIC;
signal rst_sig_reg_n_0 : STD_LOGIC;
signal \NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rescnt_reg[6]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \rescnt_reg[3]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \rescnt_reg[6]_i_1\ : label is 35;
begin
\^clk_in\ <= clk_in;
clk <= \^clk_in\;
\rescnt[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(2),
O => L(2)
);
\rescnt[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => rescnt_reg(6),
I1 => rescnt_reg(4),
I2 => rst_in_sync,
I3 => rescnt_reg(5),
I4 => rst_sig_i_2_n_0,
O => rst_sig
);
\rescnt[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(0),
O => L(0)
);
\rescnt[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(2),
I1 => rescnt_reg(3),
I2 => rst_in_sync,
O => \rescnt[3]_i_5_n_0\
);
\rescnt[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000001FFFE"
)
port map (
I0 => rst_sig_i_2_n_0,
I1 => rescnt_reg(5),
I2 => rescnt_reg(4),
I3 => rescnt_reg(6),
I4 => rescnt_reg(2),
I5 => rst_in_sync,
O => \rescnt[3]_i_6_n_0\
);
\rescnt[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000001FFFE"
)
port map (
I0 => rst_sig_i_2_n_0,
I1 => rescnt_reg(5),
I2 => rescnt_reg(4),
I3 => rescnt_reg(6),
I4 => rescnt_reg(1),
I5 => rst_in_sync,
O => \rescnt[3]_i_7_n_0\
);
\rescnt[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055005500550056"
)
port map (
I0 => rescnt_reg(0),
I1 => rst_sig_i_2_n_0,
I2 => rescnt_reg(5),
I3 => rst_in_sync,
I4 => rescnt_reg(4),
I5 => rescnt_reg(6),
O => \rescnt[3]_i_8_n_0\
);
\rescnt[6]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(4),
O => L(4)
);
\rescnt[6]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(3),
O => L(3)
);
\rescnt[6]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(5),
I1 => rescnt_reg(6),
I2 => rst_in_sync,
O => \rescnt[6]_i_4_n_0\
);
\rescnt[6]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(4),
I1 => rescnt_reg(5),
I2 => rst_in_sync,
O => \rescnt[6]_i_5_n_0\
);
\rescnt[6]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(3),
I1 => rescnt_reg(4),
I2 => rst_in_sync,
O => \rescnt[6]_i_6_n_0\
);
\rescnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(0),
Q => rescnt_reg(0),
R => '0'
);
\rescnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(1),
Q => rescnt_reg(1),
R => '0'
);
\rescnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(2),
Q => rescnt_reg(2),
R => '0'
);
\rescnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(3),
Q => rescnt_reg(3),
R => '0'
);
\rescnt_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rescnt_reg[3]_i_1_n_0\,
CO(2) => \rescnt_reg[3]_i_1_n_1\,
CO(1) => \rescnt_reg[3]_i_1_n_2\,
CO(0) => \rescnt_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => L(2),
DI(2) => rst_sig,
DI(1) => rst_sig_i_1_n_0,
DI(0) => L(0),
O(3 downto 0) => rescnt(3 downto 0),
S(3) => \rescnt[3]_i_5_n_0\,
S(2) => \rescnt[3]_i_6_n_0\,
S(1) => \rescnt[3]_i_7_n_0\,
S(0) => \rescnt[3]_i_8_n_0\
);
\rescnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(4),
Q => rescnt_reg(4),
R => '0'
);
\rescnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(5),
Q => rescnt_reg(5),
R => '0'
);
\rescnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(6),
Q => rescnt_reg(6),
R => '0'
);
\rescnt_reg[6]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rescnt_reg[3]_i_1_n_0\,
CO(3 downto 2) => \NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rescnt_reg[6]_i_1_n_2\,
CO(0) => \rescnt_reg[6]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => L(4 downto 3),
O(3) => \NLW_rescnt_reg[6]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rescnt(6 downto 4),
S(3) => '0',
S(2) => \rescnt[6]_i_4_n_0\,
S(1) => \rescnt[6]_i_5_n_0\,
S(0) => \rescnt[6]_i_6_n_0\
);
rst_in_sync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_in\,
CE => '1',
D => rst_in,
Q => rst_in_sync,
R => '0'
);
rst_n_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_sig_reg_n_0,
O => rst_n
);
rst_sig_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rst_sig_i_2_n_0,
I1 => rescnt_reg(5),
I2 => rst_in_sync,
I3 => rescnt_reg(4),
I4 => rescnt_reg(6),
O => rst_sig_i_1_n_0
);
rst_sig_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rescnt_reg(2),
I1 => rescnt_reg(3),
I2 => rst_in_sync,
I3 => rescnt_reg(0),
I4 => rescnt_reg(1),
O => rst_sig_i_2_n_0
);
rst_sig_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_in\,
CE => '1',
D => rst_sig_i_1_n_0,
Q => rst_sig_reg_n_0,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_clk_rst_generator_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_clk_rst_generator_0_0 : entity is "design_1_clk_rst_generator_0_0,clk_rst_generator,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_clk_rst_generator_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of design_1_clk_rst_generator_0_0 : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of design_1_clk_rst_generator_0_0 : entity is "clk_rst_generator,Vivado 2023.1";
end design_1_clk_rst_generator_0_0;
architecture STRUCTURE of design_1_clk_rst_generator_0_0 is
attribute CLOCK_PERIOD : integer;
attribute CLOCK_PERIOD of U0 : label is 10000;
attribute HAS_CLK_INPUT : string;
attribute HAS_CLK_INPUT of U0 : label is "TRUE";
attribute HAS_RESET_INPUT : string;
attribute HAS_RESET_INPUT of U0 : label is "TRUE";
attribute HAS_STOP_INPUT : string;
attribute HAS_STOP_INPUT of U0 : label is "TRUE";
begin
U0: entity work.design_1_clk_rst_generator_0_0_clk_rst_generator
port map (
clk => clk,
clk_in => clk_in,
rst_in => rst_in,
rst_n => rst_n,
stop_simulation => '0'
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.v
-27
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@@ -1,27 +0,0 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:45 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_clk_rst_generator_0_0 -prefix
// design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_stub.v
// Design : design_1_clk_rst_generator_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
module design_1_clk_rst_generator_0_0(clk_in, rst_in, clk, rst_n, stop_simulation)
/* synthesis syn_black_box black_box_pad_pin="rst_in,rst_n,stop_simulation" */
/* synthesis syn_force_seq_prim="clk_in" */
/* synthesis syn_force_seq_prim="clk" */;
input clk_in /* synthesis syn_isclock = 1 */;
input rst_in;
output clk /* synthesis syn_isclock = 1 */;
output rst_n;
input stop_simulation;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.vhdl
-35
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@@ -1,35 +0,0 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:45 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_clk_rst_generator_0_0 -prefix
-- design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_stub.vhdl
-- Design : design_1_clk_rst_generator_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_clk_rst_generator_0_0 is
Port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end design_1_clk_rst_generator_0_0;
architecture stub of design_1_clk_rst_generator_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,rst_in,clk,rst_n,stop_simulation";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clk_rst_generator,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/sim/design_1_clk_rst_generator_0_0.vhd
-99
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@@ -1,99 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:clk_rst_generator:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_clk_rst_generator_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END design_1_clk_rst_generator_0_0;
ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clk_rst_generator IS
GENERIC (
CLOCK_PERIOD : INTEGER;
HAS_CLK_INPUT : BOOLEAN;
HAS_RESET_INPUT : BOOLEAN;
HAS_STOP_INPUT : BOOLEAN
);
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END COMPONENT clk_rst_generator;
BEGIN
U0 : clk_rst_generator
GENERIC MAP (
CLOCK_PERIOD => 10000,
HAS_CLK_INPUT => true,
HAS_RESET_INPUT => true,
HAS_STOP_INPUT => true
)
PORT MAP (
clk_in => clk_in,
rst_in => rst_in,
clk => clk,
rst_n => rst_n,
stop_simulation => stop_simulation
);
END design_1_clk_rst_generator_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/synth/design_1_clk_rst_generator_0_0.vhd
-105
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@@ -1,105 +0,0 @@
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: wg:user:clk_rst_generator:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_clk_rst_generator_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END design_1_clk_rst_generator_0_0;
ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clk_rst_generator IS
GENERIC (
CLOCK_PERIOD : INTEGER;
HAS_CLK_INPUT : BOOLEAN;
HAS_RESET_INPUT : BOOLEAN;
HAS_STOP_INPUT : BOOLEAN
);
PORT (
clk_in : IN STD_LOGIC;
rst_in : IN STD_LOGIC;
clk : OUT STD_LOGIC;
rst_n : OUT STD_LOGIC;
stop_simulation : IN STD_LOGIC
);
END COMPONENT clk_rst_generator;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "clk_rst_generator,Vivado 2023.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_clk_rst_generator_0_0_arch : ARCHITECTURE IS "design_1_clk_rst_generator_0_0,clk_rst_generator,{}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "package_project";
BEGIN
U0 : clk_rst_generator
GENERIC MAP (
CLOCK_PERIOD => 10000,
HAS_CLK_INPUT => true,
HAS_RESET_INPUT => true,
HAS_STOP_INPUT => true
)
PORT MAP (
clk_in => clk_in,
rst_in => rst_in,
clk => clk,
rst_n => rst_n,
stop_simulation => stop_simulation
);
END design_1_clk_rst_generator_0_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml
+5 -38
View File
@@ -2,43 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732628584"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732628584"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732628584"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732628584"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\bd_f60c.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\bd_f60c.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="bd_f60c_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\design_1_system_ila_0_0.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\design_1_system_ila_0_0.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1732629726"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1732629726"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732629724"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1732629724"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c_ooc.xdc
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################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name clk -period 10 [get_ports clk]
################################################################################
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hdl/bd_f60c_wrapper.vhd
-113
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--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Command: generate_target bd_f60c_wrapper.bd
--Design : bd_f60c_wrapper
--Purpose: IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_f60c_wrapper is
port (
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
SLOT_0_AXI_arready : in STD_LOGIC;
SLOT_0_AXI_arvalid : in STD_LOGIC;
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
SLOT_0_AXI_awready : in STD_LOGIC;
SLOT_0_AXI_awvalid : in STD_LOGIC;
SLOT_0_AXI_bready : in STD_LOGIC;
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
SLOT_0_AXI_bvalid : in STD_LOGIC;
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_rready : in STD_LOGIC;
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
SLOT_0_AXI_rvalid : in STD_LOGIC;
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_wready : in STD_LOGIC;
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
SLOT_0_AXI_wvalid : in STD_LOGIC;
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
SLOT_1_AXIS_tlast : in STD_LOGIC;
SLOT_1_AXIS_tready : in STD_LOGIC;
SLOT_1_AXIS_tvalid : in STD_LOGIC;
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
SLOT_2_AXIS_tlast : in STD_LOGIC;
SLOT_2_AXIS_tready : in STD_LOGIC;
SLOT_2_AXIS_tvalid : in STD_LOGIC;
clk : in STD_LOGIC;
resetn : in STD_LOGIC
);
end bd_f60c_wrapper;
architecture STRUCTURE of bd_f60c_wrapper is
component bd_f60c is
port (
clk : in STD_LOGIC;
resetn : in STD_LOGIC;
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
SLOT_0_AXI_arready : in STD_LOGIC;
SLOT_0_AXI_arvalid : in STD_LOGIC;
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
SLOT_0_AXI_awready : in STD_LOGIC;
SLOT_0_AXI_awvalid : in STD_LOGIC;
SLOT_0_AXI_bready : in STD_LOGIC;
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
SLOT_0_AXI_bvalid : in STD_LOGIC;
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_rready : in STD_LOGIC;
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
SLOT_0_AXI_rvalid : in STD_LOGIC;
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
SLOT_0_AXI_wready : in STD_LOGIC;
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
SLOT_0_AXI_wvalid : in STD_LOGIC;
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
SLOT_1_AXIS_tlast : in STD_LOGIC;
SLOT_1_AXIS_tready : in STD_LOGIC;
SLOT_1_AXIS_tvalid : in STD_LOGIC;
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
SLOT_2_AXIS_tlast : in STD_LOGIC;
SLOT_2_AXIS_tready : in STD_LOGIC;
SLOT_2_AXIS_tvalid : in STD_LOGIC
);
end component bd_f60c;
begin
bd_f60c_i: component bd_f60c
port map (
SLOT_0_AXI_araddr(31 downto 0) => SLOT_0_AXI_araddr(31 downto 0),
SLOT_0_AXI_arprot(2 downto 0) => SLOT_0_AXI_arprot(2 downto 0),
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
SLOT_0_AXI_awaddr(31 downto 0) => SLOT_0_AXI_awaddr(31 downto 0),
SLOT_0_AXI_awprot(2 downto 0) => SLOT_0_AXI_awprot(2 downto 0),
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
SLOT_0_AXI_bready => SLOT_0_AXI_bready,
SLOT_0_AXI_bresp(1 downto 0) => SLOT_0_AXI_bresp(1 downto 0),
SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
SLOT_0_AXI_rdata(31 downto 0) => SLOT_0_AXI_rdata(31 downto 0),
SLOT_0_AXI_rready => SLOT_0_AXI_rready,
SLOT_0_AXI_rresp(1 downto 0) => SLOT_0_AXI_rresp(1 downto 0),
SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
SLOT_0_AXI_wdata(31 downto 0) => SLOT_0_AXI_wdata(31 downto 0),
SLOT_0_AXI_wready => SLOT_0_AXI_wready,
SLOT_0_AXI_wstrb(3 downto 0) => SLOT_0_AXI_wstrb(3 downto 0),
SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
SLOT_1_AXIS_tdata(15 downto 0) => SLOT_1_AXIS_tdata(15 downto 0),
SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
SLOT_2_AXIS_tdata(15 downto 0) => SLOT_2_AXIS_tdata(15 downto 0),
SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
clk => clk,
resetn => resetn
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0_ooc.xdc
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################################################################################
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# User should update the correct clock period before proceeding further
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# For best results the frequencies should be modified# to match the target
# frequencies.
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
################################################################################
#create_clock -name clock_name -period 10 [get_ports clock_name]
################################################################################
#list of all the clock needed for ILA core
create_clock -name ILA_CLK -period 10 [get_ports clk]
################################################################################
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc
-103
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##
## ARM and HALT transfer false paths
##
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
##
## ILA Register False Paths
##
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
##
## Match Unit Configuration to Match Output false path
##
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
##
## ILA Capture Block False Paths
##
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
##
## ILA Capture State to XSDB register False Paths
##
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
##
## ILA Sample Counter Match Condition out False Paths
##
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
##
## ILA Window Counter Match Condition out False Paths
##
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
##
## Waivers
##
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc
-30
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@@ -1,30 +0,0 @@
##
## Match Unit Configuration to Match Output false path
##
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
##
## ILA Sample Counter Match Condition out False Paths
##
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
##
## ILA Window Counter Match Condition out False Paths
##
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/sim/bd_f60c_ila_lib_0.vhd
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-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY bd_f60c_ila_lib_0 IS
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
probe18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END bd_f60c_ila_lib_0;
ARCHITECTURE bd_f60c_ila_lib_0_arch OF bd_f60c_ila_lib_0 IS
BEGIN
END bd_f60c_ila_lib_0_arch;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/synth/bd_f60c_ila_lib_0.vhd
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_f60c_slot_0_aw_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_4_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.IN32_WIDTH(1),
.IN33_WIDTH(1),
.IN34_WIDTH(1),
.IN35_WIDTH(1),
.IN36_WIDTH(1),
.IN37_WIDTH(1),
.IN38_WIDTH(1),
.IN39_WIDTH(1),
.IN40_WIDTH(1),
.IN41_WIDTH(1),
.IN42_WIDTH(1),
.IN43_WIDTH(1),
.IN44_WIDTH(1),
.IN45_WIDTH(1),
.IN46_WIDTH(1),
.IN47_WIDTH(1),
.IN48_WIDTH(1),
.IN49_WIDTH(1),
.IN50_WIDTH(1),
.IN51_WIDTH(1),
.IN52_WIDTH(1),
.IN53_WIDTH(1),
.IN54_WIDTH(1),
.IN55_WIDTH(1),
.IN56_WIDTH(1),
.IN57_WIDTH(1),
.IN58_WIDTH(1),
.IN59_WIDTH(1),
.IN60_WIDTH(1),
.IN61_WIDTH(1),
.IN62_WIDTH(1),
.IN63_WIDTH(1),
.IN64_WIDTH(1),
.IN65_WIDTH(1),
.IN66_WIDTH(1),
.IN67_WIDTH(1),
.IN68_WIDTH(1),
.IN69_WIDTH(1),
.IN70_WIDTH(1),
.IN71_WIDTH(1),
.IN72_WIDTH(1),
.IN73_WIDTH(1),
.IN74_WIDTH(1),
.IN75_WIDTH(1),
.IN76_WIDTH(1),
.IN77_WIDTH(1),
.IN78_WIDTH(1),
.IN79_WIDTH(1),
.IN80_WIDTH(1),
.IN81_WIDTH(1),
.IN82_WIDTH(1),
.IN83_WIDTH(1),
.IN84_WIDTH(1),
.IN85_WIDTH(1),
.IN86_WIDTH(1),
.IN87_WIDTH(1),
.IN88_WIDTH(1),
.IN89_WIDTH(1),
.IN90_WIDTH(1),
.IN91_WIDTH(1),
.IN92_WIDTH(1),
.IN93_WIDTH(1),
.IN94_WIDTH(1),
.IN95_WIDTH(1),
.IN96_WIDTH(1),
.IN97_WIDTH(1),
.IN98_WIDTH(1),
.IN99_WIDTH(1),
.IN100_WIDTH(1),
.IN101_WIDTH(1),
.IN102_WIDTH(1),
.IN103_WIDTH(1),
.IN104_WIDTH(1),
.IN105_WIDTH(1),
.IN106_WIDTH(1),
.IN107_WIDTH(1),
.IN108_WIDTH(1),
.IN109_WIDTH(1),
.IN110_WIDTH(1),
.IN111_WIDTH(1),
.IN112_WIDTH(1),
.IN113_WIDTH(1),
.IN114_WIDTH(1),
.IN115_WIDTH(1),
.IN116_WIDTH(1),
.IN117_WIDTH(1),
.IN118_WIDTH(1),
.IN119_WIDTH(1),
.IN120_WIDTH(1),
.IN121_WIDTH(1),
.IN122_WIDTH(1),
.IN123_WIDTH(1),
.IN124_WIDTH(1),
.IN125_WIDTH(1),
.IN126_WIDTH(1),
.IN127_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.In32(1'B0),
.In33(1'B0),
.In34(1'B0),
.In35(1'B0),
.In36(1'B0),
.In37(1'B0),
.In38(1'B0),
.In39(1'B0),
.In40(1'B0),
.In41(1'B0),
.In42(1'B0),
.In43(1'B0),
.In44(1'B0),
.In45(1'B0),
.In46(1'B0),
.In47(1'B0),
.In48(1'B0),
.In49(1'B0),
.In50(1'B0),
.In51(1'B0),
.In52(1'B0),
.In53(1'B0),
.In54(1'B0),
.In55(1'B0),
.In56(1'B0),
.In57(1'B0),
.In58(1'B0),
.In59(1'B0),
.In60(1'B0),
.In61(1'B0),
.In62(1'B0),
.In63(1'B0),
.In64(1'B0),
.In65(1'B0),
.In66(1'B0),
.In67(1'B0),
.In68(1'B0),
.In69(1'B0),
.In70(1'B0),
.In71(1'B0),
.In72(1'B0),
.In73(1'B0),
.In74(1'B0),
.In75(1'B0),
.In76(1'B0),
.In77(1'B0),
.In78(1'B0),
.In79(1'B0),
.In80(1'B0),
.In81(1'B0),
.In82(1'B0),
.In83(1'B0),
.In84(1'B0),
.In85(1'B0),
.In86(1'B0),
.In87(1'B0),
.In88(1'B0),
.In89(1'B0),
.In90(1'B0),
.In91(1'B0),
.In92(1'B0),
.In93(1'B0),
.In94(1'B0),
.In95(1'B0),
.In96(1'B0),
.In97(1'B0),
.In98(1'B0),
.In99(1'B0),
.In100(1'B0),
.In101(1'B0),
.In102(1'B0),
.In103(1'B0),
.In104(1'B0),
.In105(1'B0),
.In106(1'B0),
.In107(1'B0),
.In108(1'B0),
.In109(1'B0),
.In110(1'B0),
.In111(1'B0),
.In112(1'B0),
.In113(1'B0),
.In114(1'B0),
.In115(1'B0),
.In116(1'B0),
.In117(1'B0),
.In118(1'B0),
.In119(1'B0),
.In120(1'B0),
.In121(1'B0),
.In122(1'B0),
.In123(1'B0),
.In124(1'B0),
.In125(1'B0),
.In126(1'B0),
.In127(1'B0),
.dout(dout)
);
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/synth/bd_f60c_slot_0_aw_0.v
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@@ -1,332 +0,0 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 4
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_aw_0,xlconcat_v2_1_4_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_f60c_slot_0_aw_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDT\
H=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN\
62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WI\
DTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_f60c_slot_0_aw_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_4_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.IN32_WIDTH(1),
.IN33_WIDTH(1),
.IN34_WIDTH(1),
.IN35_WIDTH(1),
.IN36_WIDTH(1),
.IN37_WIDTH(1),
.IN38_WIDTH(1),
.IN39_WIDTH(1),
.IN40_WIDTH(1),
.IN41_WIDTH(1),
.IN42_WIDTH(1),
.IN43_WIDTH(1),
.IN44_WIDTH(1),
.IN45_WIDTH(1),
.IN46_WIDTH(1),
.IN47_WIDTH(1),
.IN48_WIDTH(1),
.IN49_WIDTH(1),
.IN50_WIDTH(1),
.IN51_WIDTH(1),
.IN52_WIDTH(1),
.IN53_WIDTH(1),
.IN54_WIDTH(1),
.IN55_WIDTH(1),
.IN56_WIDTH(1),
.IN57_WIDTH(1),
.IN58_WIDTH(1),
.IN59_WIDTH(1),
.IN60_WIDTH(1),
.IN61_WIDTH(1),
.IN62_WIDTH(1),
.IN63_WIDTH(1),
.IN64_WIDTH(1),
.IN65_WIDTH(1),
.IN66_WIDTH(1),
.IN67_WIDTH(1),
.IN68_WIDTH(1),
.IN69_WIDTH(1),
.IN70_WIDTH(1),
.IN71_WIDTH(1),
.IN72_WIDTH(1),
.IN73_WIDTH(1),
.IN74_WIDTH(1),
.IN75_WIDTH(1),
.IN76_WIDTH(1),
.IN77_WIDTH(1),
.IN78_WIDTH(1),
.IN79_WIDTH(1),
.IN80_WIDTH(1),
.IN81_WIDTH(1),
.IN82_WIDTH(1),
.IN83_WIDTH(1),
.IN84_WIDTH(1),
.IN85_WIDTH(1),
.IN86_WIDTH(1),
.IN87_WIDTH(1),
.IN88_WIDTH(1),
.IN89_WIDTH(1),
.IN90_WIDTH(1),
.IN91_WIDTH(1),
.IN92_WIDTH(1),
.IN93_WIDTH(1),
.IN94_WIDTH(1),
.IN95_WIDTH(1),
.IN96_WIDTH(1),
.IN97_WIDTH(1),
.IN98_WIDTH(1),
.IN99_WIDTH(1),
.IN100_WIDTH(1),
.IN101_WIDTH(1),
.IN102_WIDTH(1),
.IN103_WIDTH(1),
.IN104_WIDTH(1),
.IN105_WIDTH(1),
.IN106_WIDTH(1),
.IN107_WIDTH(1),
.IN108_WIDTH(1),
.IN109_WIDTH(1),
.IN110_WIDTH(1),
.IN111_WIDTH(1),
.IN112_WIDTH(1),
.IN113_WIDTH(1),
.IN114_WIDTH(1),
.IN115_WIDTH(1),
.IN116_WIDTH(1),
.IN117_WIDTH(1),
.IN118_WIDTH(1),
.IN119_WIDTH(1),
.IN120_WIDTH(1),
.IN121_WIDTH(1),
.IN122_WIDTH(1),
.IN123_WIDTH(1),
.IN124_WIDTH(1),
.IN125_WIDTH(1),
.IN126_WIDTH(1),
.IN127_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.In32(1'B0),
.In33(1'B0),
.In34(1'B0),
.In35(1'B0),
.In36(1'B0),
.In37(1'B0),
.In38(1'B0),
.In39(1'B0),
.In40(1'B0),
.In41(1'B0),
.In42(1'B0),
.In43(1'B0),
.In44(1'B0),
.In45(1'B0),
.In46(1'B0),
.In47(1'B0),
.In48(1'B0),
.In49(1'B0),
.In50(1'B0),
.In51(1'B0),
.In52(1'B0),
.In53(1'B0),
.In54(1'B0),
.In55(1'B0),
.In56(1'B0),
.In57(1'B0),
.In58(1'B0),
.In59(1'B0),
.In60(1'B0),
.In61(1'B0),
.In62(1'B0),
.In63(1'B0),
.In64(1'B0),
.In65(1'B0),
.In66(1'B0),
.In67(1'B0),
.In68(1'B0),
.In69(1'B0),
.In70(1'B0),
.In71(1'B0),
.In72(1'B0),
.In73(1'B0),
.In74(1'B0),
.In75(1'B0),
.In76(1'B0),
.In77(1'B0),
.In78(1'B0),
.In79(1'B0),
.In80(1'B0),
.In81(1'B0),
.In82(1'B0),
.In83(1'B0),
.In84(1'B0),
.In85(1'B0),
.In86(1'B0),
.In87(1'B0),
.In88(1'B0),
.In89(1'B0),
.In90(1'B0),
.In91(1'B0),
.In92(1'B0),
.In93(1'B0),
.In94(1'B0),
.In95(1'B0),
.In96(1'B0),
.In97(1'B0),
.In98(1'B0),
.In99(1'B0),
.In100(1'B0),
.In101(1'B0),
.In102(1'B0),
.In103(1'B0),
.In104(1'B0),
.In105(1'B0),
.In106(1'B0),
.In107(1'B0),
.In108(1'B0),
.In109(1'B0),
.In110(1'B0),
.In111(1'B0),
.In112(1'B0),
.In113(1'B0),
.In114(1'B0),
.In115(1'B0),
.In116(1'B0),
.In117(1'B0),
.In118(1'B0),
.In119(1'B0),
.In120(1'B0),
.In121(1'B0),
.In122(1'B0),
.In123(1'B0),
.In124(1'B0),
.In125(1'B0),
.In126(1'B0),
.In127(1'B0),
.dout(dout)
);
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml
+129 -386
View File
File diff suppressed because it is too large Load Diff
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/sim/bd_f60c_slot_0_w_0.v
-328
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@@ -1,328 +0,0 @@
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_f60c_slot_0_w_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_4_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.IN32_WIDTH(1),
.IN33_WIDTH(1),
.IN34_WIDTH(1),
.IN35_WIDTH(1),
.IN36_WIDTH(1),
.IN37_WIDTH(1),
.IN38_WIDTH(1),
.IN39_WIDTH(1),
.IN40_WIDTH(1),
.IN41_WIDTH(1),
.IN42_WIDTH(1),
.IN43_WIDTH(1),
.IN44_WIDTH(1),
.IN45_WIDTH(1),
.IN46_WIDTH(1),
.IN47_WIDTH(1),
.IN48_WIDTH(1),
.IN49_WIDTH(1),
.IN50_WIDTH(1),
.IN51_WIDTH(1),
.IN52_WIDTH(1),
.IN53_WIDTH(1),
.IN54_WIDTH(1),
.IN55_WIDTH(1),
.IN56_WIDTH(1),
.IN57_WIDTH(1),
.IN58_WIDTH(1),
.IN59_WIDTH(1),
.IN60_WIDTH(1),
.IN61_WIDTH(1),
.IN62_WIDTH(1),
.IN63_WIDTH(1),
.IN64_WIDTH(1),
.IN65_WIDTH(1),
.IN66_WIDTH(1),
.IN67_WIDTH(1),
.IN68_WIDTH(1),
.IN69_WIDTH(1),
.IN70_WIDTH(1),
.IN71_WIDTH(1),
.IN72_WIDTH(1),
.IN73_WIDTH(1),
.IN74_WIDTH(1),
.IN75_WIDTH(1),
.IN76_WIDTH(1),
.IN77_WIDTH(1),
.IN78_WIDTH(1),
.IN79_WIDTH(1),
.IN80_WIDTH(1),
.IN81_WIDTH(1),
.IN82_WIDTH(1),
.IN83_WIDTH(1),
.IN84_WIDTH(1),
.IN85_WIDTH(1),
.IN86_WIDTH(1),
.IN87_WIDTH(1),
.IN88_WIDTH(1),
.IN89_WIDTH(1),
.IN90_WIDTH(1),
.IN91_WIDTH(1),
.IN92_WIDTH(1),
.IN93_WIDTH(1),
.IN94_WIDTH(1),
.IN95_WIDTH(1),
.IN96_WIDTH(1),
.IN97_WIDTH(1),
.IN98_WIDTH(1),
.IN99_WIDTH(1),
.IN100_WIDTH(1),
.IN101_WIDTH(1),
.IN102_WIDTH(1),
.IN103_WIDTH(1),
.IN104_WIDTH(1),
.IN105_WIDTH(1),
.IN106_WIDTH(1),
.IN107_WIDTH(1),
.IN108_WIDTH(1),
.IN109_WIDTH(1),
.IN110_WIDTH(1),
.IN111_WIDTH(1),
.IN112_WIDTH(1),
.IN113_WIDTH(1),
.IN114_WIDTH(1),
.IN115_WIDTH(1),
.IN116_WIDTH(1),
.IN117_WIDTH(1),
.IN118_WIDTH(1),
.IN119_WIDTH(1),
.IN120_WIDTH(1),
.IN121_WIDTH(1),
.IN122_WIDTH(1),
.IN123_WIDTH(1),
.IN124_WIDTH(1),
.IN125_WIDTH(1),
.IN126_WIDTH(1),
.IN127_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.In32(1'B0),
.In33(1'B0),
.In34(1'B0),
.In35(1'B0),
.In36(1'B0),
.In37(1'B0),
.In38(1'B0),
.In39(1'B0),
.In40(1'B0),
.In41(1'B0),
.In42(1'B0),
.In43(1'B0),
.In44(1'B0),
.In45(1'B0),
.In46(1'B0),
.In47(1'B0),
.In48(1'B0),
.In49(1'B0),
.In50(1'B0),
.In51(1'B0),
.In52(1'B0),
.In53(1'B0),
.In54(1'B0),
.In55(1'B0),
.In56(1'B0),
.In57(1'B0),
.In58(1'B0),
.In59(1'B0),
.In60(1'B0),
.In61(1'B0),
.In62(1'B0),
.In63(1'B0),
.In64(1'B0),
.In65(1'B0),
.In66(1'B0),
.In67(1'B0),
.In68(1'B0),
.In69(1'B0),
.In70(1'B0),
.In71(1'B0),
.In72(1'B0),
.In73(1'B0),
.In74(1'B0),
.In75(1'B0),
.In76(1'B0),
.In77(1'B0),
.In78(1'B0),
.In79(1'B0),
.In80(1'B0),
.In81(1'B0),
.In82(1'B0),
.In83(1'B0),
.In84(1'B0),
.In85(1'B0),
.In86(1'B0),
.In87(1'B0),
.In88(1'B0),
.In89(1'B0),
.In90(1'B0),
.In91(1'B0),
.In92(1'B0),
.In93(1'B0),
.In94(1'B0),
.In95(1'B0),
.In96(1'B0),
.In97(1'B0),
.In98(1'B0),
.In99(1'B0),
.In100(1'B0),
.In101(1'B0),
.In102(1'B0),
.In103(1'B0),
.In104(1'B0),
.In105(1'B0),
.In106(1'B0),
.In107(1'B0),
.In108(1'B0),
.In109(1'B0),
.In110(1'B0),
.In111(1'B0),
.In112(1'B0),
.In113(1'B0),
.In114(1'B0),
.In115(1'B0),
.In116(1'B0),
.In117(1'B0),
.In118(1'B0),
.In119(1'B0),
.In120(1'B0),
.In121(1'B0),
.In122(1'B0),
.In123(1'B0),
.In124(1'B0),
.In125(1'B0),
.In126(1'B0),
.In127(1'B0),
.dout(dout)
);
endmodule

Some files were not shown because too many files have changed in this diff Show More