M1: Automat gefixt
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@@ -32,8 +32,8 @@ architecture rtl of spi_rom_control is
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signal RegDataEn : std_logic;
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-- Finite State Machine
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type state_t is (S_ReadRom, S_ProvideData, S_DeadEnd, S_ERROR);
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signal state : state_t := S_ReadRom;
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type state_t is (S_CountAddress, S_ReadRom, S_ProvideData, S_DeadEnd, S_ERROR);
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signal state : state_t := S_CountAddress;
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signal state_next : state_t;
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begin
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@@ -71,16 +71,23 @@ begin
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-- Berechnung des Folgezustands und der Mealy-Ausgaenge
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case state is
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when S_CountAddress =>
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if reset = '1' then
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state_next <= S_CountAddress;
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CntAddrRst <= '1';
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else
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state_next <= S_ReadRom;
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end if;
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when S_ReadRom =>
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if reset = '1' then
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state_next <= S_ReadRom;
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state_next <= S_CountAddress;
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CntAddrRst <= '1';
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else
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state_next <= S_ProvideData;
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end if;
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when S_ProvideData =>
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if reset = '1' then
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state_next <= S_ReadRom;
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state_next <= S_CountAddress;
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CntAddrRst <= '1';
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elsif m_ready = '0' then
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state_next <= S_ProvideData;
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@@ -88,23 +95,23 @@ begin
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if CtrlBits = "10" then
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state_next <= S_DeadEnd;
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elsif CtrlBits = "00" then
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state_next <= S_ReadRom;
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state_next <= S_CountAddress;
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CntAddrEn <= '1';
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elsif CtrlBits = "01" or CtrlBits = "11" then
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state_next <= S_ReadRom;
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state_next <= S_CountAddress;
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CntAddrRst <= '1';
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end if;
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end if;
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when S_DeadEnd =>
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if reset = '1' then
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state_next <= S_ReadRom;
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state_next <= S_CountAddress;
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CntAddrRst <= '1';
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else
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state_next <= S_DeadEnd;
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end if;
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when S_ERROR =>
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if reset = '1' then
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state_next <= S_ReadRom;
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state_next <= S_CountAddress;
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CntAddrRst <= '1';
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else
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state_next <= S_ERROR;
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@@ -128,6 +135,8 @@ begin
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RegDataEn <= '0';
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case state_next is
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when S_CountAddress =>
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null;
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when S_ReadRom =>
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RegDataEn <= '1';
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when S_ProvideData =>
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@@ -51,6 +51,7 @@ if {1} {
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}
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if {1} {
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add wave -noupdate -divider "spi_transmitter"
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add wave -noupdate -divider Steuerwerk
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add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/state
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add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/state_next
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