M1: Rechenwerk für spi_rom_control

Milestone1/sources/spi2display.vhd

@@ -60,6 +60,9 @@ begin
     );
 
     Control_Inst: entity work.spi_rom_control
+    generic map (
+        AW      => AW
+    )
     port map (
         clk     => clk,
         reset   => reset,

Milestone1/sources/spi_rom_control.vhd

@@ -3,13 +3,16 @@ use IEEE.STD_LOGIC_1164.ALL;
 use ieee.numeric_std.all;
 
 entity spi_rom_control is
+    generic(
+        AW           : positive := 8
+    );
     port (
         -- control io
         clk     : in std_logic;
         reset   : in std_logic;
 
         -- Interface rom
-        addr    : out std_logic_vector(7 downto 0);
+        addr    : out std_logic_vector(AW-1 downto 0);
         din     : in  std_logic_vector(9 downto 0);
 
         -- Streaming Interface spi_transmitter
@@ -22,8 +25,34 @@ end entity;
 
 architecture rtl of spi_rom_control is
 
+    signal CtrlBits   : std_logic_vector(1 downto 0);
+    signal CntAddrEn  : std_logic;
+    signal CntAddrRst : std_logic;
+    signal RegDataEn  : std_logic;
+
 begin
 
+    RegData: process
+        variable Q : std_logic_vector(9 downto 0) := (others =>'0');
+    begin
+        wait until rising_edge(clk);
+        if RegDataEn = '1' then
+            m_data <= din(7 downto 0);
+            CtrlBits <= din(9 downto 8);
+        end if;
+    end process;
+
+    CntAddr: process
+        variable cntVal : unsigned(AW-1 downto 0) := (others=>'0');
+    begin
+        wait until rising_edge(clk);
+        if CntAddrRst = '1' then
+            cntVal := 0;
+        elsif CntAddrEn = '1' then
+            cntVal := cntVal + 1;
+        end if;
+        addr <= std_logic_vector(cntVal);
+    end process;
 
 
 end architecture;

Milestone1/sources/test_spi2display.do

@@ -5,6 +5,7 @@ if { [file exists work] == 0} {
 
 # Benoetigte Dateien uebersetzen
 vcom -work work spi_transmitter.vhd
+vcom -work work spi_rom_control.vhd
 vcom -work work spi2display_rom.vhd
 vcom -work work spi2display.vhd
 vcom -work work spi2display_tb.vhd