Merge branch 'M1_refinement' into 'main'

M1 refinement See merge request NdotPaul/es-praktikum!1
2024-10-21 21:39:07 +00:00
parent e43074233f 468880b845
commit 32eb1fec5a
15 changed files with 796 additions and 236 deletions
@@ -103,6 +103,12 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
+      <File Path="$PPRDIR/../sources/spi_rom_control.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
      <File Path="$PPRDIR/../sources/spi2display.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -20,10 +20,14 @@ end;

 architecture rtl of spi2display is

-    constant AW : POSITIVE := 8;
+    constant AW     : POSITIVE := 8;

-    signal addr : std_logic_vector(AW-1 downto 0);
-    signal data : std_logic_vector(9 downto 0);
+    signal addr     : std_logic_vector(AW-1 downto 0);
+    signal data_rom : std_logic_vector(9 downto 0);
+
+    signal data     : std_logic_vector(7 downto 0);
+    signal valid    : std_logic;
+    signal ready    : std_logic;

 begin

@@ -33,13 +37,16 @@ begin
        CLKDIV => CLOCK_FREQ / (SCK_FREQ * 4)
    )
    port map (
-        clk    => clk,
-        reset  => reset,
-        data   => data,
-        addr   => addr,
-        mosi   => mosi,
-        sck    => sck,
-        ssel   => ssel
+        clk     => clk,
+        reset   => reset,
+
+        s_data  => data,
+        s_valid => valid,
+        s_ready => ready,
+
+        mosi    => mosi,
+        sck     => sck,
+        ssel    => ssel
    );

    Rom_Inst: entity work.spi2display_rom
@@ -49,7 +56,23 @@ begin
    port map (
        clk  => clk,
        addr => addr,
-        dout => data
+        dout => data_rom
+    );
+
+    Control_Inst: entity work.spi_rom_control
+    generic map (
+        AW      => AW
+    )
+    port map (
+        clk     => clk,
+        reset   => reset,
+
+        addr    => addr,
+        din     => data_rom,
+
+        m_data  => data,
+        m_valid => valid,
+        m_ready => ready
    );

 end rtl;
@@ -33,12 +33,13 @@ begin
    begin
        reset <= '0' after 100 * clk_half_period;

-        wait for 45 us;
-        wait until rising_edge(clk);
-        reset <= '1';
-        wait for 1 us;
-        wait until rising_edge(clk);
-        reset <= '0';
+        -- wait for 45 us;
+        -- wait until rising_edge(clk);
+        -- reset <= '1';
+        -- wait for 1 us;
+        -- wait until rising_edge(clk);
+        -- reset <= '0';
+        wait;
    end process;

    dut: entity work.spi2display
@@ -0,0 +1,151 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity spi_rom_control is
+    generic(
+        AW           : positive := 8
+    );
+    port (
+        -- control io
+        clk     : in std_logic;
+        reset   : in std_logic;
+
+        -- Interface rom
+        addr    : out std_logic_vector(AW-1 downto 0);
+        din     : in  std_logic_vector(9 downto 0);
+
+        -- Streaming Interface spi_transmitter
+        m_data  : out std_logic_vector(7 downto 0);
+        m_valid : out std_logic;
+        m_ready : in  std_logic
+    );
+end entity;
+
+
+architecture rtl of spi_rom_control is
+
+    -- Steuersignale fuer Zustandsmaschine
+    signal CtrlBits   : std_logic_vector(1 downto 0);
+    signal CntAddrEn  : std_logic;
+    signal CntAddrRst : std_logic;
+    signal RegDataEn  : std_logic;
+
+    -- Finite State Machine
+    type state_t is (S_CountAddress, S_ReadRom, S_ProvideData, S_DeadEnd, S_ERROR);
+    signal state      : state_t := S_CountAddress;
+    signal state_next : state_t;
+
+begin
+
+    RegData: process
+        variable Q : std_logic_vector(9 downto 0) := (others =>'0');
+    begin
+        wait until rising_edge(clk);
+        if RegDataEn = '1' then
+            Q := din;
+        end if;
+        m_data <= Q(7 downto 0);
+        CtrlBits <= Q(9 downto 8);
+    end process;
+
+    CntAddr: process
+        variable cntVal : unsigned(AW-1 downto 0) := (others=>'0');
+    begin
+        wait until rising_edge(clk);
+        if CntAddrRst = '1' then
+            cntVal := (others=>'0');
+        elsif CntAddrEn = '1' then
+            cntVal := cntVal + 1;
+        end if;
+        addr <= std_logic_vector(cntVal);
+    end process;
+
+    -- Prozesse fuer endlichen Automaten
+    Transition: process(state, reset, m_ready, CtrlBits)
+    begin
+        -- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
+        state_next <= S_ERROR;
+        CntAddrEn  <= '0';
+        CntAddrRst <= '0';
+
+        -- Berechnung des Folgezustands und der Mealy-Ausgaenge
+        case state is
+            when S_CountAddress =>
+                if reset = '1' then
+                    state_next <= S_CountAddress;
+                    CntAddrRst <= '1';
+                else
+                    state_next <= S_ReadRom;
+                end if;
+            when S_ReadRom =>
+                if reset = '1' then
+                    state_next <= S_CountAddress;
+                    CntAddrRst <= '1';
+                else
+                    state_next <= S_ProvideData;
+                end if;
+            when S_ProvideData =>
+                if reset = '1' then
+                    state_next <= S_CountAddress;
+                    CntAddrRst <= '1';
+                elsif m_ready = '0' then
+                    state_next <= S_ProvideData;
+                elsif m_ready = '1' then
+                    if CtrlBits = "10" then
+                        state_next <= S_DeadEnd;
+                    elsif CtrlBits = "00" then
+                        state_next <= S_CountAddress;
+                        CntAddrEn <= '1';
+                    elsif CtrlBits = "01" or CtrlBits = "11" then
+                        state_next <= S_CountAddress;
+                        CntAddrRst <= '1';
+                    end if;
+                end if;
+            when S_DeadEnd =>
+                if reset = '1' then
+                    state_next <= S_CountAddress;
+                    CntAddrRst <= '1';
+                else
+                    state_next <= S_DeadEnd;
+                end if;
+            when S_ERROR =>
+                if reset = '1' then
+                    state_next <= S_CountAddress;
+                    CntAddrRst <= '1';
+                else
+                    state_next <= S_ERROR;
+                    CntAddrEn  <= 'X';
+                    CntAddrRst <= 'X';
+                end if;
+        end case;
+    end process;
+
+    -- Register fuer Zustand und Ausgaenge
+    Reg: process
+    begin
+        wait until rising_edge(clk);
+
+        -- Zustandswechsel
+        state <= state_next;
+
+        -- Berechnung der Moore-Ausgaenge
+        -- Default-Werte
+        m_valid   <= '0';
+        RegDataEn <= '0';
+
+        case state_next is
+            when S_CountAddress =>
+                null;
+            when S_ReadRom =>
+                RegDataEn <= '1';
+            when S_ProvideData =>
+                m_valid   <= '1';
+            when S_DeadEnd =>
+                null;
+            when S_ERROR =>
+                m_valid   <= 'X';
+                RegDataEn <= 'X';
+        end case;
+    end process;
+end architecture;
@@ -9,230 +9,200 @@ entity spi_transmitter is
        AW      : positive  := 8;
        CLKDIV  : positive  := 100000/4
    );
-
    port (
        clk          : in  std_logic;
        reset        : in  std_logic := '1';
-        data         : in  std_logic_vector (   9 downto 0);
-        addr         : out std_logic_vector (AW-1 downto 0);
+
+        s_data       : in  std_logic_vector (7 downto 0);
+        s_valid      : in  std_logic;
+        s_ready      : out std_logic;
+
        mosi         : out std_logic:='1';
        sck          : out std_logic:='1';
        ssel         : out std_logic:='1'
-       );
-end;
+        );
+    end;

-architecture rtl of spi_transmitter is
+    architecture rtl of spi_transmitter is

    -- Steuersignale zwischen Steuerwerk und Rechenwerk
-    signal cntAddrRst   : std_logic := '0';
-    signal cntAddrEn    : std_logic := '0';
    signal CntSckTc     : std_logic := '0';
+    signal CntSckRst    : std_logic := '0';
    signal RegDataLd    : std_logic := '0';
-    signal RegDataShift : std_logic := '0';
+    signal RegDataEn    : std_logic := '0';
    signal CntBitsEn    : std_logic := '0';
    signal CntBitsTC    : std_logic := '0';
-    signal CtrlBits     : std_logic_vector(1 downto 0) := "00";
+    signal CntBitsRst   : std_logic := '0';
+
+    -- Finite state machine
+    type state_t is (S_IDLE, S_STEP_1, S_STEP_2, S_STEP_3, S_STEP_4, S_ERROR);
+    signal state      : state_t := S_IDLE;
+    signal state_next : state_t;

 begin

-        Rechenwerk : block
-        begin
-            -- Zaehler fuer Adresse
-            CntAddr: process
-                variable cntVal : unsigned(AW-1 downto 0) := (others=>'0');
-            begin
-                wait until rising_edge(clk);
-                if reset = '1' or CntAddrRst = '1' then
-                    cntVal := (others=>'0');
-                elsif cntAddrEn = '1' then
-                    cntVal := cntVal + 1;
-                end if;
-
-                addr <= std_logic_vector(cntVal);
-            end process;
-
-            -- Zaehler fuer SPI-Takt SCK
-            CntSck: process
-                variable cntVal : unsigned(31 downto 0) := (others=>'0');
-            begin
-                wait until rising_edge(clk);
-                if reset = '1' or cntVal = 0 then
-                    cntVal := to_unsigned(CLKDIV-1, 32);
-                else
-                    cntVal := cntVal - 1;
-                end if;
-
-                if cntVal = 0 then
-                    CntSckTc <= '1';
-                else
-                    CntSckTc <= '0';
-                end if;
-            end process;
-
-            -- Zaheler fuer zu sendende Bits
-            CntBits: process
-                variable cntVal : unsigned(2 downto 0) := (others=>'0');
-            begin
-                wait until rising_edge(clk);
-                if reset = '1' then
-                    cntVal := to_unsigned(0, 3);
-                elsif CntBitsEn = '1' then
-                    if cntVal = 0 then
-                        cntVal := to_unsigned(7, 3);
-                    else
-                        cntVal := cntVal - 1;
-                    end if;
-                end if;
-
-                if cntVal = 0 then
-                    CntBitsTC <= '1';
-                else
-                    CntBitsTC <= '0';
-                end if;
-            end process;
-
-            -- Schieberegister Daten
-            RegData: process
-                variable Q : std_logic_vector(7 downto 0) := (others=>'0');
-            begin
-                wait until rising_edge(clk);
-                if RegDataLd = '1' then
-                    Q := data(7 downto 0);
-                elsif RegDataShift = '1' then
-                    Q := Q(6 downto 0) & '0';
-                end if;
-                mosi <= Q(7);
-            end process;
-        end block;
-
-    Steuerwerk : block
-        -- Typ fuer die Zustandswerte
-        type state_t is (S_START, S_STEP_1, S_STEP_2, S_STEP_3, S_STEP_4, S_DEAD_END, S_ERROR);
-        -- Interne Signale fuer Rechenwerk
-        signal state      : state_t := S_START;
-        signal state_next : state_t;
+    -- Zaehler fuer SPI-Takt SCK
+    CntSck: process
+        variable cntVal : unsigned(31 downto 0) := (others=>'0');
    begin
-        -- Kontrollbits
-        CtrlBits <= data(9 downto 8);
+        wait until rising_edge(clk);
+        if CntSckRst = '1' or cntVal = 0 then
+            cntVal := to_unsigned(CLKDIV-1, 32);
+        else
+            cntVal := cntVal - 1;
+        end if;

-        -- Prozess zur Berechnung des Folgezustandes und der Mealy-Ausgaenge
-        Transition: process(Reset, CntSckTc, CntBitsTC, CtrlBits)
-        begin
-            -- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
-            state_next   <= S_ERROR;
-            RegDataLd    <= '0';
-            RegDataShift <= '0';
-            cntAddrEn    <= '0';
-            CntBitsEn    <= '0';
-            cntAddrRst   <= '0';
+        if cntVal = 0 then
+            CntSckTc <= '1';
+        else
+            CntSckTc <= '0';
+        end if;
+    end process;

-            -- Berechnung des Folgezustandes und der Mealy-Ausgaenge
-            case state is
-                when S_START =>
-                    If reset = '1' then
-                        state_next <= S_START;
-                    elsif CntSckTc = '1' then
-                        state_next <= S_STEP_1;
-                        RegDataLd <= '1';
-                    elsif CntSckTc = '0' then
-                        state_next <= S_START;
-                    end if;
-                when S_STEP_1 =>
-                    If reset = '1' then
-                        state_next <= S_START;
-                    elsif CntSckTc = '1' then
-                        state_next <= S_STEP_2;
-                    elsif CntSckTc = '0' then
-                        state_next <= S_STEP_1;
-                    end if;
-                when S_STEP_2 =>
-                    If reset = '1' then
-                        state_next <= S_START;
-                    elsif CntSckTc = '1' then
-                        state_next <= S_STEP_3;
-                    elsif CntSckTc = '0' then
-                        state_next <= S_STEP_2;
-                    end if;
-                when S_STEP_3 =>
-                    If reset = '1' then
-                        state_next <= S_START;
-                    elsif CntSckTc = '1' then
-                        state_next <= S_STEP_4;
-                        CntBitsEn <= '1';
-                    elsif CntSckTc = '0' then
-                        state_next <= S_STEP_3;
-                    end if;
-                when S_STEP_4 =>
-                    If reset = '1' then
-                        state_next <= S_START;
-                    elsif CntSckTc = '0' then
-                        state_next <= S_STEP_4;
-                    elsif CntSckTc = '1' and CntBitsTC = '0' then
-                        state_next <= S_STEP_1;
-                        RegDataShift <= '1';
-                    elsif CntSckTc = '1' and CntBitsTC = '1' then
-                        if CtrlBits = "10" then
-                            state_next <= S_DEAD_END;
-                        elsif CtrlBits = "00" then
-                            state_next <= S_START;
-                            cntAddrEn <= '1';
-                        elsif CtrlBits = "11" or CtrlBits = "01" then
-                            state_next <= S_START;
-                            cntAddrRst <= '1';
-                        end if;
-                    end if;
-                when S_DEAD_END =>
-                    if reset = '1' then
-                        state_next <= S_START;
-                    else
-                        state_next <= S_DEAD_END;
-                    end if;
-                when S_ERROR =>
-                    if reset = '1' then
-                        state_next <= S_START;
-                    else
-                        state_next <= S_ERROR;
-                        RegDataLd    <= 'X';
-                        RegDataShift <= 'X';
-                        cntAddrEn    <= 'X';
-                    end if;
-            end case;
-        end process;
+    -- Zaehler fuer zu sendende Bits
+    CntBits: process
+        variable cntVal : unsigned(2 downto 0) := (others=>'0');
+    begin
+        wait until rising_edge(clk);
+        if CntBitsRst = '1' then
+            cntVal := to_unsigned(0, 3);
+        elsif CntBitsEn = '1' then
+            cntVal := cntVal + 1;
+        end if;

-        -- Register fuer Zustand und Moore-Ausgaenge
-        Reg: process
-        begin
-            wait until rising_edge(clk);
+        if cntVal = 7 then
+            CntBitsTC <= '1';
+        else
+            CntBitsTC <= '0';
+        end if;
+    end process;

-            state <= state_next;
-            -- Berechnung der Moore-Ausgaenge
-            -- Default-Werte
-            ssel <= 'X';
-            sck  <= 'X';
+    -- Schieberegister Daten
+    RegData: process
+        variable Q : std_logic_vector(7 downto 0) := (others=>'0');
+    begin
+        wait until rising_edge(clk);
+        if RegDataLd = '1' then
+            Q := s_data;               -- laden
+        elsif RegDataEn = '1' then
+            Q := Q(6 downto 0) & '0'; -- linksschieben
+        end if;
+        mosi <= Q(7);
+    end process;

-            case state_next is
-                when S_START =>
-                    ssel <= '1';
-                    sck  <= '0';
-                when S_STEP_1 =>
-                    ssel <= '0';
-                    sck  <= '0';
-                when S_STEP_2 =>
-                    ssel <= '0';
-                    sck  <= '1';
-                when S_STEP_3 =>
-                    ssel <= '0';
-                    sck  <= '1';
-                when S_STEP_4 =>
-                    ssel <= '0';
-                    sck  <= '0';
-                when S_DEAD_END =>
-                    ssel <= '1';
-                    sck  <= '0';
-                when S_ERROR =>
-                    ssel <= 'X';
-                    sck  <= 'X';
-            end case;
-        end process;
-    end block;
+    -- Prozesse fuer endlichen Automaten
+    Transition: process(state, reset, CntSckTc, CntBitsTC, s_valid)
+    begin
+        -- Default-Werte fuer Folgezustand und Mealy-Ausgaenge
+        state_next <= S_ERROR;
+        CntSckRst  <= '0';
+        RegDataLd  <= '0';
+        RegDataEn  <= '0';
+        CntBitsEn  <= '0';
+        CntBitsRst <= '0';
+
+        -- Berechnung des Folgezustandes und der Mealy-Ausgaenge
+        case state is
+            when S_IDLE =>
+                If reset = '1' then
+                    state_next <= S_IDLE;
+                elsif s_valid = '1' then
+                    state_next <= S_STEP_1;
+                    RegDataLd  <= '1';
+                    CntBitsRst <= '1';
+                    CntSckRst  <= '1';
+                elsif s_valid = '0' then
+                    state_next <= S_IDLE;
+                end if;
+            when S_STEP_1 =>
+                If reset = '1' then
+                    state_next <= S_IDLE;
+                elsif CntSckTc = '1' then
+                    state_next <= S_STEP_2;
+                elsif CntSckTc = '0' then
+                    state_next <= S_STEP_1;
+                end if;
+            when S_STEP_2 =>
+                If reset = '1' then
+                    state_next <= S_IDLE;
+                elsif CntSckTc = '1' then
+                    state_next <= S_STEP_3;
+                elsif CntSckTc = '0' then
+                    state_next <= S_STEP_2;
+                end if;
+            when S_STEP_3 =>
+                If reset = '1' then
+                    state_next <= S_IDLE;
+                elsif CntSckTc = '1' then
+                    state_next <= S_STEP_4;
+                elsif CntSckTc = '0' then
+                    state_next <= S_STEP_3;
+                end if;
+            when S_STEP_4 =>
+                If reset = '1' then
+                    state_next <= S_IDLE;
+                elsif CntSckTc = '0' then
+                    state_next <= S_STEP_4;
+                elsif CntSckTc = '1' and CntBitsTC = '0' then
+                    state_next <= S_STEP_1;
+                    RegDataEn <= '1';
+                    CntBitsEn <= '1';
+                elsif CntSckTc = '1' and CntBitsTC = '1' then
+                    state_next <= S_IDLE;
+                end if;
+            when S_ERROR =>
+                if reset = '1' then
+                    state_next <= S_IDLE;
+                else
+                    state_next <= S_ERROR;
+                    CntSckRst  <= 'X';
+                    RegDataLd  <= 'X';
+                    RegDataEn  <= 'X';
+                    CntBitsEn  <= 'X';
+                    CntBitsRst <= 'X';
+                end if;
+        end case;
+    end process;
+
+    -- Register fuer Zustand und Ausgaenge
+    Reg: process
+    begin
+        wait until rising_edge(clk);
+
+        -- Zustandswechsel
+        state <= state_next;
+
+        -- Berechnung der Moore-Ausgaenge, die nur vom Zustand abhaengen
+        -- Default-Werte
+        ssel    <= 'X';
+        sck     <= 'X';
+        s_ready <= 'X';
+
+        case state_next is
+            when S_IDLE =>
+                ssel    <= '1';
+                sck     <= '0';
+                s_ready <= '1';
+            when S_STEP_1 =>
+                ssel    <= '0';
+                sck     <= '0';
+                s_ready <= '0';
+            when S_STEP_2 =>
+                ssel    <= '0';
+                sck     <= '1';
+                s_ready <= '0';
+            when S_STEP_3 =>
+                ssel    <= '0';
+                sck     <= '1';
+                s_ready <= '0';
+            when S_STEP_4 =>
+                ssel    <= '0';
+                sck     <= '0';
+                s_ready <= '0';
+            when S_ERROR =>
+                ssel    <= 'X';
+                sck     <= 'X';
+                s_ready <= 'X';
+        end case;
+    end process;
 end rtl;
@@ -0,0 +1,73 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity spi_transmitter_tb is
+end;
+
+architecture rtl of spi_transmitter_tb is
+
+    constant EXT_CLOCK_FREQ : integer := 125000000;
+    constant SCK_FREQ       : integer := 1000000;
+    constant AW             : POSITIVE := 8;
+
+    constant clk_half_period : time :=  1 sec / EXT_CLOCK_FREQ / 2;
+
+    signal clk     : std_logic := '0';
+    signal reset   : std_logic := '1';
+
+    signal s_data  : std_logic_vector(7 downto 0) := (others=>'0') ;
+    signal s_valid : std_logic := '0';
+    signal s_ready : std_logic;
+
+    signal sck     : std_logic;
+    signal mosi    : std_logic;
+    signal ssel    : std_logic;
+
+begin
+
+    clk_proc: process (clk)
+    begin
+        clk <= not clk after clk_half_period;
+    end process;
+
+    stim: process
+    begin
+        reset <= '0' after 100 * clk_half_period;
+
+        wait until reset = '0';
+        wait until rising_edge(clk);
+        s_data <= x"48";
+        s_valid <= '1';
+
+        loop
+            wait until rising_edge(clk);
+            if s_ready = '1' then
+                s_valid <= '0';
+                s_data <= (others=>'0');
+                exit;
+            end if;
+        end loop;
+
+        wait;
+
+    end process;
+
+    dut: entity work.spi_transmitter
+    generic map (
+        AW     => AW,
+        CLKDIV => EXT_CLOCK_FREQ / (SCK_FREQ * 4)
+    )
+    port map (
+        clk     => clk,
+        reset   => reset,
+
+        s_data  => s_data,
+        s_valid => s_valid,
+        s_ready => s_ready,
+
+        mosi    => mosi,
+        sck     => sck,
+        ssel    => ssel
+    );
+end architecture;
@@ -5,6 +5,7 @@ if { [file exists work] == 0} {

 # Benoetigte Dateien uebersetzen
 vcom -work work spi_transmitter.vhd
+vcom -work work spi_rom_control.vhd
 vcom -work work spi2display_rom.vhd
 vcom -work work spi2display.vhd
 vcom -work work spi2display_tb.vhd
@@ -30,23 +31,41 @@ if {1} {
 }

 if {1} {
-	add wave -divider "Interne Signale"
-	add wave -noupdate -ascii /spi2display_tb/dut/SPI_Transmitter_Inst/data
-	add wave -noupdate -hexadecimal /spi2display_tb/dut/SPI_Transmitter_Inst/addr
-	add wave -divider "Steuerwerk"
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/Steuerwerk/state
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/Steuerwerk/state_next
-	add wave -divider "Steuersignale"
+	add wave -noupdate -divider {Interne Signale}
+	add wave -noupdate /spi2display_tb/dut/addr
+	add wave -noupdate -radix ascii /spi2display_tb/dut/data_rom
+	add wave -noupdate -radix ascii /spi2display_tb/dut/data
+	add wave -noupdate /spi2display_tb/dut/valid
+	add wave -noupdate /spi2display_tb/dut/ready
+	add wave -noupdate -divider spi_rom_control
+	add wave -noupdate -divider Steuerwerk
+	add wave -noupdate /spi2display_tb/dut/Control_Inst/state
+	add wave -noupdate /spi2display_tb/dut/Control_Inst/state_next
+	add wave -noupdate /spi2display_tb/dut/Control_Inst/CtrlBits
+	add wave -noupdate /spi2display_tb/dut/Control_Inst/CntAddrEn
+	add wave -noupdate /spi2display_tb/dut/Control_Inst/CntAddrRst
+	add wave -noupdate /spi2display_tb/dut/Control_Inst/RegDataEn
+	add wave -noupdate -divider Rechenwerk
+	add wave -noupdate -label RegData -radix ascii /spi2display_tb/dut/Control_Inst/RegData/Q
+	add wave -noupdate -label CntAddr /spi2display_tb/dut/Control_Inst/CntAddr/cntVal
+}
+
+if {1} {
+	add wave -noupdate -divider "spi_transmitter"
+	add wave -noupdate -divider Steuerwerk
+	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/state
+	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/state_next
 	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CntSckTc
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CntBitsTC
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CtrlBits
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/cntAddrEn
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/cntAddrRst
+	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CntSckRst
 	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/RegDataLd
-	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/RegDataShift
+	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/RegDataEn
 	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CntBitsEn
-	add wave -divider "Rechenwerk"
-	add wave -noupdate -unsigned -label CounterBits /spi2display_tb/dut/SPI_Transmitter_Inst/Rechenwerk/CntBits/cntVal
+	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CntBitsTC
+	add wave -noupdate /spi2display_tb/dut/SPI_Transmitter_Inst/CntBitsRst
+	add wave -noupdate -divider Rechenwerk
+	add wave -noupdate -label RegData /spi2display_tb/dut/SPI_Transmitter_Inst/RegData/Q
+	add wave -noupdate -label CntSck /spi2display_tb/dut/SPI_Transmitter_Inst/CntSck/cntVal
+	add wave -noupdate -label CntBits /spi2display_tb/dut/SPI_Transmitter_Inst/CntBits/cntVal
 }

 run 1000 us
@@ -0,0 +1,44 @@
+# work-Bibliothek erzeugen, falls nicht schon vorhanden
+if { [file exists work] == 0} {
+	vlib work
+}
+
+# Benoetigte Dateien uebersetzen
+vcom -work work spi_transmitter.vhd
+vcom -work work spi_transmitter_tb.vhd
+
+# Simulator starten
+vsim -voptargs=+acc spi_transmitter_tb
+
+# Breite der Namensspalte
+configure wave -namecolwidth 128
+configure wave -datasetprefix 0
+configure wave -signalnamewidth 1
+configure wave -namecolwidth 154
+configure wave -valuecolwidth 100
+set NumericStdNoWarnings 1
+
+add wave -divider "Externe Signale"
+add wave -noupdate /spi_transmitter_tb/clk
+add wave -noupdate /spi_transmitter_tb/reset
+add wave -noupdate /spi_transmitter_tb/s_data
+add wave -noupdate /spi_transmitter_tb/s_valid
+add wave -noupdate /spi_transmitter_tb/s_ready
+add wave -noupdate /spi_transmitter_tb/sck
+add wave -noupdate /spi_transmitter_tb/mosi
+add wave -noupdate /spi_transmitter_tb/ssel
+
+add wave -divider "Interne Signale"
+add wave -noupdate /spi_transmitter_tb/dut/state
+add wave -noupdate /spi_transmitter_tb/dut/state_next
+add wave -noupdate /spi_transmitter_tb/dut/CntSckTc
+add wave -noupdate /spi_transmitter_tb/dut/CntSckRst
+add wave -noupdate /spi_transmitter_tb/dut/RegDataLd
+add wave -noupdate /spi_transmitter_tb/dut/RegDataEn
+add wave -noupdate /spi_transmitter_tb/dut/CntBitsEn
+add wave -noupdate /spi_transmitter_tb/dut/CntBitsTC
+add wave -noupdate /spi_transmitter_tb/dut/CntBitsRst
+add wave -noupdate -label CntBits /spi_transmitter_tb/dut/CntBits/cntVal
+add wave -noupdate -label RegDataQ /spi_transmitter_tb/dut/RegData/Q
+
+run 1000 us
@@ -0,0 +1,223 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="63" Path="C:/Studium/5.SemesterOSNA/ElektronischeSysteme/Praktikum/es_praktikumv2/es-praktikum/Milestone2/VivadoProjekt/axis_audio_bitcrusher/axis_audio_bitcrusher.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="5d14f671135a48969d5ef9dccee6654d"/>
+    <Option Name="Part" Val="xc7z020clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.1"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.3"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.3"/>
+    <Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
+    <Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.1"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../../../../../../Users/basti/AppData/Roaming/Xilinx/Vivado/2023.1/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="zybo-z7-20"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../axis_audio_bitcrusher.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="axis_audio_bitcrusher"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../../milestone2.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="axis_audio_bitcrusher"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="20">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all
+use ieee.numeric_std.all
+
+entity axis_audio_bitcrusher is
+    generic
+    (
+        BIT_REDUCTION      : integer     := 14;
+        HAS_LAST           : boolean     := false
+    );
+    port
+    (
+        AXIS_ACLK               : in  std_logic;
+		AXIS_ARESETN            : in  std_logic;
+
+        -- AXI Streaming Target Port
+        S_AXIS_TVALID           : in  std_logic := '0';
+        S_AXIS_TDATA            : in  std_logic_vector(15 downto 0) := (others => '0');
+        S_AXIS_TLAST            : in  std_logic := '0';
+        S_AXIS_TREADY           : out std_logic;
+
+        -- AXI Streaming Initiator Port
+        M_AXIS_TVALID           : out std_logic;
+        M_AXIS_TDATA            : out std_logic_vector(15 downto 0);
+        M_AXIS_TLAST            : out std_logic;
+        M_AXIS_TREADY           : in  std_logic := '1'
+    );  
+end;
+
+architecture rtl of axis_audio_bitcrusher is
+    reg_out <= reg_in(31 downto x) & (others => '0');  -- Setze die Bits 0 bis (x-1) auf Null
+begin
+
+end;
@@ -0,0 +1,15 @@
+create_clock -add -name clk_pin -period 8.00 [get_ports clk ];
+set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports clk]; # Board Clock (125 MHZ)
+
+set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports reset];
+#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports switch];
+
+set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 PULLUP true} [get_ports i2c_scl_io];
+set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 PULLUP true} [get_ports i2c_sda_io];
+set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports bclk];
+set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports pb_dat];
+set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports pb_lrc];
+set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports rec_dat];
+set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports rec_lrc];
+set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports mute];
+set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports mclk];
@@ -4,11 +4,12 @@
 ## Verwendete Softwareversionen

 - Vivado 2023.1
+- ModelSim - INTEL FPGA STARTER EDITION 2020.1


 ## Fortschritt

- [ ] Milestone1
+- [X] Milestone1
 - [ ] Milestone2
 - [ ] Milestone3
 - [ ] Milestone4