M3: Blockdesign angelegt + Simulation
This commit is contained in:
Matthias Biermann
@@ -0,0 +1,85 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="design_1_wrapper_behav.wdb" id="1">
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<top_modules>
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<top_module name="design_1_wrapper" />
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<top_module name="glbl" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="230,762.430 ns"></ZoomStartTime>
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<ZoomEndTime time="230,867.515 ns"></ZoomEndTime>
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<Cursor1Time time="230,850.000 ns"></Cursor1Time>
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</zoom_setting>
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||||
<column_width_setting>
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||||
<NameColumnWidth column_width="262"></NameColumnWidth>
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||||
<ValueColumnWidth column_width="118"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="10" />
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<wvobject fp_name="/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL_ACLK" type="logic">
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<obj_property name="ElementShortName">M_AXIL_ACLK</obj_property>
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<obj_property name="ObjectShortName">M_AXIL_ACLK</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/clk_rst_generator_0/rst_n" type="logic">
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<obj_property name="ElementShortName">rst_n</obj_property>
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<obj_property name="ObjectShortName">rst_n</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL" type="protoinst">
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<obj_property name="ElementShortName">M_AXIL</obj_property>
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<obj_property name="ObjectShortName">M_AXIL</obj_property>
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<obj_property name="children_use_element_short_name">true</obj_property>
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<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
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<obj_property name="EnumTransactionColorTable">0=blank 1=#D399FF 2=pink</obj_property>
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<obj_property name="EnumTransactionValueTable">0=blank;1=Read;2=Write;3=Read/Write</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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<obj_property name="CustomSignalColor">turquoise</obj_property>
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<obj_property name="Render_Data">/design_1_wrapper/design_1_i/axil_master_with_rom_0/M_AXIL.readWriteSummary</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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<obj_property name="CellHeight">36</obj_property>
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||||
<obj_property name="isExpanded"></obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS" type="protoinst">
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<obj_property name="children_use_element_short_name">true</obj_property>
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<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
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||||
<obj_property name="EnumTransactionColorTable">fff,fff=blank</obj_property>
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<obj_property name="UseCustomSignalColor">true</obj_property>
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<obj_property name="CustomSignalColor">#00E600</obj_property>
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<obj_property name="Render_Data">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.streamWaveData</obj_property>
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<obj_property name="Number_Overlay">2</obj_property>
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<obj_property name="Overlay_Object_0">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.linkStarve</obj_property>
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<obj_property name="Overlay_Color_0">#99E600</obj_property>
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<obj_property name="Overlay_Object_1">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.linkStall</obj_property>
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<obj_property name="Overlay_Color_1">#E64C00</obj_property>
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<obj_property name="Detail_Data">/design_1_wrapper/design_1_i/axis_audio_stereo2mo_0/M_AXIS.streamTooltipData</obj_property>
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<obj_property name="ElementShortName">M_AXIS</obj_property>
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<obj_property name="ObjectShortName">M_AXIS</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axis_audio_mono2ster_0/S_AXIS" type="protoinst">
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<obj_property name="ElementShortName">S_AXIS</obj_property>
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<obj_property name="ObjectShortName">S_AXIS</obj_property>
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</wvobject>
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<wvobject type="divider" fp_name="divider52">
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<obj_property name="label">Interne Signale</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/ip_active" type="logic">
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<obj_property name="ElementShortName">ip_active</obj_property>
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<obj_property name="ObjectShortName">ip_active</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/c0" type="array">
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<obj_property name="ElementShortName">c0[7:0]</obj_property>
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<obj_property name="ObjectShortName">c0[7:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/c1" type="array">
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<obj_property name="ElementShortName">c1[7:0]</obj_property>
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<obj_property name="ObjectShortName">c1[7:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/design_1_wrapper/design_1_i/axis_prog_audio_filt_0/U0/c2" type="array">
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<obj_property name="ElementShortName">c2[7:0]</obj_property>
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<obj_property name="ObjectShortName">c2[7:0]</obj_property>
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</wvobject>
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</wave_config>
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@@ -0,0 +1,203 @@
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{
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"graphjs": {
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"version": "1.0",
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"keys": [
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{
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"abrv": "VH",
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||||
"name": "vert_hid",
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||||
"type": "int",
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"for": "node"
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},
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{
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||||
"abrv": "VM",
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||||
"name": "vert_name",
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||||
"type": "string",
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"for": "node"
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||||
},
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{
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||||
"abrv": "VT",
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||||
"name": "vert_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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{
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"abrv": "BA",
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||||
"name": "base_addr",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "HA",
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||||
"name": "high_addr",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "BP",
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||||
"name": "base_param",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "HP",
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||||
"name": "high_param",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MA",
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||||
"name": "master_addrspace",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MX",
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||||
"name": "master_instance",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MI",
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||||
"name": "master_interface",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MS",
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||||
"name": "master_segment",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MV",
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||||
"name": "master_vlnv",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "SX",
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||||
"name": "slave_instance",
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||||
"type": "string",
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||||
"for": "node"
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},
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{
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||||
"abrv": "SI",
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||||
"name": "slave_interface",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "MM",
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||||
"name": "slave_memmap",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "SS",
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||||
"name": "slave_segment",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "SV",
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||||
"name": "slave_vlnv",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "TM",
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||||
"name": "memory_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "TU",
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||||
"name": "usage_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "LT",
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||||
"name": "lock_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "BT",
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||||
"name": "boot_type",
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||||
"type": "string",
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||||
"for": "node"
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||||
},
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||||
{
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||||
"abrv": "EH",
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||||
"name": "edge_hid",
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||||
"type": "int",
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||||
"for": "edge"
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||||
}
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||||
],
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||||
"vertice_type_order": [
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{
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||||
"abrv": "BC",
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||||
"desc": "Block Container"
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||||
},
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||||
{
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||||
"abrv": "PR",
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||||
"desc": "Parital Reference"
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||||
},
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||||
{
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||||
"abrv": "VR",
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||||
"desc": "Variant"
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||||
},
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||||
{
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||||
"abrv": "PM",
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||||
"desc": "Variant Permutations"
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||||
},
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||||
{
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||||
"abrv": "CX",
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||||
"desc": "Boundary Connection"
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||||
},
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||||
{
|
||||
"abrv": "AC",
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||||
"desc": "Assignment Coordinate"
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||||
},
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||||
{
|
||||
"abrv": "ACE",
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||||
"desc": "Excluded Assign Coordinate"
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||||
},
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||||
{
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||||
"abrv": "APX",
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||||
"desc": "Boundary Aperture"
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||||
},
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||||
{
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||||
"abrv": "CIP",
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||||
"desc": "High level Processing System"
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||||
}
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||||
],
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||||
"vertices": {
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||||
"V0": {
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||||
"VM": "design_1",
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"VT": "BC"
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||||
},
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||||
"V1": {
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||||
"VH": "2",
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||||
"VM": "design_1",
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||||
"VT": "VR"
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||||
},
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||||
"V2": {
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||||
"VH": "2",
|
||||
"VT": "PM",
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||||
"TU": "active"
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||||
}
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||||
},
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||||
"edges": [
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||||
{
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||||
"src": "V0",
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||||
"trg": "V1"
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||||
},
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||||
{
|
||||
"src": "V1",
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||||
"trg": "V2"
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||||
}
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||||
]
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||||
}
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||||
}
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||||
@@ -0,0 +1,56 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<Root MajorVersion="0" MinorVersion="40">
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||||
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1731254143"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731254149"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1731254143"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731254149"/>
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||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\design_1.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.vhd" Type="VHDL">
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||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="SIMULATION"/>
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||||
<ProcessingOrder Val="NORMAL"/>
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||||
</File>
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||||
<File Name="design_1_ooc.xdc" Type="XDC">
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||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="SYNTHESIS"/>
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||||
<UsedIn Val="IMPLEMENTATION"/>
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||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="design_1.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\design_1.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
@@ -0,0 +1,10 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
|
||||
################################################################################
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Nov 10 16:55:43 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1_wrapper.bd
|
||||
--Design : design_1_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1_wrapper is
|
||||
port (
|
||||
bclk : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
i2c_scl_io : inout STD_LOGIC;
|
||||
i2c_sda_io : inout STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
resez : in STD_LOGIC
|
||||
);
|
||||
end design_1_wrapper;
|
||||
|
||||
architecture STRUCTURE of design_1_wrapper is
|
||||
component design_1 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resez : in STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
i2c_scl_t : out STD_LOGIC;
|
||||
i2c_sda_o : out STD_LOGIC;
|
||||
i2c_sda_i : in STD_LOGIC;
|
||||
i2c_scl_o : out STD_LOGIC;
|
||||
i2c_scl_i : in STD_LOGIC;
|
||||
i2c_sda_t : out STD_LOGIC
|
||||
);
|
||||
end component design_1;
|
||||
component IOBUF is
|
||||
port (
|
||||
I : in STD_LOGIC;
|
||||
O : out STD_LOGIC;
|
||||
T : in STD_LOGIC;
|
||||
IO : inout STD_LOGIC
|
||||
);
|
||||
end component IOBUF;
|
||||
signal i2c_scl_i : STD_LOGIC;
|
||||
signal i2c_scl_o : STD_LOGIC;
|
||||
signal i2c_scl_t : STD_LOGIC;
|
||||
signal i2c_sda_i : STD_LOGIC;
|
||||
signal i2c_sda_o : STD_LOGIC;
|
||||
signal i2c_sda_t : STD_LOGIC;
|
||||
begin
|
||||
design_1_i: component design_1
|
||||
port map (
|
||||
bclk => bclk,
|
||||
clk => clk,
|
||||
i2c_scl_i => i2c_scl_i,
|
||||
i2c_scl_o => i2c_scl_o,
|
||||
i2c_scl_t => i2c_scl_t,
|
||||
i2c_sda_i => i2c_sda_i,
|
||||
i2c_sda_o => i2c_sda_o,
|
||||
i2c_sda_t => i2c_sda_t,
|
||||
mclk => mclk,
|
||||
mute => mute,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc,
|
||||
resez => resez
|
||||
);
|
||||
i2c_scl_iobuf: component IOBUF
|
||||
port map (
|
||||
I => i2c_scl_o,
|
||||
IO => i2c_scl_io,
|
||||
O => i2c_scl_i,
|
||||
T => i2c_scl_t
|
||||
);
|
||||
i2c_sda_iobuf: component IOBUF
|
||||
port map (
|
||||
I => i2c_sda_o,
|
||||
IO => i2c_sda_io,
|
||||
O => i2c_sda_i,
|
||||
T => i2c_sda_t
|
||||
);
|
||||
end STRUCTURE;
|
||||
+4867
File diff suppressed because it is too large
Load Diff
+1091
File diff suppressed because it is too large
Load Diff
+176
@@ -0,0 +1,176 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:axil_master_with_rom:1.0
|
||||
-- IP Revision: 17
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axil_master_with_rom_0_0 IS
|
||||
PORT (
|
||||
interrupt_in : IN STD_LOGIC;
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axil_master_with_rom IS
|
||||
GENERIC (
|
||||
STIM_FILENAME : STRING;
|
||||
HAS_FINISHED_OUT : BOOLEAN;
|
||||
HAS_INTERRUPT_IN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
interrupt_in : IN STD_LOGIC;
|
||||
finished_o : OUT STD_LOGIC;
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axil_master_with_rom;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
|
||||
"SERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axil_master_with_rom
|
||||
GENERIC MAP (
|
||||
STIM_FILENAME => "../../stimuli.mem",
|
||||
HAS_FINISHED_OUT => false,
|
||||
HAS_INTERRUPT_IN => true
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt_in => interrupt_in,
|
||||
M_AXIL_ACLK => M_AXIL_ACLK,
|
||||
M_AXIL_ARESETN => M_AXIL_ARESETN,
|
||||
M_AXIL_ARREADY => M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => M_AXIL_ARVALID,
|
||||
M_AXIL_ARADDR => M_AXIL_ARADDR,
|
||||
M_AXIL_ARPROT => M_AXIL_ARPROT,
|
||||
M_AXIL_RREADY => M_AXIL_RREADY,
|
||||
M_AXIL_RVALID => M_AXIL_RVALID,
|
||||
M_AXIL_RDATA => M_AXIL_RDATA,
|
||||
M_AXIL_RRESP => M_AXIL_RRESP,
|
||||
M_AXIL_AWREADY => M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => M_AXIL_AWVALID,
|
||||
M_AXIL_AWADDR => M_AXIL_AWADDR,
|
||||
M_AXIL_AWPROT => M_AXIL_AWPROT,
|
||||
M_AXIL_WREADY => M_AXIL_WREADY,
|
||||
M_AXIL_WVALID => M_AXIL_WVALID,
|
||||
M_AXIL_WDATA => M_AXIL_WDATA,
|
||||
M_AXIL_WSTRB => M_AXIL_WSTRB,
|
||||
M_AXIL_BREADY => M_AXIL_BREADY,
|
||||
M_AXIL_BVALID => M_AXIL_BVALID,
|
||||
M_AXIL_BRESP => M_AXIL_BRESP
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0_arch;
|
||||
+695
@@ -0,0 +1,695 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:22 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:27d6e957</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_audio_mono2ster_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:22 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:27d6e957</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.S_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
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||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
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|
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|
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|
||||
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|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
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|
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|
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<xilinx:enablement>
|
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.M_AXIS_TLAST" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_LAST'))">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
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<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
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<spirit:file>
|
||||
<spirit:name>sim/design_1_axis_audio_mono2ster_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_audio_mono2stereo</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_axis_audio_mono2ster_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>axis_audio_mono2stereo</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>3</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="ui.data.coregen.dd@33527e3f_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
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<xilinx:tag xilinx:name="ui.data.coregen.dd@60b70a2a_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
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<xilinx:tag xilinx:name="ui.data.coregen.dd@b393973_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@11107b6b_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@306669e8_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@3d4dbd54_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@50f254d8_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@267e2692_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@6fdc1ebf_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@79b365fa_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@425bf28e_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@2d012246_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@714d7ede_ARCHIVE_LOCATION">c:/users/winni/desktop/es/ip/axis_audio_mono2stereo/axis_audio_mono2stereo.srcs</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0c4329dc"/>
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||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="dd41f636"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="7314069d"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_audio_mono2ster_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_axis_audio_mono2ster_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_audio_mono2ster_0_0_arch OF design_1_axis_audio_mono2ster_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_mono2stereo IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_mono2stereo;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_mono2stereo
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_axis_audio_mono2ster_0_0_arch;
|
||||
+715
@@ -0,0 +1,715 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_axis_audio_stereo2mo_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">2</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDATA_NUM_BYTES</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TDEST_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TID_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TUSER_WIDTH</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TREADY</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TSTRB</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TKEEP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_TLAST</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>LAYERED_METADATA</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXIS_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF">M_AXIS:S_AXIS</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE">0.0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
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|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXIS_ACLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="99cc5cf7"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1a2f7743"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="71e811ad"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8f91c677"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="b17a0555"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_audio_stereo2mo_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_axis_audio_stereo2mo_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_audio_stereo2mo_0_0_arch OF design_1_axis_audio_stereo2mo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_stereo2mono IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_stereo2mono;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_stereo2mono
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_axis_audio_stereo2mo_0_0_arch;
|
||||
+1478
File diff suppressed because it is too large
Load Diff
+204
@@ -0,0 +1,204 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_prog_audio_filt_0_1 IS
|
||||
PORT (
|
||||
AXI_ACLK : IN STD_LOGIC;
|
||||
AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_axis_prog_audio_filt_0_1;
|
||||
|
||||
ARCHITECTURE design_1_axis_prog_audio_filt_0_1_arch OF design_1_axis_prog_audio_filt_0_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_prog_audio_filter3 IS
|
||||
GENERIC (
|
||||
COEFF_0 : INTEGER;
|
||||
COEFF_1 : INTEGER;
|
||||
COEFF_2 : INTEGER;
|
||||
SHIFT : INTEGER;
|
||||
RUN_AFTER_RESET : BOOLEAN;
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXI_ACLK : IN STD_LOGIC;
|
||||
AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_prog_audio_filter3;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
|
||||
"ITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_prog_audio_filter3
|
||||
GENERIC MAP (
|
||||
COEFF_0 => 42,
|
||||
COEFF_1 => 42,
|
||||
COEFF_2 => 42,
|
||||
SHIFT => 7,
|
||||
RUN_AFTER_RESET => true,
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXI_ACLK => AXI_ACLK,
|
||||
AXI_ARESETN => AXI_ARESETN,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_axis_prog_audio_filt_0_1_arch;
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>wg</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a3a4ca5c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a3a4ca5c</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_CLK_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_in</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.rst_in" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_RESET_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>stop_simulation</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.stop_simulation" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.HAS_STOP_INPUT'))">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:portInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Clk Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Has Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/design_1_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLOCK_PERIOD</spirit:name>
|
||||
<spirit:displayName>Clock Period [ps]</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_PERIOD">10000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_CLK_INPUT</spirit:name>
|
||||
<spirit:displayName>Clock Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CLK_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_RESET_INPUT</spirit:name>
|
||||
<spirit:displayName>Reset Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_RESET_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_STOP_INPUT</spirit:name>
|
||||
<spirit:displayName>Stop Input</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_STOP_INPUT">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_clk_rst_generator_0_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>clk_rst_generator</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dffad19"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="c53bea4f"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5ac869d7"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5fa3ca69"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 10000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0_arch;
|
||||
+974
@@ -0,0 +1,974 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xFCAD0CEC4FC8C3F2",
|
||||
"design_src": "SBD",
|
||||
"device": "xc7z020clg400-1",
|
||||
"name": "bd_f60c",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"scoped": "true",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"ila_lib": "",
|
||||
"g_inst": "",
|
||||
"slot_0_aw": "",
|
||||
"slot_0_w": "",
|
||||
"slot_0_b": "",
|
||||
"slot_0_ar": "",
|
||||
"slot_0_r": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXI": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"ADDR_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "default"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_READ_THREADS": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"NUM_WRITE_THREADS": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "default"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "default"
|
||||
},
|
||||
"RUSER_BITS_PER_BYTE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"WUSER_BITS_PER_BYTE": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_2_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "resetn"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_f60c_clk",
|
||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"ila_lib": {
|
||||
"vlnv": "xilinx.com:ip:ila:6.2",
|
||||
"xci_name": "bd_f60c_ila_lib_0",
|
||||
"xci_path": "ip\\ip_0\\bd_f60c_ila_lib_0.xci",
|
||||
"inst_hier_path": "ila_lib",
|
||||
"parameters": {
|
||||
"ALL_PROBE_SAME_MU": {
|
||||
"value": "TRUE"
|
||||
},
|
||||
"ALL_PROBE_SAME_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_ADV_TRIGGER": {
|
||||
"value": "FALSE"
|
||||
},
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "1024"
|
||||
},
|
||||
"C_EN_STRG_QUAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_ILA_CLK_FREQ": {
|
||||
"value": "100000000"
|
||||
},
|
||||
"C_INPUT_PIPE_STAGES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_MONITOR_TYPE": {
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "26"
|
||||
},
|
||||
"C_PROBE0_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE0_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE10_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE10_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE11_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE11_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE12_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE12_WIDTH": {
|
||||
"value": "4"
|
||||
},
|
||||
"C_PROBE13_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE13_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE14_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE14_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE15_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE15_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE16_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE16_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE17_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE17_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE18_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE18_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE19_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE19_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE20_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE20_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE21_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE21_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE22_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE22_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE23_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE23_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE24_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE24_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE25_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE25_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE2_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE2_WIDTH": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE3_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE3_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE4_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE4_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_PROBE5_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE5_WIDTH": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_PROBE6_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE6_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE7_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE7_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE8_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE8_WIDTH": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_PROBE9_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE9_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_TRIGIN_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_TRIGOUT_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_XLNX_HW_PROBE_INFO": {
|
||||
"value": "DEFAULT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"g_inst": {
|
||||
"vlnv": "xilinx.com:ip:gigantic_mux:1.0",
|
||||
"xci_name": "bd_f60c_g_inst_0",
|
||||
"xci_path": "ip\\ip_1\\bd_f60c_g_inst_0.xci",
|
||||
"inst_hier_path": "g_inst",
|
||||
"parameters": {
|
||||
"C_EN_GIGAMUX": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_ADDR_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_SLOT_0_AXI_ARUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_AR_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_AWUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_AW_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_AXLEN_WIDTH": {
|
||||
"value": "8"
|
||||
},
|
||||
"C_SLOT_0_AXI_AXLOCK_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_BUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_B_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_DATA_WIDTH": {
|
||||
"value": "32"
|
||||
},
|
||||
"C_SLOT_0_AXI_ID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_PROTOCOL": {
|
||||
"value": "AXI4LITE"
|
||||
},
|
||||
"C_SLOT_0_AXI_RUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_R_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_AXI_WUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_W_SEL": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_BRESP": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_BURST": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_CACHE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_LOCK": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_PROT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_QOS": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_REGION": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_RRESP": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_WSTRB": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_MAX_RD_BURSTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_MAX_WR_BURSTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_0_TXN_CNTR_EN": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_1_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_2_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_2_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_2_MON_MODE": {
|
||||
"value": "FT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"slot_0_aw": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_aw_0",
|
||||
"xci_path": "ip\\ip_2\\bd_f60c_slot_0_aw_0.xci",
|
||||
"inst_hier_path": "slot_0_aw"
|
||||
},
|
||||
"slot_0_w": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_w_0",
|
||||
"xci_path": "ip\\ip_3\\bd_f60c_slot_0_w_0.xci",
|
||||
"inst_hier_path": "slot_0_w",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
},
|
||||
"slot_0_b": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_b_0",
|
||||
"xci_path": "ip\\ip_4\\bd_f60c_slot_0_b_0.xci",
|
||||
"inst_hier_path": "slot_0_b"
|
||||
},
|
||||
"slot_0_ar": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_ar_0",
|
||||
"xci_path": "ip\\ip_5\\bd_f60c_slot_0_ar_0.xci",
|
||||
"inst_hier_path": "slot_0_ar"
|
||||
},
|
||||
"slot_0_r": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"xci_name": "bd_f60c_slot_0_r_0",
|
||||
"xci_path": "ip\\ip_6\\bd_f60c_slot_0_r_0.xci",
|
||||
"inst_hier_path": "slot_0_r",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"SLOT_0_AXI",
|
||||
"g_inst/slot_0_axi"
|
||||
]
|
||||
},
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"SLOT_1_AXIS",
|
||||
"g_inst/slot_1_axis"
|
||||
]
|
||||
},
|
||||
"Conn2": {
|
||||
"interface_ports": [
|
||||
"SLOT_2_AXIS",
|
||||
"g_inst/slot_2_axis"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"ila_lib/clk",
|
||||
"g_inst/aclk"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_ar_cnt",
|
||||
"ila_lib/probe0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_ar_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_ar/dout",
|
||||
"ila_lib/probe16"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_araddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_araddr",
|
||||
"ila_lib/probe1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arprot": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_arprot",
|
||||
"ila_lib/probe2"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_arready",
|
||||
"slot_0_ar/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_arvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_arvalid",
|
||||
"slot_0_ar/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_aw_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_aw_cnt",
|
||||
"ila_lib/probe3"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_aw_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_aw/dout",
|
||||
"ila_lib/probe13"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awaddr": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awaddr",
|
||||
"ila_lib/probe4"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awprot": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awprot",
|
||||
"ila_lib/probe5"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awready",
|
||||
"slot_0_aw/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_awvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_awvalid",
|
||||
"slot_0_aw/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_b_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_b_cnt",
|
||||
"ila_lib/probe6"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_b_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_b/dout",
|
||||
"ila_lib/probe15"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bready",
|
||||
"slot_0_b/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bresp",
|
||||
"ila_lib/probe7"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_bvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_bvalid",
|
||||
"slot_0_b/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_r_cnt": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_r_cnt",
|
||||
"ila_lib/probe8"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_r_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_r/dout",
|
||||
"ila_lib/probe17"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rdata",
|
||||
"ila_lib/probe9"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rready",
|
||||
"slot_0_r/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rresp": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rresp",
|
||||
"ila_lib/probe10"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_rvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_rvalid",
|
||||
"slot_0_r/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_w_ctrl": {
|
||||
"ports": [
|
||||
"slot_0_w/dout",
|
||||
"ila_lib/probe14"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wdata",
|
||||
"ila_lib/probe11"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wready",
|
||||
"slot_0_w/In1"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wstrb": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wstrb",
|
||||
"ila_lib/probe12"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axi_wvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axi_wvalid",
|
||||
"slot_0_w/In0"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tdata",
|
||||
"ila_lib/probe18"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tlast",
|
||||
"ila_lib/probe21"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tready",
|
||||
"ila_lib/probe20"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tvalid",
|
||||
"ila_lib/probe19"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tdata",
|
||||
"ila_lib/probe22"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tlast",
|
||||
"ila_lib/probe25"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tready",
|
||||
"ila_lib/probe24"
|
||||
]
|
||||
},
|
||||
"net_slot_2_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_2_axis_tvalid",
|
||||
"ila_lib/probe23"
|
||||
]
|
||||
},
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
"g_inst/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1731254144"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731254148"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1731254144"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731254148"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_f60c.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_f60c.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_f60c.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_f60c_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_system_ila_0_0.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_system_ila_0_0.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Command: generate_target bd_f60c_wrapper.bd
|
||||
--Design : bd_f60c_wrapper
|
||||
--Purpose: IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity bd_f60c_wrapper is
|
||||
port (
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end bd_f60c_wrapper;
|
||||
|
||||
architecture STRUCTURE of bd_f60c_wrapper is
|
||||
component bd_f60c is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC
|
||||
);
|
||||
end component bd_f60c;
|
||||
begin
|
||||
bd_f60c_i: component bd_f60c
|
||||
port map (
|
||||
SLOT_0_AXI_araddr(31 downto 0) => SLOT_0_AXI_araddr(31 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => SLOT_0_AXI_arprot(2 downto 0),
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_awaddr(31 downto 0) => SLOT_0_AXI_awaddr(31 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => SLOT_0_AXI_awprot(2 downto 0),
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_bready => SLOT_0_AXI_bready,
|
||||
SLOT_0_AXI_bresp(1 downto 0) => SLOT_0_AXI_bresp(1 downto 0),
|
||||
SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
|
||||
SLOT_0_AXI_rdata(31 downto 0) => SLOT_0_AXI_rdata(31 downto 0),
|
||||
SLOT_0_AXI_rready => SLOT_0_AXI_rready,
|
||||
SLOT_0_AXI_rresp(1 downto 0) => SLOT_0_AXI_rresp(1 downto 0),
|
||||
SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
|
||||
SLOT_0_AXI_wdata(31 downto 0) => SLOT_0_AXI_wdata(31 downto 0),
|
||||
SLOT_0_AXI_wready => SLOT_0_AXI_wready,
|
||||
SLOT_0_AXI_wstrb(3 downto 0) => SLOT_0_AXI_wstrb(3 downto 0),
|
||||
SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
|
||||
SLOT_1_AXIS_tdata(15 downto 0) => SLOT_1_AXIS_tdata(15 downto 0),
|
||||
SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
|
||||
SLOT_2_AXIS_tdata(15 downto 0) => SLOT_2_AXIS_tdata(15 downto 0),
|
||||
SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
|
||||
SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
|
||||
SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
|
||||
clk => clk,
|
||||
resetn => resetn
|
||||
);
|
||||
end STRUCTURE;
|
||||
+6156
File diff suppressed because it is too large
Load Diff
+6324
File diff suppressed because it is too large
Load Diff
+74626
File diff suppressed because it is too large
Load Diff
+89
@@ -0,0 +1,89 @@
|
||||
-- (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY bd_f60c_ila_lib_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
|
||||
|
||||
probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe5 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe12 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe18 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe22 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_f60c_ila_lib_0;
|
||||
|
||||
ARCHITECTURE bd_f60c_ila_lib_0_arch OF bd_f60c_ila_lib_0 IS
|
||||
BEGIN
|
||||
END bd_f60c_ila_lib_0_arch;
|
||||
+3042
File diff suppressed because it is too large
Load Diff
+111258
File diff suppressed because it is too large
Load Diff
+4927
File diff suppressed because it is too large
Load Diff
+4244
File diff suppressed because it is too large
Load Diff
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_f60c_slot_0_aw_0",
|
||||
"cell_name": "slot_0_aw",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_f60c_slot_0_aw_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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"IN30_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"IN35_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"IN38_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
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||||
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|
||||
"IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
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|
||||
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4869
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_aw_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_f60c_slot_0_w_0",
|
||||
"cell_name": "slot_0_w",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_f60c_slot_0_w_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4870
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_w_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_f60c_slot_0_b_0",
|
||||
"cell_name": "slot_0_b",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_f60c_slot_0_b_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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"IN42_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4869
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_b_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_f60c_slot_0_ar_0",
|
||||
"cell_name": "slot_0_ar",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_f60c_slot_0_ar_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4869
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_ar_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+307
@@ -0,0 +1,307 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "bd_f60c_slot_0_r_0",
|
||||
"cell_name": "slot_0_r",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "bd_f60c_slot_0_r_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"IN54_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN98_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN99_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../../../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"In1": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "1", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4870
File diff suppressed because it is too large
Load Diff
+328
@@ -0,0 +1,328 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_r_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"bd_f60c": {
|
||||
"proto_instances": {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+435
@@ -0,0 +1,435 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Command: generate_target bd_f60c.bd
|
||||
--Design : bd_f60c
|
||||
--Purpose: IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity bd_f60c is
|
||||
port (
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
|
||||
end bd_f60c;
|
||||
|
||||
architecture STRUCTURE of bd_f60c is
|
||||
component bd_f60c_ila_lib_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component bd_f60c_ila_lib_0;
|
||||
component bd_f60c_g_inst_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_slot_0_axi_b_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_r_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_aw_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_ar_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
slot_0_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
slot_0_axi_awvalid : in STD_LOGIC;
|
||||
slot_0_axi_awready : in STD_LOGIC;
|
||||
slot_0_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
slot_0_axi_wvalid : in STD_LOGIC;
|
||||
slot_0_axi_wready : in STD_LOGIC;
|
||||
slot_0_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
slot_0_axi_bvalid : in STD_LOGIC;
|
||||
slot_0_axi_bready : in STD_LOGIC;
|
||||
slot_0_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
slot_0_axi_arvalid : in STD_LOGIC;
|
||||
slot_0_axi_arready : in STD_LOGIC;
|
||||
slot_0_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
slot_0_axi_rvalid : in STD_LOGIC;
|
||||
slot_0_axi_rready : in STD_LOGIC;
|
||||
slot_1_axis_tvalid : in STD_LOGIC;
|
||||
slot_1_axis_tready : in STD_LOGIC;
|
||||
slot_1_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
slot_1_axis_tlast : in STD_LOGIC;
|
||||
slot_2_axis_tvalid : in STD_LOGIC;
|
||||
slot_2_axis_tready : in STD_LOGIC;
|
||||
slot_2_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
slot_2_axis_tlast : in STD_LOGIC;
|
||||
m_slot_0_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_slot_0_axi_awvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_awready : out STD_LOGIC;
|
||||
m_slot_0_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_slot_0_axi_wvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_wready : out STD_LOGIC;
|
||||
m_slot_0_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_bvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_bready : out STD_LOGIC;
|
||||
m_slot_0_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_slot_0_axi_arvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_arready : out STD_LOGIC;
|
||||
m_slot_0_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_rvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_rready : out STD_LOGIC;
|
||||
m_slot_1_axis_tvalid : out STD_LOGIC;
|
||||
m_slot_1_axis_tready : out STD_LOGIC;
|
||||
m_slot_1_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_slot_1_axis_tlast : out STD_LOGIC;
|
||||
m_slot_2_axis_tvalid : out STD_LOGIC;
|
||||
m_slot_2_axis_tready : out STD_LOGIC;
|
||||
m_slot_2_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_slot_2_axis_tlast : out STD_LOGIC
|
||||
);
|
||||
end component bd_f60c_g_inst_0;
|
||||
component bd_f60c_slot_0_aw_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_aw_0;
|
||||
component bd_f60c_slot_0_w_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_w_0;
|
||||
component bd_f60c_slot_0_b_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_b_0;
|
||||
component bd_f60c_slot_0_ar_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_ar_0;
|
||||
component bd_f60c_slot_0_r_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_r_0;
|
||||
signal Conn1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal Conn1_TLAST : STD_LOGIC;
|
||||
signal Conn1_TREADY : STD_LOGIC;
|
||||
signal Conn1_TVALID : STD_LOGIC;
|
||||
signal Conn2_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal Conn2_TLAST : STD_LOGIC;
|
||||
signal Conn2_TREADY : STD_LOGIC;
|
||||
signal Conn2_TVALID : STD_LOGIC;
|
||||
signal Conn_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_ARREADY : STD_LOGIC;
|
||||
signal Conn_ARVALID : STD_LOGIC;
|
||||
signal Conn_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_AWREADY : STD_LOGIC;
|
||||
signal Conn_AWVALID : STD_LOGIC;
|
||||
signal Conn_BREADY : STD_LOGIC;
|
||||
signal Conn_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_BVALID : STD_LOGIC;
|
||||
signal Conn_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_RREADY : STD_LOGIC;
|
||||
signal Conn_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_RVALID : STD_LOGIC;
|
||||
signal Conn_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_WREADY : STD_LOGIC;
|
||||
signal Conn_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_WVALID : STD_LOGIC;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal net_slot_0_axi_ar_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_ar_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal net_slot_0_axi_arready : STD_LOGIC;
|
||||
signal net_slot_0_axi_arvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_aw_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_aw_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal net_slot_0_axi_awready : STD_LOGIC;
|
||||
signal net_slot_0_axi_awvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_b_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_b_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_bready : STD_LOGIC;
|
||||
signal net_slot_0_axi_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_bvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_r_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_r_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_rready : STD_LOGIC;
|
||||
signal net_slot_0_axi_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_rvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_w_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_wready : STD_LOGIC;
|
||||
signal net_slot_0_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal net_slot_0_axi_wvalid : STD_LOGIC;
|
||||
signal net_slot_1_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal net_slot_1_axis_tlast : STD_LOGIC;
|
||||
signal net_slot_1_axis_tready : STD_LOGIC;
|
||||
signal net_slot_1_axis_tvalid : STD_LOGIC;
|
||||
signal net_slot_2_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal net_slot_2_axis_tlast : STD_LOGIC;
|
||||
signal net_slot_2_axis_tready : STD_LOGIC;
|
||||
signal net_slot_2_axis_tvalid : STD_LOGIC;
|
||||
signal resetn_1 : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
|
||||
attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
|
||||
attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN bd_f60c_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of SLOT_1_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of SLOT_2_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_2_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
Conn1_TDATA(15 downto 0) <= SLOT_1_AXIS_tdata(15 downto 0);
|
||||
Conn1_TLAST <= SLOT_1_AXIS_tlast;
|
||||
Conn1_TREADY <= SLOT_1_AXIS_tready;
|
||||
Conn1_TVALID <= SLOT_1_AXIS_tvalid;
|
||||
Conn2_TDATA(15 downto 0) <= SLOT_2_AXIS_tdata(15 downto 0);
|
||||
Conn2_TLAST <= SLOT_2_AXIS_tlast;
|
||||
Conn2_TREADY <= SLOT_2_AXIS_tready;
|
||||
Conn2_TVALID <= SLOT_2_AXIS_tvalid;
|
||||
Conn_ARADDR(31 downto 0) <= SLOT_0_AXI_araddr(31 downto 0);
|
||||
Conn_ARPROT(2 downto 0) <= SLOT_0_AXI_arprot(2 downto 0);
|
||||
Conn_ARREADY <= SLOT_0_AXI_arready;
|
||||
Conn_ARVALID <= SLOT_0_AXI_arvalid;
|
||||
Conn_AWADDR(31 downto 0) <= SLOT_0_AXI_awaddr(31 downto 0);
|
||||
Conn_AWPROT(2 downto 0) <= SLOT_0_AXI_awprot(2 downto 0);
|
||||
Conn_AWREADY <= SLOT_0_AXI_awready;
|
||||
Conn_AWVALID <= SLOT_0_AXI_awvalid;
|
||||
Conn_BREADY <= SLOT_0_AXI_bready;
|
||||
Conn_BRESP(1 downto 0) <= SLOT_0_AXI_bresp(1 downto 0);
|
||||
Conn_BVALID <= SLOT_0_AXI_bvalid;
|
||||
Conn_RDATA(31 downto 0) <= SLOT_0_AXI_rdata(31 downto 0);
|
||||
Conn_RREADY <= SLOT_0_AXI_rready;
|
||||
Conn_RRESP(1 downto 0) <= SLOT_0_AXI_rresp(1 downto 0);
|
||||
Conn_RVALID <= SLOT_0_AXI_rvalid;
|
||||
Conn_WDATA(31 downto 0) <= SLOT_0_AXI_wdata(31 downto 0);
|
||||
Conn_WREADY <= SLOT_0_AXI_wready;
|
||||
Conn_WSTRB(3 downto 0) <= SLOT_0_AXI_wstrb(3 downto 0);
|
||||
Conn_WVALID <= SLOT_0_AXI_wvalid;
|
||||
clk_1 <= clk;
|
||||
resetn_1 <= resetn;
|
||||
g_inst: component bd_f60c_g_inst_0
|
||||
port map (
|
||||
aclk => clk_1,
|
||||
aresetn => resetn_1,
|
||||
m_slot_0_axi_ar_cnt(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
m_slot_0_axi_araddr(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
|
||||
m_slot_0_axi_arprot(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
|
||||
m_slot_0_axi_arready => net_slot_0_axi_arready,
|
||||
m_slot_0_axi_arvalid => net_slot_0_axi_arvalid,
|
||||
m_slot_0_axi_aw_cnt(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
m_slot_0_axi_awaddr(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
|
||||
m_slot_0_axi_awprot(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
|
||||
m_slot_0_axi_awready => net_slot_0_axi_awready,
|
||||
m_slot_0_axi_awvalid => net_slot_0_axi_awvalid,
|
||||
m_slot_0_axi_b_cnt(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
m_slot_0_axi_bready => net_slot_0_axi_bready,
|
||||
m_slot_0_axi_bresp(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
m_slot_0_axi_bvalid => net_slot_0_axi_bvalid,
|
||||
m_slot_0_axi_r_cnt(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
m_slot_0_axi_rdata(31 downto 0) => net_slot_0_axi_rdata(31 downto 0),
|
||||
m_slot_0_axi_rready => net_slot_0_axi_rready,
|
||||
m_slot_0_axi_rresp(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
|
||||
m_slot_0_axi_rvalid => net_slot_0_axi_rvalid,
|
||||
m_slot_0_axi_wdata(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
m_slot_0_axi_wready => net_slot_0_axi_wready,
|
||||
m_slot_0_axi_wstrb(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
m_slot_0_axi_wvalid => net_slot_0_axi_wvalid,
|
||||
m_slot_1_axis_tdata(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
|
||||
m_slot_1_axis_tlast => net_slot_1_axis_tlast,
|
||||
m_slot_1_axis_tready => net_slot_1_axis_tready,
|
||||
m_slot_1_axis_tvalid => net_slot_1_axis_tvalid,
|
||||
m_slot_2_axis_tdata(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
|
||||
m_slot_2_axis_tlast => net_slot_2_axis_tlast,
|
||||
m_slot_2_axis_tready => net_slot_2_axis_tready,
|
||||
m_slot_2_axis_tvalid => net_slot_2_axis_tvalid,
|
||||
slot_0_axi_araddr(31 downto 0) => Conn_ARADDR(31 downto 0),
|
||||
slot_0_axi_arprot(2 downto 0) => Conn_ARPROT(2 downto 0),
|
||||
slot_0_axi_arready => Conn_ARREADY,
|
||||
slot_0_axi_arvalid => Conn_ARVALID,
|
||||
slot_0_axi_awaddr(31 downto 0) => Conn_AWADDR(31 downto 0),
|
||||
slot_0_axi_awprot(2 downto 0) => Conn_AWPROT(2 downto 0),
|
||||
slot_0_axi_awready => Conn_AWREADY,
|
||||
slot_0_axi_awvalid => Conn_AWVALID,
|
||||
slot_0_axi_bready => Conn_BREADY,
|
||||
slot_0_axi_bresp(1 downto 0) => Conn_BRESP(1 downto 0),
|
||||
slot_0_axi_bvalid => Conn_BVALID,
|
||||
slot_0_axi_rdata(31 downto 0) => Conn_RDATA(31 downto 0),
|
||||
slot_0_axi_rready => Conn_RREADY,
|
||||
slot_0_axi_rresp(1 downto 0) => Conn_RRESP(1 downto 0),
|
||||
slot_0_axi_rvalid => Conn_RVALID,
|
||||
slot_0_axi_wdata(31 downto 0) => Conn_WDATA(31 downto 0),
|
||||
slot_0_axi_wready => Conn_WREADY,
|
||||
slot_0_axi_wstrb(3 downto 0) => Conn_WSTRB(3 downto 0),
|
||||
slot_0_axi_wvalid => Conn_WVALID,
|
||||
slot_1_axis_tdata(15 downto 0) => Conn1_TDATA(15 downto 0),
|
||||
slot_1_axis_tlast => Conn1_TLAST,
|
||||
slot_1_axis_tready => Conn1_TREADY,
|
||||
slot_1_axis_tvalid => Conn1_TVALID,
|
||||
slot_2_axis_tdata(15 downto 0) => Conn2_TDATA(15 downto 0),
|
||||
slot_2_axis_tlast => Conn2_TLAST,
|
||||
slot_2_axis_tready => Conn2_TREADY,
|
||||
slot_2_axis_tvalid => Conn2_TVALID
|
||||
);
|
||||
ila_lib: component bd_f60c_ila_lib_0
|
||||
port map (
|
||||
clk => clk_1,
|
||||
probe0(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
probe1(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
|
||||
probe10(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
|
||||
probe11(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
probe12(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
probe13(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
|
||||
probe14(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
|
||||
probe15(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
|
||||
probe16(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe17(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
|
||||
probe18(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
|
||||
probe19(0) => net_slot_1_axis_tvalid,
|
||||
probe2(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
|
||||
probe20(0) => net_slot_1_axis_tready,
|
||||
probe21(0) => net_slot_1_axis_tlast,
|
||||
probe22(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
|
||||
probe23(0) => net_slot_2_axis_tvalid,
|
||||
probe24(0) => net_slot_2_axis_tready,
|
||||
probe25(0) => net_slot_2_axis_tlast,
|
||||
probe3(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
probe4(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
|
||||
probe5(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
|
||||
probe6(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
probe7(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
probe8(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
probe9(31 downto 0) => net_slot_0_axi_rdata(31 downto 0)
|
||||
);
|
||||
slot_0_ar: component bd_f60c_slot_0_ar_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_arvalid,
|
||||
In1(0) => net_slot_0_axi_arready,
|
||||
dout(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_aw: component bd_f60c_slot_0_aw_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_awvalid,
|
||||
In1(0) => net_slot_0_axi_awready,
|
||||
dout(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_b: component bd_f60c_slot_0_b_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_bvalid,
|
||||
In1(0) => net_slot_0_axi_bready,
|
||||
dout(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_r: component bd_f60c_slot_0_r_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_rvalid,
|
||||
In1(0) => net_slot_0_axi_rready,
|
||||
dout(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_w: component bd_f60c_slot_0_w_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_wvalid,
|
||||
In1(0) => net_slot_0_axi_wready,
|
||||
dout(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
+435
@@ -0,0 +1,435 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Command: generate_target bd_f60c.bd
|
||||
--Design : bd_f60c
|
||||
--Purpose: IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity bd_f60c is
|
||||
port (
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
|
||||
end bd_f60c;
|
||||
|
||||
architecture STRUCTURE of bd_f60c is
|
||||
component bd_f60c_ila_lib_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end component bd_f60c_ila_lib_0;
|
||||
component bd_f60c_g_inst_0 is
|
||||
port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
m_slot_0_axi_b_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_r_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_aw_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_ar_cnt : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
slot_0_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
slot_0_axi_awvalid : in STD_LOGIC;
|
||||
slot_0_axi_awready : in STD_LOGIC;
|
||||
slot_0_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
slot_0_axi_wvalid : in STD_LOGIC;
|
||||
slot_0_axi_wready : in STD_LOGIC;
|
||||
slot_0_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
slot_0_axi_bvalid : in STD_LOGIC;
|
||||
slot_0_axi_bready : in STD_LOGIC;
|
||||
slot_0_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
slot_0_axi_arvalid : in STD_LOGIC;
|
||||
slot_0_axi_arready : in STD_LOGIC;
|
||||
slot_0_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
slot_0_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
slot_0_axi_rvalid : in STD_LOGIC;
|
||||
slot_0_axi_rready : in STD_LOGIC;
|
||||
slot_1_axis_tvalid : in STD_LOGIC;
|
||||
slot_1_axis_tready : in STD_LOGIC;
|
||||
slot_1_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
slot_1_axis_tlast : in STD_LOGIC;
|
||||
slot_2_axis_tvalid : in STD_LOGIC;
|
||||
slot_2_axis_tready : in STD_LOGIC;
|
||||
slot_2_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
slot_2_axis_tlast : in STD_LOGIC;
|
||||
m_slot_0_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_slot_0_axi_awvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_awready : out STD_LOGIC;
|
||||
m_slot_0_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_slot_0_axi_wvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_wready : out STD_LOGIC;
|
||||
m_slot_0_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_bvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_bready : out STD_LOGIC;
|
||||
m_slot_0_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_slot_0_axi_arvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_arready : out STD_LOGIC;
|
||||
m_slot_0_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_slot_0_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_slot_0_axi_rvalid : out STD_LOGIC;
|
||||
m_slot_0_axi_rready : out STD_LOGIC;
|
||||
m_slot_1_axis_tvalid : out STD_LOGIC;
|
||||
m_slot_1_axis_tready : out STD_LOGIC;
|
||||
m_slot_1_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_slot_1_axis_tlast : out STD_LOGIC;
|
||||
m_slot_2_axis_tvalid : out STD_LOGIC;
|
||||
m_slot_2_axis_tready : out STD_LOGIC;
|
||||
m_slot_2_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_slot_2_axis_tlast : out STD_LOGIC
|
||||
);
|
||||
end component bd_f60c_g_inst_0;
|
||||
component bd_f60c_slot_0_aw_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_aw_0;
|
||||
component bd_f60c_slot_0_w_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_w_0;
|
||||
component bd_f60c_slot_0_b_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_b_0;
|
||||
component bd_f60c_slot_0_ar_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_ar_0;
|
||||
component bd_f60c_slot_0_r_0 is
|
||||
port (
|
||||
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component bd_f60c_slot_0_r_0;
|
||||
signal Conn1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal Conn1_TLAST : STD_LOGIC;
|
||||
signal Conn1_TREADY : STD_LOGIC;
|
||||
signal Conn1_TVALID : STD_LOGIC;
|
||||
signal Conn2_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal Conn2_TLAST : STD_LOGIC;
|
||||
signal Conn2_TREADY : STD_LOGIC;
|
||||
signal Conn2_TVALID : STD_LOGIC;
|
||||
signal Conn_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_ARREADY : STD_LOGIC;
|
||||
signal Conn_ARVALID : STD_LOGIC;
|
||||
signal Conn_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal Conn_AWREADY : STD_LOGIC;
|
||||
signal Conn_AWVALID : STD_LOGIC;
|
||||
signal Conn_BREADY : STD_LOGIC;
|
||||
signal Conn_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_BVALID : STD_LOGIC;
|
||||
signal Conn_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_RREADY : STD_LOGIC;
|
||||
signal Conn_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal Conn_RVALID : STD_LOGIC;
|
||||
signal Conn_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal Conn_WREADY : STD_LOGIC;
|
||||
signal Conn_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal Conn_WVALID : STD_LOGIC;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal net_slot_0_axi_ar_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_ar_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal net_slot_0_axi_arready : STD_LOGIC;
|
||||
signal net_slot_0_axi_arvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_aw_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_aw_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal net_slot_0_axi_awready : STD_LOGIC;
|
||||
signal net_slot_0_axi_awvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_b_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_b_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_bready : STD_LOGIC;
|
||||
signal net_slot_0_axi_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_bvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_r_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_r_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_rready : STD_LOGIC;
|
||||
signal net_slot_0_axi_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_rvalid : STD_LOGIC;
|
||||
signal net_slot_0_axi_w_ctrl : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal net_slot_0_axi_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal net_slot_0_axi_wready : STD_LOGIC;
|
||||
signal net_slot_0_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal net_slot_0_axi_wvalid : STD_LOGIC;
|
||||
signal net_slot_1_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal net_slot_1_axis_tlast : STD_LOGIC;
|
||||
signal net_slot_1_axis_tready : STD_LOGIC;
|
||||
signal net_slot_1_axis_tvalid : STD_LOGIC;
|
||||
signal net_slot_2_axis_tdata : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
signal net_slot_2_axis_tlast : STD_LOGIC;
|
||||
signal net_slot_2_axis_tready : STD_LOGIC;
|
||||
signal net_slot_2_axis_tvalid : STD_LOGIC;
|
||||
signal resetn_1 : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tlast : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tready : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tvalid : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
|
||||
attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
|
||||
attribute X_INTERFACE_PARAMETER : string;
|
||||
attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
|
||||
attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
|
||||
attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
|
||||
attribute X_INTERFACE_PARAMETER of SLOT_0_AXI_araddr : signal is "XIL_INTERFACENAME SLOT_0_AXI, ADDR_WIDTH 32, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN bd_f60c_clk, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.0, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
|
||||
attribute X_INTERFACE_INFO of SLOT_0_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
|
||||
attribute X_INTERFACE_INFO of SLOT_1_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of SLOT_1_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
attribute X_INTERFACE_INFO of SLOT_2_AXIS_tdata : signal is "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
|
||||
attribute X_INTERFACE_PARAMETER of SLOT_2_AXIS_tdata : signal is "XIL_INTERFACENAME SLOT_2_AXIS, CLK_DOMAIN bd_f60c_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
|
||||
begin
|
||||
Conn1_TDATA(15 downto 0) <= SLOT_1_AXIS_tdata(15 downto 0);
|
||||
Conn1_TLAST <= SLOT_1_AXIS_tlast;
|
||||
Conn1_TREADY <= SLOT_1_AXIS_tready;
|
||||
Conn1_TVALID <= SLOT_1_AXIS_tvalid;
|
||||
Conn2_TDATA(15 downto 0) <= SLOT_2_AXIS_tdata(15 downto 0);
|
||||
Conn2_TLAST <= SLOT_2_AXIS_tlast;
|
||||
Conn2_TREADY <= SLOT_2_AXIS_tready;
|
||||
Conn2_TVALID <= SLOT_2_AXIS_tvalid;
|
||||
Conn_ARADDR(31 downto 0) <= SLOT_0_AXI_araddr(31 downto 0);
|
||||
Conn_ARPROT(2 downto 0) <= SLOT_0_AXI_arprot(2 downto 0);
|
||||
Conn_ARREADY <= SLOT_0_AXI_arready;
|
||||
Conn_ARVALID <= SLOT_0_AXI_arvalid;
|
||||
Conn_AWADDR(31 downto 0) <= SLOT_0_AXI_awaddr(31 downto 0);
|
||||
Conn_AWPROT(2 downto 0) <= SLOT_0_AXI_awprot(2 downto 0);
|
||||
Conn_AWREADY <= SLOT_0_AXI_awready;
|
||||
Conn_AWVALID <= SLOT_0_AXI_awvalid;
|
||||
Conn_BREADY <= SLOT_0_AXI_bready;
|
||||
Conn_BRESP(1 downto 0) <= SLOT_0_AXI_bresp(1 downto 0);
|
||||
Conn_BVALID <= SLOT_0_AXI_bvalid;
|
||||
Conn_RDATA(31 downto 0) <= SLOT_0_AXI_rdata(31 downto 0);
|
||||
Conn_RREADY <= SLOT_0_AXI_rready;
|
||||
Conn_RRESP(1 downto 0) <= SLOT_0_AXI_rresp(1 downto 0);
|
||||
Conn_RVALID <= SLOT_0_AXI_rvalid;
|
||||
Conn_WDATA(31 downto 0) <= SLOT_0_AXI_wdata(31 downto 0);
|
||||
Conn_WREADY <= SLOT_0_AXI_wready;
|
||||
Conn_WSTRB(3 downto 0) <= SLOT_0_AXI_wstrb(3 downto 0);
|
||||
Conn_WVALID <= SLOT_0_AXI_wvalid;
|
||||
clk_1 <= clk;
|
||||
resetn_1 <= resetn;
|
||||
g_inst: component bd_f60c_g_inst_0
|
||||
port map (
|
||||
aclk => clk_1,
|
||||
aresetn => resetn_1,
|
||||
m_slot_0_axi_ar_cnt(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
m_slot_0_axi_araddr(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
|
||||
m_slot_0_axi_arprot(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
|
||||
m_slot_0_axi_arready => net_slot_0_axi_arready,
|
||||
m_slot_0_axi_arvalid => net_slot_0_axi_arvalid,
|
||||
m_slot_0_axi_aw_cnt(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
m_slot_0_axi_awaddr(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
|
||||
m_slot_0_axi_awprot(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
|
||||
m_slot_0_axi_awready => net_slot_0_axi_awready,
|
||||
m_slot_0_axi_awvalid => net_slot_0_axi_awvalid,
|
||||
m_slot_0_axi_b_cnt(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
m_slot_0_axi_bready => net_slot_0_axi_bready,
|
||||
m_slot_0_axi_bresp(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
m_slot_0_axi_bvalid => net_slot_0_axi_bvalid,
|
||||
m_slot_0_axi_r_cnt(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
m_slot_0_axi_rdata(31 downto 0) => net_slot_0_axi_rdata(31 downto 0),
|
||||
m_slot_0_axi_rready => net_slot_0_axi_rready,
|
||||
m_slot_0_axi_rresp(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
|
||||
m_slot_0_axi_rvalid => net_slot_0_axi_rvalid,
|
||||
m_slot_0_axi_wdata(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
m_slot_0_axi_wready => net_slot_0_axi_wready,
|
||||
m_slot_0_axi_wstrb(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
m_slot_0_axi_wvalid => net_slot_0_axi_wvalid,
|
||||
m_slot_1_axis_tdata(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
|
||||
m_slot_1_axis_tlast => net_slot_1_axis_tlast,
|
||||
m_slot_1_axis_tready => net_slot_1_axis_tready,
|
||||
m_slot_1_axis_tvalid => net_slot_1_axis_tvalid,
|
||||
m_slot_2_axis_tdata(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
|
||||
m_slot_2_axis_tlast => net_slot_2_axis_tlast,
|
||||
m_slot_2_axis_tready => net_slot_2_axis_tready,
|
||||
m_slot_2_axis_tvalid => net_slot_2_axis_tvalid,
|
||||
slot_0_axi_araddr(31 downto 0) => Conn_ARADDR(31 downto 0),
|
||||
slot_0_axi_arprot(2 downto 0) => Conn_ARPROT(2 downto 0),
|
||||
slot_0_axi_arready => Conn_ARREADY,
|
||||
slot_0_axi_arvalid => Conn_ARVALID,
|
||||
slot_0_axi_awaddr(31 downto 0) => Conn_AWADDR(31 downto 0),
|
||||
slot_0_axi_awprot(2 downto 0) => Conn_AWPROT(2 downto 0),
|
||||
slot_0_axi_awready => Conn_AWREADY,
|
||||
slot_0_axi_awvalid => Conn_AWVALID,
|
||||
slot_0_axi_bready => Conn_BREADY,
|
||||
slot_0_axi_bresp(1 downto 0) => Conn_BRESP(1 downto 0),
|
||||
slot_0_axi_bvalid => Conn_BVALID,
|
||||
slot_0_axi_rdata(31 downto 0) => Conn_RDATA(31 downto 0),
|
||||
slot_0_axi_rready => Conn_RREADY,
|
||||
slot_0_axi_rresp(1 downto 0) => Conn_RRESP(1 downto 0),
|
||||
slot_0_axi_rvalid => Conn_RVALID,
|
||||
slot_0_axi_wdata(31 downto 0) => Conn_WDATA(31 downto 0),
|
||||
slot_0_axi_wready => Conn_WREADY,
|
||||
slot_0_axi_wstrb(3 downto 0) => Conn_WSTRB(3 downto 0),
|
||||
slot_0_axi_wvalid => Conn_WVALID,
|
||||
slot_1_axis_tdata(15 downto 0) => Conn1_TDATA(15 downto 0),
|
||||
slot_1_axis_tlast => Conn1_TLAST,
|
||||
slot_1_axis_tready => Conn1_TREADY,
|
||||
slot_1_axis_tvalid => Conn1_TVALID,
|
||||
slot_2_axis_tdata(15 downto 0) => Conn2_TDATA(15 downto 0),
|
||||
slot_2_axis_tlast => Conn2_TLAST,
|
||||
slot_2_axis_tready => Conn2_TREADY,
|
||||
slot_2_axis_tvalid => Conn2_TVALID
|
||||
);
|
||||
ila_lib: component bd_f60c_ila_lib_0
|
||||
port map (
|
||||
clk => clk_1,
|
||||
probe0(1 downto 0) => net_slot_0_axi_ar_cnt(1 downto 0),
|
||||
probe1(31 downto 0) => net_slot_0_axi_araddr(31 downto 0),
|
||||
probe10(1 downto 0) => net_slot_0_axi_rresp(1 downto 0),
|
||||
probe11(31 downto 0) => net_slot_0_axi_wdata(31 downto 0),
|
||||
probe12(3 downto 0) => net_slot_0_axi_wstrb(3 downto 0),
|
||||
probe13(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0),
|
||||
probe14(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0),
|
||||
probe15(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0),
|
||||
probe16(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0),
|
||||
probe17(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0),
|
||||
probe18(15 downto 0) => net_slot_1_axis_tdata(15 downto 0),
|
||||
probe19(0) => net_slot_1_axis_tvalid,
|
||||
probe2(2 downto 0) => net_slot_0_axi_arprot(2 downto 0),
|
||||
probe20(0) => net_slot_1_axis_tready,
|
||||
probe21(0) => net_slot_1_axis_tlast,
|
||||
probe22(15 downto 0) => net_slot_2_axis_tdata(15 downto 0),
|
||||
probe23(0) => net_slot_2_axis_tvalid,
|
||||
probe24(0) => net_slot_2_axis_tready,
|
||||
probe25(0) => net_slot_2_axis_tlast,
|
||||
probe3(1 downto 0) => net_slot_0_axi_aw_cnt(1 downto 0),
|
||||
probe4(31 downto 0) => net_slot_0_axi_awaddr(31 downto 0),
|
||||
probe5(2 downto 0) => net_slot_0_axi_awprot(2 downto 0),
|
||||
probe6(1 downto 0) => net_slot_0_axi_b_cnt(1 downto 0),
|
||||
probe7(1 downto 0) => net_slot_0_axi_bresp(1 downto 0),
|
||||
probe8(1 downto 0) => net_slot_0_axi_r_cnt(1 downto 0),
|
||||
probe9(31 downto 0) => net_slot_0_axi_rdata(31 downto 0)
|
||||
);
|
||||
slot_0_ar: component bd_f60c_slot_0_ar_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_arvalid,
|
||||
In1(0) => net_slot_0_axi_arready,
|
||||
dout(1 downto 0) => net_slot_0_axi_ar_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_aw: component bd_f60c_slot_0_aw_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_awvalid,
|
||||
In1(0) => net_slot_0_axi_awready,
|
||||
dout(1 downto 0) => net_slot_0_axi_aw_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_b: component bd_f60c_slot_0_b_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_bvalid,
|
||||
In1(0) => net_slot_0_axi_bready,
|
||||
dout(1 downto 0) => net_slot_0_axi_b_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_r: component bd_f60c_slot_0_r_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_rvalid,
|
||||
In1(0) => net_slot_0_axi_rready,
|
||||
dout(1 downto 0) => net_slot_0_axi_r_ctrl(1 downto 0)
|
||||
);
|
||||
slot_0_w: component bd_f60c_slot_0_w_0
|
||||
port map (
|
||||
In0(0) => net_slot_0_axi_wvalid,
|
||||
In1(0) => net_slot_0_axi_wready,
|
||||
dout(1 downto 0) => net_slot_0_axi_w_ctrl(1 downto 0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
BIN
Binary file not shown.
+37115
File diff suppressed because it is too large
Load Diff
+196
@@ -0,0 +1,196 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:system_ila:1.1
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_system_ila_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_wvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_bvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_rvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rready : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_1_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_2_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC
|
||||
);
|
||||
END design_1_system_ila_0_0;
|
||||
|
||||
ARCHITECTURE design_1_system_ila_0_0_arch OF design_1_system_ila_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT bd_f60c IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_wvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_bvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_rvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rready : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_1_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_2_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT bd_f60c;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_0_AXI_awaddr: SIGNAL IS "XIL_INTERFACENAME SLOT_0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, R" &
|
||||
"USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_1_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_1_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_2_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_2_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME RST.resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.resetn RST";
|
||||
BEGIN
|
||||
U0 : bd_f60c
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
SLOT_0_AXI_awaddr => SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_wdata => SLOT_0_AXI_wdata,
|
||||
SLOT_0_AXI_wstrb => SLOT_0_AXI_wstrb,
|
||||
SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
|
||||
SLOT_0_AXI_wready => SLOT_0_AXI_wready,
|
||||
SLOT_0_AXI_bresp => SLOT_0_AXI_bresp,
|
||||
SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
|
||||
SLOT_0_AXI_bready => SLOT_0_AXI_bready,
|
||||
SLOT_0_AXI_araddr => SLOT_0_AXI_araddr,
|
||||
SLOT_0_AXI_arprot => SLOT_0_AXI_arprot,
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_rdata => SLOT_0_AXI_rdata,
|
||||
SLOT_0_AXI_rresp => SLOT_0_AXI_rresp,
|
||||
SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
|
||||
SLOT_0_AXI_rready => SLOT_0_AXI_rready,
|
||||
SLOT_1_AXIS_tdata => SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
|
||||
SLOT_2_AXIS_tdata => SLOT_2_AXIS_tdata,
|
||||
SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
|
||||
SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
|
||||
SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
|
||||
resetn => resetn
|
||||
);
|
||||
END design_1_system_ila_0_0_arch;
|
||||
+1280
File diff suppressed because it is too large
Load Diff
+166
@@ -0,0 +1,166 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:zybo_audio:1.0
|
||||
-- IP Revision: 22
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_zybo_audio_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END design_1_zybo_audio_0_0;
|
||||
|
||||
ARCHITECTURE design_1_zybo_audio_0_0_arch OF design_1_zybo_audio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT zybo_audio IS
|
||||
GENERIC (
|
||||
MIC_IN : INTEGER;
|
||||
I2C_CLKDIV : INTEGER;
|
||||
I2S_CLKDIV : INTEGER;
|
||||
HAS_RESET_PIN : BOOLEAN;
|
||||
SRR_70 : STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT zybo_audio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_pb_data: SIGNAL IS "XIL_INTERFACENAME axis_pb, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_rec_data: SIGNAL IS "XIL_INTERFACENAME axis_rec, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF axis_rec:axis_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
BEGIN
|
||||
U0 : zybo_audio
|
||||
GENERIC MAP (
|
||||
MIC_IN => 0,
|
||||
I2C_CLKDIV => 9999,
|
||||
I2S_CLKDIV => 4,
|
||||
HAS_RESET_PIN => false,
|
||||
SRR_70 => B"00000000"
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => '1',
|
||||
axis_pb_data => axis_pb_data,
|
||||
axis_pb_valid => axis_pb_valid,
|
||||
axis_pb_ready => axis_pb_ready,
|
||||
axis_rec_data => axis_rec_data,
|
||||
axis_rec_valid => axis_rec_valid,
|
||||
axis_rec_ready => axis_rec_ready,
|
||||
mute => mute,
|
||||
mclk => mclk,
|
||||
bclk => bclk,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc,
|
||||
scl_i => scl_i,
|
||||
scl_o => scl_o,
|
||||
scl_t => scl_t,
|
||||
sda_i => sda_i,
|
||||
sda_o => sda_o,
|
||||
sda_t => sda_t
|
||||
);
|
||||
END design_1_zybo_audio_0_0_arch;
|
||||
+51
@@ -0,0 +1,51 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- AXI Stream Audio Mono to Stereo
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
|
||||
entity axis_audio_mono2stereo is
|
||||
generic
|
||||
(
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(15 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_audio_mono2stereo is
|
||||
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY;
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
|
||||
M_AXIS_TDATA (31 downto 16) <= S_AXIS_TDATA;
|
||||
M_AXIS_TDATA (15 downto 0) <= S_AXIS_TDATA;
|
||||
|
||||
end;
|
||||
+1041
File diff suppressed because it is too large
Load Diff
+147
@@ -0,0 +1,147 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2c_transmitter is
|
||||
generic(
|
||||
AW : positive := 8;
|
||||
I2C_CLKDIV : positive := 9999
|
||||
);
|
||||
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic;
|
||||
data : in std_logic_vector ( 11 downto 0);
|
||||
addr : out std_logic_vector (AW-1 downto 0);
|
||||
done : out std_logic:='0';
|
||||
scl_i : in std_logic;
|
||||
scl_o : out std_logic:='1';
|
||||
scl_t : out std_logic:='1';
|
||||
sda_i : in std_logic;
|
||||
sda_o : out std_logic:='1';
|
||||
sda_t : out std_logic:='1'
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of i2c_transmitter is
|
||||
|
||||
signal nextstep : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- clock divider
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
variable cnt : unsigned(31 downto 0) := (others=>'0');
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if resetn='0' then
|
||||
nextstep <= '0';
|
||||
cnt := (others=>'0');
|
||||
else
|
||||
nextstep <= '0';
|
||||
if cnt = to_unsigned(I2C_CLKDIV,32) then
|
||||
nextstep <= '1';
|
||||
cnt := (others=>'0');
|
||||
else
|
||||
cnt := cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- transmitter core
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
type state_type is (IDLE, TRANSMIT, DEADEND);
|
||||
variable state : state_type;
|
||||
|
||||
constant NSTEPS : integer := 42;
|
||||
-- St D7 D6 D5 D4 D3 D2 D1 D0 ACK Sp
|
||||
variable sclbuffer : std_logic_vector (0 to NSTEPS-1) := "110011001100110011001100110011001100110011";
|
||||
variable sdabuffer : std_logic_vector (0 to NSTEPS-1) := "100111100001111000011110000111100001111001";
|
||||
|
||||
variable stepcnt : unsigned( 5 downto 0) := (others=>'0');
|
||||
variable addrcnt : unsigned(AW-1 downto 0) := (others=>'0');
|
||||
|
||||
variable startcond : std_logic;
|
||||
variable stopcond : std_logic;
|
||||
variable finished : std_logic;
|
||||
variable restart : std_logic;
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
if resetn='0' then
|
||||
done <= '0';
|
||||
state := IDLE;
|
||||
addrcnt := (others=>'0');
|
||||
else
|
||||
addr <= std_logic_vector(addrcnt);
|
||||
sda_o <= '0';
|
||||
sda_t <= '1';
|
||||
scl_o <= '0';
|
||||
scl_t <= '1';
|
||||
case state is
|
||||
when IDLE =>
|
||||
done <= '0';
|
||||
if nextstep = '1' then
|
||||
stepcnt := (others=>'0');
|
||||
|
||||
startcond := data(11); -- 1 = send start condition
|
||||
stopcond := data(10); -- 1 = send stop condition
|
||||
finished := data( 9); -- 1 = stop fsm after sending current byte
|
||||
restart := data( 8); -- 1 = restart transfer sequence from address 0 ELSE stop FSM
|
||||
for i in 0 to 7 loop
|
||||
sdabuffer(3+4*i to 6+4*i) := (others=>data(7-i));
|
||||
end loop;
|
||||
sdabuffer( 1 to 2) := (others=>not startcond);
|
||||
sdabuffer(NSTEPS-3 to NSTEPS-2) := (others=>not stopcond);
|
||||
sclbuffer(NSTEPS-4 to NSTEPS-3) := (others=>not stopcond);
|
||||
|
||||
state := TRANSMIT;
|
||||
end if;
|
||||
|
||||
|
||||
when TRANSMIT =>
|
||||
done <= '0'; -- default assignment
|
||||
if sclbuffer(to_integer(stepcnt)) = '0' then
|
||||
scl_t <= '0';
|
||||
else
|
||||
scl_t <= '1';
|
||||
end if;
|
||||
if sdabuffer(to_integer(stepcnt)) = '0' then
|
||||
sda_t <= '0';
|
||||
else
|
||||
sda_t <= '1';
|
||||
end if;
|
||||
|
||||
if nextstep = '1' then
|
||||
if stepcnt = NSTEPS-1 then -- byte finished ?
|
||||
stepcnt := (others=>'0');
|
||||
if finished = '0' then -- sequence of I2C commands finished?
|
||||
addrcnt:= addrcnt + 1;
|
||||
state := IDLE;
|
||||
elsif restart = '1' then -- restart (send again) ?
|
||||
addrcnt:= (others=>'0');
|
||||
state := IDLE;
|
||||
else
|
||||
state := DEADEND;
|
||||
end if;
|
||||
else
|
||||
stepcnt := stepcnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when DEADEND => -- this is the point of no return
|
||||
done <= '1';
|
||||
sda_t <= '1';
|
||||
scl_t <= '1';
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
+135
@@ -0,0 +1,135 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2s_transceiver is
|
||||
generic(
|
||||
I2S_CLKDIV : natural := 4 -- fs = sysclk / 512 / (clkdiv+1)
|
||||
);
|
||||
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic;
|
||||
i2c_done : in std_logic;
|
||||
|
||||
axis_pb_data : in std_logic_vector (31 downto 0);
|
||||
axis_pb_valid : in std_logic;
|
||||
axis_pb_ready : out std_logic;
|
||||
|
||||
axis_rec_data : out std_logic_vector (31 downto 0);
|
||||
axis_rec_valid : out std_logic;
|
||||
axis_rec_ready : in std_logic;
|
||||
|
||||
mclk : out std_logic;
|
||||
mute : out std_logic;
|
||||
|
||||
bclk : out std_logic;
|
||||
pb_dat : out std_logic;
|
||||
pb_lrc : out std_logic;
|
||||
rec_dat : in std_logic;
|
||||
rec_lrc : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of i2s_transceiver is
|
||||
|
||||
signal mclk_s : std_logic := '0';
|
||||
signal bclk_s : std_logic := '0';
|
||||
signal bclk_period_s : unsigned(5 downto 0) := (others=>'0');
|
||||
|
||||
begin
|
||||
|
||||
mute <= i2c_done;
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- mclk / bclk generation
|
||||
-- mclk = sysclk / 2 / (clkdiv+1) = 256*fs
|
||||
-- bclk = mclk / 4 = 64 * fs
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
variable mcnt : unsigned(7 downto 0) := (others=>'0');
|
||||
variable bcnt : unsigned(1 downto 0) := (others=>'0');
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
if resetn='0' or i2c_done = '0' then
|
||||
mcnt := (others=>'0');
|
||||
mclk_s <= '0';
|
||||
bclk_s <= '0';
|
||||
bclk_period_s <= (others=>'0');
|
||||
else
|
||||
if mcnt = to_unsigned(I2S_CLKDIV,8) then
|
||||
mclk_s <= not mclk_s;
|
||||
if bcnt = "11" then
|
||||
if (bclk_s = '1') then
|
||||
bclk_period_s <= bclk_period_s + 1;
|
||||
end if;
|
||||
bclk_s <= not bclk_s;
|
||||
end if;
|
||||
mcnt := (others=>'0');
|
||||
bcnt := bcnt + 1;
|
||||
else
|
||||
mcnt := mcnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- data transmission
|
||||
-----------------------------------------------------------------
|
||||
process
|
||||
variable pb_buffer : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable rec_buffer : std_logic_vector(31 downto 0) := (others=>'0');
|
||||
variable bclk_period_i : integer;
|
||||
variable pb_buff_loaded : boolean := false;
|
||||
variable rec_buff_transmitted : boolean := false;
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
|
||||
bclk_period_i := to_integer(bclk_period_s);
|
||||
|
||||
if resetn='0' or i2c_done = '0' then
|
||||
axis_rec_data <=(others =>'0');
|
||||
axis_rec_valid <= '0';
|
||||
axis_pb_ready <= '0';
|
||||
pb_dat <= '0';
|
||||
pb_lrc <= '0';
|
||||
rec_lrc <= '0';
|
||||
else
|
||||
axis_pb_ready <= '0';
|
||||
if axis_rec_ready = '1' then -- keep valid until data has been consumed (if ready is not asserted in time, data will be lost)
|
||||
axis_rec_valid <= '0';
|
||||
end if;
|
||||
pb_dat <= '0';
|
||||
if bclk_period_i = 0 and not pb_buff_loaded then
|
||||
pb_buff_loaded := true;
|
||||
rec_buff_transmitted := false;
|
||||
pb_buffer := axis_pb_data;
|
||||
axis_pb_ready <= '1';
|
||||
elsif bclk_period_i >= 1 and bclk_period_i <= 16 then
|
||||
pb_buff_loaded := false;
|
||||
pb_dat <= pb_buffer(32-bclk_period_i);
|
||||
if bclk_s = '1' then
|
||||
rec_buffer(32-bclk_period_i) := rec_dat;
|
||||
end if ;
|
||||
elsif bclk_period_i >= 33 and bclk_period_i <= 48 then
|
||||
pb_dat <= pb_buffer(48-bclk_period_i);
|
||||
if bclk_s = '1' then
|
||||
rec_buffer(48-bclk_period_i) := rec_dat;
|
||||
end if ;
|
||||
elsif bclk_period_i = 63 and not rec_buff_transmitted then
|
||||
rec_buff_transmitted := true;
|
||||
axis_rec_data <= rec_buffer;
|
||||
axis_rec_valid <= '1';
|
||||
end if;
|
||||
|
||||
pb_lrc <= not bclk_period_s(5);
|
||||
rec_lrc <= not bclk_period_s(5);
|
||||
end if;
|
||||
|
||||
mclk <= mclk_s;
|
||||
bclk <= bclk_s;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- This IP supports standalone audio without CPU intervention on ZyBO-Boards
|
||||
------------------------------------------------------------------------------
|
||||
-- Output/input data is delivered as AXI-Stream
|
||||
-- Initially (or after reset) the ZyBo Audio Codec is programmed via I2C
|
||||
-- The I2C sequence is defined by the "ROM" contents
|
||||
-- After programming is finished Audio Data is delivered via AXIS interfaces
|
||||
-- Audio Stream Data is 32 bits wide => [31:16] right channel [15:0] left channel
|
||||
|
||||
-- Master Clock and Bit Clock for the Audio Codec are derived from internal clock dividers
|
||||
-- Clock division is controlled by Generics (see comments below)
|
||||
|
||||
-- OOC synthesis is setup for a clk frequency of 125 MHz -> see contraints file
|
||||
|
||||
-- Prof. Dr.-Ing W. Gehrke, 06/2020
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
------------------------
|
||||
-- entity section
|
||||
------------------------
|
||||
|
||||
entity zybo_audio is
|
||||
generic (
|
||||
HAS_RESET_PIN : boolean := false; -- use reset pin?
|
||||
MIC_IN : natural := 0; -- 0 => Line In Input, 1=> Mic input
|
||||
SRR_70 : std_logic_vector(7 downto 0) := "00000000"; -- sample rate register [7:0]
|
||||
I2C_CLKDIV : positive := 9999; -- SCL = clk / 4 / (I2C_CLKDIV+1)
|
||||
I2S_CLKDIV : natural := 4 -- mclk = clk / 2 / (I2S_CLKDIV+1)
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
resetn : in std_logic := '1'; -- reset can be left unconnected
|
||||
|
||||
-- AXIS playback data
|
||||
axis_pb_data : in std_logic_vector (31 downto 0);
|
||||
axis_pb_valid : in std_logic; -- ignored! (added for compatibility), we assume that sender can deliver data when needed
|
||||
axis_pb_ready : out std_logic;
|
||||
|
||||
-- AXIS record data
|
||||
axis_rec_data : out std_logic_vector (31 downto 0);
|
||||
axis_rec_valid : out std_logic;
|
||||
axis_rec_ready : in std_logic; -- ignored! (added for compatibility), we assume data sink can receive data when needed
|
||||
|
||||
-- Audio Codec Connections
|
||||
mute : out std_logic; -- active low mute
|
||||
mclk : out std_logic; -- master clock, 256*fs
|
||||
bclk : out std_logic; -- I2S bit clock, 64 * fs
|
||||
pb_dat : out std_logic; -- I2S playback data (out)
|
||||
pb_lrc : out std_logic; -- I2S playback channel select
|
||||
rec_dat : in std_logic; -- I2S record data (in)
|
||||
rec_lrc : out std_logic; -- I2S record channel select
|
||||
|
||||
-- I2C Control for Audio Codec on ZyBo Board (SSM2603) -- insertion of Tristate-IO-Buffer is handled by Vivado
|
||||
scl_i : in std_logic;
|
||||
scl_o : out std_logic:='1';
|
||||
scl_t : out std_logic:='1';
|
||||
sda_i : in std_logic;
|
||||
sda_o : out std_logic:='1';
|
||||
sda_t : out std_logic:='1'
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
------------------------
|
||||
-- architecture section
|
||||
------------------------
|
||||
|
||||
architecture rtl of zybo_audio is
|
||||
constant I2C_ROM_ADDR_WIDTH : positive := 8; -- 8 is a bit overdone ;-) -- but let's stick to the save side in case of future extensions
|
||||
|
||||
signal resetn_internal : std_logic;
|
||||
signal i2c_addr : std_logic_vector(I2C_ROM_ADDR_WIDTH-1 downto 0);
|
||||
signal i2c_data : std_logic_vector(11 downto 0);
|
||||
signal i2c_done : std_logic;
|
||||
|
||||
begin
|
||||
resetn_internal <= resetn when HAS_RESET_PIN else '1'; -- if reset used, reset feed through, else always 1
|
||||
|
||||
-- "ROM" containing I2C sequence for audio codec setup
|
||||
i2c_rom : entity work.zybo_audio_i2c_rom
|
||||
generic map(
|
||||
MIC_IN => MIC_IN,
|
||||
SRR_70 => SRR_70,
|
||||
AW => I2C_ROM_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
addr => i2c_addr, -- "ROM" addr
|
||||
dout => i2c_data -- 8 bit output data
|
||||
);
|
||||
|
||||
-- I2C Transmitter FSM
|
||||
i2c : entity work.i2c_transmitter
|
||||
generic map(
|
||||
AW => I2C_ROM_ADDR_WIDTH,
|
||||
I2C_CLKDIV => I2C_CLKDIV
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
resetn => resetn_internal,
|
||||
|
||||
-- Internal I2C data from "ROM"
|
||||
data => i2c_data, -- 8 bit output data
|
||||
addr => i2c_addr, -- "ROM" addr
|
||||
done => i2c_done, -- 1 if I2C sequence finished
|
||||
|
||||
-- I2C IO
|
||||
sda_i => sda_i, -- Input (not used)
|
||||
sda_o => sda_o, -- Output
|
||||
sda_t => sda_t, -- Tristate Enable (1=Tristate)
|
||||
scl_i => scl_i, -- Input (not used)
|
||||
scl_o => scl_o, -- Output
|
||||
scl_t => scl_t -- Tristate Enable (1=Tristate)
|
||||
);
|
||||
|
||||
-- I2S <-> AXIS Transceiver
|
||||
i2s : entity work.i2s_transceiver
|
||||
generic map(
|
||||
I2S_CLKDIV => I2S_CLKDIV -- fs = sysclk / 512 / (clkdiv+1)
|
||||
)
|
||||
port map(
|
||||
clk => clk,
|
||||
resetn => resetn_internal,
|
||||
i2c_done => i2c_done, -- 1= I2C Transmitter has finished transmission
|
||||
|
||||
-- Playback (Output) data
|
||||
axis_pb_data => axis_pb_data,
|
||||
axis_pb_valid => axis_pb_valid,
|
||||
axis_pb_ready => axis_pb_ready,
|
||||
|
||||
-- Record (Input) data
|
||||
axis_rec_data => axis_rec_data,
|
||||
axis_rec_valid => axis_rec_valid,
|
||||
axis_rec_ready => axis_rec_ready,
|
||||
|
||||
-- Connections to audio codec on Zybo Board (SSM2603)
|
||||
mclk => mclk,
|
||||
mute => mute,
|
||||
bclk => bclk,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc
|
||||
);
|
||||
|
||||
end;
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity zybo_audio_i2c_rom is
|
||||
generic(
|
||||
MIC_IN : natural := 0;
|
||||
SRR_70 : std_logic_vector(7 downto 0) := "00000000"; -- sample rate register [7:0]
|
||||
AW : positive := 8
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
dout : out std_logic_vector(11 downto 0) -- Data out
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of zybo_audio_i2c_rom is
|
||||
|
||||
constant R0_LEFT_ADC_VOL : std_logic_vector (6 downto 0) := "0000000";
|
||||
constant R1_RIGHT_ADC_VOL : std_logic_vector (6 downto 0) := "0000001";
|
||||
constant R2_LEFT_DAC_VOL : std_logic_vector (6 downto 0) := "0000010";
|
||||
constant R3_RIGHT_DAC_VOL : std_logic_vector (6 downto 0) := "0000011";
|
||||
constant R4_ANALOG_PATH : std_logic_vector (6 downto 0) := "0000100";
|
||||
constant R5_DIGITAL_PATH : std_logic_vector (6 downto 0) := "0000101";
|
||||
constant R6_POWER_MGMT : std_logic_vector (6 downto 0) := "0000110";
|
||||
constant R7_DIGITAL_IF : std_logic_vector (6 downto 0) := "0000111";
|
||||
constant R8_SAMPLE_RATE : std_logic_vector (6 downto 0) := "0001000";
|
||||
constant R9_ACTIVE : std_logic_vector (6 downto 0) := "0001001";
|
||||
constant R15_SOFTWARE_RESET : std_logic_vector (6 downto 0) := "0001111";
|
||||
constant R16_ALC_CONTROL_1 : std_logic_vector (6 downto 0) := "0010000";
|
||||
constant R17_ALC_CONTROL_2 : std_logic_vector (6 downto 0) := "0010001";
|
||||
constant R18_ALC_CONTROL_2 : std_logic_vector (6 downto 0) := "0010010";
|
||||
|
||||
constant USE_MIC_INPUT : std_logic_vector (0 downto 0) := std_logic_vector(to_unsigned(MIC_IN,1));
|
||||
constant MIC_MUTE : std_logic_vector (0 downto 0) := (others=>not USE_MIC_INPUT(0));
|
||||
|
||||
|
||||
constant i2c_addr : std_logic_vector(6 downto 0) := "0011010"; -- SSM2603 I2C address
|
||||
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(11 downto 0);
|
||||
signal mem : tmem := (
|
||||
"1000"&i2c_addr&"0" , "0000"&R9_ACTIVE &"0", "0100"&"00000001", -- Diese beiden I2C-Zugriffe von R.H. (06/20)
|
||||
"1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT &"0", "0100"&"00100000", -- In SW-Ansteuerung des Codecs läuft dieser nicht, wenn diese Zeilen fehlen (Erklärung unklar)
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- Praktische Tests zeigen, dass dies mit dieser Implementierung nicht der Fall ist
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- dennoch wird die beiden Zugriffe hier mit aufgenommen - schaden werden sie nicht
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- anschließend ein paar dummy Zugriffe als Delay
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
|
||||
"1000"&i2c_addr&"0" , "0000"&R15_SOFTWARE_RESET&"0","0100"&"00000000",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- dummy => approx. 1 ms delay @ 100 kHz SCL freq
|
||||
"1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT &"0", "0100"&"00110000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R0_LEFT_ADC_VOL &"0", "0100"&"00010111",
|
||||
"1000"&i2c_addr&"0" , "0000"&R1_RIGHT_ADC_VOL&"0", "0100"&"00010111",
|
||||
"1000"&i2c_addr&"0" , "0000"&R2_LEFT_DAC_VOL &"1", "0100"&"01111001",
|
||||
"1000"&i2c_addr&"0" , "0000"&R3_RIGHT_DAC_VOL&"1", "0100"&"01111001",
|
||||
"1000"&i2c_addr&"0" , "0000"&R4_ANALOG_PATH &"0", "0100"&"00000000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R5_DIGITAL_PATH &"0", "0100"&"00000000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R7_DIGITAL_IF &"0", "0100"&"00001010",
|
||||
"1000"&i2c_addr&"0" , "0000"&R8_SAMPLE_RATE &"0", "0100"&SRR_70,
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF",
|
||||
"0000"&x"FF","0000"&x"FF","0000"&x"FF", -- dummy => approx. 1 ms delay @ 100 kHz SCL freq
|
||||
"1000"&i2c_addr&"0" , "0000"&R9_ACTIVE &"0", "0100"&"00000001",
|
||||
"1000"&i2c_addr&"0" , "0000"&R6_POWER_MGMT &"0", "0100"&"00000000",
|
||||
"1000"&i2c_addr&"0" , "0000"&R4_ANALOG_PATH &"0", "0100"&"00010"&USE_MIC_INPUT&MIC_MUTE&"0",
|
||||
|
||||
others=>"0010"&x"FF");
|
||||
|
||||
begin
|
||||
process begin
|
||||
wait until rising_edge(clk);
|
||||
dout <= mem(to_integer(unsigned(addr)));
|
||||
end process;
|
||||
end;
|
||||
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- clk_rst_generator.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_rst_generator is
|
||||
generic
|
||||
(
|
||||
CLOCK_PERIOD : integer := 10000;
|
||||
HAS_CLK_INPUT : boolean := true;
|
||||
HAS_RESET_INPUT : boolean := true;
|
||||
HAS_STOP_INPUT : boolean := true
|
||||
);
|
||||
port
|
||||
(
|
||||
clk_in : in std_logic := '1';
|
||||
rst_in : in std_logic := '0';
|
||||
|
||||
clk : out std_logic;
|
||||
rst_n : out std_logic;
|
||||
|
||||
stop_simulation : in std_logic := '0'
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of clk_rst_generator is
|
||||
|
||||
signal clk_sim : std_logic := '1';
|
||||
signal clk_in_sig : std_logic := '1';
|
||||
signal clk_sig : std_logic := '1';
|
||||
signal rst_sig : std_logic := '0';
|
||||
signal rst_in_sync : std_logic := '0';
|
||||
|
||||
begin
|
||||
clk <= clk_sig;
|
||||
rst_n <= not rst_sig;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- CLOCK GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
clk_sig <= clk_in_sig and clk_sim;
|
||||
-- Dies ist kein gated Clock!
|
||||
-- Fuer die Synthese ist clk_sim konstant '1'
|
||||
-- somit wird die UND-Verknuepfung 'wegoptimiert'
|
||||
-- und was übrig bleibt, ist ein 'Draht'
|
||||
|
||||
-- synthesis translate_off
|
||||
clk_sim <= not clk_sim after (1ps * CLOCK_PERIOD)/2;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
assert not HAS_CLK_INPUT report "CLK_RST_GENERATOR: !!! Be aware !!! -- clk is delayed by 1 delta cycle compared to clk_in " severity note;
|
||||
assert not HAS_CLK_INPUT report "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" severity note;
|
||||
-- synthesis translate_on
|
||||
|
||||
process (clk_in) begin
|
||||
clk_in_sig <= clk_in;
|
||||
-- synthesis translate_off
|
||||
clk_in_sig <= '1';
|
||||
-- synthesis translate_on
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- RESET GENERATION
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
process
|
||||
variable rescnt : unsigned (6 downto 0) := (others=>'1');
|
||||
begin
|
||||
wait until rising_edge(clk_sig);
|
||||
|
||||
rst_in_sync <= rst_in;
|
||||
if rst_in_sync = '1' then
|
||||
rescnt := (others=>'1');
|
||||
end if;
|
||||
|
||||
if rescnt = 0 then
|
||||
rst_sig <= '0';
|
||||
else
|
||||
rescnt := rescnt - 1;
|
||||
rst_sig <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
-- STOP SIMULATION INPUT (simulation only)
|
||||
---------------------------------------------------------------
|
||||
---------------------------------------------------------------
|
||||
|
||||
-- synthesis translate_off
|
||||
process (stop_simulation) begin
|
||||
if stop_simulation = '1' then
|
||||
assert false report "CLK_RST_GENERATOR: End of simulation. (this is not an error - please ignore any 'failure' messages)" severity failure;
|
||||
end if;
|
||||
end process;
|
||||
-- synthesis translate_on
|
||||
|
||||
end rtl;
|
||||
+58
@@ -0,0 +1,58 @@
|
||||
--------------------------------------------------------------------------
|
||||
--
|
||||
-- AXI Stream Audio Stereo to Mono
|
||||
--
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2020/2021
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axis_audio_stereo2mono is
|
||||
generic
|
||||
(
|
||||
HAS_LAST : boolean := false
|
||||
);
|
||||
port
|
||||
(
|
||||
AXIS_ACLK : in std_logic;
|
||||
|
||||
-- AXI Streaming Target Port
|
||||
S_AXIS_TVALID : in std_logic;
|
||||
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
|
||||
S_AXIS_TLAST : in std_logic := '0';
|
||||
S_AXIS_TREADY : out std_logic;
|
||||
|
||||
-- AXI Streaming Initiator Port
|
||||
M_AXIS_TVALID : out std_logic;
|
||||
M_AXIS_TDATA : out std_logic_vector(15 downto 0);
|
||||
M_AXIS_TLAST : out std_logic;
|
||||
M_AXIS_TREADY : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture section
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
architecture rtl of axis_audio_stereo2mono is
|
||||
signal m_valid_sig : std_logic := '0';
|
||||
begin
|
||||
|
||||
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
|
||||
|
||||
process begin
|
||||
wait until rising_edge(AXIS_ACLK);
|
||||
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
|
||||
M_AXIS_TDATA <= std_logic_vector(signed(S_AXIS_TDATA(31)&S_AXIS_TDATA(31 downto 17))+signed(S_AXIS_TDATA(15)&S_AXIS_TDATA(15 downto 1)));
|
||||
M_AXIS_TVALID <= S_AXIS_TVALID;
|
||||
m_valid_sig <= S_AXIS_TVALID;
|
||||
M_AXIS_TLAST <= S_AXIS_TLAST;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end;
|
||||
+284
@@ -0,0 +1,284 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axil_master_with_rom.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
-- AXIL-Master
|
||||
--
|
||||
-- Transactions des Masters werden durch ein ladbares ROM definiert
|
||||
-- Die Inhalte des ROMs werden aus einer Datei geladen und bei Synthese und Simulation verwendet
|
||||
-- Das ROM besitzt eine Wortbreite von 40 bit
|
||||
-- Für einen Befehl werden 1 bis 2 Worte verwendet
|
||||
-- Nur 'wal' verwendet 2 40 - Bit - Worte
|
||||
--
|
||||
-- Die Codierung ist nachfolgend dargestellt :
|
||||
-- command wal : <39 : 8> Adresse <3 : 0> Befehl(wal = 1)
|
||||
-- <39 : 8> Daten <3 : 0> Befehl WStrobe
|
||||
-- command ral : <39 : 8> Adresse <3 : 0> Befehl(ral = 2)
|
||||
-- command wfi : Befehl(wfi = 6)
|
||||
-- command ral : <15 : 8> Wartezyklen <3 : 0> Befehl(slp = 7)
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity axil_master_with_rom is
|
||||
generic
|
||||
(
|
||||
HAS_INTERRUPT_IN : boolean := true;
|
||||
HAS_FINISHED_OUT : boolean := false;
|
||||
STIM_FILENAME : string := "../../stimuli.mem"
|
||||
);
|
||||
port
|
||||
(
|
||||
interrupt_in : in std_logic:='0';
|
||||
finished_o : out std_logic;
|
||||
|
||||
M_AXIL_ACLK : in std_logic;
|
||||
M_AXIL_ARESETN : in std_logic;
|
||||
|
||||
M_AXIL_ARREADY : in std_logic;
|
||||
M_AXIL_ARVALID : out std_logic;
|
||||
M_AXIL_ARADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_ARPROT : out std_logic_vector(2 downto 0);
|
||||
M_AXIL_RREADY : out std_logic;
|
||||
M_AXIL_RVALID : in std_logic;
|
||||
M_AXIL_RDATA : in std_logic_vector(31 downto 0);
|
||||
M_AXIL_RRESP : in std_logic_vector(1 downto 0);
|
||||
M_AXIL_AWREADY : in std_logic;
|
||||
M_AXIL_AWVALID : out std_logic;
|
||||
M_AXIL_AWADDR : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_AWPROT : out std_logic_vector(2 downto 0);
|
||||
M_AXIL_WREADY : in std_logic;
|
||||
M_AXIL_WVALID : out std_logic;
|
||||
M_AXIL_WDATA : out std_logic_vector(31 downto 0);
|
||||
M_AXIL_WSTRB : out std_logic_vector(3 downto 0);
|
||||
M_AXIL_BREADY : out std_logic;
|
||||
M_AXIL_BVALID : in std_logic;
|
||||
M_AXIL_BRESP : in std_logic_vector(1 downto 0)
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axil_master_with_rom is
|
||||
|
||||
|
||||
type TSTATE is (INIT,INIT_WAIT,
|
||||
GET_COMMAND,
|
||||
WR_ADDR,WR_ADDR_WAIT1,WR_ADDR_WAIT2,WR_DATA,WR_DATA_WAIT,WR_RESP,
|
||||
RD_ADDR,RD_DATA,
|
||||
WAIT_FOR_INT,
|
||||
SLEEP,SLEEP_WAIT,
|
||||
FINISHED
|
||||
);
|
||||
|
||||
signal state : TSTATE := INIT;
|
||||
|
||||
constant ADDR_WIDTH_CMD_ROM : integer := 12;
|
||||
|
||||
signal mdata : std_logic_vector(39 downto 0);
|
||||
signal maddr : std_logic_vector(ADDR_WIDTH_CMD_ROM-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
cmdrom : entity work.axilm_rom
|
||||
generic map (
|
||||
FILENAME => STIM_FILENAME,
|
||||
DW => 40,
|
||||
AW => ADDR_WIDTH_CMD_ROM
|
||||
)
|
||||
port map (
|
||||
clk => M_AXIL_ACLK,
|
||||
a => maddr,
|
||||
q => mdata
|
||||
);
|
||||
|
||||
|
||||
process
|
||||
variable cnt8 : unsigned( 7 downto 0);
|
||||
variable cnt32 : unsigned(31 downto 0);
|
||||
variable addr_accepted : boolean;
|
||||
variable data_accepted : boolean;
|
||||
|
||||
begin
|
||||
wait until rising_edge(M_AXIL_ACLK);
|
||||
|
||||
if M_AXIL_ARESETN = '0' then
|
||||
state <= INIT;
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others=>'X');
|
||||
M_AXIL_ARPROT <= (others=>'0');
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_AWADDR <= (others=>'X');
|
||||
M_AXIL_AWPROT <= (others=>'0');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_BREADY <= '0';
|
||||
finished_o <= '0';
|
||||
else
|
||||
case state is
|
||||
|
||||
----
|
||||
-- Init
|
||||
----
|
||||
when INIT =>
|
||||
finished_o <= '0';
|
||||
cnt8 := x"10";
|
||||
maddr <= (others=>'0');
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others=>'X');
|
||||
M_AXIL_ARPROT <= (others=>'0');
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_AWADDR <= (others=>'X');
|
||||
M_AXIL_AWPROT <= (others=>'0');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_BREADY <= '0';
|
||||
state <= INIT_WAIT;
|
||||
|
||||
when INIT_WAIT =>
|
||||
cnt8 := cnt8 - 1;
|
||||
if cnt8 = 0 then
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when GET_COMMAND =>
|
||||
case (mdata(3 downto 0)) is
|
||||
when x"0" => state <= FINISHED;
|
||||
when x"1" => state <= WR_ADDR;
|
||||
when x"2" => state <= RD_ADDR;
|
||||
when x"6" => state <= WAIT_FOR_INT;
|
||||
when x"7" => state <= SLEEP;
|
||||
when others => maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
end case;
|
||||
|
||||
|
||||
----
|
||||
-- Write
|
||||
----
|
||||
when WR_ADDR =>
|
||||
M_AXIL_AWVALID <= '1';
|
||||
M_AXIL_AWADDR <= mdata(39 downto 8);
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_ARADDR <= (others => 'X');
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
addr_accepted := false;
|
||||
data_accepted := false;
|
||||
state <= WR_ADDR_WAIT1;
|
||||
when WR_ADDR_WAIT1 =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
state <= WR_ADDR_WAIT2;
|
||||
when WR_ADDR_WAIT2 =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
state <= WR_DATA;
|
||||
when WR_DATA =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
M_AXIL_WSTRB <= mdata( 3 downto 0);
|
||||
M_AXIL_WDATA <= mdata(39 downto 8);
|
||||
M_AXIL_WVALID <= '1';
|
||||
state <= WR_DATA_WAIT;
|
||||
when WR_DATA_WAIT =>
|
||||
if (M_AXIL_AWREADY = '1') then
|
||||
M_AXIL_AWVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
if (M_AXIL_WREADY = '1') then
|
||||
M_AXIL_WVALID <= '0';
|
||||
data_accepted := true;
|
||||
end if;
|
||||
|
||||
if (addr_accepted and data_accepted) then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
M_AXIL_AWVALID <= '0';
|
||||
M_AXIL_WSTRB <= (others=>'X');
|
||||
M_AXIL_WDATA <= (others=>'X');
|
||||
M_AXIL_WVALID <= '0';
|
||||
M_AXIL_BREADY <= '1';
|
||||
state <= WR_RESP;
|
||||
end if;
|
||||
when WR_RESP =>
|
||||
if M_AXIL_BVALID = '1' then
|
||||
M_AXIL_BREADY <= '0';
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
|
||||
----
|
||||
-- Read
|
||||
----
|
||||
when RD_ADDR =>
|
||||
M_AXIL_ARVALID <= '1';
|
||||
M_AXIL_ARADDR <= mdata(39 downto 8);
|
||||
M_AXIL_AWVALID <= 'X';
|
||||
M_AXIL_AWADDR <= (others => 'X');
|
||||
M_AXIL_RREADY <= '1';
|
||||
addr_accepted := false;
|
||||
state <= RD_DATA;
|
||||
when RD_DATA =>
|
||||
if (M_AXIL_ARREADY = '1') then
|
||||
M_AXIL_ARVALID <= '0';
|
||||
addr_accepted := true;
|
||||
end if;
|
||||
if (M_AXIL_RVALID = '1') then
|
||||
M_AXIL_RREADY <= '0';
|
||||
data_accepted := true;
|
||||
end if;
|
||||
if (addr_accepted and data_accepted) then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
M_AXIL_ARVALID <= '0';
|
||||
M_AXIL_RREADY <= '0';
|
||||
M_AXIL_ARADDR <= (others => 'X');
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when WAIT_FOR_INT =>
|
||||
if (interrupt_in = '1') then
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when SLEEP =>
|
||||
cnt32 := unsigned(mdata(39 downto 8));
|
||||
-- synthesis translate_off
|
||||
cnt32 := x"0000"&unsigned(mdata(39 downto 24)); -- fuer Simulation Wartezeit um 65536 verringern
|
||||
-- synthesis translate_on
|
||||
maddr <= std_logic_vector(unsigned(maddr) + 1);
|
||||
state <= SLEEP_WAIT;
|
||||
|
||||
when SLEEP_WAIT =>
|
||||
if (cnt32 /= 0) then
|
||||
cnt32 := cnt32 - 1;
|
||||
else
|
||||
state <= GET_COMMAND;
|
||||
end if;
|
||||
|
||||
when FINISHED =>
|
||||
finished_o <= '1';
|
||||
|
||||
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end;
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- axilm_rom.vhd - entity/architecture pair
|
||||
------------------------------------------------------------------------------
|
||||
----------------------------------------------------------
|
||||
-- Prof. Dr.-Ing. W. Gehrke (c) 2024
|
||||
----------------------------------------------------------
|
||||
|
||||
-- ref. https://docs.amd.com/r/en-US/ug901-vivado-synthesis/VHDL-Code-Example
|
||||
|
||||
use std.textio.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
entity axilm_rom is
|
||||
|
||||
generic (
|
||||
FILENAME : string;
|
||||
DW : integer; -- Data Width
|
||||
AW : integer -- Address Width
|
||||
);
|
||||
port (
|
||||
clk : in std_logic; -- Clock
|
||||
a : in std_logic_vector(AW-1 downto 0); -- Address
|
||||
q : out std_logic_vector(DW-1 downto 0) -- Data out port
|
||||
);
|
||||
end;
|
||||
|
||||
|
||||
architecture rtl of axilm_rom is
|
||||
type tmem is array(0 to 2**AW-1) of std_logic_vector(DW-1 downto 0);
|
||||
|
||||
impure function InitMemFromFile(MemFileName : in string) return tmem is
|
||||
FILE MemFile : text is in MemFileName;
|
||||
variable MemFileLine : line;
|
||||
variable mem : tmem;
|
||||
begin
|
||||
for i in tmem'range loop
|
||||
readline(MemFile, MemFileLine);
|
||||
read(MemFileLine, mem(i));
|
||||
end loop;
|
||||
return mem;
|
||||
end function;
|
||||
|
||||
constant mem : tmem := InitMemFromFile(
|
||||
-- synthesis translate_off
|
||||
"../../" &
|
||||
-- synthesis translate_on
|
||||
FILENAME);
|
||||
|
||||
begin
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
q <= mem(to_integer(unsigned(a)));
|
||||
end process;
|
||||
end;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+287
@@ -0,0 +1,287 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
nsFylERiuG7mpTKUIOx2ctX6bezOiVe7YLeXdrNT5EcXJeoUZJQBgRY9zpMCohWLZVJIz5ayl5ae
|
||||
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|
||||
k1jcY8lFjetrBZOo7Tg=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
AB1sYtukt5mXbeMyi/lgTz8BCAY61ptehv0vQg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
shtWPi1XoFPsFP3Q6GB8b8IHUMjsXmDTTfwF9IGG9gPGcZY/f4njhpqff0fSyG0oUuTYStZ7bZNK
|
||||
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|
||||
a9/LrZ2uzBBzAo7zHMY=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
knvWAAxWkfz6AAtQB7jMJ1FHLy7fRYm9KI3gm8pRV982DAd2aSwO2DDUsgYz/0nXstBb2i7kfusi
|
||||
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|
||||
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|
||||
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|
||||
2Lodrp/uTk41S5ga0S142suf1vixEbsLt8Jd3A==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
fNmi3pGuVT4Ek4sb4B8QYuGRjbNE5fCWNZPQ3HtaxoCmgQVj6V7m+WnlQ4sV1/fyRFzfm+cS6tdD
|
||||
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|
||||
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|
||||
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|
||||
OO2gqrMgzKMHqHx28cFT5P5wPltWhh+vkFAngA==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
YcCXZF3TxRWwHPrSiEu++e+rXiU309Kp7Lam6HESEjorpJOWid9x6jnNQT6KV1a6rmVkUelAeuv8
|
||||
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|
||||
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|
||||
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|
||||
EvHxMN5n4ZLBneMHuAMYzSAtuPSU/kW0Utuauw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
b/ikbNkY/8vWVmXkQQuseZIc9Ft5dbZ7HhnvpYanTPQq8abw5e8ttsiUN5p0Gy4+TEKVw9wLZgxh
|
||||
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|
||||
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|
||||
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|
||||
zDoMHc5vM5cQ1BHDEzCITwQUL34e5amtzEO3HQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
O+qJMqYzGEakU98OWV7eCxSuO9qw2mI8hd337qqQnnJFexK2G4tEd7nlLBpK+NkeDwXvW602oIoV
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
lS23lbsML4iLFvURB3qgD7fuVIqK/Nr04HhjVvxDa0RN9Ql26FzIigHn
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
KKGbxyUf8cxDPfqfYf0PPB52LS26x6XmFIfQlDFUBAA04hTF7HocsmopvNCk2vsKiEXxB1bHvKNL
|
||||
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|
||||
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|
||||
xL1AngB545p0XKdkBv5YOxlhINAIpAQTjdPiM1I2df2o2I6mbZpjS2BsIOMJipEsvw2soc9eW/Tm
|
||||
BL0oElfsCxTkqxNUXjTtgPCO9K4pIhF4qwi8Pg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11376)
|
||||
`pragma protect data_block
|
||||
qvXUzIRz5FPcvtu+R954oR4c/CAPnWZYGcu/WVb49Z3b/mZaj9xZxuoWfcPJZKPH1ZhdV85cG/cF
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
pDr0YAAIzpQsB/xEO48uADYywstsgZHGm4DGE15f/b/taxq4Spg7THbxbi6ZO76f5Q4eI0NSglZ7
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
jpV2X2iF2dPLbbIxQL0p1z+Apb3JnOW2TjUwh3pNkTGLu+keR4fwVfPikhr0tmPh7mXSw9M+B7/D
|
||||
Xe8JsnSP6v2iN+1XHo/eWc1eRfO3O1wwqKKuoxD7Yi0skdC0xie+SMcgu82FWiOO6L5O+xZRNm+6
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
UM/GSlQBzeYDE4/+xY75i+21ied5FkNoHmXNaPZMpVEiGSHrggPnIL4r9oEYYzaQsmoXJ8VxNxUy
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
iYRjH7zfskdun/1DP/S95ohM4y0p5s6I4SsnlQDhhiECR3oI52N4rs0hfPLKzpugD3j8HlUXr/Fz
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
iiWQKFUyOMH9XVjs2nO09aY7QIU7uPM3beuK2G4r1AUNVr3e4SD1+TkeC2lhU4d2HZcE4YCS8i2+
|
||||
Io+hADE7I1zwkHEyK4bxMKo1r+YmQFk+6KMSW/MATT2Pt8Ha8GplDK8jLySjLUPOoGiSRGnSLUo+
|
||||
R1Vc4cEKW+niKFqZVULF3KH8YED3nSxfZc5T+Et3+HmiAo7JY5YdMEnj7AJhjCm9QUOmDTH1EpEM
|
||||
WrqDIdzQznic3OejCol9hmS0RYfAmlxEi1KgZOmw9JY2Yi8mOE2J6QDJ7Y2ervxyyKDGYFPTA9kD
|
||||
ffkxVXlS4sIvq+/sSAcaBpHn3tPoroABWXMQd8MNy4IGAWFPSuhr/CiKg8NGt0XiBsN//Ka97kAu
|
||||
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|
||||
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|
||||
SCR882R20m6HjaaG/3SUqzac0mAdZtuxxSu1YUjd+9kp/kFEhvNjC5wTYnEuLz7T0OW8X9AZ956p
|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
qY5yY+Z9REBIYqBIGaS27ku0bSbXwFPHQhHX0s/xqPiU
|
||||
`pragma protect end_protected
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"design_1": {
|
||||
"proto_instances": {
|
||||
"/axil_master_with_rom_0/M_AXIL": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_AXIL_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXIL_ARADDR"},
|
||||
"ARESETN": { "actual": "M_AXIL_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXIL_ARPROT"},
|
||||
"ARREADY": { "actual": "M_AXIL_ARREADY"},
|
||||
"ARVALID": { "actual": "M_AXIL_ARVALID"},
|
||||
"AWADDR": { "actual": "M_AXIL_AWADDR"},
|
||||
"AWPROT": { "actual": "M_AXIL_AWPROT"},
|
||||
"AWREADY": { "actual": "M_AXIL_AWREADY"},
|
||||
"AWVALID": { "actual": "M_AXIL_AWVALID"},
|
||||
"BREADY": { "actual": "M_AXIL_BREADY"},
|
||||
"BRESP": { "actual": "M_AXIL_BRESP"},
|
||||
"BVALID": { "actual": "M_AXIL_BVALID"},
|
||||
"RDATA": { "actual": "M_AXIL_RDATA"},
|
||||
"RREADY": { "actual": "M_AXIL_RREADY"},
|
||||
"RRESP": { "actual": "M_AXIL_RRESP"},
|
||||
"RVALID": { "actual": "M_AXIL_RVALID"},
|
||||
"WDATA": { "actual": "M_AXIL_WDATA"},
|
||||
"WREADY": { "actual": "M_AXIL_WREADY"},
|
||||
"WSTRB": { "actual": "M_AXIL_WSTRB"},
|
||||
"WVALID": { "actual": "M_AXIL_WVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_mono2ster_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_audio_stereo2mo_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "AXIS_ACLK"},
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_prog_audio_filt_0/M_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"TDATA": { "actual": "M_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "M_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "M_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "M_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_prog_audio_filt_0/S_AXIL": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ARADDR": { "actual": "S_AXIL_ARADDR"},
|
||||
"ARREADY": { "actual": "S_AXIL_ARREADY"},
|
||||
"ARVALID": { "actual": "S_AXIL_ARVALID"},
|
||||
"AWADDR": { "actual": "S_AXIL_AWADDR"},
|
||||
"AWREADY": { "actual": "S_AXIL_AWREADY"},
|
||||
"AWVALID": { "actual": "S_AXIL_AWVALID"},
|
||||
"BREADY": { "actual": "S_AXIL_BREADY"},
|
||||
"BRESP": { "actual": "S_AXIL_BRESP"},
|
||||
"BVALID": { "actual": "S_AXIL_BVALID"},
|
||||
"RDATA": { "actual": "S_AXIL_RDATA"},
|
||||
"RREADY": { "actual": "S_AXIL_RREADY"},
|
||||
"RRESP": { "actual": "S_AXIL_RRESP"},
|
||||
"RVALID": { "actual": "S_AXIL_RVALID"},
|
||||
"WDATA": { "actual": "S_AXIL_WDATA"},
|
||||
"WREADY": { "actual": "S_AXIL_WREADY"},
|
||||
"WSTRB": { "actual": "S_AXIL_WSTRB"},
|
||||
"WVALID": { "actual": "S_AXIL_WVALID"}
|
||||
}
|
||||
},
|
||||
"/axis_prog_audio_filt_0/S_AXIS": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"TDATA": { "actual": "S_AXIS_TDATA"},
|
||||
"TLAST": { "actual": "S_AXIS_TLAST"},
|
||||
"TREADY": { "actual": "S_AXIS_TREADY"},
|
||||
"TVALID": { "actual": "S_AXIS_TVALID"}
|
||||
}
|
||||
},
|
||||
"/zybo_audio_0/axis_pb": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "clk"},
|
||||
"TDATA": { "actual": "axis_pb_data"},
|
||||
"TREADY": { "actual": "axis_pb_ready"},
|
||||
"TVALID": { "actual": "axis_pb_valid"}
|
||||
}
|
||||
},
|
||||
"/zybo_audio_0/axis_rec": {
|
||||
"interface": "xilinx.com:interface:axis:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "clk"},
|
||||
"TDATA": { "actual": "axis_rec_data"},
|
||||
"TREADY": { "actual": "axis_rec_ready"},
|
||||
"TVALID": { "actual": "axis_rec_valid"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,449 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Nov 10 16:55:43 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1 is
|
||||
port (
|
||||
bclk : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
i2c_scl_i : in STD_LOGIC;
|
||||
i2c_scl_o : out STD_LOGIC;
|
||||
i2c_scl_t : out STD_LOGIC;
|
||||
i2c_sda_i : in STD_LOGIC;
|
||||
i2c_sda_o : out STD_LOGIC;
|
||||
i2c_sda_t : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
resez : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
|
||||
end design_1;
|
||||
|
||||
architecture STRUCTURE of design_1 is
|
||||
component design_1_axis_prog_audio_filt_0_1 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_prog_audio_filt_0_1;
|
||||
component design_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component design_1_clk_rst_generator_0_0;
|
||||
component design_1_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_stereo2mo_0_0;
|
||||
component design_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
interrupt_in : in STD_LOGIC;
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axil_master_with_rom_0_0;
|
||||
component design_1_system_ila_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end component design_1_system_ila_0_0;
|
||||
component design_1_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_mono2ster_0_0;
|
||||
component design_1_zybo_audio_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
axis_pb_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_pb_valid : in STD_LOGIC;
|
||||
axis_pb_ready : out STD_LOGIC;
|
||||
axis_rec_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_rec_valid : out STD_LOGIC;
|
||||
axis_rec_ready : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
scl_i : in STD_LOGIC;
|
||||
scl_o : out STD_LOGIC;
|
||||
scl_t : out STD_LOGIC;
|
||||
sda_i : in STD_LOGIC;
|
||||
sda_o : out STD_LOGIC;
|
||||
sda_t : out STD_LOGIC
|
||||
);
|
||||
end component design_1_zybo_audio_0_0;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DONT_TOUCH : boolean;
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWADDR";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WSTRB";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TLAST";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal rec_dat_1 : STD_LOGIC;
|
||||
signal resez_1 : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal zybo_audio_0_axis_rec_TREADY : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TVALID : STD_LOGIC;
|
||||
signal zybo_audio_0_bclk : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_T : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_T : STD_LOGIC;
|
||||
signal zybo_audio_0_mclk : STD_LOGIC;
|
||||
signal zybo_audio_0_mute : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_dat : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_lrc : STD_LOGIC;
|
||||
signal zybo_audio_0_rec_lrc : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
begin
|
||||
bclk <= zybo_audio_0_bclk;
|
||||
clk_1 <= clk;
|
||||
i2c_scl_o <= zybo_audio_0_i2c_SCL_O;
|
||||
i2c_scl_t <= zybo_audio_0_i2c_SCL_T;
|
||||
i2c_sda_o <= zybo_audio_0_i2c_SDA_O;
|
||||
i2c_sda_t <= zybo_audio_0_i2c_SDA_T;
|
||||
mclk <= zybo_audio_0_mclk;
|
||||
mute <= zybo_audio_0_mute;
|
||||
pb_dat <= zybo_audio_0_pb_dat;
|
||||
pb_lrc <= zybo_audio_0_pb_lrc;
|
||||
rec_dat_1 <= rec_dat;
|
||||
rec_lrc <= zybo_audio_0_rec_lrc;
|
||||
resez_1 <= resez;
|
||||
zybo_audio_0_i2c_SCL_I <= i2c_scl_i;
|
||||
zybo_audio_0_i2c_SDA_I <= i2c_sda_i;
|
||||
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => '0'
|
||||
);
|
||||
axis_audio_mono2ster_0: component design_1_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_stereo2mo_0: component design_1_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => zybo_audio_0_axis_rec_TREADY,
|
||||
S_AXIS_TVALID => zybo_audio_0_axis_rec_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component design_1_axis_prog_audio_filt_0_1
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(7 downto 0),
|
||||
S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_AWADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(7 downto 0),
|
||||
S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component design_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => clk_1,
|
||||
rst_in => resez_1,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
system_ila_0: component design_1_system_ila_0_0
|
||||
port map (
|
||||
SLOT_0_AXI_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
SLOT_0_AXI_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
SLOT_0_AXI_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
SLOT_0_AXI_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
SLOT_0_AXI_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
SLOT_0_AXI_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
SLOT_0_AXI_bready => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
SLOT_0_AXI_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
SLOT_0_AXI_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
SLOT_0_AXI_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
SLOT_0_AXI_rready => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
SLOT_0_AXI_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
SLOT_0_AXI_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
SLOT_0_AXI_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
SLOT_0_AXI_wready => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
SLOT_0_AXI_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
SLOT_0_AXI_wvalid => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
SLOT_1_AXIS_tdata(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_1_AXIS_tlast => '0',
|
||||
SLOT_1_AXIS_tready => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
SLOT_1_AXIS_tvalid => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
SLOT_2_AXIS_tdata(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_2_AXIS_tlast => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
SLOT_2_AXIS_tready => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
SLOT_2_AXIS_tvalid => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n
|
||||
);
|
||||
zybo_audio_0: component design_1_zybo_audio_0_0
|
||||
port map (
|
||||
axis_pb_data(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
axis_pb_ready => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
axis_pb_valid => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
axis_rec_data(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
axis_rec_ready => zybo_audio_0_axis_rec_TREADY,
|
||||
axis_rec_valid => zybo_audio_0_axis_rec_TVALID,
|
||||
bclk => zybo_audio_0_bclk,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
mclk => zybo_audio_0_mclk,
|
||||
mute => zybo_audio_0_mute,
|
||||
pb_dat => zybo_audio_0_pb_dat,
|
||||
pb_lrc => zybo_audio_0_pb_lrc,
|
||||
rec_dat => rec_dat_1,
|
||||
rec_lrc => zybo_audio_0_rec_lrc,
|
||||
scl_i => zybo_audio_0_i2c_SCL_I,
|
||||
scl_o => zybo_audio_0_i2c_SCL_O,
|
||||
scl_t => zybo_audio_0_i2c_SCL_T,
|
||||
sda_i => zybo_audio_0_i2c_SDA_I,
|
||||
sda_o => zybo_audio_0_i2c_SDA_O,
|
||||
sda_t => zybo_audio_0_i2c_SDA_T
|
||||
);
|
||||
end STRUCTURE;
|
||||
Binary file not shown.
@@ -0,0 +1,449 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Nov 10 16:55:42 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity design_1 is
|
||||
port (
|
||||
bclk : out STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
i2c_scl_i : in STD_LOGIC;
|
||||
i2c_scl_o : out STD_LOGIC;
|
||||
i2c_scl_t : out STD_LOGIC;
|
||||
i2c_sda_i : in STD_LOGIC;
|
||||
i2c_sda_o : out STD_LOGIC;
|
||||
i2c_sda_t : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
resez : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of design_1 : entity is "design_1.hwdef";
|
||||
end design_1;
|
||||
|
||||
architecture STRUCTURE of design_1 is
|
||||
component design_1_axis_prog_audio_filt_0_1 is
|
||||
port (
|
||||
AXI_ACLK : in STD_LOGIC;
|
||||
AXI_ARESETN : in STD_LOGIC;
|
||||
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_AWVALID : in STD_LOGIC;
|
||||
S_AXIL_AWREADY : out STD_LOGIC;
|
||||
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_WVALID : in STD_LOGIC;
|
||||
S_AXIL_WREADY : out STD_LOGIC;
|
||||
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXIL_BVALID : out STD_LOGIC;
|
||||
S_AXIL_BREADY : in STD_LOGIC;
|
||||
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S_AXIL_ARVALID : in STD_LOGIC;
|
||||
S_AXIL_ARREADY : out STD_LOGIC;
|
||||
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIL_RVALID : out STD_LOGIC;
|
||||
S_AXIL_RREADY : in STD_LOGIC;
|
||||
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TLAST : in STD_LOGIC;
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TLAST : out STD_LOGIC;
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_prog_audio_filt_0_1;
|
||||
component design_1_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component design_1_clk_rst_generator_0_0;
|
||||
component design_1_axis_audio_stereo2mo_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_stereo2mo_0_0;
|
||||
component design_1_axil_master_with_rom_0_0 is
|
||||
port (
|
||||
interrupt_in : in STD_LOGIC;
|
||||
M_AXIL_ACLK : in STD_LOGIC;
|
||||
M_AXIL_ARESETN : in STD_LOGIC;
|
||||
M_AXIL_ARREADY : in STD_LOGIC;
|
||||
M_AXIL_ARVALID : out STD_LOGIC;
|
||||
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_RREADY : out STD_LOGIC;
|
||||
M_AXIL_RVALID : in STD_LOGIC;
|
||||
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXIL_AWREADY : in STD_LOGIC;
|
||||
M_AXIL_AWVALID : out STD_LOGIC;
|
||||
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXIL_WREADY : in STD_LOGIC;
|
||||
M_AXIL_WVALID : out STD_LOGIC;
|
||||
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXIL_BREADY : out STD_LOGIC;
|
||||
M_AXIL_BVALID : in STD_LOGIC;
|
||||
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component design_1_axil_master_with_rom_0_0;
|
||||
component design_1_system_ila_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
end component design_1_system_ila_0_0;
|
||||
component design_1_axis_audio_mono2ster_0_0 is
|
||||
port (
|
||||
AXIS_ACLK : in STD_LOGIC;
|
||||
S_AXIS_TVALID : in STD_LOGIC;
|
||||
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
S_AXIS_TREADY : out STD_LOGIC;
|
||||
M_AXIS_TVALID : out STD_LOGIC;
|
||||
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXIS_TREADY : in STD_LOGIC
|
||||
);
|
||||
end component design_1_axis_audio_mono2ster_0_0;
|
||||
component design_1_zybo_audio_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
axis_pb_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_pb_valid : in STD_LOGIC;
|
||||
axis_pb_ready : out STD_LOGIC;
|
||||
axis_rec_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_rec_valid : out STD_LOGIC;
|
||||
axis_rec_ready : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
scl_i : in STD_LOGIC;
|
||||
scl_o : out STD_LOGIC;
|
||||
scl_t : out STD_LOGIC;
|
||||
sda_i : in STD_LOGIC;
|
||||
sda_o : out STD_LOGIC;
|
||||
sda_t : out STD_LOGIC
|
||||
);
|
||||
end component design_1_zybo_audio_0_0;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DONT_TOUCH : boolean;
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWADDR";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WSTRB";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TLAST";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal rec_dat_1 : STD_LOGIC;
|
||||
signal resez_1 : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal zybo_audio_0_axis_rec_TREADY : STD_LOGIC;
|
||||
signal zybo_audio_0_axis_rec_TVALID : STD_LOGIC;
|
||||
signal zybo_audio_0_bclk : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SCL_T : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_I : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_O : STD_LOGIC;
|
||||
signal zybo_audio_0_i2c_SDA_T : STD_LOGIC;
|
||||
signal zybo_audio_0_mclk : STD_LOGIC;
|
||||
signal zybo_audio_0_mute : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_dat : STD_LOGIC;
|
||||
signal zybo_audio_0_pb_lrc : STD_LOGIC;
|
||||
signal zybo_audio_0_rec_lrc : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
begin
|
||||
bclk <= zybo_audio_0_bclk;
|
||||
clk_1 <= clk;
|
||||
i2c_scl_o <= zybo_audio_0_i2c_SCL_O;
|
||||
i2c_scl_t <= zybo_audio_0_i2c_SCL_T;
|
||||
i2c_sda_o <= zybo_audio_0_i2c_SDA_O;
|
||||
i2c_sda_t <= zybo_audio_0_i2c_SDA_T;
|
||||
mclk <= zybo_audio_0_mclk;
|
||||
mute <= zybo_audio_0_mute;
|
||||
pb_dat <= zybo_audio_0_pb_dat;
|
||||
pb_lrc <= zybo_audio_0_pb_lrc;
|
||||
rec_dat_1 <= rec_dat;
|
||||
rec_lrc <= zybo_audio_0_rec_lrc;
|
||||
resez_1 <= resez;
|
||||
zybo_audio_0_i2c_SCL_I <= i2c_scl_i;
|
||||
zybo_audio_0_i2c_SDA_I <= i2c_sda_i;
|
||||
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
|
||||
port map (
|
||||
M_AXIL_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIL_ARADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
M_AXIL_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIL_ARPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
M_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
M_AXIL_AWADDR(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
M_AXIL_AWPROT(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
M_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
M_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
M_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
M_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
M_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
M_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
M_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
M_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
M_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
M_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
M_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
M_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
interrupt_in => '0'
|
||||
);
|
||||
axis_audio_mono2ster_0: component design_1_axis_audio_mono2ster_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
|
||||
);
|
||||
axis_audio_stereo2mo_0: component design_1_axis_audio_stereo2mo_0_0
|
||||
port map (
|
||||
AXIS_ACLK => clk_rst_generator_0_clk,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
S_AXIS_TDATA(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
S_AXIS_TREADY => zybo_audio_0_axis_rec_TREADY,
|
||||
S_AXIS_TVALID => zybo_audio_0_axis_rec_TVALID
|
||||
);
|
||||
axis_prog_audio_filt_0: component design_1_axis_prog_audio_filt_0_1
|
||||
port map (
|
||||
AXI_ACLK => clk_rst_generator_0_clk,
|
||||
AXI_ARESETN => clk_rst_generator_0_rst_n,
|
||||
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
M_AXIS_TLAST => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
S_AXIL_ARADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(7 downto 0),
|
||||
S_AXIL_ARREADY => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
S_AXIL_ARVALID => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
S_AXIL_AWADDR(7 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(7 downto 0),
|
||||
S_AXIL_AWREADY => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
S_AXIL_AWVALID => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
S_AXIL_BREADY => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
S_AXIL_BRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
S_AXIL_BVALID => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
S_AXIL_RDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
S_AXIL_RREADY => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
S_AXIL_RRESP(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
S_AXIL_RVALID => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
S_AXIL_WDATA(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
S_AXIL_WREADY => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
S_AXIL_WSTRB(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
S_AXIL_WVALID => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
|
||||
);
|
||||
clk_rst_generator_0: component design_1_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => clk_1,
|
||||
rst_in => resez_1,
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
system_ila_0: component design_1_system_ila_0_0
|
||||
port map (
|
||||
SLOT_0_AXI_araddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_ARADDR(31 downto 0),
|
||||
SLOT_0_AXI_arprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_ARPROT(2 downto 0),
|
||||
SLOT_0_AXI_arready => axil_master_with_rom_0_M_AXIL_ARREADY,
|
||||
SLOT_0_AXI_arvalid => axil_master_with_rom_0_M_AXIL_ARVALID,
|
||||
SLOT_0_AXI_awaddr(31 downto 0) => axil_master_with_rom_0_M_AXIL_AWADDR(31 downto 0),
|
||||
SLOT_0_AXI_awprot(2 downto 0) => axil_master_with_rom_0_M_AXIL_AWPROT(2 downto 0),
|
||||
SLOT_0_AXI_awready => axil_master_with_rom_0_M_AXIL_AWREADY,
|
||||
SLOT_0_AXI_awvalid => axil_master_with_rom_0_M_AXIL_AWVALID,
|
||||
SLOT_0_AXI_bready => axil_master_with_rom_0_M_AXIL_BREADY,
|
||||
SLOT_0_AXI_bresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_BRESP(1 downto 0),
|
||||
SLOT_0_AXI_bvalid => axil_master_with_rom_0_M_AXIL_BVALID,
|
||||
SLOT_0_AXI_rdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_RDATA(31 downto 0),
|
||||
SLOT_0_AXI_rready => axil_master_with_rom_0_M_AXIL_RREADY,
|
||||
SLOT_0_AXI_rresp(1 downto 0) => axil_master_with_rom_0_M_AXIL_RRESP(1 downto 0),
|
||||
SLOT_0_AXI_rvalid => axil_master_with_rom_0_M_AXIL_RVALID,
|
||||
SLOT_0_AXI_wdata(31 downto 0) => axil_master_with_rom_0_M_AXIL_WDATA(31 downto 0),
|
||||
SLOT_0_AXI_wready => axil_master_with_rom_0_M_AXIL_WREADY,
|
||||
SLOT_0_AXI_wstrb(3 downto 0) => axil_master_with_rom_0_M_AXIL_WSTRB(3 downto 0),
|
||||
SLOT_0_AXI_wvalid => axil_master_with_rom_0_M_AXIL_WVALID,
|
||||
SLOT_1_AXIS_tdata(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_1_AXIS_tlast => '0',
|
||||
SLOT_1_AXIS_tready => axis_audio_stereo2mo_0_M_AXIS_TREADY,
|
||||
SLOT_1_AXIS_tvalid => axis_audio_stereo2mo_0_M_AXIS_TVALID,
|
||||
SLOT_2_AXIS_tdata(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
|
||||
SLOT_2_AXIS_tlast => axis_prog_audio_filt_0_M_AXIS_TLAST,
|
||||
SLOT_2_AXIS_tready => axis_prog_audio_filt_0_M_AXIS_TREADY,
|
||||
SLOT_2_AXIS_tvalid => axis_prog_audio_filt_0_M_AXIS_TVALID,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n
|
||||
);
|
||||
zybo_audio_0: component design_1_zybo_audio_0_0
|
||||
port map (
|
||||
axis_pb_data(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
|
||||
axis_pb_ready => axis_audio_mono2ster_0_M_AXIS_TREADY,
|
||||
axis_pb_valid => axis_audio_mono2ster_0_M_AXIS_TVALID,
|
||||
axis_rec_data(31 downto 0) => zybo_audio_0_axis_rec_TDATA(31 downto 0),
|
||||
axis_rec_ready => zybo_audio_0_axis_rec_TREADY,
|
||||
axis_rec_valid => zybo_audio_0_axis_rec_TVALID,
|
||||
bclk => zybo_audio_0_bclk,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
mclk => zybo_audio_0_mclk,
|
||||
mute => zybo_audio_0_mute,
|
||||
pb_dat => zybo_audio_0_pb_dat,
|
||||
pb_lrc => zybo_audio_0_pb_lrc,
|
||||
rec_dat => rec_dat_1,
|
||||
rec_lrc => zybo_audio_0_rec_lrc,
|
||||
scl_i => zybo_audio_0_i2c_SCL_I,
|
||||
scl_o => zybo_audio_0_i2c_SCL_O,
|
||||
scl_t => zybo_audio_0_i2c_SCL_T,
|
||||
sda_i => zybo_audio_0_i2c_SDA_I,
|
||||
sda_o => zybo_audio_0_i2c_SDA_O,
|
||||
sda_t => zybo_audio_0_i2c_SDA_T
|
||||
);
|
||||
end STRUCTURE;
|
||||
+864
@@ -0,0 +1,864 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>module_ref</spirit:library>
|
||||
<spirit:name>axis_prog_audio_filter3</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIS</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TLAST</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIS_TREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S_AXIL</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave>
|
||||
<spirit:memoryMapRef spirit:memoryMapRef="S_AXIL"/>
|
||||
</spirit:slave>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWADDR</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_AWREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WSTRB</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_WREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BRESP</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_BREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_ARADDR</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_ARVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_ARREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RDATA</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RRESP</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RVALID</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>S_AXIL_RREADY</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXI_ARESETN</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXI_ARESETN</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>AXI_ACLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>AXI_ACLK</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXI_ACLK.ASSOCIATED_RESET">AXI_ARESETN</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:memoryMaps>
|
||||
<spirit:memoryMap>
|
||||
<spirit:name>S_AXIL</spirit:name>
|
||||
<spirit:displayName>S_AXIL</spirit:displayName>
|
||||
<spirit:addressBlock>
|
||||
<spirit:name>reg0</spirit:name>
|
||||
<spirit:displayName>reg0</spirit:displayName>
|
||||
<spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:baseAddress>
|
||||
<spirit:range spirit:format="bitString" spirit:bitStringLength="13" spirit:minimum="4096" spirit:rangeType="long">0x1000</spirit:range>
|
||||
<spirit:width spirit:format="long">32</spirit:width>
|
||||
<spirit:usage>register</spirit:usage>
|
||||
</spirit:addressBlock>
|
||||
</spirit:memoryMap>
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>VHDL</spirit:language>
|
||||
<spirit:modelName>axis_prog_audio_filter3</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
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||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TLAST</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>M_AXIS_TREADY</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>COEFF_0</spirit:name>
|
||||
<spirit:displayName>Coeff 0</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_0">42</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>COEFF_1</spirit:name>
|
||||
<spirit:displayName>Coeff 1</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_1">42</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>COEFF_2</spirit:name>
|
||||
<spirit:displayName>Coeff 2</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_2">42</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SHIFT</spirit:name>
|
||||
<spirit:displayName>Shift</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHIFT">7</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>RUN_AFTER_RESET</spirit:name>
|
||||
<spirit:displayName>Run After Reset</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RUN_AFTER_RESET">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="boolean">
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/axis_prog_audio_filter3_v1_0.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_5efbb7ff</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_prog_audio_filter3:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_0</spirit:name>
|
||||
<spirit:displayName>Coeff 0</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_0">42</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_1</spirit:name>
|
||||
<spirit:displayName>Coeff 1</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_1">42</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>COEFF_2</spirit:name>
|
||||
<spirit:displayName>Coeff 2</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_2">42</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SHIFT</spirit:name>
|
||||
<spirit:displayName>Shift</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SHIFT">7</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RUN_AFTER_RESET</spirit:name>
|
||||
<spirit:displayName>Run After Reset</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.RUN_AFTER_RESET">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>HAS_LAST</spirit:name>
|
||||
<spirit:displayName>Has Last</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LAST">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axis_prog_audio_filter3_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axis_prog_audio_filter3_v1_0</xilinx:displayName>
|
||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
||||
<xilinx:designToolContexts>
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-11-09T23:36:52Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+100
@@ -0,0 +1,100 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "COEFF_0" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "COEFF_1" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "COEFF_2" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "HAS_LAST" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "RUN_AFTER_RESET" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SHIFT" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_0 { PARAM_VALUE.COEFF_0 } {
|
||||
# Procedure called to update COEFF_0 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_0 { PARAM_VALUE.COEFF_0 } {
|
||||
# Procedure called to validate COEFF_0
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_1 { PARAM_VALUE.COEFF_1 } {
|
||||
# Procedure called to update COEFF_1 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_1 { PARAM_VALUE.COEFF_1 } {
|
||||
# Procedure called to validate COEFF_1
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.COEFF_2 { PARAM_VALUE.COEFF_2 } {
|
||||
# Procedure called to update COEFF_2 when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.COEFF_2 { PARAM_VALUE.COEFF_2 } {
|
||||
# Procedure called to validate COEFF_2
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.HAS_LAST { PARAM_VALUE.HAS_LAST } {
|
||||
# Procedure called to update HAS_LAST when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.HAS_LAST { PARAM_VALUE.HAS_LAST } {
|
||||
# Procedure called to validate HAS_LAST
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.RUN_AFTER_RESET { PARAM_VALUE.RUN_AFTER_RESET } {
|
||||
# Procedure called to update RUN_AFTER_RESET when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.RUN_AFTER_RESET { PARAM_VALUE.RUN_AFTER_RESET } {
|
||||
# Procedure called to validate RUN_AFTER_RESET
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SHIFT { PARAM_VALUE.SHIFT } {
|
||||
# Procedure called to update SHIFT when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SHIFT { PARAM_VALUE.SHIFT } {
|
||||
# Procedure called to validate SHIFT
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_0 { MODELPARAM_VALUE.COEFF_0 PARAM_VALUE.COEFF_0 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_0}] ${MODELPARAM_VALUE.COEFF_0}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_1 { MODELPARAM_VALUE.COEFF_1 PARAM_VALUE.COEFF_1 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_1}] ${MODELPARAM_VALUE.COEFF_1}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.COEFF_2 { MODELPARAM_VALUE.COEFF_2 PARAM_VALUE.COEFF_2 } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.COEFF_2}] ${MODELPARAM_VALUE.COEFF_2}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SHIFT { MODELPARAM_VALUE.SHIFT PARAM_VALUE.SHIFT } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SHIFT}] ${MODELPARAM_VALUE.SHIFT}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.RUN_AFTER_RESET { MODELPARAM_VALUE.RUN_AFTER_RESET PARAM_VALUE.RUN_AFTER_RESET } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.RUN_AFTER_RESET}] ${MODELPARAM_VALUE.RUN_AFTER_RESET}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.HAS_LAST { MODELPARAM_VALUE.HAS_LAST PARAM_VALUE.HAS_LAST } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.HAS_LAST}] ${MODELPARAM_VALUE.HAS_LAST}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,627 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xD8B513DD6C968B8A",
|
||||
"device": "xc7z020clg400-1",
|
||||
"gen_directory": "../../../../es-milestone3.gen/sources_1/bd/design_1",
|
||||
"name": "design_1",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"axis_prog_audio_filt_0": "",
|
||||
"clk_rst_generator_0": "",
|
||||
"axis_audio_stereo2mo_0": "",
|
||||
"axil_master_with_rom_0": "",
|
||||
"system_ila_0": "",
|
||||
"axis_audio_mono2ster_0": "",
|
||||
"zybo_audio_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"i2c": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:iic:1.0",
|
||||
"vlnv": "xilinx.com:interface:iic_rtl:1.0",
|
||||
"port_maps": {
|
||||
"SCL_T": {
|
||||
"physical_name": "i2c_scl_t",
|
||||
"direction": "O"
|
||||
},
|
||||
"SDA_O": {
|
||||
"physical_name": "i2c_sda_o",
|
||||
"direction": "O"
|
||||
},
|
||||
"SDA_I": {
|
||||
"physical_name": "i2c_sda_i",
|
||||
"direction": "I"
|
||||
},
|
||||
"SCL_O": {
|
||||
"physical_name": "i2c_scl_o",
|
||||
"direction": "O"
|
||||
},
|
||||
"SCL_I": {
|
||||
"physical_name": "i2c_scl_i",
|
||||
"direction": "I"
|
||||
},
|
||||
"SDA_T": {
|
||||
"physical_name": "i2c_sda_t",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"direction": "I"
|
||||
},
|
||||
"resez": {
|
||||
"direction": "I"
|
||||
},
|
||||
"rec_dat": {
|
||||
"direction": "I"
|
||||
},
|
||||
"mute": {
|
||||
"direction": "O"
|
||||
},
|
||||
"mclk": {
|
||||
"direction": "O"
|
||||
},
|
||||
"bclk": {
|
||||
"direction": "O"
|
||||
},
|
||||
"pb_dat": {
|
||||
"direction": "O"
|
||||
},
|
||||
"pb_lrc": {
|
||||
"direction": "O"
|
||||
},
|
||||
"rec_lrc": {
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"axis_prog_audio_filt_0": {
|
||||
"vlnv": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"xci_name": "design_1_axis_prog_audio_filt_0_1",
|
||||
"xci_path": "ip\\design_1_axis_prog_audio_filt_0_1\\design_1_axis_prog_audio_filt_0_1.xci",
|
||||
"inst_hier_path": "axis_prog_audio_filt_0",
|
||||
"reference_info": {
|
||||
"ref_type": "hdl",
|
||||
"ref_name": "axis_prog_audio_filter3",
|
||||
"boundary_crc": "0x0"
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXIS": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "M_AXIS_TDATA",
|
||||
"direction": "O",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "M_AXIS_TLAST",
|
||||
"direction": "O"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "M_AXIS_TVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "M_AXIS_TREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": {
|
||||
"value": "2",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TDEST_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"TUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TSTRB": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_TLAST": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
}
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": {
|
||||
"physical_name": "S_AXIS_TDATA",
|
||||
"direction": "I",
|
||||
"left": "15",
|
||||
"right": "0"
|
||||
},
|
||||
"TLAST": {
|
||||
"physical_name": "S_AXIS_TLAST",
|
||||
"direction": "I"
|
||||
},
|
||||
"TVALID": {
|
||||
"physical_name": "S_AXIS_TVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"TREADY": {
|
||||
"physical_name": "S_AXIS_TREADY",
|
||||
"direction": "O"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": {
|
||||
"value": "32",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"PROTOCOL": {
|
||||
"value": "AXI4LITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ID_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ADDR_WIDTH": {
|
||||
"value": "8",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"AWUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"ARUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"WUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"RUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"BUSER_WIDTH": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"READ_WRITE_MODE": {
|
||||
"value": "READ_WRITE",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_LOCK": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_PROT": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_CACHE": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_QOS": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_REGION": {
|
||||
"value": "0",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_WSTRB": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_BRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"HAS_RRESP": {
|
||||
"value": "1",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"SUPPORTS_NARROW_BURST": {
|
||||
"value": "0",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_READ_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"NUM_WRITE_OUTSTANDING": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "1",
|
||||
"value_src": "auto"
|
||||
}
|
||||
},
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"port_maps": {
|
||||
"AWADDR": {
|
||||
"physical_name": "S_AXIL_AWADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"AWVALID": {
|
||||
"physical_name": "S_AXIL_AWVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"AWREADY": {
|
||||
"physical_name": "S_AXIL_AWREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"WDATA": {
|
||||
"physical_name": "S_AXIL_WDATA",
|
||||
"direction": "I",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"WSTRB": {
|
||||
"physical_name": "S_AXIL_WSTRB",
|
||||
"direction": "I",
|
||||
"left": "3",
|
||||
"right": "0"
|
||||
},
|
||||
"WVALID": {
|
||||
"physical_name": "S_AXIL_WVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"WREADY": {
|
||||
"physical_name": "S_AXIL_WREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"BRESP": {
|
||||
"physical_name": "S_AXIL_BRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"BVALID": {
|
||||
"physical_name": "S_AXIL_BVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"BREADY": {
|
||||
"physical_name": "S_AXIL_BREADY",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARADDR": {
|
||||
"physical_name": "S_AXIL_ARADDR",
|
||||
"direction": "I",
|
||||
"left": "7",
|
||||
"right": "0"
|
||||
},
|
||||
"ARVALID": {
|
||||
"physical_name": "S_AXIL_ARVALID",
|
||||
"direction": "I"
|
||||
},
|
||||
"ARREADY": {
|
||||
"physical_name": "S_AXIL_ARREADY",
|
||||
"direction": "O"
|
||||
},
|
||||
"RDATA": {
|
||||
"physical_name": "S_AXIL_RDATA",
|
||||
"direction": "O",
|
||||
"left": "31",
|
||||
"right": "0"
|
||||
},
|
||||
"RRESP": {
|
||||
"physical_name": "S_AXIL_RRESP",
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0"
|
||||
},
|
||||
"RVALID": {
|
||||
"physical_name": "S_AXIL_RVALID",
|
||||
"direction": "O"
|
||||
},
|
||||
"RREADY": {
|
||||
"physical_name": "S_AXIL_RREADY",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"AXI_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "AXI_ARESETN",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"clk_rst_generator_0": {
|
||||
"vlnv": "wg:user:clk_rst_generator:1.0",
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
|
||||
"inst_hier_path": "clk_rst_generator_0"
|
||||
},
|
||||
"axis_audio_stereo2mo_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"xci_name": "design_1_axis_audio_stereo2mo_0_0",
|
||||
"xci_path": "ip\\design_1_axis_audio_stereo2mo_0_0\\design_1_axis_audio_stereo2mo_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_stereo2mo_0"
|
||||
},
|
||||
"axil_master_with_rom_0": {
|
||||
"vlnv": "wg:user:axil_master_with_rom:1.0",
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
|
||||
"inst_hier_path": "axil_master_with_rom_0",
|
||||
"interface_ports": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"base_address": {
|
||||
"minimum": "0x00000000",
|
||||
"maximum": "0xFFFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "4G",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"system_ila_0": {
|
||||
"vlnv": "xilinx.com:ip:system_ila:1.1",
|
||||
"xci_name": "design_1_system_ila_0_0",
|
||||
"xci_path": "ip\\design_1_system_ila_0_0\\design_1_system_ila_0_0.xci",
|
||||
"inst_hier_path": "system_ila_0",
|
||||
"parameters": {
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "3"
|
||||
},
|
||||
"C_SLOT": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_SLOT_1_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"C_SLOT_2_INTF_TYPE": {
|
||||
"value": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXI": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"SLOT_2_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_mono2ster_0": {
|
||||
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"xci_name": "design_1_axis_audio_mono2ster_0_0",
|
||||
"xci_path": "ip\\design_1_axis_audio_mono2ster_0_0\\design_1_axis_audio_mono2ster_0_0.xci",
|
||||
"inst_hier_path": "axis_audio_mono2ster_0"
|
||||
},
|
||||
"zybo_audio_0": {
|
||||
"vlnv": "xilinx.com:user:zybo_audio:1.0",
|
||||
"xci_name": "design_1_zybo_audio_0_0",
|
||||
"xci_path": "ip\\design_1_zybo_audio_0_0\\design_1_zybo_audio_0_0.xci",
|
||||
"inst_hier_path": "zybo_audio_0"
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axil_master_with_rom_0_M_AXIL": {
|
||||
"interface_ports": [
|
||||
"axil_master_with_rom_0/M_AXIL",
|
||||
"axis_prog_audio_filt_0/S_AXIL",
|
||||
"system_ila_0/SLOT_0_AXI"
|
||||
]
|
||||
},
|
||||
"axis_audio_mono2ster_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_mono2ster_0/M_AXIS",
|
||||
"zybo_audio_0/axis_pb"
|
||||
]
|
||||
},
|
||||
"axis_audio_stereo2mo_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_audio_stereo2mo_0/M_AXIS",
|
||||
"axis_prog_audio_filt_0/S_AXIS",
|
||||
"system_ila_0/SLOT_1_AXIS"
|
||||
]
|
||||
},
|
||||
"axis_prog_audio_filt_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_prog_audio_filt_0/M_AXIS",
|
||||
"axis_audio_mono2ster_0/S_AXIS",
|
||||
"system_ila_0/SLOT_2_AXIS"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_axis_rec": {
|
||||
"interface_ports": [
|
||||
"zybo_audio_0/axis_rec",
|
||||
"axis_audio_stereo2mo_0/S_AXIS"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_i2c": {
|
||||
"interface_ports": [
|
||||
"i2c",
|
||||
"zybo_audio_0/i2c"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"clk_rst_generator_0/clk_in"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_clk": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/clk",
|
||||
"axis_audio_stereo2mo_0/AXIS_ACLK",
|
||||
"axil_master_with_rom_0/M_AXIL_ACLK",
|
||||
"axis_prog_audio_filt_0/AXI_ACLK",
|
||||
"axis_audio_mono2ster_0/AXIS_ACLK",
|
||||
"zybo_audio_0/clk",
|
||||
"system_ila_0/clk"
|
||||
]
|
||||
},
|
||||
"clk_rst_generator_0_rst_n": {
|
||||
"ports": [
|
||||
"clk_rst_generator_0/rst_n",
|
||||
"axil_master_with_rom_0/M_AXIL_ARESETN",
|
||||
"axis_prog_audio_filt_0/AXI_ARESETN",
|
||||
"system_ila_0/resetn"
|
||||
]
|
||||
},
|
||||
"rec_dat_1": {
|
||||
"ports": [
|
||||
"rec_dat",
|
||||
"zybo_audio_0/rec_dat"
|
||||
]
|
||||
},
|
||||
"resez_1": {
|
||||
"ports": [
|
||||
"resez",
|
||||
"clk_rst_generator_0/rst_in"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_bclk": {
|
||||
"ports": [
|
||||
"zybo_audio_0/bclk",
|
||||
"bclk"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_mclk": {
|
||||
"ports": [
|
||||
"zybo_audio_0/mclk",
|
||||
"mclk"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_mute": {
|
||||
"ports": [
|
||||
"zybo_audio_0/mute",
|
||||
"mute"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_pb_dat": {
|
||||
"ports": [
|
||||
"zybo_audio_0/pb_dat",
|
||||
"pb_dat"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_pb_lrc": {
|
||||
"ports": [
|
||||
"zybo_audio_0/pb_lrc",
|
||||
"pb_lrc"
|
||||
]
|
||||
},
|
||||
"zybo_audio_0_rec_lrc": {
|
||||
"ports": [
|
||||
"zybo_audio_0/rec_lrc",
|
||||
"rec_lrc"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "design_1",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "design_1",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+171
@@ -0,0 +1,171 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axil_master_with_rom_0_0",
|
||||
"cell_name": "axil_master_with_rom_0",
|
||||
"component_reference": "wg:user:axil_master_with_rom:1.0",
|
||||
"ip_revision": "17",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "user", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axil_master_with_rom_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"STIM_FILENAME": [ { "value": "../../stimuli.mem", "resolve_type": "generated", "usage": "all" } ],
|
||||
"HAS_FINISHED_OUT": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_INTERRUPT_IN": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "17" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"interrupt_in": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"M_AXIL_ACLK": [ { "direction": "in" } ],
|
||||
"M_AXIL_ARESETN": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"M_AXIL_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIL_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXIL_AWREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXIL_WREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_WVALID": [ { "direction": "out" } ],
|
||||
"M_AXIL_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIL_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXIL_BREADY": [ { "direction": "out" } ],
|
||||
"M_AXIL_BVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXIL_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "M_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "M_AXIL_AWADDR" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXIL_AWPROT" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXIL_ARADDR" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXIL_ARPROT" } ],
|
||||
"ARVALID": [ { "physical_name": "M_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "M_AXIL_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIL_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIL", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "M_AXIL_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "M_AXIL_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
"M_AXIL": {
|
||||
"range": "0x100000000",
|
||||
"display_name": "M_AXIL",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_audio_mono2ster_0_0",
|
||||
"cell_name": "axis_audio_mono2ster_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_mono2stereo:1.0",
|
||||
"ip_revision": "3",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_audio_mono2ster_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
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|
||||
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|
||||
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|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "3" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
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|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
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|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_audio_stereo2mo_0_0",
|
||||
"cell_name": "axis_audio_stereo2mo_0",
|
||||
"component_reference": "xilinx.com:user:axis_audio_stereo2mono:1.0",
|
||||
"ip_revision": "4",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_audio_stereo2mo_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
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|
||||
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|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "4" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
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|
||||
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|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
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|
||||
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|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
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|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXIS_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS:S_AXIS", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXIS_ACLK" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+238
@@ -0,0 +1,238 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_axis_prog_audio_filt_0_1",
|
||||
"cell_name": "axis_prog_audio_filt_0",
|
||||
"component_reference": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"COEFF_0": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"COEFF_1": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"COEFF_2": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SHIFT": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_axis_prog_audio_filt_0_1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"COEFF_0": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"COEFF_1": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"COEFF_2": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SHIFT": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"AXI_ACLK": [ { "direction": "in" } ],
|
||||
"AXI_ARESETN": [ { "direction": "in" } ],
|
||||
"S_AXIL_AWADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_AWVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_AWREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_WVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_WREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_WSTRB": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "1" } ],
|
||||
"S_AXIL_BVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_BREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_BRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIL_ARADDR": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIL_ARVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_ARREADY": [ { "direction": "out" } ],
|
||||
"S_AXIL_RDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"S_AXIL_RVALID": [ { "direction": "out" } ],
|
||||
"S_AXIL_RREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"S_AXIL_RRESP": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"S_AXIS_TVALID": [ { "direction": "in" } ],
|
||||
"S_AXIS_TDATA": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"S_AXIS_TLAST": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"S_AXIS_TREADY": [ { "direction": "out" } ],
|
||||
"M_AXIS_TVALID": [ { "direction": "out" } ],
|
||||
"M_AXIS_TDATA": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"M_AXIS_TLAST": [ { "direction": "out" } ],
|
||||
"M_AXIS_TREADY": [ { "direction": "in", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "M_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "M_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "M_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "M_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "S_AXIS_TDATA" } ],
|
||||
"TLAST": [ { "physical_name": "S_AXIS_TLAST" } ],
|
||||
"TVALID": [ { "physical_name": "S_AXIS_TVALID" } ],
|
||||
"TREADY": [ { "physical_name": "S_AXIS_TREADY" } ]
|
||||
}
|
||||
},
|
||||
"S_AXIL": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "S_AXIL_AWADDR" } ],
|
||||
"AWVALID": [ { "physical_name": "S_AXIL_AWVALID" } ],
|
||||
"AWREADY": [ { "physical_name": "S_AXIL_AWREADY" } ],
|
||||
"WDATA": [ { "physical_name": "S_AXIL_WDATA" } ],
|
||||
"WSTRB": [ { "physical_name": "S_AXIL_WSTRB" } ],
|
||||
"WVALID": [ { "physical_name": "S_AXIL_WVALID" } ],
|
||||
"WREADY": [ { "physical_name": "S_AXIL_WREADY" } ],
|
||||
"BRESP": [ { "physical_name": "S_AXIL_BRESP" } ],
|
||||
"BVALID": [ { "physical_name": "S_AXIL_BVALID" } ],
|
||||
"BREADY": [ { "physical_name": "S_AXIL_BREADY" } ],
|
||||
"ARADDR": [ { "physical_name": "S_AXIL_ARADDR" } ],
|
||||
"ARVALID": [ { "physical_name": "S_AXIL_ARVALID" } ],
|
||||
"ARREADY": [ { "physical_name": "S_AXIL_ARREADY" } ],
|
||||
"RDATA": [ { "physical_name": "S_AXIL_RDATA" } ],
|
||||
"RRESP": [ { "physical_name": "S_AXIL_RRESP" } ],
|
||||
"RVALID": [ { "physical_name": "S_AXIL_RVALID" } ],
|
||||
"RREADY": [ { "physical_name": "S_AXIL_RREADY" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "AXI_ARESETN" } ]
|
||||
}
|
||||
},
|
||||
"AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "AXI_ARESETN", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "AXI_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXIL": {
|
||||
"display_name": "S_AXIL",
|
||||
"address_blocks": {
|
||||
"reg0": {
|
||||
"base_address": "0x0",
|
||||
"range": "0x1000",
|
||||
"display_name": "reg0",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_clk_rst_generator_0_0",
|
||||
"cell_name": "clk_rst_generator_0",
|
||||
"component_reference": "wg:user:clk_rst_generator:1.0",
|
||||
"ip_revision": "7",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_clk_rst_generator_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CLOCK_PERIOD": [ { "value": "10000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_CLK_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_RESET_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"HAS_STOP_INPUT": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "7" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"rst_in": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"clk": [ { "direction": "out" } ],
|
||||
"rst_n": [ { "direction": "out" } ],
|
||||
"stop_simulation": [ { "direction": "in", "driver_value": "0x0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+4042
File diff suppressed because it is too large
Load Diff
+159
@@ -0,0 +1,159 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "design_1_zybo_audio_0_0",
|
||||
"cell_name": "zybo_audio_0",
|
||||
"component_reference": "xilinx.com:user:zybo_audio:1.0",
|
||||
"ip_revision": "22",
|
||||
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"MIC_IN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"I2C_CLKDIV": [ { "value": "9999", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"I2S_CLKDIV": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "design_1_zybo_audio_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_RESET_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SRR_70": [ { "value": "\"00000000\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"MIC_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"I2C_CLKDIV": [ { "value": "9999", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"I2S_CLKDIV": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"HAS_RESET_PIN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SRR_70": [ { "value": "\"00000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "digilentinc.com:zybo-z7-20:part0:1.2" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z020" } ],
|
||||
"PACKAGE": [ { "value": "clg400" } ],
|
||||
"PREFHDL": [ { "value": "VHDL" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "22" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"axis_pb_data": [ { "direction": "in", "size_left": "31", "size_right": "0" } ],
|
||||
"axis_pb_valid": [ { "direction": "in" } ],
|
||||
"axis_pb_ready": [ { "direction": "out" } ],
|
||||
"axis_rec_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"axis_rec_valid": [ { "direction": "out" } ],
|
||||
"axis_rec_ready": [ { "direction": "in" } ],
|
||||
"mute": [ { "direction": "out" } ],
|
||||
"mclk": [ { "direction": "out" } ],
|
||||
"bclk": [ { "direction": "out" } ],
|
||||
"pb_dat": [ { "direction": "out" } ],
|
||||
"pb_lrc": [ { "direction": "out" } ],
|
||||
"rec_dat": [ { "direction": "in" } ],
|
||||
"rec_lrc": [ { "direction": "out" } ],
|
||||
"scl_i": [ { "direction": "in" } ],
|
||||
"scl_o": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"scl_t": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"sda_i": [ { "direction": "in" } ],
|
||||
"sda_o": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"sda_t": [ { "direction": "out", "driver_value": "0x1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "axis_rec:axis_pb", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"axis_pb": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_pb_data" } ],
|
||||
"TVALID": [ { "physical_name": "axis_pb_valid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_pb_ready" } ]
|
||||
}
|
||||
},
|
||||
"axis_rec": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "axis_rec_data" } ],
|
||||
"TVALID": [ { "physical_name": "axis_rec_valid" } ],
|
||||
"TREADY": [ { "physical_name": "axis_rec_ready" } ]
|
||||
}
|
||||
},
|
||||
"i2c": {
|
||||
"vlnv": "xilinx.com:interface:iic:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:iic_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"SCL_T": [ { "physical_name": "scl_t" } ],
|
||||
"SDA_O": [ { "physical_name": "sda_o" } ],
|
||||
"SDA_I": [ { "physical_name": "sda_i" } ],
|
||||
"SCL_O": [ { "physical_name": "scl_o" } ],
|
||||
"SCL_I": [ { "physical_name": "scl_i" } ],
|
||||
"SDA_T": [ { "physical_name": "sda_t" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.85789",
|
||||
"Default View_TopLeft":"813,-59",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port port-id_clk -pg 1 -lvl 0 -x -240 -y -40 -defaultsOSRD
|
||||
preplace port port-id_resez -pg 1 -lvl 0 -x -240 -y 0 -defaultsOSRD
|
||||
preplace port port-id_rec_dat -pg 1 -lvl 0 -x -240 -y 200 -defaultsOSRD
|
||||
preplace port port-id_mute -pg 1 -lvl 6 -x 1270 -y 10 -defaultsOSRD
|
||||
preplace port port-id_mclk -pg 1 -lvl 6 -x 1270 -y 230 -defaultsOSRD
|
||||
preplace port port-id_bclk -pg 1 -lvl 6 -x 1270 -y 260 -defaultsOSRD
|
||||
preplace port port-id_pb_dat -pg 1 -lvl 6 -x 1270 -y 40 -defaultsOSRD
|
||||
preplace port port-id_pb_lrc -pg 1 -lvl 6 -x 1270 -y 300 -defaultsOSRD
|
||||
preplace port port-id_rec_lrc -pg 1 -lvl 6 -x 1270 -y 190 -defaultsOSRD
|
||||
preplace port i2c -pg 1 -lvl 6 -x 1270 -y 80 -defaultsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 600 -y -110 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -20 -y 0 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 2 -x 320 -y -90 -defaultsOSRD
|
||||
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 320 -y 110 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 4 -x 860 -y -170 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 860 -y 110 -defaultsOSRD
|
||||
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1100 -y 130 -defaultsOSRD
|
||||
preplace netloc clk_1 1 0 1 -220 -40n
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 460 0 740 190 970
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 470 -20 750
|
||||
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 980
|
||||
preplace netloc resez_1 1 0 1 N 0
|
||||
preplace netloc zybo_audio_0_bclk 1 5 1 1220 140n
|
||||
preplace netloc zybo_audio_0_mclk 1 5 1 1240 120n
|
||||
preplace netloc zybo_audio_0_mute 1 5 1 1220 10n
|
||||
preplace netloc zybo_audio_0_pb_dat 1 5 1 1230 40n
|
||||
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1210 180n
|
||||
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1250 190n
|
||||
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 440 -210 NJ
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 N 110
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 450 -200 730J
|
||||
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 730 -170n
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1210
|
||||
preplace netloc zybo_audio_0_i2c 1 5 1 N 80
|
||||
levelinfo -pg 1 -240 -20 320 600 860 1100 1270
|
||||
pagesize -pg 1 -db -bbox -sgen -340 -420 1450 560
|
||||
"
|
||||
}
|
||||
0
|
||||
@@ -48,6 +48,7 @@
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../IP"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
@@ -60,20 +61,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="zybo-z7-20"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="5"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="2"/>
|
||||
<Option Name="WTModelSimExportSim" Val="2"/>
|
||||
<Option Name="WTQuestaExportSim" Val="2"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="2"/>
|
||||
<Option Name="WTRivieraExportSim" Val="2"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="2"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -97,9 +98,22 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_prog_audio_filter3"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
@@ -117,9 +131,14 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/design_1_wrapper_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axis_prog_audio_filter3"/>
|
||||
<Option Name="TopModule" Val="design_1_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
@@ -130,6 +149,7 @@
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/design_1_wrapper_behav.wcfg"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
@@ -160,9 +180,7 @@
|
||||
<Runs Version="1" Minor="20">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
@@ -171,9 +189,7 @@
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
0000000000000000000000000000000000000001
|
||||
0000000000000000000000000000000100001111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000010000001000000001000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011011110000001000001111000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000010000000010001110000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000100000000010000010000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000010000000001
|
||||
0000011000000000010000000000000000001111
|
||||
0001011001011010000010111100000000000111
|
||||
0000000000000000000000000000000000000000
|
||||
Reference in New Issue
Block a user