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M3: Filter IP beschrieben

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This commit is contained in:
Matthias Biermann
2024-11-09 21:31:54 +01:00
parent 476e15ac75
commit c37d2dead5
2 changed files with 107 additions and 35 deletions
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Milestone3/es-milestone3/es-milestone3.xpr
+6 -2
View File
@@ -160,7 +160,9 @@
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -169,7 +171,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
Milestone3/sources/axis_audio_filter3.vhd
+101 -33
View File
@@ -57,47 +57,115 @@ end;
architecture rtl of axis_prog_audio_filter3 is
signal m_valid_sig : std_logic := '0';
-- Signale fuer AXI-Lite Register
signal ip_active : std_logic := '0';
signal c0 : signed( 7 downto 0) := to_signed(COEFF_0,8);
signal c1 : signed( 7 downto 0) := to_signed(COEFF_1,8);
signal c2 : signed( 7 downto 0) := to_signed(COEFF_2,8);
signal shift_sig : signed( 2 downto 0) := to_signed(SHIFT,3);
begin
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
S_AXIS_TREADY <= M_AXIS_TREADY or (not m_valid_sig);
process
constant c0 : signed( 7 downto 0) := to_signed(COEFF_0,8);
constant c1 : signed( 7 downto 0) := to_signed(COEFF_1,8);
constant c2 : signed( 7 downto 0) := to_signed(COEFF_2,8);
variable s0 : signed(15 downto 0) := (others=>'0');
variable s1 : signed(15 downto 0) := (others=>'0');
variable s2 : signed(15 downto 0) := (others=>'0');
variable p0 : signed(23 downto 0);
variable p1 : signed(23 downto 0);
variable p2 : signed(23 downto 0);
variable res : signed(25 downto 0);
begin
wait until rising_edge(AXI_ACLK);
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
M_AXIS_TVALID <= S_AXIS_TVALID;
S_AXIL_BRESP <= (others=>'0'); -- No write errors
S_AXIL_RRESP <= (others=>'0'); -- No read errors
S_AXIL_ARREADY <= '1'; -- IP is always ready
S_AXIL_AWREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
S_AXIL_WREADY <= S_AXIL_AWVALID and S_AXIL_WVALID;
if HAS_LAST then
M_AXIS_TLAST <= S_AXIS_TLAST;
end if;
process
variable s0 : signed(15 downto 0) := (others=>'0');
variable s1 : signed(15 downto 0) := (others=>'0');
variable s2 : signed(15 downto 0) := (others=>'0');
variable p0 : signed(23 downto 0);
variable p1 : signed(23 downto 0);
variable p2 : signed(23 downto 0);
variable res : signed(25 downto 0);
begin
wait until rising_edge(AXI_ACLK);
m_valid_sig <= S_AXIS_TVALID;
-- AXI-Stream Schnittstelle
if M_AXIS_TREADY = '1' or m_valid_sig = '0' then
M_AXIS_TVALID <= S_AXIS_TVALID;
if S_AXIS_TVALID = '1' then
s2 := s1;
s1 := s0;
s0 := signed(S_AXIS_TDATA);
if HAS_LAST then
M_AXIS_TLAST <= S_AXIS_TLAST;
end if;
p0 := s0*c0;
p1 := s1*c1;
p2 := s2*c2;
m_valid_sig <= S_AXIS_TVALID;
res := (p0(23)&p0(23)&p0);
res := res + (p1(23)&p1(23)&p1);
res := res + (p2(23)&p2(23)&p2);
if S_AXIS_TVALID = '1' then
s2 := s1;
s1 := s0;
s0 := signed(S_AXIS_TDATA);
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
end if;
end if;
p0 := s0*c0;
p1 := s1*c1;
p2 := s2*c2;
res := (p0(23)&p0(23)&p0);
res := res + (p1(23)&p1(23)&p1);
res := res + (p2(23)&p2(23)&p2);
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
end if;
end if;
-- AXI-Lite Schnittstelle
if AXI_ARESETN = '0' then
S_AXIL_BVALID <= '0';
S_AXIL_RVALID <= '0';
c0 <= to_signed(COEFF_0,8);
c1 <= to_signed(COEFF_1,8);
c2 <= to_signed(COEFF_2,8);
shift_sig <= to_signed(SHIFT,3);
ip_active <= '1';
else
-- Lesezugriff
if S_AXIL_RREADY = '1' then
S_AXIL_RVALID <= '0';
end if;
if S_AXIL_ARVALID = '1' then
S_AXIL_RDATA <= (others=>'0');
if S_AXIL_ARADDR(7 downto 0) = x"00" then
S_AXIL_RDATA(26 downto 0) <= std_logic_vector(shift_sig) & std_logic_vector(c2) & std_logic_vector(c1) & std_logic_vector(c0);
elsif S_AXIL_ARADDR(7 downto 0) = x"04" then
S_AXIL_RDATA(0) <= ip_active;
end if;
S_AXIL_RVALID <= '1';
end if;
-- Schreibzugriff
if S_AXIL_BREADY = '1' then
S_AXIL_BVALID <= '0';
end if;
if S_AXIL_AWVALID = '1' and S_AXIL_WVALID = '1' then
S_AXIL_BVALID <= '1';
-- Register schreiben
if S_AXIL_AWADDR = x"00" then
if S_AXIL_WSTRB(0) = '1' then
ip_active <= S_AXIL_WDATA(0);
end if;
elsif S_AXIL_AWADDR = x"04" then
if S_AXIL_WSTRB(0) = '1' then
c0 <= signed(S_AXIL_WDATA(7 downto 0));
end if;
if S_AXIL_WSTRB(1) = '1' then
c1 <= signed(S_AXIL_WDATA(15 downto 8));
end if;
if S_AXIL_WSTRB(2) = '1' then
c2 <= signed(S_AXIL_WDATA(23 downto 16));
end if;
if S_AXIL_WSTRB(3) = '1' then
shift_sig <= signed(S_AXIL_WDATA(26 downto 24));
end if;
end if;
end if;
end if;
end process;
end;