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M3: Fehler bei Shiftsignal behoben

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This commit is contained in:
Matthias Biermann
2024-11-22 17:09:48 +01:00
parent ca3c571813
commit 5134bdb0ee
65 changed files with 177403 additions and 104364 deletions
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml
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@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732118291"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732118291"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732118291"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732118291"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
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@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Nov 10 17:21:44 2024
--Date : Wed Nov 20 16:57:58 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
@@ -24,7 +24,7 @@ entity design_1_wrapper is
pb_lrc : out STD_LOGIC;
rec_dat : in STD_LOGIC;
rec_lrc : out STD_LOGIC;
resez : in STD_LOGIC
reset : in STD_LOGIC
);
end design_1_wrapper;
@@ -38,7 +38,7 @@ architecture STRUCTURE of design_1_wrapper is
i2c_scl_i : in STD_LOGIC;
i2c_sda_t : out STD_LOGIC;
clk : in STD_LOGIC;
resez : in STD_LOGIC;
reset : in STD_LOGIC;
rec_dat : in STD_LOGIC;
mute : out STD_LOGIC;
mclk : out STD_LOGIC;
@@ -79,7 +79,7 @@ design_1_i: component design_1
pb_lrc => pb_lrc,
rec_dat => rec_dat,
rec_lrc => rec_lrc,
resez => resez
reset => reset
);
i2c_scl_iobuf: component IOBUF
port map (
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
+7 -7
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 10 17:21:50 2024" VIVADOVERSION="2023.1">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Nov 20 16:58:10 2024" VIVADOVERSION="2023.1">
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -39,7 +39,7 @@
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk_in"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="resez" SIGIS="undef" SIGNAME="External_Ports_resez">
<PORT DIR="I" NAME="reset" SIGIS="undef" SIGNAME="External_Ports_reset">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_rst_generator_0" PORT="rst_in"/>
</CONNECTIONS>
@@ -693,26 +693,26 @@
<CONNECTION INSTANCE="External_Ports" PORT="clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="rst_in" SIGIS="undef" SIGNAME="External_Ports_resez">
<PORT DIR="I" NAME="rst_in" SIGIS="undef" SIGNAME="External_Ports_reset">
<CONNECTIONS>
<CONNECTION INSTANCE="External_Ports" PORT="resez"/>
<CONNECTION INSTANCE="External_Ports" PORT="reset"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="clk" SIGIS="undef" SIGNAME="clk_rst_generator_0_clk">
<CONNECTIONS>
<CONNECTION INSTANCE="axis_audio_stereo2mo_0" PORT="AXIS_ACLK"/>
<CONNECTION INSTANCE="axil_master_with_rom_0" PORT="M_AXIL_ACLK"/>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ACLK"/>
<CONNECTION INSTANCE="axis_audio_mono2ster_0" PORT="AXIS_ACLK"/>
<CONNECTION INSTANCE="zybo_audio_0" PORT="clk"/>
<CONNECTION INSTANCE="system_ila_0" PORT="clk"/>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ACLK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="rst_n" SIGIS="undef" SIGNAME="clk_rst_generator_0_rst_n">
<CONNECTIONS>
<CONNECTION INSTANCE="axil_master_with_rom_0" PORT="M_AXIL_ARESETN"/>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ARESETN"/>
<CONNECTION INSTANCE="system_ila_0" PORT="resetn"/>
<CONNECTION INSTANCE="axis_prog_audio_filt_0" PORT="AXI_ARESETN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="stop_simulation" SIGIS="undef"/>
@@ -3287,7 +3287,7 @@
<PARAMETER NAME="C_PROBE2_WIDTH" VALUE="1"/>
<PARAMETER NAME="C_PROBE1_WIDTH" VALUE="1"/>
<PARAMETER NAME="C_PROBE0_WIDTH" VALUE="1"/>
<PARAMETER NAME="C_DATA_DEPTH" VALUE="1024"/>
<PARAMETER NAME="C_DATA_DEPTH" VALUE="16384"/>
<PARAMETER NAME="C_NUM_OF_PROBES" VALUE="1"/>
<PARAMETER NAME="C_XLNX_HW_PROBE_INFO" VALUE="DEFAULT"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_system_ila_0_0"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
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@@ -612,6 +612,10 @@
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:48:16 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:45b54a85</spirit:value>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_sim_netlist.v
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_sim_netlist.vhdl
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.v
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@@ -0,0 +1,47 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:41:13 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axil_master_with_rom_0_0 -prefix
// design_1_axil_master_with_rom_0_0_ design_1_axil_master_with_rom_0_0_stub.v
// Design : design_1_axil_master_with_rom_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axil_master_with_rom,Vivado 2023.1" *)
module design_1_axil_master_with_rom_0_0(interrupt_in, M_AXIL_ACLK, M_AXIL_ARESETN,
M_AXIL_ARREADY, M_AXIL_ARVALID, M_AXIL_ARADDR, M_AXIL_ARPROT, M_AXIL_RREADY, M_AXIL_RVALID,
M_AXIL_RDATA, M_AXIL_RRESP, M_AXIL_AWREADY, M_AXIL_AWVALID, M_AXIL_AWADDR, M_AXIL_AWPROT,
M_AXIL_WREADY, M_AXIL_WVALID, M_AXIL_WDATA, M_AXIL_WSTRB, M_AXIL_BREADY, M_AXIL_BVALID,
M_AXIL_BRESP)
/* synthesis syn_black_box black_box_pad_pin="interrupt_in,M_AXIL_ARESETN,M_AXIL_ARREADY,M_AXIL_ARVALID,M_AXIL_ARADDR[31:0],M_AXIL_ARPROT[2:0],M_AXIL_RREADY,M_AXIL_RVALID,M_AXIL_RDATA[31:0],M_AXIL_RRESP[1:0],M_AXIL_AWREADY,M_AXIL_AWVALID,M_AXIL_AWADDR[31:0],M_AXIL_AWPROT[2:0],M_AXIL_WREADY,M_AXIL_WVALID,M_AXIL_WDATA[31:0],M_AXIL_WSTRB[3:0],M_AXIL_BREADY,M_AXIL_BVALID,M_AXIL_BRESP[1:0]" */
/* synthesis syn_force_seq_prim="M_AXIL_ACLK" */;
input interrupt_in;
input M_AXIL_ACLK /* synthesis syn_isclock = 1 */;
input M_AXIL_ARESETN;
input M_AXIL_ARREADY;
output M_AXIL_ARVALID;
output [31:0]M_AXIL_ARADDR;
output [2:0]M_AXIL_ARPROT;
output M_AXIL_RREADY;
input M_AXIL_RVALID;
input [31:0]M_AXIL_RDATA;
input [1:0]M_AXIL_RRESP;
input M_AXIL_AWREADY;
output M_AXIL_AWVALID;
output [31:0]M_AXIL_AWADDR;
output [2:0]M_AXIL_AWPROT;
input M_AXIL_WREADY;
output M_AXIL_WVALID;
output [31:0]M_AXIL_WDATA;
output [3:0]M_AXIL_WSTRB;
output M_AXIL_BREADY;
input M_AXIL_BVALID;
input [1:0]M_AXIL_BRESP;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0_stub.vhdl
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@@ -0,0 +1,52 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:41:13 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_axil_master_with_rom_0_0 -prefix
-- design_1_axil_master_with_rom_0_0_ design_1_axil_master_with_rom_0_0_stub.vhdl
-- Design : design_1_axil_master_with_rom_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axil_master_with_rom_0_0 is
Port (
interrupt_in : in STD_LOGIC;
M_AXIL_ACLK : in STD_LOGIC;
M_AXIL_ARESETN : in STD_LOGIC;
M_AXIL_ARREADY : in STD_LOGIC;
M_AXIL_ARVALID : out STD_LOGIC;
M_AXIL_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_RREADY : out STD_LOGIC;
M_AXIL_RVALID : in STD_LOGIC;
M_AXIL_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXIL_AWREADY : in STD_LOGIC;
M_AXIL_AWVALID : out STD_LOGIC;
M_AXIL_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXIL_WREADY : in STD_LOGIC;
M_AXIL_WVALID : out STD_LOGIC;
M_AXIL_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIL_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXIL_BREADY : out STD_LOGIC;
M_AXIL_BVALID : in STD_LOGIC;
M_AXIL_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end design_1_axil_master_with_rom_0_0;
architecture stub of design_1_axil_master_with_rom_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "interrupt_in,M_AXIL_ACLK,M_AXIL_ARESETN,M_AXIL_ARREADY,M_AXIL_ARVALID,M_AXIL_ARADDR[31:0],M_AXIL_ARPROT[2:0],M_AXIL_RREADY,M_AXIL_RVALID,M_AXIL_RDATA[31:0],M_AXIL_RRESP[1:0],M_AXIL_AWREADY,M_AXIL_AWVALID,M_AXIL_AWADDR[31:0],M_AXIL_AWPROT[2:0],M_AXIL_WREADY,M_AXIL_WVALID,M_AXIL_WDATA[31:0],M_AXIL_WSTRB[3:0],M_AXIL_BREADY,M_AXIL_BVALID,M_AXIL_BRESP[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axil_master_with_rom,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml
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@@ -457,6 +457,10 @@
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:48:42 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:2c94a4ed</spirit:value>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_sim_netlist.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:37 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
// design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_sim_netlist.v
// Design : design_1_axis_audio_mono2ster_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* HAS_LAST = "FALSE" *)
module design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TLAST,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TREADY);
input AXIS_ACLK;
input S_AXIS_TVALID;
input [15:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [31:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
wire \<const0> ;
wire M_AXIS_TREADY;
wire [15:0]S_AXIS_TDATA;
wire S_AXIS_TVALID;
assign M_AXIS_TDATA[31:16] = S_AXIS_TDATA;
assign M_AXIS_TDATA[15:0] = S_AXIS_TDATA;
assign M_AXIS_TLAST = \<const0> ;
assign M_AXIS_TVALID = S_AXIS_TVALID;
assign S_AXIS_TREADY = M_AXIS_TREADY;
GND GND
(.G(\<const0> ));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_axis_audio_mono2ster_0_0
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TREADY);
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [15:0]S_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [31:0]M_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
wire [31:0]M_AXIS_TDATA;
wire M_AXIS_TREADY;
wire M_AXIS_TVALID;
wire [15:0]S_AXIS_TDATA;
wire S_AXIS_TREADY;
wire S_AXIS_TVALID;
wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
(* HAS_LAST = "FALSE" *)
design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo U0
(.AXIS_ACLK(1'b0),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TLAST(1'b0),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TVALID(S_AXIS_TVALID));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_sim_netlist.vhdl
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@@ -0,0 +1,108 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:37 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
-- design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_sim_netlist.vhdl
-- Design : design_1_axis_audio_mono2ster_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
attribute HAS_LAST : string;
attribute HAS_LAST of design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo : entity is "FALSE";
end design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo;
architecture STRUCTURE of design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo is
signal \<const0>\ : STD_LOGIC;
signal \^m_axis_tready\ : STD_LOGIC;
signal \^s_axis_tdata\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^s_axis_tvalid\ : STD_LOGIC;
begin
M_AXIS_TDATA(31 downto 16) <= \^s_axis_tdata\(15 downto 0);
M_AXIS_TDATA(15 downto 0) <= \^s_axis_tdata\(15 downto 0);
M_AXIS_TLAST <= \<const0>\;
M_AXIS_TVALID <= \^s_axis_tvalid\;
S_AXIS_TREADY <= \^m_axis_tready\;
\^m_axis_tready\ <= M_AXIS_TREADY;
\^s_axis_tdata\(15 downto 0) <= S_AXIS_TDATA(15 downto 0);
\^s_axis_tvalid\ <= S_AXIS_TVALID;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_mono2ster_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_axis_audio_mono2ster_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_axis_audio_mono2ster_0_0 : entity is "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_axis_audio_mono2ster_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of design_1_axis_audio_mono2ster_0_0 : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of design_1_axis_audio_mono2ster_0_0 : entity is "axis_audio_mono2stereo,Vivado 2023.1";
end design_1_axis_audio_mono2ster_0_0;
architecture STRUCTURE of design_1_axis_audio_mono2ster_0_0 is
signal NLW_U0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
attribute HAS_LAST : string;
attribute HAS_LAST of U0 : label is "FALSE";
attribute x_interface_info : string;
attribute x_interface_info of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
attribute x_interface_info of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
attribute x_interface_parameter of M_AXIS_TVALID : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
attribute x_interface_info of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
attribute x_interface_parameter of S_AXIS_TVALID : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
attribute x_interface_info of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
begin
U0: entity work.design_1_axis_audio_mono2ster_0_0_axis_audio_mono2stereo
port map (
AXIS_ACLK => '0',
M_AXIS_TDATA(31 downto 0) => M_AXIS_TDATA(31 downto 0),
M_AXIS_TLAST => NLW_U0_M_AXIS_TLAST_UNCONNECTED,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
S_AXIS_TDATA(15 downto 0) => S_AXIS_TDATA(15 downto 0),
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TVALID => S_AXIS_TVALID
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:37 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
// design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_stub.v
// Design : design_1_axis_audio_mono2ster_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_audio_mono2stereo,Vivado 2023.1" *)
module design_1_axis_audio_mono2ster_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA,
S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
/* synthesis syn_black_box black_box_pad_pin="AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY" */;
input AXIS_ACLK;
input S_AXIS_TVALID;
input [15:0]S_AXIS_TDATA;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [31:0]M_AXIS_TDATA;
input M_AXIS_TREADY;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:37 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_axis_audio_mono2ster_0_0 -prefix
-- design_1_axis_audio_mono2ster_0_0_ design_1_axis_audio_mono2ster_0_0_stub.vhdl
-- Design : design_1_axis_audio_mono2ster_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axis_audio_mono2ster_0_0 is
Port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end design_1_axis_audio_mono2ster_0_0;
architecture stub of design_1_axis_audio_mono2ster_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[31:0],M_AXIS_TREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_audio_mono2stereo,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml
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<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:49:04 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:fcf1b95b</spirit:value>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_sim_netlist.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:47 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
// design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_sim_netlist.v
// Design : design_1_axis_audio_stereo2mo_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* HAS_LAST = "FALSE" *)
module design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TLAST,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TLAST,
M_AXIS_TREADY);
input AXIS_ACLK;
input S_AXIS_TVALID;
input [31:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [15:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
wire \<const0> ;
wire AXIS_ACLK;
wire [15:0]M_AXIS_TDATA;
wire \M_AXIS_TDATA[11]_i_2_n_0 ;
wire \M_AXIS_TDATA[11]_i_3_n_0 ;
wire \M_AXIS_TDATA[11]_i_4_n_0 ;
wire \M_AXIS_TDATA[11]_i_5_n_0 ;
wire \M_AXIS_TDATA[15]_i_2_n_0 ;
wire \M_AXIS_TDATA[15]_i_3_n_0 ;
wire \M_AXIS_TDATA[15]_i_4_n_0 ;
wire \M_AXIS_TDATA[15]_i_5_n_0 ;
wire \M_AXIS_TDATA[3]_i_2_n_0 ;
wire \M_AXIS_TDATA[3]_i_3_n_0 ;
wire \M_AXIS_TDATA[3]_i_4_n_0 ;
wire \M_AXIS_TDATA[3]_i_5_n_0 ;
wire \M_AXIS_TDATA[7]_i_2_n_0 ;
wire \M_AXIS_TDATA[7]_i_3_n_0 ;
wire \M_AXIS_TDATA[7]_i_4_n_0 ;
wire \M_AXIS_TDATA[7]_i_5_n_0 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_0 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[11]_i_1_n_3 ;
wire \M_AXIS_TDATA_reg[15]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[15]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[15]_i_1_n_3 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_0 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[3]_i_1_n_3 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_0 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_1 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_2 ;
wire \M_AXIS_TDATA_reg[7]_i_1_n_3 ;
wire M_AXIS_TREADY;
wire M_AXIS_TVALID;
wire [31:0]S_AXIS_TDATA;
wire S_AXIS_TREADY;
wire S_AXIS_TVALID;
wire [15:0]p_0_in;
wire [3:3]\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED ;
assign M_AXIS_TLAST = \<const0> ;
GND GND
(.G(\<const0> ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_2
(.I0(S_AXIS_TDATA[28]),
.I1(S_AXIS_TDATA[12]),
.O(\M_AXIS_TDATA[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_3
(.I0(S_AXIS_TDATA[27]),
.I1(S_AXIS_TDATA[11]),
.O(\M_AXIS_TDATA[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_4
(.I0(S_AXIS_TDATA[26]),
.I1(S_AXIS_TDATA[10]),
.O(\M_AXIS_TDATA[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[11]_i_5
(.I0(S_AXIS_TDATA[25]),
.I1(S_AXIS_TDATA[9]),
.O(\M_AXIS_TDATA[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\M_AXIS_TDATA[15]_i_2
(.I0(S_AXIS_TDATA[31]),
.O(\M_AXIS_TDATA[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[15]_i_3
(.I0(S_AXIS_TDATA[31]),
.I1(S_AXIS_TDATA[15]),
.O(\M_AXIS_TDATA[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[15]_i_4
(.I0(S_AXIS_TDATA[30]),
.I1(S_AXIS_TDATA[14]),
.O(\M_AXIS_TDATA[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[15]_i_5
(.I0(S_AXIS_TDATA[29]),
.I1(S_AXIS_TDATA[13]),
.O(\M_AXIS_TDATA[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_2
(.I0(S_AXIS_TDATA[20]),
.I1(S_AXIS_TDATA[4]),
.O(\M_AXIS_TDATA[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_3
(.I0(S_AXIS_TDATA[19]),
.I1(S_AXIS_TDATA[3]),
.O(\M_AXIS_TDATA[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_4
(.I0(S_AXIS_TDATA[18]),
.I1(S_AXIS_TDATA[2]),
.O(\M_AXIS_TDATA[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[3]_i_5
(.I0(S_AXIS_TDATA[17]),
.I1(S_AXIS_TDATA[1]),
.O(\M_AXIS_TDATA[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_2
(.I0(S_AXIS_TDATA[24]),
.I1(S_AXIS_TDATA[8]),
.O(\M_AXIS_TDATA[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_3
(.I0(S_AXIS_TDATA[23]),
.I1(S_AXIS_TDATA[7]),
.O(\M_AXIS_TDATA[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_4
(.I0(S_AXIS_TDATA[22]),
.I1(S_AXIS_TDATA[6]),
.O(\M_AXIS_TDATA[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\M_AXIS_TDATA[7]_i_5
(.I0(S_AXIS_TDATA[21]),
.I1(S_AXIS_TDATA[5]),
.O(\M_AXIS_TDATA[7]_i_5_n_0 ));
FDRE \M_AXIS_TDATA_reg[0]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[0]),
.Q(M_AXIS_TDATA[0]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[10]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[10]),
.Q(M_AXIS_TDATA[10]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[11]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[11]),
.Q(M_AXIS_TDATA[11]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[11]_i_1
(.CI(\M_AXIS_TDATA_reg[7]_i_1_n_0 ),
.CO({\M_AXIS_TDATA_reg[11]_i_1_n_0 ,\M_AXIS_TDATA_reg[11]_i_1_n_1 ,\M_AXIS_TDATA_reg[11]_i_1_n_2 ,\M_AXIS_TDATA_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(S_AXIS_TDATA[28:25]),
.O(p_0_in[11:8]),
.S({\M_AXIS_TDATA[11]_i_2_n_0 ,\M_AXIS_TDATA[11]_i_3_n_0 ,\M_AXIS_TDATA[11]_i_4_n_0 ,\M_AXIS_TDATA[11]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[12]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[12]),
.Q(M_AXIS_TDATA[12]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[13]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[13]),
.Q(M_AXIS_TDATA[13]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[14]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[14]),
.Q(M_AXIS_TDATA[14]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[15]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[15]),
.Q(M_AXIS_TDATA[15]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[15]_i_1
(.CI(\M_AXIS_TDATA_reg[11]_i_1_n_0 ),
.CO({\NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED [3],\M_AXIS_TDATA_reg[15]_i_1_n_1 ,\M_AXIS_TDATA_reg[15]_i_1_n_2 ,\M_AXIS_TDATA_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\M_AXIS_TDATA[15]_i_2_n_0 ,S_AXIS_TDATA[30:29]}),
.O(p_0_in[15:12]),
.S({1'b1,\M_AXIS_TDATA[15]_i_3_n_0 ,\M_AXIS_TDATA[15]_i_4_n_0 ,\M_AXIS_TDATA[15]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[1]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[1]),
.Q(M_AXIS_TDATA[1]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[2]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[2]),
.Q(M_AXIS_TDATA[2]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[3]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[3]),
.Q(M_AXIS_TDATA[3]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[3]_i_1
(.CI(1'b0),
.CO({\M_AXIS_TDATA_reg[3]_i_1_n_0 ,\M_AXIS_TDATA_reg[3]_i_1_n_1 ,\M_AXIS_TDATA_reg[3]_i_1_n_2 ,\M_AXIS_TDATA_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(S_AXIS_TDATA[20:17]),
.O(p_0_in[3:0]),
.S({\M_AXIS_TDATA[3]_i_2_n_0 ,\M_AXIS_TDATA[3]_i_3_n_0 ,\M_AXIS_TDATA[3]_i_4_n_0 ,\M_AXIS_TDATA[3]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[4]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[4]),
.Q(M_AXIS_TDATA[4]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[5]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[5]),
.Q(M_AXIS_TDATA[5]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[6]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[6]),
.Q(M_AXIS_TDATA[6]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[7]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[7]),
.Q(M_AXIS_TDATA[7]),
.R(1'b0));
CARRY4 \M_AXIS_TDATA_reg[7]_i_1
(.CI(\M_AXIS_TDATA_reg[3]_i_1_n_0 ),
.CO({\M_AXIS_TDATA_reg[7]_i_1_n_0 ,\M_AXIS_TDATA_reg[7]_i_1_n_1 ,\M_AXIS_TDATA_reg[7]_i_1_n_2 ,\M_AXIS_TDATA_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(S_AXIS_TDATA[24:21]),
.O(p_0_in[7:4]),
.S({\M_AXIS_TDATA[7]_i_2_n_0 ,\M_AXIS_TDATA[7]_i_3_n_0 ,\M_AXIS_TDATA[7]_i_4_n_0 ,\M_AXIS_TDATA[7]_i_5_n_0 }));
FDRE \M_AXIS_TDATA_reg[8]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[8]),
.Q(M_AXIS_TDATA[8]),
.R(1'b0));
FDRE \M_AXIS_TDATA_reg[9]
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(p_0_in[9]),
.Q(M_AXIS_TDATA[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
M_AXIS_TVALID_reg
(.C(AXIS_ACLK),
.CE(S_AXIS_TREADY),
.D(S_AXIS_TVALID),
.Q(M_AXIS_TVALID),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
S_AXIS_TREADY_INST_0
(.I0(M_AXIS_TREADY),
.I1(M_AXIS_TVALID),
.O(S_AXIS_TREADY));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_axis_audio_stereo2mo_0_0
(AXIS_ACLK,
S_AXIS_TVALID,
S_AXIS_TDATA,
S_AXIS_TREADY,
M_AXIS_TVALID,
M_AXIS_TDATA,
M_AXIS_TREADY);
(* x_interface_info = "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input AXIS_ACLK;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input S_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input [31:0]S_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output S_AXIS_TREADY;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output M_AXIS_TVALID;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output [15:0]M_AXIS_TDATA;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input M_AXIS_TREADY;
wire AXIS_ACLK;
wire [15:0]M_AXIS_TDATA;
wire M_AXIS_TREADY;
wire M_AXIS_TVALID;
wire [31:0]S_AXIS_TDATA;
wire S_AXIS_TREADY;
wire S_AXIS_TVALID;
wire NLW_U0_M_AXIS_TLAST_UNCONNECTED;
(* HAS_LAST = "FALSE" *)
design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono U0
(.AXIS_ACLK(AXIS_ACLK),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TLAST(NLW_U0_M_AXIS_TLAST_UNCONNECTED),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.S_AXIS_TDATA({S_AXIS_TDATA[31:17],1'b0,S_AXIS_TDATA[15:1],1'b0}),
.S_AXIS_TLAST(1'b0),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TVALID(S_AXIS_TVALID));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_sim_netlist.vhdl
+491
View File
@@ -0,0 +1,491 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:47 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
-- design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_sim_netlist.vhdl
-- Design : design_1_axis_audio_stereo2mo_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
attribute HAS_LAST : string;
attribute HAS_LAST of design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono : entity is "FALSE";
end design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono;
architecture STRUCTURE of design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono is
signal \<const0>\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[11]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[15]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[3]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_2_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_3_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_4_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA[7]_i_5_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \M_AXIS_TDATA_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \^m_axis_tvalid\ : STD_LOGIC;
signal \^s_axis_tready\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
M_AXIS_TLAST <= \<const0>\;
M_AXIS_TVALID <= \^m_axis_tvalid\;
S_AXIS_TREADY <= \^s_axis_tready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\M_AXIS_TDATA[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(28),
I1 => S_AXIS_TDATA(12),
O => \M_AXIS_TDATA[11]_i_2_n_0\
);
\M_AXIS_TDATA[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(27),
I1 => S_AXIS_TDATA(11),
O => \M_AXIS_TDATA[11]_i_3_n_0\
);
\M_AXIS_TDATA[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(26),
I1 => S_AXIS_TDATA(10),
O => \M_AXIS_TDATA[11]_i_4_n_0\
);
\M_AXIS_TDATA[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(25),
I1 => S_AXIS_TDATA(9),
O => \M_AXIS_TDATA[11]_i_5_n_0\
);
\M_AXIS_TDATA[15]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => S_AXIS_TDATA(31),
O => \M_AXIS_TDATA[15]_i_2_n_0\
);
\M_AXIS_TDATA[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(31),
I1 => S_AXIS_TDATA(15),
O => \M_AXIS_TDATA[15]_i_3_n_0\
);
\M_AXIS_TDATA[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(30),
I1 => S_AXIS_TDATA(14),
O => \M_AXIS_TDATA[15]_i_4_n_0\
);
\M_AXIS_TDATA[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(29),
I1 => S_AXIS_TDATA(13),
O => \M_AXIS_TDATA[15]_i_5_n_0\
);
\M_AXIS_TDATA[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(20),
I1 => S_AXIS_TDATA(4),
O => \M_AXIS_TDATA[3]_i_2_n_0\
);
\M_AXIS_TDATA[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(19),
I1 => S_AXIS_TDATA(3),
O => \M_AXIS_TDATA[3]_i_3_n_0\
);
\M_AXIS_TDATA[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(18),
I1 => S_AXIS_TDATA(2),
O => \M_AXIS_TDATA[3]_i_4_n_0\
);
\M_AXIS_TDATA[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(17),
I1 => S_AXIS_TDATA(1),
O => \M_AXIS_TDATA[3]_i_5_n_0\
);
\M_AXIS_TDATA[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(24),
I1 => S_AXIS_TDATA(8),
O => \M_AXIS_TDATA[7]_i_2_n_0\
);
\M_AXIS_TDATA[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(23),
I1 => S_AXIS_TDATA(7),
O => \M_AXIS_TDATA[7]_i_3_n_0\
);
\M_AXIS_TDATA[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(22),
I1 => S_AXIS_TDATA(6),
O => \M_AXIS_TDATA[7]_i_4_n_0\
);
\M_AXIS_TDATA[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => S_AXIS_TDATA(21),
I1 => S_AXIS_TDATA(5),
O => \M_AXIS_TDATA[7]_i_5_n_0\
);
\M_AXIS_TDATA_reg[0]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(0),
Q => M_AXIS_TDATA(0),
R => '0'
);
\M_AXIS_TDATA_reg[10]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(10),
Q => M_AXIS_TDATA(10),
R => '0'
);
\M_AXIS_TDATA_reg[11]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(11),
Q => M_AXIS_TDATA(11),
R => '0'
);
\M_AXIS_TDATA_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \M_AXIS_TDATA_reg[7]_i_1_n_0\,
CO(3) => \M_AXIS_TDATA_reg[11]_i_1_n_0\,
CO(2) => \M_AXIS_TDATA_reg[11]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[11]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => S_AXIS_TDATA(28 downto 25),
O(3 downto 0) => p_0_in(11 downto 8),
S(3) => \M_AXIS_TDATA[11]_i_2_n_0\,
S(2) => \M_AXIS_TDATA[11]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[11]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[11]_i_5_n_0\
);
\M_AXIS_TDATA_reg[12]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(12),
Q => M_AXIS_TDATA(12),
R => '0'
);
\M_AXIS_TDATA_reg[13]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(13),
Q => M_AXIS_TDATA(13),
R => '0'
);
\M_AXIS_TDATA_reg[14]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(14),
Q => M_AXIS_TDATA(14),
R => '0'
);
\M_AXIS_TDATA_reg[15]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(15),
Q => M_AXIS_TDATA(15),
R => '0'
);
\M_AXIS_TDATA_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \M_AXIS_TDATA_reg[11]_i_1_n_0\,
CO(3) => \NLW_M_AXIS_TDATA_reg[15]_i_1_CO_UNCONNECTED\(3),
CO(2) => \M_AXIS_TDATA_reg[15]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[15]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \M_AXIS_TDATA[15]_i_2_n_0\,
DI(1 downto 0) => S_AXIS_TDATA(30 downto 29),
O(3 downto 0) => p_0_in(15 downto 12),
S(3) => '1',
S(2) => \M_AXIS_TDATA[15]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[15]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[15]_i_5_n_0\
);
\M_AXIS_TDATA_reg[1]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(1),
Q => M_AXIS_TDATA(1),
R => '0'
);
\M_AXIS_TDATA_reg[2]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(2),
Q => M_AXIS_TDATA(2),
R => '0'
);
\M_AXIS_TDATA_reg[3]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(3),
Q => M_AXIS_TDATA(3),
R => '0'
);
\M_AXIS_TDATA_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \M_AXIS_TDATA_reg[3]_i_1_n_0\,
CO(2) => \M_AXIS_TDATA_reg[3]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[3]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => S_AXIS_TDATA(20 downto 17),
O(3 downto 0) => p_0_in(3 downto 0),
S(3) => \M_AXIS_TDATA[3]_i_2_n_0\,
S(2) => \M_AXIS_TDATA[3]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[3]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[3]_i_5_n_0\
);
\M_AXIS_TDATA_reg[4]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(4),
Q => M_AXIS_TDATA(4),
R => '0'
);
\M_AXIS_TDATA_reg[5]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(5),
Q => M_AXIS_TDATA(5),
R => '0'
);
\M_AXIS_TDATA_reg[6]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(6),
Q => M_AXIS_TDATA(6),
R => '0'
);
\M_AXIS_TDATA_reg[7]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(7),
Q => M_AXIS_TDATA(7),
R => '0'
);
\M_AXIS_TDATA_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \M_AXIS_TDATA_reg[3]_i_1_n_0\,
CO(3) => \M_AXIS_TDATA_reg[7]_i_1_n_0\,
CO(2) => \M_AXIS_TDATA_reg[7]_i_1_n_1\,
CO(1) => \M_AXIS_TDATA_reg[7]_i_1_n_2\,
CO(0) => \M_AXIS_TDATA_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => S_AXIS_TDATA(24 downto 21),
O(3 downto 0) => p_0_in(7 downto 4),
S(3) => \M_AXIS_TDATA[7]_i_2_n_0\,
S(2) => \M_AXIS_TDATA[7]_i_3_n_0\,
S(1) => \M_AXIS_TDATA[7]_i_4_n_0\,
S(0) => \M_AXIS_TDATA[7]_i_5_n_0\
);
\M_AXIS_TDATA_reg[8]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(8),
Q => M_AXIS_TDATA(8),
R => '0'
);
\M_AXIS_TDATA_reg[9]\: unisim.vcomponents.FDRE
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => p_0_in(9),
Q => M_AXIS_TDATA(9),
R => '0'
);
M_AXIS_TVALID_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => AXIS_ACLK,
CE => \^s_axis_tready\,
D => S_AXIS_TVALID,
Q => \^m_axis_tvalid\,
R => '0'
);
S_AXIS_TREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => M_AXIS_TREADY,
I1 => \^m_axis_tvalid\,
O => \^s_axis_tready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axis_audio_stereo2mo_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_axis_audio_stereo2mo_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_axis_audio_stereo2mo_0_0 : entity is "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_axis_audio_stereo2mo_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of design_1_axis_audio_stereo2mo_0_0 : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of design_1_axis_audio_stereo2mo_0_0 : entity is "axis_audio_stereo2mono,Vivado 2023.1";
end design_1_axis_audio_stereo2mo_0_0;
architecture STRUCTURE of design_1_axis_audio_stereo2mo_0_0 is
signal NLW_U0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
attribute HAS_LAST : string;
attribute HAS_LAST of U0 : label is "FALSE";
attribute x_interface_info : string;
attribute x_interface_info of AXIS_ACLK : signal is "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXIS_ACLK : signal is "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
attribute x_interface_info of M_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
attribute x_interface_parameter of M_AXIS_TVALID : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of S_AXIS_TREADY : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
attribute x_interface_info of S_AXIS_TVALID : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
attribute x_interface_parameter of S_AXIS_TVALID : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
attribute x_interface_info of M_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
attribute x_interface_info of S_AXIS_TDATA : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
begin
U0: entity work.design_1_axis_audio_stereo2mo_0_0_axis_audio_stereo2mono
port map (
AXIS_ACLK => AXIS_ACLK,
M_AXIS_TDATA(15 downto 0) => M_AXIS_TDATA(15 downto 0),
M_AXIS_TLAST => NLW_U0_M_AXIS_TLAST_UNCONNECTED,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TVALID => M_AXIS_TVALID,
S_AXIS_TDATA(31 downto 17) => S_AXIS_TDATA(31 downto 17),
S_AXIS_TDATA(16) => '0',
S_AXIS_TDATA(15 downto 1) => S_AXIS_TDATA(15 downto 1),
S_AXIS_TDATA(0) => '0',
S_AXIS_TLAST => '0',
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TVALID => S_AXIS_TVALID
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:47 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
// design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_stub.v
// Design : design_1_axis_audio_stereo2mo_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_audio_stereo2mono,Vivado 2023.1" *)
module design_1_axis_audio_stereo2mo_0_0(AXIS_ACLK, S_AXIS_TVALID, S_AXIS_TDATA,
S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TREADY)
/* synthesis syn_black_box black_box_pad_pin="S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY" */
/* synthesis syn_force_seq_prim="AXIS_ACLK" */;
input AXIS_ACLK /* synthesis syn_isclock = 1 */;
input S_AXIS_TVALID;
input [31:0]S_AXIS_TDATA;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [15:0]M_AXIS_TDATA;
input M_AXIS_TREADY;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:47 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_axis_audio_stereo2mo_0_0 -prefix
-- design_1_axis_audio_stereo2mo_0_0_ design_1_axis_audio_stereo2mo_0_0_stub.vhdl
-- Design : design_1_axis_audio_stereo2mo_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axis_audio_stereo2mo_0_0 is
Port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end design_1_axis_audio_stereo2mo_0_0;
architecture stub of design_1_axis_audio_stereo2mo_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "AXIS_ACLK,S_AXIS_TVALID,S_AXIS_TDATA[31:0],S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_audio_stereo2mono,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml
+6 -2
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<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 16:00:07 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
@@ -944,7 +948,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:10 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -964,7 +968,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:10 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_sim_netlist.v
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Wed Nov 20 17:00:07 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.v
// Design : design_1_axis_prog_audio_filt_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_prog_audio_filter3,Vivado 2023.1" *)
module design_1_axis_prog_audio_filt_0_1(AXI_ACLK, AXI_ARESETN, S_AXIL_AWADDR,
S_AXIL_AWVALID, S_AXIL_AWREADY, S_AXIL_WDATA, S_AXIL_WVALID, S_AXIL_WREADY, S_AXIL_WSTRB,
S_AXIL_BVALID, S_AXIL_BREADY, S_AXIL_BRESP, S_AXIL_ARADDR, S_AXIL_ARVALID, S_AXIL_ARREADY,
S_AXIL_RDATA, S_AXIL_RVALID, S_AXIL_RREADY, S_AXIL_RRESP, S_AXIS_TVALID, S_AXIS_TDATA,
S_AXIS_TLAST, S_AXIS_TREADY, M_AXIS_TVALID, M_AXIS_TDATA, M_AXIS_TLAST, M_AXIS_TREADY)
/* synthesis syn_black_box black_box_pad_pin="AXI_ARESETN,S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY" */
/* synthesis syn_force_seq_prim="AXI_ACLK" */;
input AXI_ACLK /* synthesis syn_isclock = 1 */;
input AXI_ARESETN;
input [7:0]S_AXIL_AWADDR;
input S_AXIL_AWVALID;
output S_AXIL_AWREADY;
input [31:0]S_AXIL_WDATA;
input S_AXIL_WVALID;
output S_AXIL_WREADY;
input [3:0]S_AXIL_WSTRB;
output S_AXIL_BVALID;
input S_AXIL_BREADY;
output [1:0]S_AXIL_BRESP;
input [7:0]S_AXIL_ARADDR;
input S_AXIL_ARVALID;
output S_AXIL_ARREADY;
output [31:0]S_AXIL_RDATA;
output S_AXIL_RVALID;
input S_AXIL_RREADY;
output [1:0]S_AXIL_RRESP;
input S_AXIS_TVALID;
input [15:0]S_AXIS_TDATA;
input S_AXIS_TLAST;
output S_AXIS_TREADY;
output M_AXIS_TVALID;
output [15:0]M_AXIS_TDATA;
output M_AXIS_TLAST;
input M_AXIS_TREADY;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Wed Nov 20 17:00:07 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1_stub.vhdl
-- Design : design_1_axis_prog_audio_filt_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_axis_prog_audio_filt_0_1 is
Port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end design_1_axis_prog_audio_filt_0_1;
architecture stub of design_1_axis_prog_audio_filt_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "AXI_ACLK,AXI_ARESETN,S_AXIL_AWADDR[7:0],S_AXIL_AWVALID,S_AXIL_AWREADY,S_AXIL_WDATA[31:0],S_AXIL_WVALID,S_AXIL_WREADY,S_AXIL_WSTRB[3:0],S_AXIL_BVALID,S_AXIL_BREADY,S_AXIL_BRESP[1:0],S_AXIL_ARADDR[7:0],S_AXIL_ARVALID,S_AXIL_ARREADY,S_AXIL_RDATA[31:0],S_AXIL_RVALID,S_AXIL_RREADY,S_AXIL_RRESP[1:0],S_AXIS_TVALID,S_AXIS_TDATA[15:0],S_AXIS_TLAST,S_AXIS_TREADY,M_AXIS_TVALID,M_AXIS_TDATA[15:0],M_AXIS_TLAST,M_AXIS_TREADY";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_prog_audio_filter3,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
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@@ -52,6 +52,10 @@
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Nov 20 15:50:57 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5839f862</spirit:value>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.v
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@@ -0,0 +1,375 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:45 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_clk_rst_generator_0_0 -prefix
// design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_sim_netlist.v
// Design : design_1_clk_rst_generator_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CLOCK_PERIOD = "10000" *) (* HAS_CLK_INPUT = "TRUE" *) (* HAS_RESET_INPUT = "TRUE" *)
(* HAS_STOP_INPUT = "TRUE" *)
module design_1_clk_rst_generator_0_0_clk_rst_generator
(clk_in,
rst_in,
clk,
rst_n,
stop_simulation);
input clk_in;
input rst_in;
output clk;
output rst_n;
input stop_simulation;
wire [4:0]L;
wire clk_in;
wire [6:0]rescnt;
wire \rescnt[3]_i_5_n_0 ;
wire \rescnt[3]_i_6_n_0 ;
wire \rescnt[3]_i_7_n_0 ;
wire \rescnt[3]_i_8_n_0 ;
wire \rescnt[6]_i_4_n_0 ;
wire \rescnt[6]_i_5_n_0 ;
wire \rescnt[6]_i_6_n_0 ;
wire [6:0]rescnt_reg;
wire \rescnt_reg[3]_i_1_n_0 ;
wire \rescnt_reg[3]_i_1_n_1 ;
wire \rescnt_reg[3]_i_1_n_2 ;
wire \rescnt_reg[3]_i_1_n_3 ;
wire \rescnt_reg[6]_i_1_n_2 ;
wire \rescnt_reg[6]_i_1_n_3 ;
wire rst_in;
wire rst_in_sync;
wire rst_n;
wire rst_sig;
wire rst_sig_i_1_n_0;
wire rst_sig_i_2_n_0;
wire rst_sig_reg_n_0;
wire [3:2]\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED ;
assign clk = clk_in;
LUT2 #(
.INIT(4'hE))
\rescnt[3]_i_2
(.I0(rst_in_sync),
.I1(rescnt_reg[2]),
.O(L[2]));
LUT5 #(
.INIT(32'h00000001))
\rescnt[3]_i_3
(.I0(rescnt_reg[6]),
.I1(rescnt_reg[4]),
.I2(rst_in_sync),
.I3(rescnt_reg[5]),
.I4(rst_sig_i_2_n_0),
.O(rst_sig));
LUT2 #(
.INIT(4'hE))
\rescnt[3]_i_4
(.I0(rst_in_sync),
.I1(rescnt_reg[0]),
.O(L[0]));
LUT3 #(
.INIT(8'hF9))
\rescnt[3]_i_5
(.I0(rescnt_reg[2]),
.I1(rescnt_reg[3]),
.I2(rst_in_sync),
.O(\rescnt[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h000000000001FFFE))
\rescnt[3]_i_6
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rescnt_reg[4]),
.I3(rescnt_reg[6]),
.I4(rescnt_reg[2]),
.I5(rst_in_sync),
.O(\rescnt[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000000000001FFFE))
\rescnt[3]_i_7
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rescnt_reg[4]),
.I3(rescnt_reg[6]),
.I4(rescnt_reg[1]),
.I5(rst_in_sync),
.O(\rescnt[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0055005500550056))
\rescnt[3]_i_8
(.I0(rescnt_reg[0]),
.I1(rst_sig_i_2_n_0),
.I2(rescnt_reg[5]),
.I3(rst_in_sync),
.I4(rescnt_reg[4]),
.I5(rescnt_reg[6]),
.O(\rescnt[3]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\rescnt[6]_i_2
(.I0(rst_in_sync),
.I1(rescnt_reg[4]),
.O(L[4]));
LUT2 #(
.INIT(4'hE))
\rescnt[6]_i_3
(.I0(rst_in_sync),
.I1(rescnt_reg[3]),
.O(L[3]));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_4
(.I0(rescnt_reg[5]),
.I1(rescnt_reg[6]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_4_n_0 ));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_5
(.I0(rescnt_reg[4]),
.I1(rescnt_reg[5]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_5_n_0 ));
LUT3 #(
.INIT(8'hF9))
\rescnt[6]_i_6
(.I0(rescnt_reg[3]),
.I1(rescnt_reg[4]),
.I2(rst_in_sync),
.O(\rescnt[6]_i_6_n_0 ));
FDRE #(
.INIT(1'b1))
\rescnt_reg[0]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[0]),
.Q(rescnt_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[1]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[1]),
.Q(rescnt_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[2]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[2]),
.Q(rescnt_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[3]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[3]),
.Q(rescnt_reg[3]),
.R(1'b0));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \rescnt_reg[3]_i_1
(.CI(1'b0),
.CO({\rescnt_reg[3]_i_1_n_0 ,\rescnt_reg[3]_i_1_n_1 ,\rescnt_reg[3]_i_1_n_2 ,\rescnt_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({L[2],rst_sig,rst_sig_i_1_n_0,L[0]}),
.O(rescnt[3:0]),
.S({\rescnt[3]_i_5_n_0 ,\rescnt[3]_i_6_n_0 ,\rescnt[3]_i_7_n_0 ,\rescnt[3]_i_8_n_0 }));
FDRE #(
.INIT(1'b1))
\rescnt_reg[4]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[4]),
.Q(rescnt_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[5]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[5]),
.Q(rescnt_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\rescnt_reg[6]
(.C(clk_in),
.CE(1'b1),
.D(rescnt[6]),
.Q(rescnt_reg[6]),
.R(1'b0));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \rescnt_reg[6]_i_1
(.CI(\rescnt_reg[3]_i_1_n_0 ),
.CO({\NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED [3:2],\rescnt_reg[6]_i_1_n_2 ,\rescnt_reg[6]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,L[4:3]}),
.O({\NLW_rescnt_reg[6]_i_1_O_UNCONNECTED [3],rescnt[6:4]}),
.S({1'b0,\rescnt[6]_i_4_n_0 ,\rescnt[6]_i_5_n_0 ,\rescnt[6]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
rst_in_sync_reg
(.C(clk_in),
.CE(1'b1),
.D(rst_in),
.Q(rst_in_sync),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_n_INST_0
(.I0(rst_sig_reg_n_0),
.O(rst_n));
LUT5 #(
.INIT(32'hFFFFFFFE))
rst_sig_i_1
(.I0(rst_sig_i_2_n_0),
.I1(rescnt_reg[5]),
.I2(rst_in_sync),
.I3(rescnt_reg[4]),
.I4(rescnt_reg[6]),
.O(rst_sig_i_1_n_0));
LUT5 #(
.INIT(32'hFFFFFFFE))
rst_sig_i_2
(.I0(rescnt_reg[2]),
.I1(rescnt_reg[3]),
.I2(rst_in_sync),
.I3(rescnt_reg[0]),
.I4(rescnt_reg[1]),
.O(rst_sig_i_2_n_0));
FDRE #(
.INIT(1'b0))
rst_sig_reg
(.C(clk_in),
.CE(1'b1),
.D(rst_sig_i_1_n_0),
.Q(rst_sig_reg_n_0),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_clk_rst_generator_0_0,clk_rst_generator,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "package_project" *)
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
(* NotValidForBitStream *)
module design_1_clk_rst_generator_0_0
(clk_in,
rst_in,
clk,
rst_n,
stop_simulation);
input clk_in;
input rst_in;
output clk;
output rst_n;
input stop_simulation;
wire clk;
wire clk_in;
wire rst_in;
wire rst_n;
(* CLOCK_PERIOD = "10000" *)
(* HAS_CLK_INPUT = "TRUE" *)
(* HAS_RESET_INPUT = "TRUE" *)
(* HAS_STOP_INPUT = "TRUE" *)
design_1_clk_rst_generator_0_0_clk_rst_generator U0
(.clk(clk),
.clk_in(clk_in),
.rst_in(rst_in),
.rst_n(rst_n),
.stop_simulation(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_sim_netlist.vhdl
+402
View File
@@ -0,0 +1,402 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:45 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_clk_rst_generator_0_0 -prefix
-- design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_sim_netlist.vhdl
-- Design : design_1_clk_rst_generator_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_clk_rst_generator_0_0_clk_rst_generator is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
attribute CLOCK_PERIOD : integer;
attribute CLOCK_PERIOD of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is 10000;
attribute HAS_CLK_INPUT : string;
attribute HAS_CLK_INPUT of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
attribute HAS_RESET_INPUT : string;
attribute HAS_RESET_INPUT of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
attribute HAS_STOP_INPUT : string;
attribute HAS_STOP_INPUT of design_1_clk_rst_generator_0_0_clk_rst_generator : entity is "TRUE";
end design_1_clk_rst_generator_0_0_clk_rst_generator;
architecture STRUCTURE of design_1_clk_rst_generator_0_0_clk_rst_generator is
signal L : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^clk_in\ : STD_LOGIC;
signal rescnt : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \rescnt[3]_i_5_n_0\ : STD_LOGIC;
signal \rescnt[3]_i_6_n_0\ : STD_LOGIC;
signal \rescnt[3]_i_7_n_0\ : STD_LOGIC;
signal \rescnt[3]_i_8_n_0\ : STD_LOGIC;
signal \rescnt[6]_i_4_n_0\ : STD_LOGIC;
signal \rescnt[6]_i_5_n_0\ : STD_LOGIC;
signal \rescnt[6]_i_6_n_0\ : STD_LOGIC;
signal rescnt_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \rescnt_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rescnt_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rescnt_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rescnt_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rescnt_reg[6]_i_1_n_2\ : STD_LOGIC;
signal \rescnt_reg[6]_i_1_n_3\ : STD_LOGIC;
signal rst_in_sync : STD_LOGIC;
signal rst_sig : STD_LOGIC;
signal rst_sig_i_1_n_0 : STD_LOGIC;
signal rst_sig_i_2_n_0 : STD_LOGIC;
signal rst_sig_reg_n_0 : STD_LOGIC;
signal \NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rescnt_reg[6]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \rescnt_reg[3]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \rescnt_reg[6]_i_1\ : label is 35;
begin
\^clk_in\ <= clk_in;
clk <= \^clk_in\;
\rescnt[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(2),
O => L(2)
);
\rescnt[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => rescnt_reg(6),
I1 => rescnt_reg(4),
I2 => rst_in_sync,
I3 => rescnt_reg(5),
I4 => rst_sig_i_2_n_0,
O => rst_sig
);
\rescnt[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(0),
O => L(0)
);
\rescnt[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(2),
I1 => rescnt_reg(3),
I2 => rst_in_sync,
O => \rescnt[3]_i_5_n_0\
);
\rescnt[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000001FFFE"
)
port map (
I0 => rst_sig_i_2_n_0,
I1 => rescnt_reg(5),
I2 => rescnt_reg(4),
I3 => rescnt_reg(6),
I4 => rescnt_reg(2),
I5 => rst_in_sync,
O => \rescnt[3]_i_6_n_0\
);
\rescnt[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000001FFFE"
)
port map (
I0 => rst_sig_i_2_n_0,
I1 => rescnt_reg(5),
I2 => rescnt_reg(4),
I3 => rescnt_reg(6),
I4 => rescnt_reg(1),
I5 => rst_in_sync,
O => \rescnt[3]_i_7_n_0\
);
\rescnt[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055005500550056"
)
port map (
I0 => rescnt_reg(0),
I1 => rst_sig_i_2_n_0,
I2 => rescnt_reg(5),
I3 => rst_in_sync,
I4 => rescnt_reg(4),
I5 => rescnt_reg(6),
O => \rescnt[3]_i_8_n_0\
);
\rescnt[6]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(4),
O => L(4)
);
\rescnt[6]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rst_in_sync,
I1 => rescnt_reg(3),
O => L(3)
);
\rescnt[6]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(5),
I1 => rescnt_reg(6),
I2 => rst_in_sync,
O => \rescnt[6]_i_4_n_0\
);
\rescnt[6]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(4),
I1 => rescnt_reg(5),
I2 => rst_in_sync,
O => \rescnt[6]_i_5_n_0\
);
\rescnt[6]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"F9"
)
port map (
I0 => rescnt_reg(3),
I1 => rescnt_reg(4),
I2 => rst_in_sync,
O => \rescnt[6]_i_6_n_0\
);
\rescnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(0),
Q => rescnt_reg(0),
R => '0'
);
\rescnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(1),
Q => rescnt_reg(1),
R => '0'
);
\rescnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(2),
Q => rescnt_reg(2),
R => '0'
);
\rescnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(3),
Q => rescnt_reg(3),
R => '0'
);
\rescnt_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rescnt_reg[3]_i_1_n_0\,
CO(2) => \rescnt_reg[3]_i_1_n_1\,
CO(1) => \rescnt_reg[3]_i_1_n_2\,
CO(0) => \rescnt_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => L(2),
DI(2) => rst_sig,
DI(1) => rst_sig_i_1_n_0,
DI(0) => L(0),
O(3 downto 0) => rescnt(3 downto 0),
S(3) => \rescnt[3]_i_5_n_0\,
S(2) => \rescnt[3]_i_6_n_0\,
S(1) => \rescnt[3]_i_7_n_0\,
S(0) => \rescnt[3]_i_8_n_0\
);
\rescnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(4),
Q => rescnt_reg(4),
R => '0'
);
\rescnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(5),
Q => rescnt_reg(5),
R => '0'
);
\rescnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => \^clk_in\,
CE => '1',
D => rescnt(6),
Q => rescnt_reg(6),
R => '0'
);
\rescnt_reg[6]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rescnt_reg[3]_i_1_n_0\,
CO(3 downto 2) => \NLW_rescnt_reg[6]_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rescnt_reg[6]_i_1_n_2\,
CO(0) => \rescnt_reg[6]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => L(4 downto 3),
O(3) => \NLW_rescnt_reg[6]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rescnt(6 downto 4),
S(3) => '0',
S(2) => \rescnt[6]_i_4_n_0\,
S(1) => \rescnt[6]_i_5_n_0\,
S(0) => \rescnt[6]_i_6_n_0\
);
rst_in_sync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_in\,
CE => '1',
D => rst_in,
Q => rst_in_sync,
R => '0'
);
rst_n_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_sig_reg_n_0,
O => rst_n
);
rst_sig_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rst_sig_i_2_n_0,
I1 => rescnt_reg(5),
I2 => rst_in_sync,
I3 => rescnt_reg(4),
I4 => rescnt_reg(6),
O => rst_sig_i_1_n_0
);
rst_sig_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rescnt_reg(2),
I1 => rescnt_reg(3),
I2 => rst_in_sync,
I3 => rescnt_reg(0),
I4 => rescnt_reg(1),
O => rst_sig_i_2_n_0
);
rst_sig_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_in\,
CE => '1',
D => rst_sig_i_1_n_0,
Q => rst_sig_reg_n_0,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_clk_rst_generator_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_clk_rst_generator_0_0 : entity is "design_1_clk_rst_generator_0_0,clk_rst_generator,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_clk_rst_generator_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of design_1_clk_rst_generator_0_0 : entity is "package_project";
attribute x_core_info : string;
attribute x_core_info of design_1_clk_rst_generator_0_0 : entity is "clk_rst_generator,Vivado 2023.1";
end design_1_clk_rst_generator_0_0;
architecture STRUCTURE of design_1_clk_rst_generator_0_0 is
attribute CLOCK_PERIOD : integer;
attribute CLOCK_PERIOD of U0 : label is 10000;
attribute HAS_CLK_INPUT : string;
attribute HAS_CLK_INPUT of U0 : label is "TRUE";
attribute HAS_RESET_INPUT : string;
attribute HAS_RESET_INPUT of U0 : label is "TRUE";
attribute HAS_STOP_INPUT : string;
attribute HAS_STOP_INPUT of U0 : label is "TRUE";
begin
U0: entity work.design_1_clk_rst_generator_0_0_clk_rst_generator
port map (
clk => clk,
clk_in => clk_in,
rst_in => rst_in,
rst_n => rst_n,
stop_simulation => '0'
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.v
+27
View File
@@ -0,0 +1,27 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:40:45 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_clk_rst_generator_0_0 -prefix
// design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_stub.v
// Design : design_1_clk_rst_generator_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "clk_rst_generator,Vivado 2023.1" *)
module design_1_clk_rst_generator_0_0(clk_in, rst_in, clk, rst_n, stop_simulation)
/* synthesis syn_black_box black_box_pad_pin="rst_in,rst_n,stop_simulation" */
/* synthesis syn_force_seq_prim="clk_in" */
/* synthesis syn_force_seq_prim="clk" */;
input clk_in /* synthesis syn_isclock = 1 */;
input rst_in;
output clk /* synthesis syn_isclock = 1 */;
output rst_n;
input stop_simulation;
endmodule
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0_stub.vhdl
+35
View File
@@ -0,0 +1,35 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:40:45 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_clk_rst_generator_0_0 -prefix
-- design_1_clk_rst_generator_0_0_ design_1_clk_rst_generator_0_0_stub.vhdl
-- Design : design_1_clk_rst_generator_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity design_1_clk_rst_generator_0_0 is
Port (
clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end design_1_clk_rst_generator_0_0;
architecture stub of design_1_clk_rst_generator_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,rst_in,clk,rst_n,stop_simulation";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clk_rst_generator,Vivado 2023.1";
begin
end;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bd
+1 -1
View File
@@ -336,7 +336,7 @@
"value": "FALSE"
},
"C_DATA_DEPTH": {
"value": "1024"
"value": "16384"
},
"C_EN_STRG_QUAL": {
"value": "0"
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bda
-203
View File
@@ -1,203 +0,0 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "bd_f60c",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "bd_f60c",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
}
]
}
}
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml
+4 -10
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731255710"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732118289"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732118289"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732118289"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732118289"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\bd_f60c.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
@@ -39,12 +39,6 @@
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\bd_f60c.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
</CompositeFile>
</Root>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/hw_handoff/design_1_system_ila_0_0.hwh
+2 -2
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 10 17:21:49 2024" VIVADOVERSION="2023.1">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Nov 20 16:58:09 2024" VIVADOVERSION="2023.1">
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="bd_f60c" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -2119,7 +2119,7 @@
<PARAMETER NAME="C_NUM_MONITOR_SLOTS" VALUE="1"/>
<PARAMETER NAME="C_ENABLE_ILA_AXI_MON" VALUE="0"/>
<PARAMETER NAME="C_NUM_OF_PROBES" VALUE="26"/>
<PARAMETER NAME="C_DATA_DEPTH" VALUE="1024"/>
<PARAMETER NAME="C_DATA_DEPTH" VALUE="16384"/>
<PARAMETER NAME="C_MAJOR_VERSION" VALUE="2023"/>
<PARAMETER NAME="C_MINOR_VERSION" VALUE="1"/>
<PARAMETER NAME="C_BUILD_REVISION" VALUE="0"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci
+2 -2
View File
@@ -2055,7 +2055,7 @@
"C_PROBE2_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "1024", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "bd_f60c_ila_lib_0", "resolve_type": "user", "usage": "all" } ],
@@ -3136,7 +3136,7 @@
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_ILA_AXI_MON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MAJOR_VERSION": [ { "value": "2023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MINOR_VERSION": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_BUILD_REVISION": [ { "value": "0", "format": "long", "usage": "all" } ],
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml
+11 -11
View File
@@ -1046,11 +1046,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:46 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:01 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ced36408</spirit:value>
<spirit:value>9:1964941d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1065,11 +1065,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:46 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:02 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ced36408</spirit:value>
<spirit:value>9:1964941d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1080,7 +1080,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ced36408</spirit:value>
<spirit:value>9:1964941d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1096,11 +1096,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:46 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:02 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f59151c5</spirit:value>
<spirit:value>9:6cb62d17</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1116,11 +1116,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:46 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:01 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ced36408</spirit:value>
<spirit:value>9:1964941d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -28998,7 +28998,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_DATA_DEPTH</spirit:name>
<spirit:displayName>Sample Data Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_DEPTH">1024</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_DEPTH">16384</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_MAJOR_VERSION</spirit:name>
@@ -69461,7 +69461,7 @@
<spirit:parameter>
<spirit:name>C_DATA_DEPTH</spirit:name>
<spirit:displayName>Sample Data Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">1024</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">16384</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/synth/bd_f60c_ila_lib_0.vhd
+2 -2
View File
@@ -4232,7 +4232,7 @@ ATTRIBUTE X_CORE_INFO OF bd_f60c_ila_lib_0_arch : ARCHITECTURE IS "ila,Vivado 20
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_f60c_ila_lib_0_arch : ARCHITECTURE IS "bd_f60c_ila_lib_0,ila_v6_2_13_ila,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bd_f60c_ila_lib_0_arch : ARCHITECTURE IS "bd_f60c_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=26,C_DATA_DEPTH=1024,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=2,C_PROBE1_WIDTH=32,C_PROBE2_WIDTH=3,C_PROBE3_WIDTH=2,C_PROBE4_WIDTH=32,C_PROBE5_WIDTH=3,C_PROBE6_WIDTH=2,C_PROBE7_WIDTH=2,C_PROBE8_WIDTH=2,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=2,C_PROBE11_WIDTH=32,C_PROBE12_WIDTH=4,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=2,C_PROBE15_WIDTH=2,C_PROBE16_WIDTH=2,C_PROBE17_WIDTH=2,C_PROBE18_WIDTH=16,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=16,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
ATTRIBUTE CORE_GENERATION_INFO OF bd_f60c_ila_lib_0_arch : ARCHITECTURE IS "bd_f60c_ila_lib_0,ila,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=6.2,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=26,C_DATA_DEPTH=16384,C_MAJOR_VERSION=2023,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=6,C_CORE_MINOR_VER=2,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=2,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_DDR_ILA=0,C_DDR_CLK_GEN=0,C_CLK_FREQ=200,C_CLK_PERIOD=5.0,C_CLKFBOUT_MULT_F=10,C_DIVCLK_DIVIDE=3,C_CLKOUT0_DIVIDE_F=10,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_ILA_CLK_FREQ=100000000,C_PROBE0_WIDTH=2,C_PROBE1_WIDTH=32,C_PROBE2_WIDTH=3,C_PROBE3_WIDTH=2,C_PROBE4_WIDTH=32,C_PROBE5_WIDTH=3,C_PROBE6_WIDTH=2,C_PROBE7_WIDTH=2,C_PROBE8_WIDTH=2,C_PROBE9_WIDTH=32,C_PROBE10_WIDTH=2,C_PROBE11_WIDTH=32,C_PROBE12_WIDTH=4,C_PROBE13_WIDTH=2,C_PROBE14_WIDTH=2,C_PROBE15_WIDTH=2,C_PROBE16_WIDTH=2,C_PROBE17_WIDTH=2,C_PROBE18_WIDTH=16,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=16,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,"&
"C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,"&
"C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,"&
"C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,"&
@@ -4280,7 +4280,7 @@ C_CAPTURE_TYPE => 0,
C_MU_TYPE => 0,
C_TC_TYPE => 0,
C_NUM_OF_PROBES => 26,
C_DATA_DEPTH => 1024,
C_DATA_DEPTH => 16384,
C_MAJOR_VERSION => 2023,
C_MINOR_VERSION => 1,
C_BUILD_REVISION => 0,
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0.xml
+4 -4
View File
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:48 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:07 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:48 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:07 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:48 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:07 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:48 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:07 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:09 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:09 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:09 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:08 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:49 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:09 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/sim/bd_f60c.protoinst
-9
View File
@@ -1,9 +0,0 @@
{
"version": "1.0",
"modules": {
"bd_f60c": {
"proto_instances": {
}
}
}
}
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/sim/bd_f60c.vhd
+1 -1
View File
@@ -42,7 +42,7 @@ entity bd_f60c is
resetn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
end bd_f60c;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/bd_f60c.vhd
+1 -1
View File
@@ -42,7 +42,7 @@ entity bd_f60c is
resetn : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
end bd_f60c;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/synth/design_1_system_ila_0_0.hwdef
BIN
View File
Binary file not shown.
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xml
+17 -25
View File
@@ -904,11 +904,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:57:59 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a070c315</spirit:value>
<spirit:value>9:5a9d8cb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -922,11 +922,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:10:54 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:47:30 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:e553d29d</spirit:value>
<spirit:value>9:d2a398c3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -940,11 +940,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:10:21 UTC 2024</spirit:value>
<spirit:value>Sun Nov 10 19:39:41 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6383835e</spirit:value>
<spirit:value>9:1eaebf2b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -958,11 +958,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:30:22 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a070c315</spirit:value>
<spirit:value>9:5a9d8cb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -977,11 +977,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:57:59 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a070c315</spirit:value>
<spirit:value>9:5a9d8cb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -994,11 +994,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5c520230</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>rtl</spirit:value>
<spirit:value>9:383766bf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1014,15 +1010,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
<spirit:value>Sun Nov 10 19:39:58 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5c520230</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>rtl</spirit:value>
<spirit:value>9:383766bf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1038,11 +1030,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:57:59 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a070c315</spirit:value>
<spirit:value>9:5a9d8cb3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -30629,7 +30621,7 @@
<spirit:parameter>
<spirit:name>C_DATA_DEPTH</spirit:name>
<spirit:displayName>Sample Data Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">1024</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">16384</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -37015,7 +37007,6 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>System ILA</xilinx:displayName>
<xilinx:supportsDeferredElaboration>true</xilinx:supportsDeferredElaboration>
<xilinx:coreRevision>14</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="xilinx.com:ip:system_ila:1.0_ARCHIVE_LOCATION">/proj/xhdhdstaff/niloyr/debug_tools/IP3_niloyr_cs/DEV/output/internal/vivado/data/ip/xilinx</xilinx:tag>
@@ -37085,6 +37076,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DATA_DEPTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_MONITOR_SLOTS" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_AXIS_TDATA_WIDTH" xilinx:valuePermission="bd_and_user"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.v
+66543 -37720
View File
File diff suppressed because it is too large Load Diff
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_sim_netlist.vhdl
+97420 -65927
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File diff suppressed because it is too large Load Diff
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
+3 -3
View File
@@ -2,10 +2,10 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:30:16 2024
// Date : Wed Nov 20 16:54:37 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top design_1_system_ila_0_0 -prefix
// design_1_system_ila_0_0_ design_1_system_ila_0_0_stub.v
// Design : design_1_system_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
+3 -3
View File
@@ -2,10 +2,10 @@
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:30:16 2024
-- Date : Wed Nov 20 16:54:37 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_system_ila_0_0 -prefix
-- design_1_system_ila_0_0_ design_1_system_ila_0_0_stub.vhdl
-- Design : design_1_system_ila_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/synth/design_1_system_ila_0_0.vhd
+57 -57
View File
@@ -231,63 +231,63 @@ ARCHITECTURE design_1_system_ila_0_0_arch OF design_1_system_ila_0_0 IS
"8_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE81_WIDT" &
"H=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE52_" &
"WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH=1,C_PROB" &
"E24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=1024,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=DEFAULT,C" &
"omponent_Name=design_1_system_ila_0_0,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1008_" &
"MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984_MU_CNT=1,C_P" &
"ROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959_MU_CNT=1,C_P" &
"ROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934_MU_CNT=1,C_P" &
"ROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909_MU_CNT=1,C_P" &
"ROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884_MU_CNT=1,C_P" &
"ROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859_MU_CNT=1,C_P" &
"ROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834_MU_CNT=1,C_P" &
"ROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809_MU_CNT=1,C_P" &
"ROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784_MU_CNT=1,C_P" &
"ROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759_MU_CNT=1,C_P" &
"ROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734_MU_CNT=1,C_P" &
"ROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709_MU_CNT=1,C_P" &
"ROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684_MU_CNT=1,C_P" &
"ROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659_MU_CNT=1,C_P" &
"ROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634_MU_CNT=1,C_P" &
"ROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609_MU_CNT=1,C_P" &
"ROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584_MU_CNT=1,C_P" &
"ROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559_MU_CNT=1,C_P" &
"ROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534_MU_CNT=1,C_P" &
"ROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509_MU_CNT=1,C_P" &
"ROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484_MU_CNT=1,C_P" &
"ROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459_MU_CNT=1,C_P" &
"ROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434_MU_CNT=1,C_P" &
"ROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409_MU_CNT=1,C_P" &
"ROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384_MU_CNT=1,C_P" &
"ROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359_MU_CNT=1,C_P" &
"ROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334_MU_CNT=1,C_P" &
"ROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309_MU_CNT=1,C_P" &
"ROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284_MU_CNT=1,C_P" &
"ROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259_MU_CNT=1,C_P" &
"ROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234_MU_CNT=1,C_P" &
"ROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209_MU_CNT=1,C_P" &
"ROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184_MU_CNT=1,C_P" &
"ROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159_MU_CNT=1,C_P" &
"ROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134_MU_CNT=1,C_P" &
"ROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109_MU_CNT=1,C_P" &
"ROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE83_MU_CNT=1," &
"C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROB" &
"E56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE30_MU" &
"_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PRO" &
"BE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TRIGIN_EN=false,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=3,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_0_AXIS_TUSER_" &
"WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_1_INTF_TYPE=xilinx.com_int" &
"erface_axis_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_axis_rtl_1.0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_interface_aximm_rt" &
"l_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WIDTH=AUTO,C_SLO" &
"T_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLOT_3_AXIS_TUSE" &
"R_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER_WIDTH=1,C_" &
"SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WIDTH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6_AXI_ADDR_WID" &
"TH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLOT_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_WIDTH=AUTO,C_S" &
"LOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_9_AXI_WUSER" &
"_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADDR_WIDTH=AUTO," &
"C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_AXIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXIS_TUSER_WIDTH" &
"=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_13_AXI_AWUSER_" &
"WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_AXI_DATA_WIDTH" &
"=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_15_AXIS_TID_W" &
"IDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AUTO,C_PROBE_WIDTH_PROPAGATION=AUTO}";
"E24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=16384,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=DEFAULT," &
"Component_Name=design_1_system_ila_0_0,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1008" &
"_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984_MU_CNT=1,C_" &
"PROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959_MU_CNT=1,C_" &
"PROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934_MU_CNT=1,C_" &
"PROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909_MU_CNT=1,C_" &
"PROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884_MU_CNT=1,C_" &
"PROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859_MU_CNT=1,C_" &
"PROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834_MU_CNT=1,C_" &
"PROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809_MU_CNT=1,C_" &
"PROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784_MU_CNT=1,C_" &
"PROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759_MU_CNT=1,C_" &
"PROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734_MU_CNT=1,C_" &
"PROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709_MU_CNT=1,C_" &
"PROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684_MU_CNT=1,C_" &
"PROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659_MU_CNT=1,C_" &
"PROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634_MU_CNT=1,C_" &
"PROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609_MU_CNT=1,C_" &
"PROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584_MU_CNT=1,C_" &
"PROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559_MU_CNT=1,C_" &
"PROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534_MU_CNT=1,C_" &
"PROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509_MU_CNT=1,C_" &
"PROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484_MU_CNT=1,C_" &
"PROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459_MU_CNT=1,C_" &
"PROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434_MU_CNT=1,C_" &
"PROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409_MU_CNT=1,C_" &
"PROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384_MU_CNT=1,C_" &
"PROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359_MU_CNT=1,C_" &
"PROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334_MU_CNT=1,C_" &
"PROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309_MU_CNT=1,C_" &
"PROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284_MU_CNT=1,C_" &
"PROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259_MU_CNT=1,C_" &
"PROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234_MU_CNT=1,C_" &
"PROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209_MU_CNT=1,C_" &
"PROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184_MU_CNT=1,C_" &
"PROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159_MU_CNT=1,C_" &
"PROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134_MU_CNT=1,C_" &
"PROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109_MU_CNT=1,C_" &
"PROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE83_MU_CNT=1" &
",C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PRO" &
"BE56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE30_M" &
"U_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PR" &
"OBE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TRIGIN_EN=false,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=3,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_0_AXIS_TUSER" &
"_WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_1_INTF_TYPE=xilinx.com_in" &
"terface_axis_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_axis_rtl_1.0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_interface_aximm_r" &
"tl_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WIDTH=AUTO,C_SL" &
"OT_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLOT_3_AXIS_TUS" &
"ER_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER_WIDTH=1,C" &
"_SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WIDTH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6_AXI_ADDR_WI" &
"DTH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLOT_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_WIDTH=AUTO,C_" &
"SLOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_9_AXI_WUSE" &
"R_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADDR_WIDTH=AUTO" &
",C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_AXIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXIS_TUSER_WIDT" &
"H=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_13_AXI_AWUSER" &
"_WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_AXI_DATA_WIDT" &
"H=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_15_AXIS_TID_" &
"WIDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AUTO,C_PROBE_WIDTH_PROPAGATION=AUTO}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xml
+13 -13
View File
@@ -540,7 +540,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Nov 10 16:24:54 UTC 2024</spirit:value>
<spirit:value>Wed Nov 20 15:58:11 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -998,18 +998,6 @@
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_zybo_audio_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_zybo_audio_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_zybo_audio_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
@@ -1024,6 +1012,18 @@
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_zybo_audio_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>design_1_zybo_audio_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_sim_netlist.v
+4 -7
View File
@@ -2,10 +2,10 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:24:54 2024
// Date : Sun Nov 10 17:41:01 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top design_1_zybo_audio_0_0 -prefix
// design_1_zybo_audio_0_0_ design_1_zybo_audio_0_0_sim_netlist.v
// Design : design_1_zybo_audio_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -105,7 +105,6 @@ module design_1_zybo_audio_0_0
.sda_t(sda_t));
endmodule
(* ORIG_REF_NAME = "i2c_transmitter" *)
module design_1_zybo_audio_0_0_i2c_transmitter
(scl_t,
sda_t,
@@ -1662,7 +1661,6 @@ module design_1_zybo_audio_0_0_i2c_transmitter
.R(\stepcnt[5]_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "i2s_transceiver" *)
module design_1_zybo_audio_0_0_i2s_transceiver
(axis_pb_ready,
mclk,
@@ -3512,7 +3510,7 @@ module design_1_zybo_audio_0_0_i2s_transceiver
endmodule
(* HAS_RESET_PIN = "FALSE" *) (* I2C_CLKDIV = "9999" *) (* I2S_CLKDIV = "4" *)
(* MIC_IN = "0" *) (* ORIG_REF_NAME = "zybo_audio" *) (* SRR_70 = "8'b00000000" *)
(* MIC_IN = "0" *) (* SRR_70 = "8'b00000000" *)
module design_1_zybo_audio_0_0_zybo_audio
(clk,
resetn,
@@ -3652,7 +3650,6 @@ module design_1_zybo_audio_0_0_zybo_audio
.rec_lrc(rec_lrc));
endmodule
(* ORIG_REF_NAME = "zybo_audio_i2c_rom" *)
module design_1_zybo_audio_0_0_zybo_audio_i2c_rom
(Q,
\dout_reg[9]_0 ,
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_sim_netlist.vhdl
+3 -11
View File
@@ -2,10 +2,10 @@
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:24:54 2024
-- Date : Sun Nov 10 17:41:01 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_zybo_audio_0_0 -prefix
-- design_1_zybo_audio_0_0_ design_1_zybo_audio_0_0_sim_netlist.vhdl
-- Design : design_1_zybo_audio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -38,8 +38,6 @@ entity design_1_zybo_audio_0_0_i2c_transmitter is
finished_reg_0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_zybo_audio_0_0_i2c_transmitter : entity is "i2c_transmitter";
end design_1_zybo_audio_0_0_i2c_transmitter;
architecture STRUCTURE of design_1_zybo_audio_0_0_i2c_transmitter is
@@ -2072,8 +2070,6 @@ entity design_1_zybo_audio_0_0_i2s_transceiver is
rec_dat : in STD_LOGIC;
axis_pb_data : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_zybo_audio_0_0_i2s_transceiver : entity is "i2s_transceiver";
end design_1_zybo_audio_0_0_i2s_transceiver;
architecture STRUCTURE of design_1_zybo_audio_0_0_i2s_transceiver is
@@ -4512,8 +4508,6 @@ entity design_1_zybo_audio_0_0_zybo_audio_i2c_rom is
\dout_reg[1]_0\ : in STD_LOGIC;
\dout_reg[0]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_zybo_audio_0_0_zybo_audio_i2c_rom : entity is "zybo_audio_i2c_rom";
end design_1_zybo_audio_0_0_zybo_audio_i2c_rom;
architecture STRUCTURE of design_1_zybo_audio_0_0_zybo_audio_i2c_rom is
@@ -4652,8 +4646,6 @@ entity design_1_zybo_audio_0_0_zybo_audio is
attribute I2S_CLKDIV of design_1_zybo_audio_0_0_zybo_audio : entity is 4;
attribute MIC_IN : integer;
attribute MIC_IN of design_1_zybo_audio_0_0_zybo_audio : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_zybo_audio_0_0_zybo_audio : entity is "zybo_audio";
attribute SRR_70 : string;
attribute SRR_70 of design_1_zybo_audio_0_0_zybo_audio : entity is "8'b00000000";
end design_1_zybo_audio_0_0_zybo_audio;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
+3 -3
View File
@@ -2,10 +2,10 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
// Date : Sun Nov 10 17:24:54 2024
// Date : Sun Nov 10 17:41:01 2024
// Host : BiermannSurface running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top design_1_zybo_audio_0_0 -prefix
// design_1_zybo_audio_0_0_ design_1_zybo_audio_0_0_stub.v
// Design : design_1_zybo_audio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.vhdl
+3 -3
View File
@@ -2,10 +2,10 @@
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
-- Date : Sun Nov 10 17:24:54 2024
-- Date : Sun Nov 10 17:41:01 2024
-- Host : BiermannSurface running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top design_1_zybo_audio_0_0 -prefix
-- design_1_zybo_audio_0_0_ design_1_zybo_audio_0_0_stub.vhdl
-- Design : design_1_zybo_audio_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/sim/design_1.vhd
+34 -34
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Nov 10 17:21:43 2024
--Date : Wed Nov 20 16:57:58 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
@@ -28,7 +28,7 @@ entity design_1 is
pb_lrc : out STD_LOGIC;
rec_dat : in STD_LOGIC;
rec_lrc : out STD_LOGIC;
resez : in STD_LOGIC
reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
@@ -37,37 +37,6 @@ entity design_1 is
end design_1;
architecture STRUCTURE of design_1 is
component design_1_axis_prog_audio_filt_0_1 is
port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component design_1_axis_prog_audio_filt_0_1;
component design_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
@@ -182,6 +151,37 @@ architecture STRUCTURE of design_1 is
sda_t : out STD_LOGIC
);
end component design_1_zybo_audio_0_0;
component design_1_axis_prog_audio_filt_0_1 is
port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component design_1_axis_prog_audio_filt_0_1;
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute CONN_BUS_INFO : string;
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
@@ -332,7 +332,7 @@ begin
pb_lrc <= zybo_audio_0_pb_lrc;
rec_dat_1 <= rec_dat;
rec_lrc <= zybo_audio_0_rec_lrc;
resez_1 <= resez;
resez_1 <= reset;
zybo_audio_0_i2c_SCL_I <= i2c_scl_i;
zybo_audio_0_i2c_SDA_I <= i2c_sda_i;
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.hwdef
BIN
View File
Binary file not shown.
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.vhd
+34 -34
View File
@@ -2,7 +2,7 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Sun Nov 10 17:21:43 2024
--Date : Wed Nov 20 16:57:58 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
@@ -28,7 +28,7 @@ entity design_1 is
pb_lrc : out STD_LOGIC;
rec_dat : in STD_LOGIC;
rec_lrc : out STD_LOGIC;
resez : in STD_LOGIC
reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_1 : entity is "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
@@ -37,37 +37,6 @@ entity design_1 is
end design_1;
architecture STRUCTURE of design_1 is
component design_1_axis_prog_audio_filt_0_1 is
port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component design_1_axis_prog_audio_filt_0_1;
component design_1_clk_rst_generator_0_0 is
port (
clk_in : in STD_LOGIC;
@@ -182,6 +151,37 @@ architecture STRUCTURE of design_1 is
sda_t : out STD_LOGIC
);
end component design_1_zybo_audio_0_0;
component design_1_axis_prog_audio_filt_0_1 is
port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component design_1_axis_prog_audio_filt_0_1;
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute CONN_BUS_INFO : string;
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
@@ -332,7 +332,7 @@ begin
pb_lrc <= zybo_audio_0_pb_lrc;
rec_dat_1 <= rec_dat;
rec_lrc <= zybo_audio_0_rec_lrc;
resez_1 <= resez;
resez_1 <= reset;
zybo_audio_0_i2c_SCL_I <= i2c_scl_i;
zybo_audio_0_i2c_SDA_I <= i2c_sda_i;
axil_master_with_rom_0: component design_1_axil_master_with_rom_0_0
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/mref/axis_prog_audio_filter3/component.xml
+3 -3
View File
@@ -301,7 +301,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>58fe8523</spirit:value>
<spirit:value>5e84dc0e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -314,7 +314,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>58fe8523</spirit:value>
<spirit:value>5e84dc0e</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -855,7 +855,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-11-10T16:10:21Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-11-20T15:56:44Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/design_1.bd
+99 -96
View File
@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0xD8B513DD6C968B8A",
"boundary_crc": "0x20E2EFC194C17796",
"device": "xc7z020clg400-1",
"gen_directory": "../../../../es-milestone3.gen/sources_1/bd/design_1",
"name": "design_1",
@@ -11,13 +11,13 @@
"validated": "true"
},
"design_tree": {
"axis_prog_audio_filt_0": "",
"clk_rst_generator_0": "",
"axis_audio_stereo2mo_0": "",
"axil_master_with_rom_0": "",
"system_ila_0": "",
"axis_audio_mono2ster_0": "",
"zybo_audio_0": ""
"zybo_audio_0": "",
"axis_prog_audio_filt_0": ""
},
"interface_ports": {
"i2c": {
@@ -56,7 +56,7 @@
"clk": {
"direction": "I"
},
"resez": {
"reset": {
"direction": "I"
},
"rec_dat": {
@@ -82,6 +82,96 @@
}
},
"components": {
"clk_rst_generator_0": {
"vlnv": "wg:user:clk_rst_generator:1.0",
"xci_name": "design_1_clk_rst_generator_0_0",
"xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
"inst_hier_path": "clk_rst_generator_0"
},
"axis_audio_stereo2mo_0": {
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
"xci_name": "design_1_axis_audio_stereo2mo_0_0",
"xci_path": "ip\\design_1_axis_audio_stereo2mo_0_0\\design_1_axis_audio_stereo2mo_0_0.xci",
"inst_hier_path": "axis_audio_stereo2mo_0"
},
"axil_master_with_rom_0": {
"vlnv": "wg:user:axil_master_with_rom:1.0",
"xci_name": "design_1_axil_master_with_rom_0_0",
"xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
"inst_hier_path": "axil_master_with_rom_0",
"interface_ports": {
"M_AXIL": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Master",
"address_space_ref": "M_AXIL",
"base_address": {
"minimum": "0x00000000",
"maximum": "0xFFFFFFFF",
"width": "32"
}
}
},
"addressing": {
"address_spaces": {
"M_AXIL": {
"range": "4G",
"width": "32"
}
}
}
},
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "design_1_system_ila_0_0",
"xci_path": "ip\\design_1_system_ila_0_0\\design_1_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_DATA_DEPTH": {
"value": "16384"
},
"C_NUM_MONITOR_SLOTS": {
"value": "3"
},
"C_SLOT": {
"value": "2"
},
"C_SLOT_1_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
},
"C_SLOT_2_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
}
},
"interface_ports": {
"SLOT_0_AXI": {
"mode": "Monitor",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"SLOT_1_AXIS": {
"mode": "Monitor",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"SLOT_2_AXIS": {
"mode": "Monitor",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
}
}
},
"axis_audio_mono2ster_0": {
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
"xci_name": "design_1_axis_audio_mono2ster_0_0",
"xci_path": "ip\\design_1_axis_audio_mono2ster_0_0\\design_1_axis_audio_mono2ster_0_0.xci",
"inst_hier_path": "axis_audio_mono2ster_0"
},
"zybo_audio_0": {
"vlnv": "xilinx.com:user:zybo_audio:1.0",
"xci_name": "design_1_zybo_audio_0_0",
"xci_path": "ip\\design_1_zybo_audio_0_0\\design_1_zybo_audio_0_0.xci",
"inst_hier_path": "zybo_audio_0"
},
"axis_prog_audio_filt_0": {
"vlnv": "xilinx.com:module_ref:axis_prog_audio_filter3:1.0",
"xci_name": "design_1_axis_prog_audio_filt_0_1",
@@ -418,93 +508,6 @@
}
}
}
},
"clk_rst_generator_0": {
"vlnv": "wg:user:clk_rst_generator:1.0",
"xci_name": "design_1_clk_rst_generator_0_0",
"xci_path": "ip\\design_1_clk_rst_generator_0_0\\design_1_clk_rst_generator_0_0.xci",
"inst_hier_path": "clk_rst_generator_0"
},
"axis_audio_stereo2mo_0": {
"vlnv": "xilinx.com:user:axis_audio_stereo2mono:1.0",
"xci_name": "design_1_axis_audio_stereo2mo_0_0",
"xci_path": "ip\\design_1_axis_audio_stereo2mo_0_0\\design_1_axis_audio_stereo2mo_0_0.xci",
"inst_hier_path": "axis_audio_stereo2mo_0"
},
"axil_master_with_rom_0": {
"vlnv": "wg:user:axil_master_with_rom:1.0",
"xci_name": "design_1_axil_master_with_rom_0_0",
"xci_path": "ip\\design_1_axil_master_with_rom_0_0\\design_1_axil_master_with_rom_0_0.xci",
"inst_hier_path": "axil_master_with_rom_0",
"interface_ports": {
"M_AXIL": {
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "Master",
"address_space_ref": "M_AXIL",
"base_address": {
"minimum": "0x00000000",
"maximum": "0xFFFFFFFF",
"width": "32"
}
}
},
"addressing": {
"address_spaces": {
"M_AXIL": {
"range": "4G",
"width": "32"
}
}
}
},
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "design_1_system_ila_0_0",
"xci_path": "ip\\design_1_system_ila_0_0\\design_1_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_NUM_MONITOR_SLOTS": {
"value": "3"
},
"C_SLOT": {
"value": "2"
},
"C_SLOT_1_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
},
"C_SLOT_2_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
}
},
"interface_ports": {
"SLOT_0_AXI": {
"mode": "Monitor",
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
},
"SLOT_1_AXIS": {
"mode": "Monitor",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"SLOT_2_AXIS": {
"mode": "Monitor",
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
}
}
},
"axis_audio_mono2ster_0": {
"vlnv": "xilinx.com:user:axis_audio_mono2stereo:1.0",
"xci_name": "design_1_axis_audio_mono2ster_0_0",
"xci_path": "ip\\design_1_axis_audio_mono2ster_0_0\\design_1_axis_audio_mono2ster_0_0.xci",
"inst_hier_path": "axis_audio_mono2ster_0"
},
"zybo_audio_0": {
"vlnv": "xilinx.com:user:zybo_audio:1.0",
"xci_name": "design_1_zybo_audio_0_0",
"xci_path": "ip\\design_1_zybo_audio_0_0\\design_1_zybo_audio_0_0.xci",
"inst_hier_path": "zybo_audio_0"
}
},
"interface_nets": {
@@ -584,18 +587,18 @@
"clk_rst_generator_0/clk",
"axis_audio_stereo2mo_0/AXIS_ACLK",
"axil_master_with_rom_0/M_AXIL_ACLK",
"axis_prog_audio_filt_0/AXI_ACLK",
"axis_audio_mono2ster_0/AXIS_ACLK",
"zybo_audio_0/clk",
"system_ila_0/clk"
"system_ila_0/clk",
"axis_prog_audio_filt_0/AXI_ACLK"
]
},
"clk_rst_generator_0_rst_n": {
"ports": [
"clk_rst_generator_0/rst_n",
"axil_master_with_rom_0/M_AXIL_ARESETN",
"axis_prog_audio_filt_0/AXI_ARESETN",
"system_ila_0/resetn"
"system_ila_0/resetn",
"axis_prog_audio_filt_0/AXI_ARESETN"
]
},
"rec_dat_1": {
@@ -606,7 +609,7 @@
},
"resez_1": {
"ports": [
"resez",
"reset",
"clk_rst_generator_0/rst_in"
]
},
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci
+1 -1
View File
@@ -2571,7 +2571,7 @@
"C_PROBE2_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "1024", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "design_1_system_ila_0_0", "resolve_type": "user", "usage": "all" } ],
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
+27 -27
View File
@@ -1,45 +1,45 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.42004",
"Default View_TopLeft":"49,-254",
"Default View_TopLeft":"356,-313",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
preplace port i2c -pg 1 -lvl 6 -x 1270 -y 80 -defaultsOSRD
preplace port i2c -pg 1 -lvl 6 -x 1340 -y 80 -defaultsOSRD
preplace port port-id_clk -pg 1 -lvl 0 -x -240 -y -40 -defaultsOSRD
preplace port port-id_resez -pg 1 -lvl 0 -x -240 -y 0 -defaultsOSRD
preplace port port-id_reset -pg 1 -lvl 0 -x -240 -y 0 -defaultsOSRD
preplace port port-id_rec_dat -pg 1 -lvl 0 -x -240 -y 200 -defaultsOSRD
preplace port port-id_mute -pg 1 -lvl 6 -x 1270 -y 10 -defaultsOSRD
preplace port port-id_mclk -pg 1 -lvl 6 -x 1270 -y 230 -defaultsOSRD
preplace port port-id_bclk -pg 1 -lvl 6 -x 1270 -y 260 -defaultsOSRD
preplace port port-id_pb_dat -pg 1 -lvl 6 -x 1270 -y 40 -defaultsOSRD
preplace port port-id_pb_lrc -pg 1 -lvl 6 -x 1270 -y 300 -defaultsOSRD
preplace port port-id_rec_lrc -pg 1 -lvl 6 -x 1270 -y 190 -defaultsOSRD
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 600 -y -110 -defaultsOSRD
preplace port port-id_mute -pg 1 -lvl 6 -x 1340 -y 10 -defaultsOSRD
preplace port port-id_mclk -pg 1 -lvl 6 -x 1340 -y 230 -defaultsOSRD
preplace port port-id_bclk -pg 1 -lvl 6 -x 1340 -y 260 -defaultsOSRD
preplace port port-id_pb_dat -pg 1 -lvl 6 -x 1340 -y 40 -defaultsOSRD
preplace port port-id_pb_lrc -pg 1 -lvl 6 -x 1340 -y 300 -defaultsOSRD
preplace port port-id_rec_lrc -pg 1 -lvl 6 -x 1340 -y 190 -defaultsOSRD
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -20 -y 0 -defaultsOSRD
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 2 -x 320 -y -90 -defaultsOSRD
preplace inst axil_master_with_rom_0 -pg 1 -lvl 2 -x 320 -y 110 -defaultsOSRD
preplace inst system_ila_0 -pg 1 -lvl 4 -x 860 -y -170 -defaultsOSRD
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 860 -y 110 -defaultsOSRD
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1100 -y 130 -defaultsOSRD
preplace inst system_ila_0 -pg 1 -lvl 4 -x 940 -y -170 -defaultsOSRD
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 940 -y 110 -defaultsOSRD
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1170 -y 130 -defaultsOSRD
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 640 -y -110 -defaultsOSRD
preplace netloc clk_1 1 0 1 -220 -40n
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 460 0 740 180 970
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 470 -20 750
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 980
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 500 0 820 180 1050
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 510 -20 830
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 1060
preplace netloc resez_1 1 0 1 N 0
preplace netloc zybo_audio_0_bclk 1 5 1 1220 140n
preplace netloc zybo_audio_0_mclk 1 5 1 1240 120n
preplace netloc zybo_audio_0_mute 1 5 1 1220 10n
preplace netloc zybo_audio_0_pb_dat 1 5 1 1230 40n
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1210 180n
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1250 190n
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 440 -210 NJ
preplace netloc zybo_audio_0_bclk 1 5 1 1290 140n
preplace netloc zybo_audio_0_mclk 1 5 1 1310 120n
preplace netloc zybo_audio_0_mute 1 5 1 1290 10n
preplace netloc zybo_audio_0_pb_dat 1 5 1 1300 40n
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1280 180n
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1320 190n
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 480 -210 NJ
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 N 110
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 450 -200 730J
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 730 -170n
preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1210
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 490 -200 770J
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 810 -170n
preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1280
preplace netloc zybo_audio_0_i2c 1 5 1 N 80
levelinfo -pg 1 -240 -20 320 600 860 1100 1270
levelinfo -pg 1 -240 -20 320 640 940 1170 1340
pagesize -pg 1 -db -bbox -sgen -340 -420 1450 560
"
}
Milestone3/es-milestone3/es-milestone3.xpr
+25 -113
View File
@@ -4,7 +4,7 @@
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="63" Path="C:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ac364057cd1843739edfb55c505ac94b"/>
@@ -104,8 +104,11 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
@@ -113,17 +116,8 @@
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci">
<Proxy FileSetName="design_1_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xci">
<Proxy FileSetName="design_1_zybo_audio_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
@@ -175,6 +169,14 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@@ -203,18 +205,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_system_ila_0_0" RelGenDir="$PGENDIR/design_1_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="design_1_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_zybo_audio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_zybo_audio_0_0" RelGenDir="$PGENDIR/design_1_zybo_audio_0_0">
<Config>
<Option Name="TopModule" Val="design_1_zybo_audio_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_axis_prog_audio_filt_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axis_prog_audio_filt_0_1" RelGenDir="$PGENDIR/design_1_axis_prog_audio_filt_0_1">
<Config>
<Option Name="TopModule" Val="design_1_axis_prog_audio_filt_0_1"/>
@@ -241,7 +231,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
@@ -253,9 +243,7 @@
</Run>
<Run Id="design_1_axis_audio_stereo2mo_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_audio_stereo2mo_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_stereo2mo_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_audio_stereo2mo_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -265,9 +253,7 @@
</Run>
<Run Id="design_1_axil_master_with_rom_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axil_master_with_rom_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axil_master_with_rom_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axil_master_with_rom_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -277,9 +263,7 @@
</Run>
<Run Id="design_1_clk_rst_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_rst_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_rst_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_rst_generator_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -289,33 +273,7 @@
</Run>
<Run Id="design_1_axis_audio_mono2ster_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_audio_mono2ster_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_mono2ster_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_zybo_audio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_zybo_audio_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_zybo_audio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -355,9 +313,7 @@
</Run>
<Run Id="design_1_axis_audio_stereo2mo_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_stereo2mo_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_audio_stereo2mo_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_stereo2mo_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -374,9 +330,7 @@
</Run>
<Run Id="design_1_axil_master_with_rom_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axil_master_with_rom_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axil_master_with_rom_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axil_master_with_rom_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -393,9 +347,7 @@
</Run>
<Run Id="design_1_clk_rst_generator_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_clk_rst_generator_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_rst_generator_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_rst_generator_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -412,47 +364,7 @@
</Run>
<Run Id="design_1_axis_audio_mono2ster_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_audio_mono2ster_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_audio_mono2ster_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_zybo_audio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_zybo_audio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
Milestone3/sources/axis_audio_filter3.vhd
+1 -1
View File
@@ -109,7 +109,7 @@ begin
res := res + (p1(23)&p1(23)&p1);
res := res + (p2(23)&p2(23)&p2);
M_AXIS_TDATA <= std_logic_vector(res(SHIFT+15 downto SHIFT));
M_AXIS_TDATA <= std_logic_vector(res(to_integer(shift_sig)+15 downto to_integer(shift_sig)));
end if;
end if;