M3: Synthese Blockdesign
This commit is contained in:
Matthias Biermann
@@ -2,10 +2,10 @@
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="STALE" Timestamp="1731254143"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731254149"/>
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<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1731254143"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731254149"/>
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<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1731255710"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731255710"/>
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<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1731255710"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731255710"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\design_1.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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+8
-8
@@ -2,7 +2,7 @@
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--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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--Date : Sun Nov 10 16:55:43 2024
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--Date : Sun Nov 10 17:21:44 2024
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--Host : BiermannSurface running 64-bit major release (build 9200)
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--Command : generate_target design_1_wrapper.bd
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--Design : design_1_wrapper
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@@ -31,6 +31,12 @@ end design_1_wrapper;
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architecture STRUCTURE of design_1_wrapper is
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component design_1 is
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port (
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i2c_scl_t : out STD_LOGIC;
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i2c_sda_o : out STD_LOGIC;
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i2c_sda_i : in STD_LOGIC;
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i2c_scl_o : out STD_LOGIC;
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i2c_scl_i : in STD_LOGIC;
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i2c_sda_t : out STD_LOGIC;
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clk : in STD_LOGIC;
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resez : in STD_LOGIC;
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rec_dat : in STD_LOGIC;
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@@ -39,13 +45,7 @@ architecture STRUCTURE of design_1_wrapper is
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bclk : out STD_LOGIC;
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pb_dat : out STD_LOGIC;
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pb_lrc : out STD_LOGIC;
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rec_lrc : out STD_LOGIC;
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i2c_scl_t : out STD_LOGIC;
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i2c_sda_o : out STD_LOGIC;
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i2c_sda_i : in STD_LOGIC;
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i2c_scl_o : out STD_LOGIC;
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i2c_scl_i : in STD_LOGIC;
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i2c_sda_t : out STD_LOGIC
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rec_lrc : out STD_LOGIC
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);
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end component design_1;
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component IOBUF is
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+31
-31
@@ -1,9 +1,39 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 10 16:55:48 2024" VIVADOVERSION="2023.1">
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<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 10 17:21:50 2024" VIVADOVERSION="2023.1">
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<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
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<EXTERNALPORTS>
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<PORT DIR="O" NAME="i2c_scl_t" SIGIS="undef" SIGNAME="zybo_audio_0_scl_t">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="scl_t"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_sda_o" SIGIS="undef" SIGNAME="zybo_audio_0_sda_o">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="sda_o"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="i2c_sda_i" SIGIS="undef" SIGNAME="zybo_audio_0_sda_i">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="sda_i"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_scl_o" SIGIS="undef" SIGNAME="zybo_audio_0_scl_o">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="scl_o"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="i2c_scl_i" SIGIS="undef" SIGNAME="zybo_audio_0_scl_i">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="scl_i"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_sda_t" SIGIS="undef" SIGNAME="zybo_audio_0_sda_t">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="sda_t"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="clk" SIGIS="undef" SIGNAME="External_Ports_clk">
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<CONNECTIONS>
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<CONNECTION INSTANCE="clk_rst_generator_0" PORT="clk_in"/>
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@@ -49,36 +79,6 @@
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<CONNECTION INSTANCE="zybo_audio_0" PORT="rec_lrc"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_scl_t" SIGIS="undef" SIGNAME="zybo_audio_0_scl_t">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="scl_t"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_sda_o" SIGIS="undef" SIGNAME="zybo_audio_0_sda_o">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="sda_o"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="i2c_sda_i" SIGIS="undef" SIGNAME="zybo_audio_0_sda_i">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="sda_i"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_scl_o" SIGIS="undef" SIGNAME="zybo_audio_0_scl_o">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="scl_o"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="I" NAME="i2c_scl_i" SIGIS="undef" SIGNAME="zybo_audio_0_scl_i">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="scl_i"/>
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</CONNECTIONS>
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</PORT>
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<PORT DIR="O" NAME="i2c_sda_t" SIGIS="undef" SIGNAME="zybo_audio_0_sda_t">
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<CONNECTIONS>
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<CONNECTION INSTANCE="zybo_audio_0" PORT="sda_t"/>
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</CONNECTIONS>
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</PORT>
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</EXTERNALPORTS>
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<EXTERNALINTERFACES>
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+1
@@ -0,0 +1 @@
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create_clock -period 10.000 -name M_AXIL_ACLK -waveform {0.000 5.000} [get_ports M_AXIL_ACLK]
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+157
-2
@@ -577,7 +577,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
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<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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@@ -585,6 +585,50 @@
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:modelName>axil_master_with_rom</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:45b54a85</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_externalfiles</spirit:name>
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<spirit:displayName>External Files</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:45b54a85</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_synthesisconstraints</spirit:name>
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<spirit:displayName>Synthesis Constraints</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
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<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:45b54a85</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
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<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
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@@ -597,7 +641,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
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||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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@@ -605,6 +649,26 @@
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
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<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
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<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
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<spirit:language>vhdl</spirit:language>
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||||
<spirit:modelName>design_1_axil_master_with_rom_0_0</spirit:modelName>
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||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:45b54a85</spirit:value>
|
||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
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||||
<spirit:ports>
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||||
<spirit:port>
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||||
@@ -614,6 +678,7 @@
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||||
<spirit:wireTypeDefs>
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -636,6 +701,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -655,6 +721,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -667,6 +734,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -682,6 +750,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -697,6 +766,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -713,6 +783,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -729,6 +800,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -741,6 +813,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -753,6 +826,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -772,6 +846,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -791,6 +866,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -806,6 +882,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -821,6 +898,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -837,6 +915,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -853,6 +932,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -865,6 +945,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -880,6 +961,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -896,6 +978,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -912,6 +995,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -924,6 +1008,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -936,6 +1021,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -955,6 +1041,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1001,6 +1088,66 @@
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axil_master_with_rom.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axil_master_with_rom_clocks.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axil_master_with_rom_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/d271/sources_1/new/axilm_rom.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/d271/sources_1/new/axil_master_with_rom.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axil_master_with_rom_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axil_master_with_rom_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axil_master_with_rom_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axil_master_with_rom_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axil_master_with_rom_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1009,6 +1156,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_axil_master_with_rom_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axil_master_with_rom</spirit:description>
|
||||
<spirit:parameters>
|
||||
|
||||
+182
@@ -0,0 +1,182 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:axil_master_with_rom:1.0
|
||||
-- IP Revision: 17
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axil_master_with_rom_0_0 IS
|
||||
PORT (
|
||||
interrupt_in : IN STD_LOGIC;
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axil_master_with_rom_0_0_arch OF design_1_axil_master_with_rom_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axil_master_with_rom IS
|
||||
GENERIC (
|
||||
STIM_FILENAME : STRING;
|
||||
HAS_FINISHED_OUT : BOOLEAN;
|
||||
HAS_INTERRUPT_IN : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
interrupt_in : IN STD_LOGIC;
|
||||
finished_o : OUT STD_LOGIC;
|
||||
M_AXIL_ACLK : IN STD_LOGIC;
|
||||
M_AXIL_ARESETN : IN STD_LOGIC;
|
||||
M_AXIL_ARREADY : IN STD_LOGIC;
|
||||
M_AXIL_ARVALID : OUT STD_LOGIC;
|
||||
M_AXIL_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_RREADY : OUT STD_LOGIC;
|
||||
M_AXIL_RVALID : IN STD_LOGIC;
|
||||
M_AXIL_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXIL_AWREADY : IN STD_LOGIC;
|
||||
M_AXIL_AWVALID : OUT STD_LOGIC;
|
||||
M_AXIL_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXIL_WREADY : IN STD_LOGIC;
|
||||
M_AXIL_WVALID : OUT STD_LOGIC;
|
||||
M_AXIL_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIL_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXIL_BREADY : OUT STD_LOGIC;
|
||||
M_AXIL_BVALID : IN STD_LOGIC;
|
||||
M_AXIL_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axil_master_with_rom;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "axil_master_with_rom,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axil_master_with_rom_0_0_arch : ARCHITECTURE IS "design_1_axil_master_with_rom_0_0,axil_master_with_rom,{}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axil_master_with_rom_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ACLK: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ACLK, ASSOCIATED_BUSIF M_AXIL, ASSOCIATED_RESET M_AXIL_ARESETN, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIL_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARESETN: SIGNAL IS "XIL_INTERFACENAME M_AXIL_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 M_AXIL_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIL_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, IN" &
|
||||
"SERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXIL WVALID";
|
||||
BEGIN
|
||||
U0 : axil_master_with_rom
|
||||
GENERIC MAP (
|
||||
STIM_FILENAME => "../../stimuli.mem",
|
||||
HAS_FINISHED_OUT => false,
|
||||
HAS_INTERRUPT_IN => true
|
||||
)
|
||||
PORT MAP (
|
||||
interrupt_in => interrupt_in,
|
||||
M_AXIL_ACLK => M_AXIL_ACLK,
|
||||
M_AXIL_ARESETN => M_AXIL_ARESETN,
|
||||
M_AXIL_ARREADY => M_AXIL_ARREADY,
|
||||
M_AXIL_ARVALID => M_AXIL_ARVALID,
|
||||
M_AXIL_ARADDR => M_AXIL_ARADDR,
|
||||
M_AXIL_ARPROT => M_AXIL_ARPROT,
|
||||
M_AXIL_RREADY => M_AXIL_RREADY,
|
||||
M_AXIL_RVALID => M_AXIL_RVALID,
|
||||
M_AXIL_RDATA => M_AXIL_RDATA,
|
||||
M_AXIL_RRESP => M_AXIL_RRESP,
|
||||
M_AXIL_AWREADY => M_AXIL_AWREADY,
|
||||
M_AXIL_AWVALID => M_AXIL_AWVALID,
|
||||
M_AXIL_AWADDR => M_AXIL_AWADDR,
|
||||
M_AXIL_AWPROT => M_AXIL_AWPROT,
|
||||
M_AXIL_WREADY => M_AXIL_WREADY,
|
||||
M_AXIL_WVALID => M_AXIL_WVALID,
|
||||
M_AXIL_WDATA => M_AXIL_WDATA,
|
||||
M_AXIL_WSTRB => M_AXIL_WSTRB,
|
||||
M_AXIL_BREADY => M_AXIL_BREADY,
|
||||
M_AXIL_BVALID => M_AXIL_BVALID,
|
||||
M_AXIL_BRESP => M_AXIL_BRESP
|
||||
);
|
||||
END design_1_axil_master_with_rom_0_0_arch;
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 10.000 [get_ports AXIS_ACLK]
|
||||
+139
-2
@@ -422,7 +422,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:22 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -430,6 +430,50 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_mono2stereo</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2c94a4ed</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2c94a4ed</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2c94a4ed</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
@@ -442,7 +486,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:22 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -450,6 +494,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_audio_mono2ster_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:2c94a4ed</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
@@ -459,6 +523,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -471,6 +536,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -487,6 +553,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -502,6 +569,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -524,6 +592,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -536,6 +605,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -552,6 +622,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -564,6 +635,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -583,6 +655,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -608,6 +681,62 @@
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axis_audio_mono2stereo.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axis_audio_mono2stereo_clocks.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axis_audio_mono2stereo_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/4738/sources_1/new/axis_audio_mono2stereo.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_mono2ster_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -616,6 +745,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_axis_audio_mono2ster_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_audio_mono2stereo</spirit:description>
|
||||
<spirit:parameters>
|
||||
|
||||
+122
@@ -0,0 +1,122 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_mono2stereo:1.0
|
||||
-- IP Revision: 3
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_audio_mono2ster_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_axis_audio_mono2ster_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_audio_mono2ster_0_0_arch OF design_1_axis_audio_mono2ster_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_mono2stereo IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_mono2stereo;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "axis_audio_mono2stereo,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_audio_mono2ster_0_0_arch : ARCHITECTURE IS "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "design_1_axis_audio_mono2ster_0_0,axis_audio_mono2stereo,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_mono2stereo,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HAS_LAST=false}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_audio_mono2ster_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_mono2stereo
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_axis_audio_mono2ster_0_0_arch;
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 10.000 [get_ports AXIS_ACLK]
|
||||
+139
-2
@@ -422,7 +422,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -430,6 +430,50 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_audio_stereo2mono</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
@@ -442,7 +486,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -450,6 +494,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_audio_stereo2mo_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:fcf1b95b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
@@ -459,6 +523,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -471,6 +536,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -487,6 +553,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -502,6 +569,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -524,6 +592,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -536,6 +605,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -552,6 +622,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -564,6 +635,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -583,6 +655,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -608,6 +681,62 @@
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axis_audio_stereo2mono.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axis_audio_stereo2mono_clocks.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/axis_audio_stereo2mono_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9e1d/sources_1/new/axis_audio_stereo2mono.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_stereo2mo_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_stereo2mo_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_stereo2mo_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_stereo2mo_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_audio_stereo2mo_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -616,6 +745,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_axis_audio_stereo2mo_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>axis_audio_stereo2mono</spirit:description>
|
||||
<spirit:parameters>
|
||||
|
||||
+122
@@ -0,0 +1,122 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:axis_audio_stereo2mono:1.0
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_audio_stereo2mo_0_0 IS
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_axis_audio_stereo2mo_0_0;
|
||||
|
||||
ARCHITECTURE design_1_axis_audio_stereo2mo_0_0_arch OF design_1_axis_audio_stereo2mo_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_audio_stereo2mono IS
|
||||
GENERIC (
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXIS_ACLK : IN STD_LOGIC;
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_audio_stereo2mono;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "axis_audio_stereo2mono,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_audio_stereo2mo_0_0_arch : ARCHITECTURE IS "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "design_1_axis_audio_stereo2mo_0_0,axis_audio_stereo2mono,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axis_audio_stereo2mono,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HAS_LAST=false}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_audio_stereo2mo_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXIS_ACLK: SIGNAL IS "XIL_INTERFACENAME AXIS_ACLK, ASSOCIATED_BUSIF M_AXIS:S_AXIS, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXIS_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXIS_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_audio_stereo2mono
|
||||
GENERIC MAP (
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXIS_ACLK => AXIS_ACLK,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => '0',
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_axis_audio_stereo2mo_0_0_arch;
|
||||
+148
-20
@@ -895,6 +895,43 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>axis_prog_audio_filter3</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d2381e3b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d2381e3b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d2381e3b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
@@ -907,7 +944,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -915,6 +952,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_axis_prog_audio_filt_0_1</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d2381e3b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
@@ -924,6 +981,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -936,6 +994,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -952,6 +1011,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -967,6 +1027,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -982,6 +1043,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -998,6 +1060,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1013,6 +1076,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1028,6 +1092,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1044,6 +1109,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1059,6 +1125,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1071,6 +1138,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1090,6 +1158,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1106,6 +1175,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1121,6 +1191,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1136,6 +1207,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1152,6 +1224,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1164,6 +1237,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1176,6 +1250,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1195,6 +1270,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1207,6 +1283,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1223,6 +1300,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1238,6 +1316,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1253,6 +1332,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1265,6 +1345,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1281,6 +1362,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1293,6 +1375,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1305,6 +1388,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1355,6 +1439,42 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_prog_audio_filt_0_1.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_prog_audio_filt_0_1_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_prog_audio_filt_0_1_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_prog_audio_filt_0_1_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_axis_prog_audio_filt_0_1_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1363,6 +1483,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_axis_prog_audio_filt_0_1.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:axis_prog_audio_filter3:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
@@ -1427,36 +1555,36 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+212
@@ -0,0 +1,212 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:axis_prog_audio_filter3:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_axis_prog_audio_filt_0_1 IS
|
||||
PORT (
|
||||
AXI_ACLK : IN STD_LOGIC;
|
||||
AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END design_1_axis_prog_audio_filt_0_1;
|
||||
|
||||
ARCHITECTURE design_1_axis_prog_audio_filt_0_1_arch OF design_1_axis_prog_audio_filt_0_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axis_prog_audio_filter3 IS
|
||||
GENERIC (
|
||||
COEFF_0 : INTEGER;
|
||||
COEFF_1 : INTEGER;
|
||||
COEFF_2 : INTEGER;
|
||||
SHIFT : INTEGER;
|
||||
RUN_AFTER_RESET : BOOLEAN;
|
||||
HAS_LAST : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
AXI_ACLK : IN STD_LOGIC;
|
||||
AXI_ARESETN : IN STD_LOGIC;
|
||||
S_AXIL_AWADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_AWVALID : IN STD_LOGIC;
|
||||
S_AXIL_AWREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_WVALID : IN STD_LOGIC;
|
||||
S_AXIL_WREADY : OUT STD_LOGIC;
|
||||
S_AXIL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXIL_BVALID : OUT STD_LOGIC;
|
||||
S_AXIL_BREADY : IN STD_LOGIC;
|
||||
S_AXIL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIL_ARADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXIL_ARVALID : IN STD_LOGIC;
|
||||
S_AXIL_ARREADY : OUT STD_LOGIC;
|
||||
S_AXIL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXIL_RVALID : OUT STD_LOGIC;
|
||||
S_AXIL_RREADY : IN STD_LOGIC;
|
||||
S_AXIL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN STD_LOGIC;
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN STD_LOGIC;
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT STD_LOGIC;
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT axis_prog_audio_filter3;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "axis_prog_audio_filter3,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axis_prog_audio_filt_0_1_arch : ARCHITECTURE IS "design_1_axis_prog_audio_filt_0_1,axis_prog_audio_filter3,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "design_1_axis_prog_audio_filt_0_1,axis_prog_audio_filter3,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axis_prog_audio_filter3,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,COEFF_0=42,COEFF_1=42,COEFF_2=42,SHIFT=7,RUN_AFTER_RESET=true,HAS_LAST=false}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_axis_prog_audio_filt_0_1_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ACLK: SIGNAL IS "XIL_INTERFACENAME AXI_ACLK, ASSOCIATED_RESET AXI_ARESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF AXI_ARESETN: SIGNAL IS "XIL_INTERFACENAME AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIL_AWADDR: SIGNAL IS "XIL_INTERFACENAME S_AXIL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 8, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_B" &
|
||||
"ITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIL_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXIL WVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF S_AXIS_TVALID: SIGNAL IS "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
|
||||
BEGIN
|
||||
U0 : axis_prog_audio_filter3
|
||||
GENERIC MAP (
|
||||
COEFF_0 => 42,
|
||||
COEFF_1 => 42,
|
||||
COEFF_2 => 42,
|
||||
SHIFT => 7,
|
||||
RUN_AFTER_RESET => true,
|
||||
HAS_LAST => false
|
||||
)
|
||||
PORT MAP (
|
||||
AXI_ACLK => AXI_ACLK,
|
||||
AXI_ARESETN => AXI_ARESETN,
|
||||
S_AXIL_AWADDR => S_AXIL_AWADDR,
|
||||
S_AXIL_AWVALID => S_AXIL_AWVALID,
|
||||
S_AXIL_AWREADY => S_AXIL_AWREADY,
|
||||
S_AXIL_WDATA => S_AXIL_WDATA,
|
||||
S_AXIL_WVALID => S_AXIL_WVALID,
|
||||
S_AXIL_WREADY => S_AXIL_WREADY,
|
||||
S_AXIL_WSTRB => S_AXIL_WSTRB,
|
||||
S_AXIL_BVALID => S_AXIL_BVALID,
|
||||
S_AXIL_BREADY => S_AXIL_BREADY,
|
||||
S_AXIL_BRESP => S_AXIL_BRESP,
|
||||
S_AXIL_ARADDR => S_AXIL_ARADDR,
|
||||
S_AXIL_ARVALID => S_AXIL_ARVALID,
|
||||
S_AXIL_ARREADY => S_AXIL_ARREADY,
|
||||
S_AXIL_RDATA => S_AXIL_RDATA,
|
||||
S_AXIL_RVALID => S_AXIL_RVALID,
|
||||
S_AXIL_RREADY => S_AXIL_RREADY,
|
||||
S_AXIL_RRESP => S_AXIL_RRESP,
|
||||
S_AXIS_TVALID => S_AXIS_TVALID,
|
||||
S_AXIS_TDATA => S_AXIS_TDATA,
|
||||
S_AXIS_TLAST => S_AXIS_TLAST,
|
||||
S_AXIS_TREADY => S_AXIS_TREADY,
|
||||
M_AXIS_TVALID => M_AXIS_TVALID,
|
||||
M_AXIS_TDATA => M_AXIS_TDATA,
|
||||
M_AXIS_TLAST => M_AXIS_TLAST,
|
||||
M_AXIS_TREADY => M_AXIS_TREADY
|
||||
);
|
||||
END design_1_axis_prog_audio_filt_0_1_arch;
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 10.000 -name clk_in -waveform {0.000 5.000} [get_ports clk_in]
|
||||
+134
-2
@@ -17,7 +17,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -25,6 +25,50 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>clk_rst_generator</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5839f862</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5839f862</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5839f862</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
@@ -37,7 +81,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -45,6 +89,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_clk_rst_generator_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5839f862</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
@@ -54,6 +118,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -76,6 +141,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -98,6 +164,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -110,6 +177,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -122,6 +190,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -169,6 +238,61 @@
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/clk_rst_generator.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/clk_rst_generator_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/clk_rst_generator_clocks.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/9a97/sources_1/new/clk_rst_generator.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_clk_rst_generator_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -177,6 +301,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_clk_rst_generator_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>clk_rst_generator</spirit:description>
|
||||
<spirit:parameters>
|
||||
|
||||
+105
@@ -0,0 +1,105 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: wg:user:clk_rst_generator:1.0
|
||||
-- IP Revision: 7
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_clk_rst_generator_0_0 IS
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0;
|
||||
|
||||
ARCHITECTURE design_1_clk_rst_generator_0_0_arch OF design_1_clk_rst_generator_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT clk_rst_generator IS
|
||||
GENERIC (
|
||||
CLOCK_PERIOD : INTEGER;
|
||||
HAS_CLK_INPUT : BOOLEAN;
|
||||
HAS_RESET_INPUT : BOOLEAN;
|
||||
HAS_STOP_INPUT : BOOLEAN
|
||||
);
|
||||
PORT (
|
||||
clk_in : IN STD_LOGIC;
|
||||
rst_in : IN STD_LOGIC;
|
||||
clk : OUT STD_LOGIC;
|
||||
rst_n : OUT STD_LOGIC;
|
||||
stop_simulation : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT clk_rst_generator;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "clk_rst_generator,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_clk_rst_generator_0_0_arch : ARCHITECTURE IS "design_1_clk_rst_generator_0_0,clk_rst_generator,{}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_clk_rst_generator_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
BEGIN
|
||||
U0 : clk_rst_generator
|
||||
GENERIC MAP (
|
||||
CLOCK_PERIOD => 10000,
|
||||
HAS_CLK_INPUT => true,
|
||||
HAS_RESET_INPUT => true,
|
||||
HAS_STOP_INPUT => true
|
||||
)
|
||||
PORT MAP (
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_in,
|
||||
clk => clk,
|
||||
rst_n => rst_n,
|
||||
stop_simulation => stop_simulation
|
||||
);
|
||||
END design_1_clk_rst_generator_0_0_arch;
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "bd_f60c",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "bd_f60c",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+10
-10
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1731254144"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731254148"/>
|
||||
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1731254144"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731254148"/>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1731255710"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1731255710"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1731255710"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731255710"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_f60c.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
@@ -19,12 +19,6 @@
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_f60c.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_f60c_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
@@ -45,6 +39,12 @@
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_f60c.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 10 16:55:48 2024" VIVADOVERSION="2023.1">
|
||||
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Nov 10 17:21:49 2024" VIVADOVERSION="2023.1">
|
||||
|
||||
<SYSTEMINFO ARCH="zynq" BOARD="digilentinc.com:zybo-z7-20:part0:1.2" DEVICE="7z020" NAME="bd_f60c" PACKAGE="clg400" SPEEDGRADE="-1"/>
|
||||
|
||||
|
||||
+1392
-1032
File diff suppressed because it is too large
Load Diff
+69
@@ -0,0 +1,69 @@
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for ILA core
|
||||
|
||||
|
||||
|
||||
create_clock -name ILA_CLK -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
+103
@@ -0,0 +1,103 @@
|
||||
##
|
||||
## ARM and HALT transfer false paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Register False Paths
|
||||
##
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
|
||||
#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
|
||||
|
||||
##
|
||||
## ILA Capture Block False Paths
|
||||
##
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Capture State to XSDB register False Paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
|
||||
|
||||
|
||||
##
|
||||
## Waivers
|
||||
##
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
|
||||
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
|
||||
+8411
File diff suppressed because it is too large
Load Diff
+2725
-2
File diff suppressed because it is too large
Load Diff
+4304
File diff suppressed because it is too large
Load Diff
+198
-2
File diff suppressed because it is too large
Load Diff
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_aw_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_f60c_slot_0_aw_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDT\
|
||||
H=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN\
|
||||
62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WI\
|
||||
DTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_aw_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+198
-2
File diff suppressed because it is too large
Load Diff
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_w_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_f60c_slot_0_w_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
|
||||
=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
|
||||
2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
|
||||
TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_w_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+198
-2
File diff suppressed because it is too large
Load Diff
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_b_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_f60c_slot_0_b_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
|
||||
=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
|
||||
2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
|
||||
TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_b_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+198
-2
File diff suppressed because it is too large
Load Diff
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_ar_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_f60c_slot_0_ar_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDT\
|
||||
H=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN\
|
||||
62_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WI\
|
||||
DTH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_ar_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+198
-2
File diff suppressed because it is too large
Load Diff
+332
@@ -0,0 +1,332 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 4
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_4_xlconcat,Vivado 2023.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_f60c_slot_0_r_0,xlconcat_v2_1_4_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_f60c_slot_0_r_0,xlconcat_v2_1_4_xlconcat,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH\
|
||||
=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,IN32_WIDTH=1,IN33_WIDTH=1,IN34_WIDTH=1,IN35_WIDTH=1,IN36_WIDTH=1,IN37_WIDTH=1,IN38_WIDTH=1,IN39_WIDTH=1,IN40_WIDTH=1,IN41_WIDTH=1,IN42_WIDTH=1,IN43_WIDTH=1,IN44_WIDTH=1,IN45_WIDTH=1,IN46_WIDTH=1,IN47_WIDTH=1,IN48_WIDTH=1,IN49_WIDTH=1,IN50_WIDTH=1,IN51_WIDTH=1,IN52_WIDTH=1,IN53_WIDTH=1,IN54_WIDTH=1,IN55_WIDTH=1,IN56_WIDTH=1,IN57_WIDTH=1,IN58_WIDTH=1,IN59_WIDTH=1,IN60_WIDTH=1,IN61_WIDTH=1,IN6\
|
||||
2_WIDTH=1,IN63_WIDTH=1,IN64_WIDTH=1,IN65_WIDTH=1,IN66_WIDTH=1,IN67_WIDTH=1,IN68_WIDTH=1,IN69_WIDTH=1,IN70_WIDTH=1,IN71_WIDTH=1,IN72_WIDTH=1,IN73_WIDTH=1,IN74_WIDTH=1,IN75_WIDTH=1,IN76_WIDTH=1,IN77_WIDTH=1,IN78_WIDTH=1,IN79_WIDTH=1,IN80_WIDTH=1,IN81_WIDTH=1,IN82_WIDTH=1,IN83_WIDTH=1,IN84_WIDTH=1,IN85_WIDTH=1,IN86_WIDTH=1,IN87_WIDTH=1,IN88_WIDTH=1,IN89_WIDTH=1,IN90_WIDTH=1,IN91_WIDTH=1,IN92_WIDTH=1,IN93_WIDTH=1,IN94_WIDTH=1,IN95_WIDTH=1,IN96_WIDTH=1,IN97_WIDTH=1,IN98_WIDTH=1,IN99_WIDTH=1,IN100_WID\
|
||||
TH=1,IN101_WIDTH=1,IN102_WIDTH=1,IN103_WIDTH=1,IN104_WIDTH=1,IN105_WIDTH=1,IN106_WIDTH=1,IN107_WIDTH=1,IN108_WIDTH=1,IN109_WIDTH=1,IN110_WIDTH=1,IN111_WIDTH=1,IN112_WIDTH=1,IN113_WIDTH=1,IN114_WIDTH=1,IN115_WIDTH=1,IN116_WIDTH=1,IN117_WIDTH=1,IN118_WIDTH=1,IN119_WIDTH=1,IN120_WIDTH=1,IN121_WIDTH=1,IN122_WIDTH=1,IN123_WIDTH=1,IN124_WIDTH=1,IN125_WIDTH=1,IN126_WIDTH=1,IN127_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_f60c_slot_0_r_0 (
|
||||
In0,
|
||||
In1,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
input wire [0 : 0] In1;
|
||||
output wire [1 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_4_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.IN32_WIDTH(1),
|
||||
.IN33_WIDTH(1),
|
||||
.IN34_WIDTH(1),
|
||||
.IN35_WIDTH(1),
|
||||
.IN36_WIDTH(1),
|
||||
.IN37_WIDTH(1),
|
||||
.IN38_WIDTH(1),
|
||||
.IN39_WIDTH(1),
|
||||
.IN40_WIDTH(1),
|
||||
.IN41_WIDTH(1),
|
||||
.IN42_WIDTH(1),
|
||||
.IN43_WIDTH(1),
|
||||
.IN44_WIDTH(1),
|
||||
.IN45_WIDTH(1),
|
||||
.IN46_WIDTH(1),
|
||||
.IN47_WIDTH(1),
|
||||
.IN48_WIDTH(1),
|
||||
.IN49_WIDTH(1),
|
||||
.IN50_WIDTH(1),
|
||||
.IN51_WIDTH(1),
|
||||
.IN52_WIDTH(1),
|
||||
.IN53_WIDTH(1),
|
||||
.IN54_WIDTH(1),
|
||||
.IN55_WIDTH(1),
|
||||
.IN56_WIDTH(1),
|
||||
.IN57_WIDTH(1),
|
||||
.IN58_WIDTH(1),
|
||||
.IN59_WIDTH(1),
|
||||
.IN60_WIDTH(1),
|
||||
.IN61_WIDTH(1),
|
||||
.IN62_WIDTH(1),
|
||||
.IN63_WIDTH(1),
|
||||
.IN64_WIDTH(1),
|
||||
.IN65_WIDTH(1),
|
||||
.IN66_WIDTH(1),
|
||||
.IN67_WIDTH(1),
|
||||
.IN68_WIDTH(1),
|
||||
.IN69_WIDTH(1),
|
||||
.IN70_WIDTH(1),
|
||||
.IN71_WIDTH(1),
|
||||
.IN72_WIDTH(1),
|
||||
.IN73_WIDTH(1),
|
||||
.IN74_WIDTH(1),
|
||||
.IN75_WIDTH(1),
|
||||
.IN76_WIDTH(1),
|
||||
.IN77_WIDTH(1),
|
||||
.IN78_WIDTH(1),
|
||||
.IN79_WIDTH(1),
|
||||
.IN80_WIDTH(1),
|
||||
.IN81_WIDTH(1),
|
||||
.IN82_WIDTH(1),
|
||||
.IN83_WIDTH(1),
|
||||
.IN84_WIDTH(1),
|
||||
.IN85_WIDTH(1),
|
||||
.IN86_WIDTH(1),
|
||||
.IN87_WIDTH(1),
|
||||
.IN88_WIDTH(1),
|
||||
.IN89_WIDTH(1),
|
||||
.IN90_WIDTH(1),
|
||||
.IN91_WIDTH(1),
|
||||
.IN92_WIDTH(1),
|
||||
.IN93_WIDTH(1),
|
||||
.IN94_WIDTH(1),
|
||||
.IN95_WIDTH(1),
|
||||
.IN96_WIDTH(1),
|
||||
.IN97_WIDTH(1),
|
||||
.IN98_WIDTH(1),
|
||||
.IN99_WIDTH(1),
|
||||
.IN100_WIDTH(1),
|
||||
.IN101_WIDTH(1),
|
||||
.IN102_WIDTH(1),
|
||||
.IN103_WIDTH(1),
|
||||
.IN104_WIDTH(1),
|
||||
.IN105_WIDTH(1),
|
||||
.IN106_WIDTH(1),
|
||||
.IN107_WIDTH(1),
|
||||
.IN108_WIDTH(1),
|
||||
.IN109_WIDTH(1),
|
||||
.IN110_WIDTH(1),
|
||||
.IN111_WIDTH(1),
|
||||
.IN112_WIDTH(1),
|
||||
.IN113_WIDTH(1),
|
||||
.IN114_WIDTH(1),
|
||||
.IN115_WIDTH(1),
|
||||
.IN116_WIDTH(1),
|
||||
.IN117_WIDTH(1),
|
||||
.IN118_WIDTH(1),
|
||||
.IN119_WIDTH(1),
|
||||
.IN120_WIDTH(1),
|
||||
.IN121_WIDTH(1),
|
||||
.IN122_WIDTH(1),
|
||||
.IN123_WIDTH(1),
|
||||
.IN124_WIDTH(1),
|
||||
.IN125_WIDTH(1),
|
||||
.IN126_WIDTH(1),
|
||||
.IN127_WIDTH(1),
|
||||
.dout_width(2),
|
||||
.NUM_PORTS(2)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(In1),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.In32(1'B0),
|
||||
.In33(1'B0),
|
||||
.In34(1'B0),
|
||||
.In35(1'B0),
|
||||
.In36(1'B0),
|
||||
.In37(1'B0),
|
||||
.In38(1'B0),
|
||||
.In39(1'B0),
|
||||
.In40(1'B0),
|
||||
.In41(1'B0),
|
||||
.In42(1'B0),
|
||||
.In43(1'B0),
|
||||
.In44(1'B0),
|
||||
.In45(1'B0),
|
||||
.In46(1'B0),
|
||||
.In47(1'B0),
|
||||
.In48(1'B0),
|
||||
.In49(1'B0),
|
||||
.In50(1'B0),
|
||||
.In51(1'B0),
|
||||
.In52(1'B0),
|
||||
.In53(1'B0),
|
||||
.In54(1'B0),
|
||||
.In55(1'B0),
|
||||
.In56(1'B0),
|
||||
.In57(1'B0),
|
||||
.In58(1'B0),
|
||||
.In59(1'B0),
|
||||
.In60(1'B0),
|
||||
.In61(1'B0),
|
||||
.In62(1'B0),
|
||||
.In63(1'B0),
|
||||
.In64(1'B0),
|
||||
.In65(1'B0),
|
||||
.In66(1'B0),
|
||||
.In67(1'B0),
|
||||
.In68(1'B0),
|
||||
.In69(1'B0),
|
||||
.In70(1'B0),
|
||||
.In71(1'B0),
|
||||
.In72(1'B0),
|
||||
.In73(1'B0),
|
||||
.In74(1'B0),
|
||||
.In75(1'B0),
|
||||
.In76(1'B0),
|
||||
.In77(1'B0),
|
||||
.In78(1'B0),
|
||||
.In79(1'B0),
|
||||
.In80(1'B0),
|
||||
.In81(1'B0),
|
||||
.In82(1'B0),
|
||||
.In83(1'B0),
|
||||
.In84(1'B0),
|
||||
.In85(1'B0),
|
||||
.In86(1'B0),
|
||||
.In87(1'B0),
|
||||
.In88(1'B0),
|
||||
.In89(1'B0),
|
||||
.In90(1'B0),
|
||||
.In91(1'B0),
|
||||
.In92(1'B0),
|
||||
.In93(1'B0),
|
||||
.In94(1'B0),
|
||||
.In95(1'B0),
|
||||
.In96(1'B0),
|
||||
.In97(1'B0),
|
||||
.In98(1'B0),
|
||||
.In99(1'B0),
|
||||
.In100(1'B0),
|
||||
.In101(1'B0),
|
||||
.In102(1'B0),
|
||||
.In103(1'B0),
|
||||
.In104(1'B0),
|
||||
.In105(1'B0),
|
||||
.In106(1'B0),
|
||||
.In107(1'B0),
|
||||
.In108(1'B0),
|
||||
.In109(1'B0),
|
||||
.In110(1'B0),
|
||||
.In111(1'B0),
|
||||
.In112(1'B0),
|
||||
.In113(1'B0),
|
||||
.In114(1'B0),
|
||||
.In115(1'B0),
|
||||
.In116(1'B0),
|
||||
.In117(1'B0),
|
||||
.In118(1'B0),
|
||||
.In119(1'B0),
|
||||
.In120(1'B0),
|
||||
.In121(1'B0),
|
||||
.In122(1'B0),
|
||||
.In123(1'B0),
|
||||
.In124(1'B0),
|
||||
.In125(1'B0),
|
||||
.In126(1'B0),
|
||||
.In127(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+1
-1
@@ -42,7 +42,7 @@ entity bd_f60c is
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
|
||||
end bd_f60c;
|
||||
|
||||
+1
-1
@@ -42,7 +42,7 @@ entity bd_f60c is
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}";
|
||||
attribute CORE_GENERATION_INFO of bd_f60c : entity is "bd_f60c,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_f60c,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=OOC_per_IP}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of bd_f60c : entity is "design_1_system_ila_0_0.hwdef";
|
||||
end bd_f60c;
|
||||
|
||||
BIN
Binary file not shown.
+182
-4
@@ -893,6 +893,25 @@
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>bd_f60c</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a070c315</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_elaboratebd</spirit:name>
|
||||
<spirit:displayName>Elaborate BD</spirit:displayName>
|
||||
@@ -903,11 +922,11 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:05:08 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:10:54 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:9836552c</spirit:value>
|
||||
<spirit:value>9:e553d29d</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -921,7 +940,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sat Nov 09 23:57:14 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:10:21 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -929,6 +948,43 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:30:22 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a070c315</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:modelName>bd_f60c</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_synthesisconstraints_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a070c315</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation</spirit:displayName>
|
||||
@@ -940,6 +996,10 @@
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5c520230</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
@@ -954,12 +1014,36 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:18 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:5c520230</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_system_ila_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:a070c315</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
@@ -971,6 +1055,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -987,6 +1072,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1006,6 +1092,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1021,6 +1108,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1036,6 +1124,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1055,6 +1144,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1074,6 +1164,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1089,6 +1180,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1104,6 +1196,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1123,6 +1216,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1138,6 +1232,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1153,6 +1248,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1172,6 +1268,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1191,6 +1288,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1206,6 +1304,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1221,6 +1320,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1240,6 +1340,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1259,6 +1360,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1274,6 +1376,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1289,6 +1392,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1308,6 +1412,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1323,6 +1428,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1338,6 +1444,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1353,6 +1460,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1372,6 +1480,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1387,6 +1496,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1402,6 +1512,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1417,6 +1528,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -1432,6 +1544,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -2580,6 +2693,16 @@
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_elaboratebd_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -2594,6 +2717,52 @@
|
||||
<spirit:userFileType>block_diagram</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_synthesisconstraints_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_system_ila_0_0_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -2602,6 +2771,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_system_ila_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>The System ILA core is a customizable logic analyzer core that can be used to monitor a combination of AXI based interfaces and individual signals. This core extend the features of basic ILA for easier debugging at a system level. This includes Boolean trigger equations, customizable data capture buffer depth and optional trigger input/output ports at both signal level as well as for interfaces. The System ila core is synchronous to the design being monitored and hence all clock constraints that are applied to your design are also applied to the components inside the core. Run-time interaction with this core requires the use of Vivado Logic Analyzer feature.</spirit:description>
|
||||
<spirit:parameters>
|
||||
@@ -36838,6 +37015,7 @@
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>System ILA</xilinx:displayName>
|
||||
<xilinx:supportsDeferredElaboration>true</xilinx:supportsDeferredElaboration>
|
||||
<xilinx:coreRevision>14</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:ip:system_ila:1.0_ARCHIVE_LOCATION">/proj/xhdhdstaff/niloyr/debug_tools/IP3_niloyr_cs/DEV/output/internal/vivado/data/ip/xilinx</xilinx:tag>
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 10 -name clk [get_ports clk]
|
||||
|
||||
|
||||
+49127
File diff suppressed because one or more lines are too long
+88001
File diff suppressed because one or more lines are too long
+57
@@ -0,0 +1,57 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Nov 10 17:30:16 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.v
|
||||
// Design : design_1_system_ila_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "bd_f60c,Vivado 2023.1" *)
|
||||
module design_1_system_ila_0_0(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awvalid, SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb,
|
||||
SLOT_0_AXI_wvalid, SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid,
|
||||
SLOT_0_AXI_bready, SLOT_0_AXI_araddr, SLOT_0_AXI_arprot, SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_arready, SLOT_0_AXI_rdata, SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid,
|
||||
SLOT_0_AXI_rready, SLOT_1_AXIS_tdata, SLOT_1_AXIS_tlast, SLOT_1_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tready, SLOT_2_AXIS_tdata, SLOT_2_AXIS_tlast, SLOT_2_AXIS_tvalid,
|
||||
SLOT_2_AXIS_tready, resetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_AXIS_tdata[15:0],SLOT_1_AXIS_tlast,SLOT_1_AXIS_tvalid,SLOT_1_AXIS_tready,SLOT_2_AXIS_tdata[15:0],SLOT_2_AXIS_tlast,SLOT_2_AXIS_tvalid,SLOT_2_AXIS_tready,resetn" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]SLOT_0_AXI_awaddr;
|
||||
input [2:0]SLOT_0_AXI_awprot;
|
||||
input SLOT_0_AXI_awvalid;
|
||||
input SLOT_0_AXI_awready;
|
||||
input [31:0]SLOT_0_AXI_wdata;
|
||||
input [3:0]SLOT_0_AXI_wstrb;
|
||||
input SLOT_0_AXI_wvalid;
|
||||
input SLOT_0_AXI_wready;
|
||||
input [1:0]SLOT_0_AXI_bresp;
|
||||
input SLOT_0_AXI_bvalid;
|
||||
input SLOT_0_AXI_bready;
|
||||
input [31:0]SLOT_0_AXI_araddr;
|
||||
input [2:0]SLOT_0_AXI_arprot;
|
||||
input SLOT_0_AXI_arvalid;
|
||||
input SLOT_0_AXI_arready;
|
||||
input [31:0]SLOT_0_AXI_rdata;
|
||||
input [1:0]SLOT_0_AXI_rresp;
|
||||
input SLOT_0_AXI_rvalid;
|
||||
input SLOT_0_AXI_rready;
|
||||
input [15:0]SLOT_1_AXIS_tdata;
|
||||
input SLOT_1_AXIS_tlast;
|
||||
input SLOT_1_AXIS_tvalid;
|
||||
input SLOT_1_AXIS_tready;
|
||||
input [15:0]SLOT_2_AXIS_tdata;
|
||||
input SLOT_2_AXIS_tlast;
|
||||
input SLOT_2_AXIS_tvalid;
|
||||
input SLOT_2_AXIS_tready;
|
||||
input resetn;
|
||||
endmodule
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Sun Nov 10 17:30:16 2024
|
||||
-- Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0_stub.vhdl
|
||||
-- Design : design_1_system_ila_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_1_system_ila_0_0 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_awvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_awready : in STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
SLOT_0_AXI_wvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_wready : in STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_bvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_bready : in STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
SLOT_0_AXI_arvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_arready : in STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
SLOT_0_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
SLOT_0_AXI_rvalid : in STD_LOGIC;
|
||||
SLOT_0_AXI_rready : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_1_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
SLOT_2_AXIS_tlast : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : in STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC
|
||||
);
|
||||
|
||||
end design_1_system_ila_0_0;
|
||||
|
||||
architecture stub of design_1_system_ila_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,SLOT_0_AXI_awaddr[31:0],SLOT_0_AXI_awprot[2:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[31:0],SLOT_0_AXI_arprot[2:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_AXIS_tdata[15:0],SLOT_1_AXIS_tlast,SLOT_1_AXIS_tvalid,SLOT_1_AXIS_tready,SLOT_2_AXIS_tdata[15:0],SLOT_2_AXIS_tlast,SLOT_2_AXIS_tvalid,SLOT_2_AXIS_tready,resetn";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "bd_f60c,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+361
@@ -0,0 +1,361 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:system_ila:1.1
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_system_ila_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_wvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_bvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_rvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rready : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_1_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_2_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC
|
||||
);
|
||||
END design_1_system_ila_0_0;
|
||||
|
||||
ARCHITECTURE design_1_system_ila_0_0_arch OF design_1_system_ila_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT bd_f60c IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_awvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_awready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
SLOT_0_AXI_wvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_wready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_bvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_bready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
SLOT_0_AXI_arvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_arready : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
SLOT_0_AXI_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SLOT_0_AXI_rvalid : IN STD_LOGIC;
|
||||
SLOT_0_AXI_rready : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_1_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_1_AXIS_tready : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
SLOT_2_AXIS_tlast : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tvalid : IN STD_LOGIC;
|
||||
SLOT_2_AXIS_tready : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC
|
||||
);
|
||||
END COMPONENT bd_f60c;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "bd_f60c,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_system_ila_0_0_arch : ARCHITECTURE IS "design_1_system_ila_0_0,bd_f60c,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_system_ila_0_0_arch: ARCHITECTURE IS "design_1_system_ila_0_0,bd_f60c,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=system_ila,x_ipVersion=1.1,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_TIME_TAG=0,C_TIME_TAG_WIDTH=32,C_SLOT=2,C_SLOT_15_TYPE=0,C_SLOT_14_TYPE=0,C_SLOT_13_TYPE=0,C_SLOT_12_TYPE=0,C_SLOT_11_TYPE=0,C_SLOT_10_TYPE=0,C_SLOT_9_TYPE=0,C_SLOT_8_TYPE=0,C_SLOT_7_TYPE=0,C_SLOT_6_TYPE=0,C_SLOT_5_TYPE=0,C_SLOT_4_TYPE=0,C_SLOT_3_TYPE=0,C_SLOT_2_TYPE=0,C_SLOT_1_TYPE=0,C_SLOT_0_TYPE=0,C" &
|
||||
"_SLOT_0_MAX_RD_BURSTS=2,C_SLOT_0_MAX_WR_BURSTS=2,C_SLOT_1_MAX_RD_BURSTS=2,C_SLOT_1_MAX_WR_BURSTS=2,C_SLOT_2_MAX_RD_BURSTS=2,C_SLOT_2_MAX_WR_BURSTS=2,C_SLOT_3_MAX_RD_BURSTS=2,C_SLOT_3_MAX_WR_BURSTS=2,C_SLOT_4_MAX_RD_BURSTS=2,C_SLOT_4_MAX_WR_BURSTS=2,C_SLOT_5_MAX_RD_BURSTS=2,C_SLOT_5_MAX_WR_BURSTS=2,C_SLOT_6_MAX_RD_BURSTS=2,C_SLOT_6_MAX_WR_BURSTS=2,C_SLOT_7_MAX_RD_BURSTS=2,C_SLOT_7_MAX_WR_BURSTS=2,C_SLOT_8_MAX_RD_BURSTS=2,C_SLOT_8_MAX_WR_BURSTS=2,C_SLOT_9_MAX_RD_BURSTS=2,C_SLOT_9_MAX_WR_BURSTS=2,C" &
|
||||
"_SLOT_10_MAX_RD_BURSTS=2,C_SLOT_10_MAX_WR_BURSTS=2,C_SLOT_11_MAX_RD_BURSTS=2,C_SLOT_11_MAX_WR_BURSTS=2,C_SLOT_12_MAX_RD_BURSTS=2,C_SLOT_12_MAX_WR_BURSTS=2,C_SLOT_13_MAX_RD_BURSTS=2,C_SLOT_13_MAX_WR_BURSTS=2,C_SLOT_14_MAX_RD_BURSTS=2,C_SLOT_14_MAX_WR_BURSTS=2,C_SLOT_15_MAX_RD_BURSTS=2,C_SLOT_15_MAX_WR_BURSTS=2,C_SLOT_0_TXN_CNTR_EN=1,C_SLOT_1_TXN_CNTR_EN=1,C_SLOT_2_TXN_CNTR_EN=1,C_SLOT_3_TXN_CNTR_EN=1,C_SLOT_4_TXN_CNTR_EN=1,C_SLOT_5_TXN_CNTR_EN=1,C_SLOT_6_TXN_CNTR_EN=1,C_SLOT_7_TXN_CNTR_EN=1,C_SLO" &
|
||||
"T_8_TXN_CNTR_EN=1,C_SLOT_9_TXN_CNTR_EN=1,C_SLOT_10_TXN_CNTR_EN=1,C_SLOT_11_TXN_CNTR_EN=1,C_SLOT_12_TXN_CNTR_EN=1,C_SLOT_13_TXN_CNTR_EN=1,C_SLOT_14_TXN_CNTR_EN=1,C_SLOT_15_TXN_CNTR_EN=1,C_SLOT_0_APC_STS_EN=0,C_SLOT_1_APC_STS_EN=0,C_SLOT_2_APC_STS_EN=0,C_SLOT_3_APC_STS_EN=0,C_SLOT_4_APC_STS_EN=0,C_SLOT_5_APC_STS_EN=0,C_SLOT_6_APC_STS_EN=0,C_SLOT_7_APC_STS_EN=0,C_SLOT_8_APC_STS_EN=0,C_SLOT_9_APC_STS_EN=0,C_SLOT_10_APC_STS_EN=0,C_SLOT_11_APC_STS_EN=0,C_SLOT_12_APC_STS_EN=0,C_SLOT_13_APC_STS_EN=0,C_S" &
|
||||
"LOT_14_APC_STS_EN=0,C_SLOT_15_APC_STS_EN=0,C_SLOT_0_APC_EN=0,C_SLOT_1_APC_EN=0,C_SLOT_2_APC_EN=0,C_SLOT_3_APC_EN=0,C_SLOT_4_APC_EN=0,C_SLOT_5_APC_EN=0,C_SLOT_6_APC_EN=0,C_SLOT_7_APC_EN=0,C_SLOT_8_APC_EN=0,C_SLOT_9_APC_EN=0,C_SLOT_10_APC_EN=0,C_SLOT_11_APC_EN=0,C_SLOT_12_APC_EN=0,C_SLOT_13_APC_EN=0,C_SLOT_14_APC_EN=0,C_SLOT_15_APC_EN=0,C_SLOT_0_APC_MAX_AW_WAITS=0,C_SLOT_0_APC_MAX_AR_WAITS=0,C_SLOT_0_APC_MAX_W_WAITS=0,C_SLOT_0_APC_MAX_B_WAITS=0,C_SLOT_0_APC_MAX_R_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOU" &
|
||||
"S_WTRANSFERS_WAITS=0,C_SLOT_0_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_0_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_0_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_AW_WAITS=0,C_SLOT_1_APC_MAX_AR_WAITS=0,C_SLOT_1_APC_MAX_W_WAITS=0,C_SLOT_1_APC_MAX_B_WAITS=0,C_SLOT_1_APC_MAX_R_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_1_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_1_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_1_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_AW_WAITS=0,C_SLOT_" &
|
||||
"2_APC_MAX_AR_WAITS=0,C_SLOT_2_APC_MAX_W_WAITS=0,C_SLOT_2_APC_MAX_B_WAITS=0,C_SLOT_2_APC_MAX_R_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_2_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_2_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_2_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_AW_WAITS=0,C_SLOT_3_APC_MAX_AR_WAITS=0,C_SLOT_3_APC_MAX_W_WAITS=0,C_SLOT_3_APC_MAX_B_WAITS=0,C_SLOT_3_APC_MAX_R_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_3_APC_MAX_WLAST_TO_AWVALID_WAI" &
|
||||
"TS=0,C_SLOT_3_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_3_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_AW_WAITS=0,C_SLOT_4_APC_MAX_AR_WAITS=0,C_SLOT_4_APC_MAX_W_WAITS=0,C_SLOT_4_APC_MAX_B_WAITS=0,C_SLOT_4_APC_MAX_R_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_4_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_4_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_4_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_AW_WAITS=0,C_SLOT_5_APC_MAX_AR_WAITS=0,C_SLOT_5_APC_MAX_W_WAITS=0,C_SLOT_5_A" &
|
||||
"PC_MAX_B_WAITS=0,C_SLOT_5_APC_MAX_R_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_5_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_5_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_5_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_AW_WAITS=0,C_SLOT_6_APC_MAX_AR_WAITS=0,C_SLOT_6_APC_MAX_W_WAITS=0,C_SLOT_6_APC_MAX_B_WAITS=0,C_SLOT_6_APC_MAX_R_WAITS=0,C_SLOT_6_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_6_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_6_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_6_APC" &
|
||||
"_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_AW_WAITS=0,C_SLOT_7_APC_MAX_AR_WAITS=0,C_SLOT_7_APC_MAX_W_WAITS=0,C_SLOT_7_APC_MAX_B_WAITS=0,C_SLOT_7_APC_MAX_R_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_7_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_7_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_7_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_AW_WAITS=0,C_SLOT_8_APC_MAX_AR_WAITS=0,C_SLOT_8_APC_MAX_W_WAITS=0,C_SLOT_8_APC_MAX_B_WAITS=0,C_SLOT_8_APC_MAX_R_WAITS=0,C_SLOT_8_APC_M" &
|
||||
"AX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_8_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_8_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_8_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_AW_WAITS=0,C_SLOT_9_APC_MAX_AR_WAITS=0,C_SLOT_9_APC_MAX_W_WAITS=0,C_SLOT_9_APC_MAX_B_WAITS=0,C_SLOT_9_APC_MAX_R_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_9_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_9_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_9_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_10_APC_MAX_AW_WA" &
|
||||
"ITS=0,C_SLOT_10_APC_MAX_AR_WAITS=0,C_SLOT_10_APC_MAX_W_WAITS=0,C_SLOT_10_APC_MAX_B_WAITS=0,C_SLOT_10_APC_MAX_R_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_10_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_10_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_10_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_11_APC_MAX_AW_WAITS=0,C_SLOT_11_APC_MAX_AR_WAITS=0,C_SLOT_11_APC_MAX_W_WAITS=0,C_SLOT_11_APC_MAX_B_WAITS=0,C_SLOT_11_APC_MAX_R_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_11_" &
|
||||
"APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_11_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_11_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_AW_WAITS=0,C_SLOT_12_APC_MAX_AR_WAITS=0,C_SLOT_12_APC_MAX_W_WAITS=0,C_SLOT_12_APC_MAX_B_WAITS=0,C_SLOT_12_APC_MAX_R_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_12_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_12_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_12_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_AW_WAITS=0,C_SLOT_13_APC_MAX_AR_WAIT" &
|
||||
"S=0,C_SLOT_13_APC_MAX_W_WAITS=0,C_SLOT_13_APC_MAX_B_WAITS=0,C_SLOT_13_APC_MAX_R_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_13_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_13_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_13_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_AW_WAITS=0,C_SLOT_14_APC_MAX_AR_WAITS=0,C_SLOT_14_APC_MAX_W_WAITS=0,C_SLOT_14_APC_MAX_B_WAITS=0,C_SLOT_14_APC_MAX_R_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_14_APC_MAX_WLAST_TO_AWVALID_WAITS=" &
|
||||
"0,C_SLOT_14_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_14_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_AW_WAITS=0,C_SLOT_15_APC_MAX_AR_WAITS=0,C_SLOT_15_APC_MAX_W_WAITS=0,C_SLOT_15_APC_MAX_B_WAITS=0,C_SLOT_15_APC_MAX_R_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_WTRANSFERS_WAITS=0,C_SLOT_15_APC_MAX_WLAST_TO_AWVALID_WAITS=0,C_SLOT_15_APC_MAX_WRITE_TO_BVALID_WAITS=0,C_SLOT_15_APC_MAX_CONTINUOUS_RTRANSFERS_WAITS=0,C_BRAM_CNT=0.0,C_SLOT_0_AXI_AW_SEL_DATA=1,C_SLOT_0_AXI_W_SEL_DATA=1,C_SLOT_0_AXI_B_SE" &
|
||||
"L_DATA=1,C_SLOT_0_AXI_AR_SEL_DATA=1,C_SLOT_0_AXI_R_SEL_DATA=1,C_SLOT_1_AXI_AW_SEL_DATA=1,C_SLOT_1_AXI_W_SEL_DATA=1,C_SLOT_1_AXI_B_SEL_DATA=1,C_SLOT_1_AXI_AR_SEL_DATA=1,C_SLOT_1_AXI_R_SEL_DATA=1,C_SLOT_2_AXI_AW_SEL_DATA=1,C_SLOT_2_AXI_W_SEL_DATA=1,C_SLOT_2_AXI_B_SEL_DATA=1,C_SLOT_2_AXI_AR_SEL_DATA=1,C_SLOT_2_AXI_R_SEL_DATA=1,C_SLOT_3_AXI_AW_SEL_DATA=1,C_SLOT_3_AXI_W_SEL_DATA=1,C_SLOT_3_AXI_B_SEL_DATA=1,C_SLOT_3_AXI_AR_SEL_DATA=1,C_SLOT_3_AXI_R_SEL_DATA=1,C_SLOT_4_AXI_AW_SEL_DATA=1,C_SLOT_4_AXI_W_" &
|
||||
"SEL_DATA=1,C_SLOT_4_AXI_B_SEL_DATA=1,C_SLOT_4_AXI_AR_SEL_DATA=1,C_SLOT_4_AXI_R_SEL_DATA=1,C_SLOT_5_AXI_AW_SEL_DATA=1,C_SLOT_5_AXI_W_SEL_DATA=1,C_SLOT_5_AXI_B_SEL_DATA=1,C_SLOT_5_AXI_AR_SEL_DATA=1,C_SLOT_5_AXI_R_SEL_DATA=1,C_SLOT_6_AXI_AW_SEL_DATA=1,C_SLOT_6_AXI_W_SEL_DATA=1,C_SLOT_6_AXI_B_SEL_DATA=1,C_SLOT_6_AXI_AR_SEL_DATA=1,C_SLOT_6_AXI_R_SEL_DATA=1,C_SLOT_7_AXI_AW_SEL_DATA=1,C_SLOT_7_AXI_W_SEL_DATA=1,C_SLOT_7_AXI_B_SEL_DATA=1,C_SLOT_7_AXI_AR_SEL_DATA=1,C_SLOT_7_AXI_R_SEL_DATA=1,C_SLOT_8_AXI_A" &
|
||||
"W_SEL_DATA=1,C_SLOT_8_AXI_W_SEL_DATA=1,C_SLOT_8_AXI_B_SEL_DATA=1,C_SLOT_8_AXI_AR_SEL_DATA=1,C_SLOT_8_AXI_R_SEL_DATA=1,C_SLOT_9_AXI_AW_SEL_DATA=1,C_SLOT_9_AXI_W_SEL_DATA=1,C_SLOT_9_AXI_B_SEL_DATA=1,C_SLOT_9_AXI_AR_SEL_DATA=1,C_SLOT_9_AXI_R_SEL_DATA=1,C_SLOT_10_AXI_AW_SEL_DATA=1,C_SLOT_10_AXI_W_SEL_DATA=1,C_SLOT_10_AXI_B_SEL_DATA=1,C_SLOT_10_AXI_AR_SEL_DATA=1,C_SLOT_10_AXI_R_SEL_DATA=1,C_SLOT_11_AXI_AW_SEL_DATA=1,C_SLOT_11_AXI_W_SEL_DATA=1,C_SLOT_11_AXI_B_SEL_DATA=1,C_SLOT_11_AXI_AR_SEL_DATA=1,C_S" &
|
||||
"LOT_11_AXI_R_SEL_DATA=1,C_SLOT_12_AXI_AW_SEL_DATA=1,C_SLOT_12_AXI_W_SEL_DATA=1,C_SLOT_12_AXI_B_SEL_DATA=1,C_SLOT_12_AXI_AR_SEL_DATA=1,C_SLOT_12_AXI_R_SEL_DATA=1,C_SLOT_13_AXI_AW_SEL_DATA=1,C_SLOT_13_AXI_W_SEL_DATA=1,C_SLOT_13_AXI_B_SEL_DATA=1,C_SLOT_13_AXI_AR_SEL_DATA=1,C_SLOT_13_AXI_R_SEL_DATA=1,C_SLOT_14_AXI_AW_SEL_DATA=1,C_SLOT_14_AXI_W_SEL_DATA=1,C_SLOT_14_AXI_B_SEL_DATA=1,C_SLOT_14_AXI_AR_SEL_DATA=1,C_SLOT_14_AXI_R_SEL_DATA=1,C_SLOT_15_AXI_AW_SEL_DATA=1,C_SLOT_15_AXI_W_SEL_DATA=1,C_SLOT_15_" &
|
||||
"AXI_B_SEL_DATA=1,C_SLOT_15_AXI_AR_SEL_DATA=1,C_SLOT_15_AXI_R_SEL_DATA=1,C_SLOT_0_AXI_AW_SEL_TRIG=1,C_SLOT_0_AXI_W_SEL_TRIG=1,C_SLOT_0_AXI_B_SEL_TRIG=1,C_SLOT_0_AXI_AR_SEL_TRIG=1,C_SLOT_0_AXI_R_SEL_TRIG=1,C_SLOT_1_AXI_AW_SEL_TRIG=1,C_SLOT_1_AXI_W_SEL_TRIG=1,C_SLOT_1_AXI_B_SEL_TRIG=1,C_SLOT_1_AXI_AR_SEL_TRIG=1,C_SLOT_1_AXI_R_SEL_TRIG=1,C_SLOT_2_AXI_AW_SEL_TRIG=1,C_SLOT_2_AXI_W_SEL_TRIG=1,C_SLOT_2_AXI_B_SEL_TRIG=1,C_SLOT_2_AXI_AR_SEL_TRIG=1,C_SLOT_2_AXI_R_SEL_TRIG=1,C_SLOT_3_AXI_AW_SEL_TRIG=1,C_SLO" &
|
||||
"T_3_AXI_W_SEL_TRIG=1,C_SLOT_3_AXI_B_SEL_TRIG=1,C_SLOT_3_AXI_AR_SEL_TRIG=1,C_SLOT_3_AXI_R_SEL_TRIG=1,C_SLOT_4_AXI_AW_SEL_TRIG=1,C_SLOT_4_AXI_W_SEL_TRIG=1,C_SLOT_4_AXI_B_SEL_TRIG=1,C_SLOT_4_AXI_AR_SEL_TRIG=1,C_SLOT_4_AXI_R_SEL_TRIG=1,C_SLOT_5_AXI_AW_SEL_TRIG=1,C_SLOT_5_AXI_W_SEL_TRIG=1,C_SLOT_5_AXI_B_SEL_TRIG=1,C_SLOT_5_AXI_AR_SEL_TRIG=1,C_SLOT_5_AXI_R_SEL_TRIG=1,C_SLOT_6_AXI_AW_SEL_TRIG=1,C_SLOT_6_AXI_W_SEL_TRIG=1,C_SLOT_6_AXI_B_SEL_TRIG=1,C_SLOT_6_AXI_AR_SEL_TRIG=1,C_SLOT_6_AXI_R_SEL_TRIG=1,C_SL" &
|
||||
"OT_7_AXI_AW_SEL_TRIG=1,C_SLOT_7_AXI_W_SEL_TRIG=1,C_SLOT_7_AXI_B_SEL_TRIG=1,C_SLOT_7_AXI_AR_SEL_TRIG=1,C_SLOT_7_AXI_R_SEL_TRIG=1,C_SLOT_8_AXI_AW_SEL_TRIG=1,C_SLOT_8_AXI_W_SEL_TRIG=1,C_SLOT_8_AXI_B_SEL_TRIG=1,C_SLOT_8_AXI_AR_SEL_TRIG=1,C_SLOT_8_AXI_R_SEL_TRIG=1,C_SLOT_9_AXI_AW_SEL_TRIG=1,C_SLOT_9_AXI_W_SEL_TRIG=1,C_SLOT_9_AXI_B_SEL_TRIG=1,C_SLOT_9_AXI_AR_SEL_TRIG=1,C_SLOT_9_AXI_R_SEL_TRIG=1,C_SLOT_10_AXI_AW_SEL_TRIG=1,C_SLOT_10_AXI_W_SEL_TRIG=1,C_SLOT_10_AXI_B_SEL_TRIG=1,C_SLOT_10_AXI_AR_SEL_TRIG=" &
|
||||
"1,C_SLOT_10_AXI_R_SEL_TRIG=1,C_SLOT_11_AXI_AW_SEL_TRIG=1,C_SLOT_11_AXI_W_SEL_TRIG=1,C_SLOT_11_AXI_B_SEL_TRIG=1,C_SLOT_11_AXI_AR_SEL_TRIG=1,C_SLOT_11_AXI_R_SEL_TRIG=1,C_SLOT_12_AXI_AW_SEL_TRIG=1,C_SLOT_12_AXI_W_SEL_TRIG=1,C_SLOT_12_AXI_B_SEL_TRIG=1,C_SLOT_12_AXI_AR_SEL_TRIG=1,C_SLOT_12_AXI_R_SEL_TRIG=1,C_SLOT_13_AXI_AW_SEL_TRIG=1,C_SLOT_13_AXI_W_SEL_TRIG=1,C_SLOT_13_AXI_B_SEL_TRIG=1,C_SLOT_13_AXI_AR_SEL_TRIG=1,C_SLOT_13_AXI_R_SEL_TRIG=1,C_SLOT_14_AXI_AW_SEL_TRIG=1,C_SLOT_14_AXI_W_SEL_TRIG=1,C_SLO" &
|
||||
"T_14_AXI_B_SEL_TRIG=1,C_SLOT_14_AXI_AR_SEL_TRIG=1,C_SLOT_14_AXI_R_SEL_TRIG=1,C_SLOT_15_AXI_AW_SEL_TRIG=1,C_SLOT_15_AXI_W_SEL_TRIG=1,C_SLOT_15_AXI_B_SEL_TRIG=1,C_SLOT_15_AXI_AR_SEL_TRIG=1,C_SLOT_15_AXI_R_SEL_TRIG=1,C_SLOT_0_AXI_AW_SEL=1,C_SLOT_0_AXI_W_SEL=1,C_SLOT_0_AXI_B_SEL=1,C_SLOT_0_AXI_AR_SEL=1,C_SLOT_0_AXI_R_SEL=1,C_SLOT_1_AXI_AW_SEL=1,C_SLOT_1_AXI_W_SEL=1,C_SLOT_1_AXI_B_SEL=1,C_SLOT_1_AXI_AR_SEL=1,C_SLOT_1_AXI_R_SEL=1,C_SLOT_2_AXI_AW_SEL=1,C_SLOT_2_AXI_W_SEL=1,C_SLOT_2_AXI_B_SEL=1,C_SLOT_2" &
|
||||
"_AXI_AR_SEL=1,C_SLOT_2_AXI_R_SEL=1,C_SLOT_3_AXI_AW_SEL=1,C_SLOT_3_AXI_W_SEL=1,C_SLOT_3_AXI_B_SEL=1,C_SLOT_3_AXI_AR_SEL=1,C_SLOT_3_AXI_R_SEL=1,C_SLOT_4_AXI_AW_SEL=1,C_SLOT_4_AXI_W_SEL=1,C_SLOT_4_AXI_B_SEL=1,C_SLOT_4_AXI_AR_SEL=1,C_SLOT_4_AXI_R_SEL=1,C_SLOT_5_AXI_AW_SEL=1,C_SLOT_5_AXI_W_SEL=1,C_SLOT_5_AXI_B_SEL=1,C_SLOT_5_AXI_AR_SEL=1,C_SLOT_5_AXI_R_SEL=1,C_SLOT_6_AXI_AW_SEL=1,C_SLOT_6_AXI_W_SEL=1,C_SLOT_6_AXI_B_SEL=1,C_SLOT_6_AXI_AR_SEL=1,C_SLOT_6_AXI_R_SEL=1,C_SLOT_7_AXI_AW_SEL=1,C_SLOT_7_AXI_W_" &
|
||||
"SEL=1,C_SLOT_7_AXI_B_SEL=1,C_SLOT_7_AXI_AR_SEL=1,C_SLOT_7_AXI_R_SEL=1,C_SLOT_8_AXI_AW_SEL=1,C_SLOT_8_AXI_W_SEL=1,C_SLOT_8_AXI_B_SEL=1,C_SLOT_8_AXI_AR_SEL=1,C_SLOT_8_AXI_R_SEL=1,C_SLOT_9_AXI_AW_SEL=1,C_SLOT_9_AXI_W_SEL=1,C_SLOT_9_AXI_B_SEL=1,C_SLOT_9_AXI_AR_SEL=1,C_SLOT_9_AXI_R_SEL=1,C_SLOT_10_AXI_AW_SEL=1,C_SLOT_10_AXI_W_SEL=1,C_SLOT_10_AXI_B_SEL=1,C_SLOT_10_AXI_AR_SEL=1,C_SLOT_10_AXI_R_SEL=1,C_SLOT_11_AXI_AW_SEL=1,C_SLOT_11_AXI_W_SEL=1,C_SLOT_11_AXI_B_SEL=1,C_SLOT_11_AXI_AR_SEL=1,C_SLOT_11_AXI_" &
|
||||
"R_SEL=1,C_SLOT_12_AXI_AW_SEL=1,C_SLOT_12_AXI_W_SEL=1,C_SLOT_12_AXI_B_SEL=1,C_SLOT_12_AXI_AR_SEL=1,C_SLOT_12_AXI_R_SEL=1,C_SLOT_13_AXI_AW_SEL=1,C_SLOT_13_AXI_W_SEL=1,C_SLOT_13_AXI_B_SEL=1,C_SLOT_13_AXI_AR_SEL=1,C_SLOT_13_AXI_R_SEL=1,C_SLOT_14_AXI_AW_SEL=1,C_SLOT_14_AXI_W_SEL=1,C_SLOT_14_AXI_B_SEL=1,C_SLOT_14_AXI_AR_SEL=1,C_SLOT_14_AXI_R_SEL=1,C_SLOT_15_AXI_AW_SEL=1,C_SLOT_15_AXI_W_SEL=1,C_SLOT_15_AXI_B_SEL=1,C_SLOT_15_AXI_AR_SEL=1,C_SLOT_15_AXI_R_SEL=1,C_SLOT_0_AXI_DATA_SEL=1,C_SLOT_1_AXI_DATA_SE" &
|
||||
"L=1,C_SLOT_2_AXI_DATA_SEL=1,C_SLOT_3_AXI_DATA_SEL=1,C_SLOT_4_AXI_DATA_SEL=1,C_SLOT_5_AXI_DATA_SEL=1,C_SLOT_6_AXI_DATA_SEL=1,C_SLOT_7_AXI_DATA_SEL=1,C_SLOT_8_AXI_DATA_SEL=1,C_SLOT_9_AXI_DATA_SEL=1,C_SLOT_10_AXI_DATA_SEL=1,C_SLOT_11_AXI_DATA_SEL=1,C_SLOT_12_AXI_DATA_SEL=1,C_SLOT_13_AXI_DATA_SEL=1,C_SLOT_14_AXI_DATA_SEL=1,C_SLOT_15_AXI_DATA_SEL=1,C_SLOT_0_AXI_TRIG_SEL=1,C_SLOT_1_AXI_TRIG_SEL=1,C_SLOT_2_AXI_TRIG_SEL=1,C_SLOT_3_AXI_TRIG_SEL=1,C_SLOT_4_AXI_TRIG_SEL=1,C_SLOT_5_AXI_TRIG_SEL=1,C_SLOT_6_A" &
|
||||
"XI_TRIG_SEL=1,C_SLOT_7_AXI_TRIG_SEL=1,C_SLOT_8_AXI_TRIG_SEL=1,C_SLOT_9_AXI_TRIG_SEL=1,C_SLOT_10_AXI_TRIG_SEL=1,C_SLOT_11_AXI_TRIG_SEL=1,C_SLOT_12_AXI_TRIG_SEL=1,C_SLOT_13_AXI_TRIG_SEL=1,C_SLOT_14_AXI_TRIG_SEL=1,C_SLOT_15_AXI_TRIG_SEL=1,C_PROBE1023_TYPE=0,C_PROBE1022_TYPE=0,C_PROBE1021_TYPE=0,C_PROBE1020_TYPE=0,C_PROBE1019_TYPE=0,C_PROBE1018_TYPE=0,C_PROBE1017_TYPE=0,C_PROBE1016_TYPE=0,C_PROBE1015_TYPE=0,C_PROBE1014_TYPE=0,C_PROBE1013_TYPE=0,C_PROBE1012_TYPE=0,C_PROBE1011_TYPE=0,C_PROBE1010_TYPE=" &
|
||||
"0,C_PROBE1009_TYPE=0,C_PROBE1008_TYPE=0,C_PROBE1007_TYPE=0,C_PROBE1006_TYPE=0,C_PROBE1005_TYPE=0,C_PROBE1004_TYPE=0,C_PROBE1003_TYPE=0,C_PROBE1002_TYPE=0,C_PROBE1001_TYPE=0,C_PROBE1000_TYPE=0,C_PROBE999_TYPE=0,C_PROBE998_TYPE=0,C_PROBE997_TYPE=0,C_PROBE996_TYPE=0,C_PROBE995_TYPE=0,C_PROBE994_TYPE=0,C_PROBE993_TYPE=0,C_PROBE992_TYPE=0,C_PROBE991_TYPE=0,C_PROBE990_TYPE=0,C_PROBE989_TYPE=0,C_PROBE988_TYPE=0,C_PROBE987_TYPE=0,C_PROBE986_TYPE=0,C_PROBE985_TYPE=0,C_PROBE984_TYPE=0,C_PROBE983_TYPE=0,C_" &
|
||||
"PROBE982_TYPE=0,C_PROBE981_TYPE=0,C_PROBE980_TYPE=0,C_PROBE979_TYPE=0,C_PROBE978_TYPE=0,C_PROBE977_TYPE=0,C_PROBE976_TYPE=0,C_PROBE975_TYPE=0,C_PROBE974_TYPE=0,C_PROBE973_TYPE=0,C_PROBE972_TYPE=0,C_PROBE971_TYPE=0,C_PROBE970_TYPE=0,C_PROBE969_TYPE=0,C_PROBE968_TYPE=0,C_PROBE967_TYPE=0,C_PROBE966_TYPE=0,C_PROBE965_TYPE=0,C_PROBE964_TYPE=0,C_PROBE963_TYPE=0,C_PROBE962_TYPE=0,C_PROBE961_TYPE=0,C_PROBE960_TYPE=0,C_PROBE959_TYPE=0,C_PROBE958_TYPE=0,C_PROBE957_TYPE=0,C_PROBE956_TYPE=0,C_PROBE955_TYPE=" &
|
||||
"0,C_PROBE954_TYPE=0,C_PROBE953_TYPE=0,C_PROBE952_TYPE=0,C_PROBE951_TYPE=0,C_PROBE950_TYPE=0,C_PROBE949_TYPE=0,C_PROBE948_TYPE=0,C_PROBE947_TYPE=0,C_PROBE946_TYPE=0,C_PROBE945_TYPE=0,C_PROBE944_TYPE=0,C_PROBE943_TYPE=0,C_PROBE942_TYPE=0,C_PROBE941_TYPE=0,C_PROBE940_TYPE=0,C_PROBE939_TYPE=0,C_PROBE938_TYPE=0,C_PROBE937_TYPE=0,C_PROBE936_TYPE=0,C_PROBE935_TYPE=0,C_PROBE934_TYPE=0,C_PROBE933_TYPE=0,C_PROBE932_TYPE=0,C_PROBE931_TYPE=0,C_PROBE930_TYPE=0,C_PROBE929_TYPE=0,C_PROBE928_TYPE=0,C_PROBE927_T" &
|
||||
"YPE=0,C_PROBE926_TYPE=0,C_PROBE925_TYPE=0,C_PROBE924_TYPE=0,C_PROBE923_TYPE=0,C_PROBE922_TYPE=0,C_PROBE921_TYPE=0,C_PROBE920_TYPE=0,C_PROBE919_TYPE=0,C_PROBE918_TYPE=0,C_PROBE917_TYPE=0,C_PROBE916_TYPE=0,C_PROBE915_TYPE=0,C_PROBE914_TYPE=0,C_PROBE913_TYPE=0,C_PROBE912_TYPE=0,C_PROBE911_TYPE=0,C_PROBE910_TYPE=0,C_PROBE909_TYPE=0,C_PROBE908_TYPE=0,C_PROBE907_TYPE=0,C_PROBE906_TYPE=0,C_PROBE905_TYPE=0,C_PROBE904_TYPE=0,C_PROBE903_TYPE=0,C_PROBE902_TYPE=0,C_PROBE901_TYPE=0,C_PROBE900_TYPE=0,C_PROBE8" &
|
||||
"99_TYPE=0,C_PROBE898_TYPE=0,C_PROBE897_TYPE=0,C_PROBE896_TYPE=0,C_PROBE895_TYPE=0,C_PROBE894_TYPE=0,C_PROBE893_TYPE=0,C_PROBE892_TYPE=0,C_PROBE891_TYPE=0,C_PROBE890_TYPE=0,C_PROBE889_TYPE=0,C_PROBE888_TYPE=0,C_PROBE887_TYPE=0,C_PROBE886_TYPE=0,C_PROBE885_TYPE=0,C_PROBE884_TYPE=0,C_PROBE883_TYPE=0,C_PROBE882_TYPE=0,C_PROBE881_TYPE=0,C_PROBE880_TYPE=0,C_PROBE879_TYPE=0,C_PROBE878_TYPE=0,C_PROBE877_TYPE=0,C_PROBE876_TYPE=0,C_PROBE875_TYPE=0,C_PROBE874_TYPE=0,C_PROBE873_TYPE=0,C_PROBE872_TYPE=0,C_PR" &
|
||||
"OBE871_TYPE=0,C_PROBE870_TYPE=0,C_PROBE869_TYPE=0,C_PROBE868_TYPE=0,C_PROBE867_TYPE=0,C_PROBE866_TYPE=0,C_PROBE865_TYPE=0,C_PROBE864_TYPE=0,C_PROBE863_TYPE=0,C_PROBE862_TYPE=0,C_PROBE861_TYPE=0,C_PROBE860_TYPE=0,C_PROBE859_TYPE=0,C_PROBE858_TYPE=0,C_PROBE857_TYPE=0,C_PROBE856_TYPE=0,C_PROBE855_TYPE=0,C_PROBE854_TYPE=0,C_PROBE853_TYPE=0,C_PROBE852_TYPE=0,C_PROBE851_TYPE=0,C_PROBE850_TYPE=0,C_PROBE849_TYPE=0,C_PROBE848_TYPE=0,C_PROBE847_TYPE=0,C_PROBE846_TYPE=0,C_PROBE845_TYPE=0,C_PROBE844_TYPE=0," &
|
||||
"C_PROBE843_TYPE=0,C_PROBE842_TYPE=0,C_PROBE841_TYPE=0,C_PROBE840_TYPE=0,C_PROBE839_TYPE=0,C_PROBE838_TYPE=0,C_PROBE837_TYPE=0,C_PROBE836_TYPE=0,C_PROBE835_TYPE=0,C_PROBE834_TYPE=0,C_PROBE833_TYPE=0,C_PROBE832_TYPE=0,C_PROBE831_TYPE=0,C_PROBE830_TYPE=0,C_PROBE829_TYPE=0,C_PROBE828_TYPE=0,C_PROBE827_TYPE=0,C_PROBE826_TYPE=0,C_PROBE825_TYPE=0,C_PROBE824_TYPE=0,C_PROBE823_TYPE=0,C_PROBE822_TYPE=0,C_PROBE821_TYPE=0,C_PROBE820_TYPE=0,C_PROBE819_TYPE=0,C_PROBE818_TYPE=0,C_PROBE817_TYPE=0,C_PROBE816_TYP" &
|
||||
"E=0,C_PROBE815_TYPE=0,C_PROBE814_TYPE=0,C_PROBE813_TYPE=0,C_PROBE812_TYPE=0,C_PROBE811_TYPE=0,C_PROBE810_TYPE=0,C_PROBE809_TYPE=0,C_PROBE808_TYPE=0,C_PROBE807_TYPE=0,C_PROBE806_TYPE=0,C_PROBE805_TYPE=0,C_PROBE804_TYPE=0,C_PROBE803_TYPE=0,C_PROBE802_TYPE=0,C_PROBE801_TYPE=0,C_PROBE800_TYPE=0,C_PROBE799_TYPE=0,C_PROBE798_TYPE=0,C_PROBE797_TYPE=0,C_PROBE796_TYPE=0,C_PROBE795_TYPE=0,C_PROBE794_TYPE=0,C_PROBE793_TYPE=0,C_PROBE792_TYPE=0,C_PROBE791_TYPE=0,C_PROBE790_TYPE=0,C_PROBE789_TYPE=0,C_PROBE788" &
|
||||
"_TYPE=0,C_PROBE787_TYPE=0,C_PROBE786_TYPE=0,C_PROBE785_TYPE=0,C_PROBE784_TYPE=0,C_PROBE783_TYPE=0,C_PROBE782_TYPE=0,C_PROBE781_TYPE=0,C_PROBE780_TYPE=0,C_PROBE779_TYPE=0,C_PROBE778_TYPE=0,C_PROBE777_TYPE=0,C_PROBE776_TYPE=0,C_PROBE775_TYPE=0,C_PROBE774_TYPE=0,C_PROBE773_TYPE=0,C_PROBE772_TYPE=0,C_PROBE771_TYPE=0,C_PROBE770_TYPE=0,C_PROBE769_TYPE=0,C_PROBE768_TYPE=0,C_PROBE767_TYPE=0,C_PROBE766_TYPE=0,C_PROBE765_TYPE=0,C_PROBE764_TYPE=0,C_PROBE763_TYPE=0,C_PROBE762_TYPE=0,C_PROBE761_TYPE=0,C_PROB" &
|
||||
"E760_TYPE=0,C_PROBE759_TYPE=0,C_PROBE758_TYPE=0,C_PROBE757_TYPE=0,C_PROBE756_TYPE=0,C_PROBE755_TYPE=0,C_PROBE754_TYPE=0,C_PROBE753_TYPE=0,C_PROBE752_TYPE=0,C_PROBE751_TYPE=0,C_PROBE750_TYPE=0,C_PROBE749_TYPE=0,C_PROBE748_TYPE=0,C_PROBE747_TYPE=0,C_PROBE746_TYPE=0,C_PROBE745_TYPE=0,C_PROBE744_TYPE=0,C_PROBE743_TYPE=0,C_PROBE742_TYPE=0,C_PROBE741_TYPE=0,C_PROBE740_TYPE=0,C_PROBE739_TYPE=0,C_PROBE738_TYPE=0,C_PROBE737_TYPE=0,C_PROBE736_TYPE=0,C_PROBE735_TYPE=0,C_PROBE734_TYPE=0,C_PROBE733_TYPE=0,C_" &
|
||||
"PROBE732_TYPE=0,C_PROBE731_TYPE=0,C_PROBE730_TYPE=0,C_PROBE729_TYPE=0,C_PROBE728_TYPE=0,C_PROBE727_TYPE=0,C_PROBE726_TYPE=0,C_PROBE725_TYPE=0,C_PROBE724_TYPE=0,C_PROBE723_TYPE=0,C_PROBE722_TYPE=0,C_PROBE721_TYPE=0,C_PROBE720_TYPE=0,C_PROBE719_TYPE=0,C_PROBE718_TYPE=0,C_PROBE717_TYPE=0,C_PROBE716_TYPE=0,C_PROBE715_TYPE=0,C_PROBE714_TYPE=0,C_PROBE713_TYPE=0,C_PROBE712_TYPE=0,C_PROBE711_TYPE=0,C_PROBE710_TYPE=0,C_PROBE709_TYPE=0,C_PROBE708_TYPE=0,C_PROBE707_TYPE=0,C_PROBE706_TYPE=0,C_PROBE705_TYPE=" &
|
||||
"0,C_PROBE704_TYPE=0,C_PROBE703_TYPE=0,C_PROBE702_TYPE=0,C_PROBE701_TYPE=0,C_PROBE700_TYPE=0,C_PROBE699_TYPE=0,C_PROBE698_TYPE=0,C_PROBE697_TYPE=0,C_PROBE696_TYPE=0,C_PROBE695_TYPE=0,C_PROBE694_TYPE=0,C_PROBE693_TYPE=0,C_PROBE692_TYPE=0,C_PROBE691_TYPE=0,C_PROBE690_TYPE=0,C_PROBE689_TYPE=0,C_PROBE688_TYPE=0,C_PROBE687_TYPE=0,C_PROBE686_TYPE=0,C_PROBE685_TYPE=0,C_PROBE684_TYPE=0,C_PROBE683_TYPE=0,C_PROBE682_TYPE=0,C_PROBE681_TYPE=0,C_PROBE680_TYPE=0,C_PROBE679_TYPE=0,C_PROBE678_TYPE=0,C_PROBE677_T" &
|
||||
"YPE=0,C_PROBE676_TYPE=0,C_PROBE675_TYPE=0,C_PROBE674_TYPE=0,C_PROBE673_TYPE=0,C_PROBE672_TYPE=0,C_PROBE671_TYPE=0,C_PROBE670_TYPE=0,C_PROBE669_TYPE=0,C_PROBE668_TYPE=0,C_PROBE667_TYPE=0,C_PROBE666_TYPE=0,C_PROBE665_TYPE=0,C_PROBE664_TYPE=0,C_PROBE663_TYPE=0,C_PROBE662_TYPE=0,C_PROBE661_TYPE=0,C_PROBE660_TYPE=0,C_PROBE659_TYPE=0,C_PROBE658_TYPE=0,C_PROBE657_TYPE=0,C_PROBE656_TYPE=0,C_PROBE655_TYPE=0,C_PROBE654_TYPE=0,C_PROBE653_TYPE=0,C_PROBE652_TYPE=0,C_PROBE651_TYPE=0,C_PROBE650_TYPE=0,C_PROBE6" &
|
||||
"49_TYPE=0,C_PROBE648_TYPE=0,C_PROBE647_TYPE=0,C_PROBE646_TYPE=0,C_PROBE645_TYPE=0,C_PROBE644_TYPE=0,C_PROBE643_TYPE=0,C_PROBE642_TYPE=0,C_PROBE641_TYPE=0,C_PROBE640_TYPE=0,C_PROBE639_TYPE=0,C_PROBE638_TYPE=0,C_PROBE637_TYPE=0,C_PROBE636_TYPE=0,C_PROBE635_TYPE=0,C_PROBE634_TYPE=0,C_PROBE633_TYPE=0,C_PROBE632_TYPE=0,C_PROBE631_TYPE=0,C_PROBE630_TYPE=0,C_PROBE629_TYPE=0,C_PROBE628_TYPE=0,C_PROBE627_TYPE=0,C_PROBE626_TYPE=0,C_PROBE625_TYPE=0,C_PROBE624_TYPE=0,C_PROBE623_TYPE=0,C_PROBE622_TYPE=0,C_PR" &
|
||||
"OBE621_TYPE=0,C_PROBE620_TYPE=0,C_PROBE619_TYPE=0,C_PROBE618_TYPE=0,C_PROBE617_TYPE=0,C_PROBE616_TYPE=0,C_PROBE615_TYPE=0,C_PROBE614_TYPE=0,C_PROBE613_TYPE=0,C_PROBE612_TYPE=0,C_PROBE611_TYPE=0,C_PROBE610_TYPE=0,C_PROBE609_TYPE=0,C_PROBE608_TYPE=0,C_PROBE607_TYPE=0,C_PROBE606_TYPE=0,C_PROBE605_TYPE=0,C_PROBE604_TYPE=0,C_PROBE603_TYPE=0,C_PROBE602_TYPE=0,C_PROBE601_TYPE=0,C_PROBE600_TYPE=0,C_PROBE599_TYPE=0,C_PROBE598_TYPE=0,C_PROBE597_TYPE=0,C_PROBE596_TYPE=0,C_PROBE595_TYPE=0,C_PROBE594_TYPE=0," &
|
||||
"C_PROBE593_TYPE=0,C_PROBE592_TYPE=0,C_PROBE591_TYPE=0,C_PROBE590_TYPE=0,C_PROBE589_TYPE=0,C_PROBE588_TYPE=0,C_PROBE587_TYPE=0,C_PROBE586_TYPE=0,C_PROBE585_TYPE=0,C_PROBE584_TYPE=0,C_PROBE583_TYPE=0,C_PROBE582_TYPE=0,C_PROBE581_TYPE=0,C_PROBE580_TYPE=0,C_PROBE579_TYPE=0,C_PROBE578_TYPE=0,C_PROBE577_TYPE=0,C_PROBE576_TYPE=0,C_PROBE575_TYPE=0,C_PROBE574_TYPE=0,C_PROBE573_TYPE=0,C_PROBE572_TYPE=0,C_PROBE571_TYPE=0,C_PROBE570_TYPE=0,C_PROBE569_TYPE=0,C_PROBE568_TYPE=0,C_PROBE567_TYPE=0,C_PROBE566_TYP" &
|
||||
"E=0,C_PROBE565_TYPE=0,C_PROBE564_TYPE=0,C_PROBE563_TYPE=0,C_PROBE562_TYPE=0,C_PROBE561_TYPE=0,C_PROBE560_TYPE=0,C_PROBE559_TYPE=0,C_PROBE558_TYPE=0,C_PROBE557_TYPE=0,C_PROBE556_TYPE=0,C_PROBE555_TYPE=0,C_PROBE554_TYPE=0,C_PROBE553_TYPE=0,C_PROBE552_TYPE=0,C_PROBE551_TYPE=0,C_PROBE550_TYPE=0,C_PROBE549_TYPE=0,C_PROBE548_TYPE=0,C_PROBE547_TYPE=0,C_PROBE546_TYPE=0,C_PROBE545_TYPE=0,C_PROBE544_TYPE=0,C_PROBE543_TYPE=0,C_PROBE542_TYPE=0,C_PROBE541_TYPE=0,C_PROBE540_TYPE=0,C_PROBE539_TYPE=0,C_PROBE538" &
|
||||
"_TYPE=0,C_PROBE537_TYPE=0,C_PROBE536_TYPE=0,C_PROBE535_TYPE=0,C_PROBE534_TYPE=0,C_PROBE533_TYPE=0,C_PROBE532_TYPE=0,C_PROBE531_TYPE=0,C_PROBE530_TYPE=0,C_PROBE529_TYPE=0,C_PROBE528_TYPE=0,C_PROBE527_TYPE=0,C_PROBE526_TYPE=0,C_PROBE525_TYPE=0,C_PROBE524_TYPE=0,C_PROBE523_TYPE=0,C_PROBE522_TYPE=0,C_PROBE521_TYPE=0,C_PROBE520_TYPE=0,C_PROBE519_TYPE=0,C_PROBE518_TYPE=0,C_PROBE517_TYPE=0,C_PROBE516_TYPE=0,C_PROBE515_TYPE=0,C_PROBE514_TYPE=0,C_PROBE513_TYPE=0,C_PROBE512_TYPE=0,C_PROBE511_TYPE=0,C_PROB" &
|
||||
"E510_TYPE=0,C_PROBE509_TYPE=0,C_PROBE508_TYPE=0,C_PROBE507_TYPE=0,C_PROBE506_TYPE=0,C_PROBE505_TYPE=0,C_PROBE504_TYPE=0,C_PROBE503_TYPE=0,C_PROBE502_TYPE=0,C_PROBE501_TYPE=0,C_PROBE500_TYPE=0,C_PROBE499_TYPE=0,C_PROBE498_TYPE=0,C_PROBE497_TYPE=0,C_PROBE496_TYPE=0,C_PROBE495_TYPE=0,C_PROBE494_TYPE=0,C_PROBE493_TYPE=0,C_PROBE492_TYPE=0,C_PROBE491_TYPE=0,C_PROBE490_TYPE=0,C_PROBE489_TYPE=0,C_PROBE488_TYPE=0,C_PROBE487_TYPE=0,C_PROBE486_TYPE=0,C_PROBE485_TYPE=0,C_PROBE484_TYPE=0,C_PROBE483_TYPE=0,C_" &
|
||||
"PROBE482_TYPE=0,C_PROBE481_TYPE=0,C_PROBE480_TYPE=0,C_PROBE479_TYPE=0,C_PROBE478_TYPE=0,C_PROBE477_TYPE=0,C_PROBE476_TYPE=0,C_PROBE475_TYPE=0,C_PROBE474_TYPE=0,C_PROBE473_TYPE=0,C_PROBE472_TYPE=0,C_PROBE471_TYPE=0,C_PROBE470_TYPE=0,C_PROBE469_TYPE=0,C_PROBE468_TYPE=0,C_PROBE467_TYPE=0,C_PROBE466_TYPE=0,C_PROBE465_TYPE=0,C_PROBE464_TYPE=0,C_PROBE463_TYPE=0,C_PROBE462_TYPE=0,C_PROBE461_TYPE=0,C_PROBE460_TYPE=0,C_PROBE459_TYPE=0,C_PROBE458_TYPE=0,C_PROBE457_TYPE=0,C_PROBE456_TYPE=0,C_PROBE455_TYPE=" &
|
||||
"0,C_PROBE454_TYPE=0,C_PROBE453_TYPE=0,C_PROBE452_TYPE=0,C_PROBE451_TYPE=0,C_PROBE450_TYPE=0,C_PROBE449_TYPE=0,C_PROBE448_TYPE=0,C_PROBE447_TYPE=0,C_PROBE446_TYPE=0,C_PROBE445_TYPE=0,C_PROBE444_TYPE=0,C_PROBE443_TYPE=0,C_PROBE442_TYPE=0,C_PROBE441_TYPE=0,C_PROBE440_TYPE=0,C_PROBE439_TYPE=0,C_PROBE438_TYPE=0,C_PROBE437_TYPE=0,C_PROBE436_TYPE=0,C_PROBE435_TYPE=0,C_PROBE434_TYPE=0,C_PROBE433_TYPE=0,C_PROBE432_TYPE=0,C_PROBE431_TYPE=0,C_PROBE430_TYPE=0,C_PROBE429_TYPE=0,C_PROBE428_TYPE=0,C_PROBE427_T" &
|
||||
"YPE=0,C_PROBE426_TYPE=0,C_PROBE425_TYPE=0,C_PROBE424_TYPE=0,C_PROBE423_TYPE=0,C_PROBE422_TYPE=0,C_PROBE421_TYPE=0,C_PROBE420_TYPE=0,C_PROBE419_TYPE=0,C_PROBE418_TYPE=0,C_PROBE417_TYPE=0,C_PROBE416_TYPE=0,C_PROBE415_TYPE=0,C_PROBE414_TYPE=0,C_PROBE413_TYPE=0,C_PROBE412_TYPE=0,C_PROBE411_TYPE=0,C_PROBE410_TYPE=0,C_PROBE409_TYPE=0,C_PROBE408_TYPE=0,C_PROBE407_TYPE=0,C_PROBE406_TYPE=0,C_PROBE405_TYPE=0,C_PROBE404_TYPE=0,C_PROBE403_TYPE=0,C_PROBE402_TYPE=0,C_PROBE401_TYPE=0,C_PROBE400_TYPE=0,C_PROBE3" &
|
||||
"99_TYPE=0,C_PROBE398_TYPE=0,C_PROBE397_TYPE=0,C_PROBE396_TYPE=0,C_PROBE395_TYPE=0,C_PROBE394_TYPE=0,C_PROBE393_TYPE=0,C_PROBE392_TYPE=0,C_PROBE391_TYPE=0,C_PROBE390_TYPE=0,C_PROBE389_TYPE=0,C_PROBE388_TYPE=0,C_PROBE387_TYPE=0,C_PROBE386_TYPE=0,C_PROBE385_TYPE=0,C_PROBE384_TYPE=0,C_PROBE383_TYPE=0,C_PROBE382_TYPE=0,C_PROBE381_TYPE=0,C_PROBE380_TYPE=0,C_PROBE379_TYPE=0,C_PROBE378_TYPE=0,C_PROBE377_TYPE=0,C_PROBE376_TYPE=0,C_PROBE375_TYPE=0,C_PROBE374_TYPE=0,C_PROBE373_TYPE=0,C_PROBE372_TYPE=0,C_PR" &
|
||||
"OBE371_TYPE=0,C_PROBE370_TYPE=0,C_PROBE369_TYPE=0,C_PROBE368_TYPE=0,C_PROBE367_TYPE=0,C_PROBE366_TYPE=0,C_PROBE365_TYPE=0,C_PROBE364_TYPE=0,C_PROBE363_TYPE=0,C_PROBE362_TYPE=0,C_PROBE361_TYPE=0,C_PROBE360_TYPE=0,C_PROBE359_TYPE=0,C_PROBE358_TYPE=0,C_PROBE357_TYPE=0,C_PROBE356_TYPE=0,C_PROBE355_TYPE=0,C_PROBE354_TYPE=0,C_PROBE353_TYPE=0,C_PROBE352_TYPE=0,C_PROBE351_TYPE=0,C_PROBE350_TYPE=0,C_PROBE349_TYPE=0,C_PROBE348_TYPE=0,C_PROBE347_TYPE=0,C_PROBE346_TYPE=0,C_PROBE345_TYPE=0,C_PROBE344_TYPE=0," &
|
||||
"C_PROBE343_TYPE=0,C_PROBE342_TYPE=0,C_PROBE341_TYPE=0,C_PROBE340_TYPE=0,C_PROBE339_TYPE=0,C_PROBE338_TYPE=0,C_PROBE337_TYPE=0,C_PROBE336_TYPE=0,C_PROBE335_TYPE=0,C_PROBE334_TYPE=0,C_PROBE333_TYPE=0,C_PROBE332_TYPE=0,C_PROBE331_TYPE=0,C_PROBE330_TYPE=0,C_PROBE329_TYPE=0,C_PROBE328_TYPE=0,C_PROBE327_TYPE=0,C_PROBE326_TYPE=0,C_PROBE325_TYPE=0,C_PROBE324_TYPE=0,C_PROBE323_TYPE=0,C_PROBE322_TYPE=0,C_PROBE321_TYPE=0,C_PROBE320_TYPE=0,C_PROBE319_TYPE=0,C_PROBE318_TYPE=0,C_PROBE317_TYPE=0,C_PROBE316_TYP" &
|
||||
"E=0,C_PROBE315_TYPE=0,C_PROBE314_TYPE=0,C_PROBE313_TYPE=0,C_PROBE312_TYPE=0,C_PROBE311_TYPE=0,C_PROBE310_TYPE=0,C_PROBE309_TYPE=0,C_PROBE308_TYPE=0,C_PROBE307_TYPE=0,C_PROBE306_TYPE=0,C_PROBE305_TYPE=0,C_PROBE304_TYPE=0,C_PROBE303_TYPE=0,C_PROBE302_TYPE=0,C_PROBE301_TYPE=0,C_PROBE300_TYPE=0,C_PROBE299_TYPE=0,C_PROBE298_TYPE=0,C_PROBE297_TYPE=0,C_PROBE296_TYPE=0,C_PROBE295_TYPE=0,C_PROBE294_TYPE=0,C_PROBE293_TYPE=0,C_PROBE292_TYPE=0,C_PROBE291_TYPE=0,C_PROBE290_TYPE=0,C_PROBE289_TYPE=0,C_PROBE288" &
|
||||
"_TYPE=0,C_PROBE287_TYPE=0,C_PROBE286_TYPE=0,C_PROBE285_TYPE=0,C_PROBE284_TYPE=0,C_PROBE283_TYPE=0,C_PROBE282_TYPE=0,C_PROBE281_TYPE=0,C_PROBE280_TYPE=0,C_PROBE279_TYPE=0,C_PROBE278_TYPE=0,C_PROBE277_TYPE=0,C_PROBE276_TYPE=0,C_PROBE275_TYPE=0,C_PROBE274_TYPE=0,C_PROBE273_TYPE=0,C_PROBE272_TYPE=0,C_PROBE271_TYPE=0,C_PROBE270_TYPE=0,C_PROBE269_TYPE=0,C_PROBE268_TYPE=0,C_PROBE267_TYPE=0,C_PROBE266_TYPE=0,C_PROBE265_TYPE=0,C_PROBE264_TYPE=0,C_PROBE263_TYPE=0,C_PROBE262_TYPE=0,C_PROBE261_TYPE=0,C_PROB" &
|
||||
"E260_TYPE=0,C_PROBE259_TYPE=0,C_PROBE258_TYPE=0,C_PROBE257_TYPE=0,C_PROBE256_TYPE=0,C_PROBE255_TYPE=0,C_PROBE254_TYPE=0,C_PROBE253_TYPE=0,C_PROBE252_TYPE=0,C_PROBE251_TYPE=0,C_PROBE250_TYPE=0,C_PROBE249_TYPE=0,C_PROBE248_TYPE=0,C_PROBE247_TYPE=0,C_PROBE246_TYPE=0,C_PROBE245_TYPE=0,C_PROBE244_TYPE=0,C_PROBE243_TYPE=0,C_PROBE242_TYPE=0,C_PROBE241_TYPE=0,C_PROBE240_TYPE=0,C_PROBE239_TYPE=0,C_PROBE238_TYPE=0,C_PROBE237_TYPE=0,C_PROBE236_TYPE=0,C_PROBE235_TYPE=0,C_PROBE234_TYPE=0,C_PROBE233_TYPE=0,C_" &
|
||||
"PROBE232_TYPE=0,C_PROBE231_TYPE=0,C_PROBE230_TYPE=0,C_PROBE229_TYPE=0,C_PROBE228_TYPE=0,C_PROBE227_TYPE=0,C_PROBE226_TYPE=0,C_PROBE225_TYPE=0,C_PROBE224_TYPE=0,C_PROBE223_TYPE=0,C_PROBE222_TYPE=0,C_PROBE221_TYPE=0,C_PROBE220_TYPE=0,C_PROBE219_TYPE=0,C_PROBE218_TYPE=0,C_PROBE217_TYPE=0,C_PROBE216_TYPE=0,C_PROBE215_TYPE=0,C_PROBE214_TYPE=0,C_PROBE213_TYPE=0,C_PROBE212_TYPE=0,C_PROBE211_TYPE=0,C_PROBE210_TYPE=0,C_PROBE209_TYPE=0,C_PROBE208_TYPE=0,C_PROBE207_TYPE=0,C_PROBE206_TYPE=0,C_PROBE205_TYPE=" &
|
||||
"0,C_PROBE204_TYPE=0,C_PROBE203_TYPE=0,C_PROBE202_TYPE=0,C_PROBE201_TYPE=0,C_PROBE200_TYPE=0,C_PROBE199_TYPE=0,C_PROBE198_TYPE=0,C_PROBE197_TYPE=0,C_PROBE196_TYPE=0,C_PROBE195_TYPE=0,C_PROBE194_TYPE=0,C_PROBE193_TYPE=0,C_PROBE192_TYPE=0,C_PROBE191_TYPE=0,C_PROBE190_TYPE=0,C_PROBE189_TYPE=0,C_PROBE188_TYPE=0,C_PROBE187_TYPE=0,C_PROBE186_TYPE=0,C_PROBE185_TYPE=0,C_PROBE184_TYPE=0,C_PROBE183_TYPE=0,C_PROBE182_TYPE=0,C_PROBE181_TYPE=0,C_PROBE180_TYPE=0,C_PROBE179_TYPE=0,C_PROBE178_TYPE=0,C_PROBE177_T" &
|
||||
"YPE=0,C_PROBE176_TYPE=0,C_PROBE175_TYPE=0,C_PROBE174_TYPE=0,C_PROBE173_TYPE=0,C_PROBE172_TYPE=0,C_PROBE171_TYPE=0,C_PROBE170_TYPE=0,C_PROBE169_TYPE=0,C_PROBE168_TYPE=0,C_PROBE167_TYPE=0,C_PROBE166_TYPE=0,C_PROBE165_TYPE=0,C_PROBE164_TYPE=0,C_PROBE163_TYPE=0,C_PROBE162_TYPE=0,C_PROBE161_TYPE=0,C_PROBE160_TYPE=0,C_PROBE159_TYPE=0,C_PROBE158_TYPE=0,C_PROBE157_TYPE=0,C_PROBE156_TYPE=0,C_PROBE155_TYPE=0,C_PROBE154_TYPE=0,C_PROBE153_TYPE=0,C_PROBE152_TYPE=0,C_PROBE151_TYPE=0,C_PROBE150_TYPE=0,C_PROBE1" &
|
||||
"49_TYPE=0,C_PROBE148_TYPE=0,C_PROBE147_TYPE=0,C_PROBE146_TYPE=0,C_PROBE145_TYPE=0,C_PROBE144_TYPE=0,C_PROBE143_TYPE=0,C_PROBE142_TYPE=0,C_PROBE141_TYPE=0,C_PROBE140_TYPE=0,C_PROBE139_TYPE=0,C_PROBE138_TYPE=0,C_PROBE137_TYPE=0,C_PROBE136_TYPE=0,C_PROBE135_TYPE=0,C_PROBE134_TYPE=0,C_PROBE133_TYPE=0,C_PROBE132_TYPE=0,C_PROBE131_TYPE=0,C_PROBE130_TYPE=0,C_PROBE129_TYPE=0,C_PROBE128_TYPE=0,C_PROBE127_TYPE=0,C_PROBE126_TYPE=0,C_PROBE125_TYPE=0,C_PROBE124_TYPE=0,C_PROBE123_TYPE=0,C_PROBE122_TYPE=0,C_PR" &
|
||||
"OBE121_TYPE=0,C_PROBE120_TYPE=0,C_PROBE119_TYPE=0,C_PROBE118_TYPE=0,C_PROBE117_TYPE=0,C_PROBE116_TYPE=0,C_PROBE115_TYPE=0,C_PROBE114_TYPE=0,C_PROBE113_TYPE=0,C_PROBE112_TYPE=0,C_PROBE111_TYPE=0,C_PROBE110_TYPE=0,C_PROBE109_TYPE=0,C_PROBE108_TYPE=0,C_PROBE107_TYPE=0,C_PROBE106_TYPE=0,C_PROBE105_TYPE=0,C_PROBE104_TYPE=0,C_PROBE103_TYPE=0,C_PROBE102_TYPE=0,C_PROBE101_TYPE=0,C_PROBE100_TYPE=0,C_PROBE99_TYPE=0,C_PROBE98_TYPE=0,C_PROBE97_TYPE=0,C_PROBE96_TYPE=0,C_PROBE95_TYPE=0,C_PROBE94_TYPE=0,C_PROB" &
|
||||
"E93_TYPE=0,C_PROBE92_TYPE=0,C_PROBE91_TYPE=0,C_PROBE90_TYPE=0,C_PROBE89_TYPE=0,C_PROBE88_TYPE=0,C_PROBE87_TYPE=0,C_PROBE86_TYPE=0,C_PROBE85_TYPE=0,C_PROBE84_TYPE=0,C_PROBE83_TYPE=0,C_PROBE82_TYPE=0,C_PROBE81_TYPE=0,C_PROBE80_TYPE=0,C_PROBE79_TYPE=0,C_PROBE78_TYPE=0,C_PROBE77_TYPE=0,C_PROBE76_TYPE=0,C_PROBE75_TYPE=0,C_PROBE74_TYPE=0,C_PROBE73_TYPE=0,C_PROBE72_TYPE=0,C_PROBE71_TYPE=0,C_PROBE70_TYPE=0,C_PROBE69_TYPE=0,C_PROBE68_TYPE=0,C_PROBE67_TYPE=0,C_PROBE66_TYPE=0,C_PROBE65_TYPE=0,C_PROBE64_TYP" &
|
||||
"E=0,C_PROBE63_TYPE=0,C_PROBE62_TYPE=0,C_PROBE61_TYPE=0,C_PROBE60_TYPE=0,C_PROBE59_TYPE=0,C_PROBE58_TYPE=0,C_PROBE57_TYPE=0,C_PROBE56_TYPE=0,C_PROBE55_TYPE=0,C_PROBE54_TYPE=0,C_PROBE53_TYPE=0,C_PROBE52_TYPE=0,C_PROBE51_TYPE=0,C_PROBE50_TYPE=0,C_PROBE49_TYPE=0,C_PROBE48_TYPE=0,C_PROBE47_TYPE=0,C_PROBE46_TYPE=0,C_PROBE45_TYPE=0,C_PROBE44_TYPE=0,C_PROBE43_TYPE=0,C_PROBE42_TYPE=0,C_PROBE41_TYPE=0,C_PROBE40_TYPE=0,C_PROBE39_TYPE=0,C_PROBE38_TYPE=0,C_PROBE37_TYPE=0,C_PROBE36_TYPE=0,C_PROBE35_TYPE=0,C_P" &
|
||||
"ROBE34_TYPE=0,C_PROBE33_TYPE=0,C_PROBE32_TYPE=0,C_PROBE31_TYPE=0,C_PROBE30_TYPE=0,C_PROBE29_TYPE=0,C_PROBE28_TYPE=0,C_PROBE27_TYPE=0,C_PROBE26_TYPE=0,C_PROBE25_TYPE=0,C_PROBE24_TYPE=0,C_PROBE23_TYPE=0,C_PROBE22_TYPE=0,C_PROBE21_TYPE=0,C_PROBE20_TYPE=0,C_PROBE19_TYPE=0,C_PROBE18_TYPE=0,C_PROBE17_TYPE=0,C_PROBE16_TYPE=0,C_PROBE15_TYPE=0,C_PROBE14_TYPE=0,C_PROBE13_TYPE=0,C_PROBE12_TYPE=0,C_PROBE11_TYPE=0,C_PROBE10_TYPE=0,C_PROBE9_TYPE=0,C_PROBE8_TYPE=0,C_PROBE7_TYPE=0,C_PROBE6_TYPE=0,C_PROBE5_TYPE=" &
|
||||
"0,C_PROBE4_TYPE=0,C_PROBE3_TYPE=0,C_PROBE2_TYPE=0,C_PROBE1_TYPE=0,C_PROBE0_TYPE=0,C_PROBE1023_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1003_WIDTH=" &
|
||||
"1,C_PROBE1002_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE977_WIDTH=1,C" &
|
||||
"_PROBE976_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE957_WIDTH=1,C_PROBE956_WIDTH=1,C_PROBE955_WIDTH=1,C_PROBE954_WIDTH=1,C_PROBE953_WIDTH=1,C_PROBE952_WIDTH=1,C_PROBE951_WIDTH=1,C_PROBE" &
|
||||
"950_WIDTH=1,C_PROBE949_WIDTH=1,C_PROBE948_WIDTH=1,C_PROBE947_WIDTH=1,C_PROBE946_WIDTH=1,C_PROBE945_WIDTH=1,C_PROBE944_WIDTH=1,C_PROBE943_WIDTH=1,C_PROBE942_WIDTH=1,C_PROBE941_WIDTH=1,C_PROBE940_WIDTH=1,C_PROBE939_WIDTH=1,C_PROBE938_WIDTH=1,C_PROBE937_WIDTH=1,C_PROBE936_WIDTH=1,C_PROBE935_WIDTH=1,C_PROBE934_WIDTH=1,C_PROBE933_WIDTH=1,C_PROBE932_WIDTH=1,C_PROBE931_WIDTH=1,C_PROBE930_WIDTH=1,C_PROBE929_WIDTH=1,C_PROBE928_WIDTH=1,C_PROBE927_WIDTH=1,C_PROBE926_WIDTH=1,C_PROBE925_WIDTH=1,C_PROBE924_WI" &
|
||||
"DTH=1,C_PROBE923_WIDTH=1,C_PROBE922_WIDTH=1,C_PROBE921_WIDTH=1,C_PROBE920_WIDTH=1,C_PROBE919_WIDTH=1,C_PROBE918_WIDTH=1,C_PROBE917_WIDTH=1,C_PROBE916_WIDTH=1,C_PROBE915_WIDTH=1,C_PROBE914_WIDTH=1,C_PROBE913_WIDTH=1,C_PROBE912_WIDTH=1,C_PROBE911_WIDTH=1,C_PROBE910_WIDTH=1,C_PROBE909_WIDTH=1,C_PROBE908_WIDTH=1,C_PROBE907_WIDTH=1,C_PROBE906_WIDTH=1,C_PROBE905_WIDTH=1,C_PROBE904_WIDTH=1,C_PROBE903_WIDTH=1,C_PROBE902_WIDTH=1,C_PROBE901_WIDTH=1,C_PROBE900_WIDTH=1,C_PROBE899_WIDTH=1,C_PROBE898_WIDTH=1," &
|
||||
"C_PROBE897_WIDTH=1,C_PROBE896_WIDTH=1,C_PROBE895_WIDTH=1,C_PROBE894_WIDTH=1,C_PROBE893_WIDTH=1,C_PROBE892_WIDTH=1,C_PROBE891_WIDTH=1,C_PROBE890_WIDTH=1,C_PROBE889_WIDTH=1,C_PROBE888_WIDTH=1,C_PROBE887_WIDTH=1,C_PROBE886_WIDTH=1,C_PROBE885_WIDTH=1,C_PROBE884_WIDTH=1,C_PROBE883_WIDTH=1,C_PROBE882_WIDTH=1,C_PROBE881_WIDTH=1,C_PROBE880_WIDTH=1,C_PROBE879_WIDTH=1,C_PROBE878_WIDTH=1,C_PROBE877_WIDTH=1,C_PROBE876_WIDTH=1,C_PROBE875_WIDTH=1,C_PROBE874_WIDTH=1,C_PROBE873_WIDTH=1,C_PROBE872_WIDTH=1,C_PROB" &
|
||||
"E871_WIDTH=1,C_PROBE870_WIDTH=1,C_PROBE869_WIDTH=1,C_PROBE868_WIDTH=1,C_PROBE867_WIDTH=1,C_PROBE866_WIDTH=1,C_PROBE865_WIDTH=1,C_PROBE864_WIDTH=1,C_PROBE863_WIDTH=1,C_PROBE862_WIDTH=1,C_PROBE861_WIDTH=1,C_PROBE860_WIDTH=1,C_PROBE859_WIDTH=1,C_PROBE858_WIDTH=1,C_PROBE857_WIDTH=1,C_PROBE856_WIDTH=1,C_PROBE855_WIDTH=1,C_PROBE854_WIDTH=1,C_PROBE853_WIDTH=1,C_PROBE852_WIDTH=1,C_PROBE851_WIDTH=1,C_PROBE850_WIDTH=1,C_PROBE849_WIDTH=1,C_PROBE848_WIDTH=1,C_PROBE847_WIDTH=1,C_PROBE846_WIDTH=1,C_PROBE845_W" &
|
||||
"IDTH=1,C_PROBE844_WIDTH=1,C_PROBE843_WIDTH=1,C_PROBE842_WIDTH=1,C_PROBE841_WIDTH=1,C_PROBE840_WIDTH=1,C_PROBE839_WIDTH=1,C_PROBE838_WIDTH=1,C_PROBE837_WIDTH=1,C_PROBE836_WIDTH=1,C_PROBE835_WIDTH=1,C_PROBE834_WIDTH=1,C_PROBE833_WIDTH=1,C_PROBE832_WIDTH=1,C_PROBE831_WIDTH=1,C_PROBE830_WIDTH=1,C_PROBE829_WIDTH=1,C_PROBE828_WIDTH=1,C_PROBE827_WIDTH=1,C_PROBE826_WIDTH=1,C_PROBE825_WIDTH=1,C_PROBE824_WIDTH=1,C_PROBE823_WIDTH=1,C_PROBE822_WIDTH=1,C_PROBE821_WIDTH=1,C_PROBE820_WIDTH=1,C_PROBE819_WIDTH=1" &
|
||||
",C_PROBE818_WIDTH=1,C_PROBE817_WIDTH=1,C_PROBE816_WIDTH=1,C_PROBE815_WIDTH=1,C_PROBE814_WIDTH=1,C_PROBE813_WIDTH=1,C_PROBE812_WIDTH=1,C_PROBE811_WIDTH=1,C_PROBE810_WIDTH=1,C_PROBE809_WIDTH=1,C_PROBE808_WIDTH=1,C_PROBE807_WIDTH=1,C_PROBE806_WIDTH=1,C_PROBE805_WIDTH=1,C_PROBE804_WIDTH=1,C_PROBE803_WIDTH=1,C_PROBE802_WIDTH=1,C_PROBE801_WIDTH=1,C_PROBE800_WIDTH=1,C_PROBE799_WIDTH=1,C_PROBE798_WIDTH=1,C_PROBE797_WIDTH=1,C_PROBE796_WIDTH=1,C_PROBE795_WIDTH=1,C_PROBE794_WIDTH=1,C_PROBE793_WIDTH=1,C_PRO" &
|
||||
"BE792_WIDTH=1,C_PROBE791_WIDTH=1,C_PROBE790_WIDTH=1,C_PROBE789_WIDTH=1,C_PROBE788_WIDTH=1,C_PROBE787_WIDTH=1,C_PROBE786_WIDTH=1,C_PROBE785_WIDTH=1,C_PROBE784_WIDTH=1,C_PROBE783_WIDTH=1,C_PROBE782_WIDTH=1,C_PROBE781_WIDTH=1,C_PROBE780_WIDTH=1,C_PROBE779_WIDTH=1,C_PROBE778_WIDTH=1,C_PROBE777_WIDTH=1,C_PROBE776_WIDTH=1,C_PROBE775_WIDTH=1,C_PROBE774_WIDTH=1,C_PROBE773_WIDTH=1,C_PROBE772_WIDTH=1,C_PROBE771_WIDTH=1,C_PROBE770_WIDTH=1,C_PROBE769_WIDTH=1,C_PROBE768_WIDTH=1,C_PROBE767_WIDTH=1,C_PROBE766_" &
|
||||
"WIDTH=1,C_PROBE765_WIDTH=1,C_PROBE764_WIDTH=1,C_PROBE763_WIDTH=1,C_PROBE762_WIDTH=1,C_PROBE761_WIDTH=1,C_PROBE760_WIDTH=1,C_PROBE759_WIDTH=1,C_PROBE758_WIDTH=1,C_PROBE757_WIDTH=1,C_PROBE756_WIDTH=1,C_PROBE755_WIDTH=1,C_PROBE754_WIDTH=1,C_PROBE753_WIDTH=1,C_PROBE752_WIDTH=1,C_PROBE751_WIDTH=1,C_PROBE750_WIDTH=1,C_PROBE749_WIDTH=1,C_PROBE748_WIDTH=1,C_PROBE747_WIDTH=1,C_PROBE746_WIDTH=1,C_PROBE745_WIDTH=1,C_PROBE744_WIDTH=1,C_PROBE743_WIDTH=1,C_PROBE742_WIDTH=1,C_PROBE741_WIDTH=1,C_PROBE740_WIDTH=" &
|
||||
"1,C_PROBE739_WIDTH=1,C_PROBE738_WIDTH=1,C_PROBE737_WIDTH=1,C_PROBE736_WIDTH=1,C_PROBE735_WIDTH=1,C_PROBE734_WIDTH=1,C_PROBE733_WIDTH=1,C_PROBE732_WIDTH=1,C_PROBE731_WIDTH=1,C_PROBE730_WIDTH=1,C_PROBE729_WIDTH=1,C_PROBE728_WIDTH=1,C_PROBE727_WIDTH=1,C_PROBE726_WIDTH=1,C_PROBE725_WIDTH=1,C_PROBE724_WIDTH=1,C_PROBE723_WIDTH=1,C_PROBE722_WIDTH=1,C_PROBE721_WIDTH=1,C_PROBE720_WIDTH=1,C_PROBE719_WIDTH=1,C_PROBE718_WIDTH=1,C_PROBE717_WIDTH=1,C_PROBE716_WIDTH=1,C_PROBE715_WIDTH=1,C_PROBE714_WIDTH=1,C_PR" &
|
||||
"OBE713_WIDTH=1,C_PROBE712_WIDTH=1,C_PROBE711_WIDTH=1,C_PROBE710_WIDTH=1,C_PROBE709_WIDTH=1,C_PROBE708_WIDTH=1,C_PROBE707_WIDTH=1,C_PROBE706_WIDTH=1,C_PROBE705_WIDTH=1,C_PROBE704_WIDTH=1,C_PROBE703_WIDTH=1,C_PROBE702_WIDTH=1,C_PROBE701_WIDTH=1,C_PROBE700_WIDTH=1,C_PROBE699_WIDTH=1,C_PROBE698_WIDTH=1,C_PROBE697_WIDTH=1,C_PROBE696_WIDTH=1,C_PROBE695_WIDTH=1,C_PROBE694_WIDTH=1,C_PROBE693_WIDTH=1,C_PROBE692_WIDTH=1,C_PROBE691_WIDTH=1,C_PROBE690_WIDTH=1,C_PROBE689_WIDTH=1,C_PROBE688_WIDTH=1,C_PROBE687" &
|
||||
"_WIDTH=1,C_PROBE686_WIDTH=1,C_PROBE685_WIDTH=1,C_PROBE684_WIDTH=1,C_PROBE683_WIDTH=1,C_PROBE682_WIDTH=1,C_PROBE681_WIDTH=1,C_PROBE680_WIDTH=1,C_PROBE679_WIDTH=1,C_PROBE678_WIDTH=1,C_PROBE677_WIDTH=1,C_PROBE676_WIDTH=1,C_PROBE675_WIDTH=1,C_PROBE674_WIDTH=1,C_PROBE673_WIDTH=1,C_PROBE672_WIDTH=1,C_PROBE671_WIDTH=1,C_PROBE670_WIDTH=1,C_PROBE669_WIDTH=1,C_PROBE668_WIDTH=1,C_PROBE667_WIDTH=1,C_PROBE666_WIDTH=1,C_PROBE665_WIDTH=1,C_PROBE664_WIDTH=1,C_PROBE663_WIDTH=1,C_PROBE662_WIDTH=1,C_PROBE661_WIDTH" &
|
||||
"=1,C_PROBE660_WIDTH=1,C_PROBE659_WIDTH=1,C_PROBE658_WIDTH=1,C_PROBE657_WIDTH=1,C_PROBE656_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE654_WIDTH=1,C_PROBE653_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE635_WIDTH=1,C_P" &
|
||||
"ROBE634_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE631_WIDTH=1,C_PROBE630_WIDTH=1,C_PROBE629_WIDTH=1,C_PROBE628_WIDTH=1,C_PROBE627_WIDTH=1,C_PROBE626_WIDTH=1,C_PROBE625_WIDTH=1,C_PROBE624_WIDTH=1,C_PROBE623_WIDTH=1,C_PROBE622_WIDTH=1,C_PROBE621_WIDTH=1,C_PROBE620_WIDTH=1,C_PROBE619_WIDTH=1,C_PROBE618_WIDTH=1,C_PROBE617_WIDTH=1,C_PROBE616_WIDTH=1,C_PROBE615_WIDTH=1,C_PROBE614_WIDTH=1,C_PROBE613_WIDTH=1,C_PROBE612_WIDTH=1,C_PROBE611_WIDTH=1,C_PROBE610_WIDTH=1,C_PROBE609_WIDTH=1,C_PROBE60" &
|
||||
"8_WIDTH=1,C_PROBE607_WIDTH=1,C_PROBE606_WIDTH=1,C_PROBE605_WIDTH=1,C_PROBE604_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE582_WIDT" &
|
||||
"H=1,C_PROBE581_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE556_WIDTH=1,C_" &
|
||||
"PROBE555_WIDTH=1,C_PROBE554_WIDTH=1,C_PROBE553_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE530_WIDTH=1,C_PROBE5" &
|
||||
"29_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE503_WID" &
|
||||
"TH=1,C_PROBE502_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE477_WIDTH=1,C" &
|
||||
"_PROBE476_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE" &
|
||||
"450_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE424_WI" &
|
||||
"DTH=1,C_PROBE423_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE398_WIDTH=1," &
|
||||
"C_PROBE397_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE372_WIDTH=1,C_PROB" &
|
||||
"E371_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE345_W" &
|
||||
"IDTH=1,C_PROBE344_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE319_WIDTH=1" &
|
||||
",C_PROBE318_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE293_WIDTH=1,C_PRO" &
|
||||
"BE292_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE266_" &
|
||||
"WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE240_WIDTH=" &
|
||||
"1,C_PROBE239_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE214_WIDTH=1,C_PR" &
|
||||
"OBE213_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE187" &
|
||||
"_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE161_WIDTH" &
|
||||
"=1,C_PROBE160_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE135_WIDTH=1,C_P" &
|
||||
"ROBE134_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE10" &
|
||||
"8_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE81_WIDT" &
|
||||
"H=1,C_PROBE80_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE52_" &
|
||||
"WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE25_WIDTH=1,C_PROB" &
|
||||
"E24_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE0_WIDTH=1,C_DATA_DEPTH=1024,C_NUM_OF_PROBES=1,C_XLNX_HW_PROBE_INFO=DEFAULT,C" &
|
||||
"omponent_Name=design_1_system_ila_0_0,C_PROBE70_WIDTH=1,C_TRIGOUT_EN=false,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_DDR_CLK_GEN=FALSE,C_EN_DDR_ILA=FALSE,C_ADV_TRIGGER=FALSE,C_PROBE1023_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1008_" &
|
||||
"MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE984_MU_CNT=1,C_P" &
|
||||
"ROBE983_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE959_MU_CNT=1,C_P" &
|
||||
"ROBE958_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE934_MU_CNT=1,C_P" &
|
||||
"ROBE933_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE909_MU_CNT=1,C_P" &
|
||||
"ROBE908_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE884_MU_CNT=1,C_P" &
|
||||
"ROBE883_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE859_MU_CNT=1,C_P" &
|
||||
"ROBE858_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE834_MU_CNT=1,C_P" &
|
||||
"ROBE833_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE809_MU_CNT=1,C_P" &
|
||||
"ROBE808_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE784_MU_CNT=1,C_P" &
|
||||
"ROBE783_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE759_MU_CNT=1,C_P" &
|
||||
"ROBE758_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE734_MU_CNT=1,C_P" &
|
||||
"ROBE733_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE709_MU_CNT=1,C_P" &
|
||||
"ROBE708_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE684_MU_CNT=1,C_P" &
|
||||
"ROBE683_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE659_MU_CNT=1,C_P" &
|
||||
"ROBE658_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE634_MU_CNT=1,C_P" &
|
||||
"ROBE633_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE609_MU_CNT=1,C_P" &
|
||||
"ROBE608_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE584_MU_CNT=1,C_P" &
|
||||
"ROBE583_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE559_MU_CNT=1,C_P" &
|
||||
"ROBE558_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE534_MU_CNT=1,C_P" &
|
||||
"ROBE533_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE509_MU_CNT=1,C_P" &
|
||||
"ROBE508_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE484_MU_CNT=1,C_P" &
|
||||
"ROBE483_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE459_MU_CNT=1,C_P" &
|
||||
"ROBE458_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE434_MU_CNT=1,C_P" &
|
||||
"ROBE433_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE409_MU_CNT=1,C_P" &
|
||||
"ROBE408_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE384_MU_CNT=1,C_P" &
|
||||
"ROBE383_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE359_MU_CNT=1,C_P" &
|
||||
"ROBE358_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE334_MU_CNT=1,C_P" &
|
||||
"ROBE333_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE309_MU_CNT=1,C_P" &
|
||||
"ROBE308_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE284_MU_CNT=1,C_P" &
|
||||
"ROBE283_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE259_MU_CNT=1,C_P" &
|
||||
"ROBE258_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE234_MU_CNT=1,C_P" &
|
||||
"ROBE233_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE209_MU_CNT=1,C_P" &
|
||||
"ROBE208_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE184_MU_CNT=1,C_P" &
|
||||
"ROBE183_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE159_MU_CNT=1,C_P" &
|
||||
"ROBE158_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE134_MU_CNT=1,C_P" &
|
||||
"ROBE133_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE109_MU_CNT=1,C_P" &
|
||||
"ROBE108_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE83_MU_CNT=1," &
|
||||
"C_PROBE82_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROB" &
|
||||
"E56_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE30_MU" &
|
||||
"_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PRO" &
|
||||
"BE3_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE0_MU_CNT=1,C_TRIGIN_EN=false,EN_BRAM_DRC=TRUE,ALL_PROBE_SAME_MU=TRUE,ALL_PROBE_SAME_MU_CNT=1,C_NUM_MONITOR_SLOTS=3,C_SLOT_0_AXI_ARUSER_WIDTH=1,C_SLOT_0_AXI_RUSER_WIDTH=1,C_SLOT_0_AXI_AWUSER_WIDTH=1,C_SLOT_0_AXI_WUSER_WIDTH=1,C_SLOT_0_AXI_BUSER_WIDTH=1,C_SLOT_0_AXI_ID_WIDTH=AUTO,C_SLOT_0_AXI_DATA_WIDTH=AUTO,C_SLOT_0_AXI_ADDR_WIDTH=AUTO,C_SLOT_0_AXI_PROTOCOL=AXI4,C_SLOT_0_AXIS_TDATA_WIDTH=AUTO,C_SLOT_0_AXIS_TID_WIDTH=AUTO,C_SLOT_0_AXIS_TUSER_" &
|
||||
"WIDTH=AUTO,C_SLOT_0_AXIS_TDEST_WIDTH=AUTO,C_SLOT_1_AXI_ARUSER_WIDTH=1,C_SLOT_1_AXI_RUSER_WIDTH=1,C_SLOT_1_AXI_AWUSER_WIDTH=1,C_SLOT_1_AXI_WUSER_WIDTH=1,C_SLOT_1_AXI_BUSER_WIDTH=1,C_SLOT_1_AXI_ID_WIDTH=AUTO,C_SLOT_1_AXI_DATA_WIDTH=AUTO,C_SLOT_1_AXI_ADDR_WIDTH=AUTO,C_SLOT_1_AXI_PROTOCOL=AXI4,C_SLOT_1_AXIS_TDATA_WIDTH=AUTO,C_SLOT_1_AXIS_TID_WIDTH=AUTO,C_SLOT_1_AXIS_TUSER_WIDTH=AUTO,C_SLOT_1_AXIS_TDEST_WIDTH=AUTO,C_SLOT_0_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_1_INTF_TYPE=xilinx.com_int" &
|
||||
"erface_axis_rtl_1.0,C_SLOT_2_INTF_TYPE=xilinx.com_interface_axis_rtl_1.0,C_SLOT_3_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_4_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_5_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_6_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_7_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_8_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_9_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_10_INTF_TYPE=xilinx.com_interface_aximm_rt" &
|
||||
"l_1.0,C_SLOT_11_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_12_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_13_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_14_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_SLOT_15_INTF_TYPE=xilinx.com_interface_aximm_rtl_1.0,C_MON_TYPE=INTERFACE,C_SLOT_2_AXI_ARUSER_WIDTH=1,C_SLOT_2_AXI_RUSER_WIDTH=1,C_SLOT_2_AXI_AWUSER_WIDTH=1,C_SLOT_2_AXI_WUSER_WIDTH=1,C_SLOT_2_AXI_BUSER_WIDTH=1,C_SLOT_2_AXI_ID_WIDTH=AUTO,C_SLOT_2_AXI_DATA_WIDTH=AUTO,C_SLO" &
|
||||
"T_2_AXI_ADDR_WIDTH=AUTO,C_SLOT_2_AXI_PROTOCOL=AXI4,C_SLOT_2_AXIS_TDATA_WIDTH=AUTO,C_SLOT_2_AXIS_TID_WIDTH=AUTO,C_SLOT_2_AXIS_TUSER_WIDTH=AUTO,C_SLOT_2_AXIS_TDEST_WIDTH=AUTO,C_SLOT_3_AXI_ARUSER_WIDTH=1,C_SLOT_3_AXI_RUSER_WIDTH=1,C_SLOT_3_AXI_AWUSER_WIDTH=1,C_SLOT_3_AXI_WUSER_WIDTH=1,C_SLOT_3_AXI_BUSER_WIDTH=1,C_SLOT_3_AXI_ID_WIDTH=AUTO,C_SLOT_3_AXI_DATA_WIDTH=AUTO,C_SLOT_3_AXI_ADDR_WIDTH=AUTO,C_SLOT_3_AXI_PROTOCOL=AXI4,C_SLOT_3_AXIS_TDATA_WIDTH=AUTO,C_SLOT_3_AXIS_TID_WIDTH=AUTO,C_SLOT_3_AXIS_TUSE" &
|
||||
"R_WIDTH=AUTO,C_SLOT_3_AXIS_TDEST_WIDTH=AUTO,C_SLOT_4_AXI_ARUSER_WIDTH=1,C_SLOT_4_AXI_RUSER_WIDTH=1,C_SLOT_4_AXI_AWUSER_WIDTH=1,C_SLOT_4_AXI_WUSER_WIDTH=1,C_SLOT_4_AXI_BUSER_WIDTH=1,C_SLOT_4_AXI_ID_WIDTH=AUTO,C_SLOT_4_AXI_DATA_WIDTH=AUTO,C_SLOT_4_AXI_ADDR_WIDTH=AUTO,C_SLOT_4_AXI_PROTOCOL=AXI4,C_SLOT_4_AXIS_TDATA_WIDTH=AUTO,C_SLOT_4_AXIS_TID_WIDTH=AUTO,C_SLOT_4_AXIS_TUSER_WIDTH=AUTO,C_SLOT_4_AXIS_TDEST_WIDTH=AUTO,C_SLOT_5_AXI_ARUSER_WIDTH=1,C_SLOT_5_AXI_RUSER_WIDTH=1,C_SLOT_5_AXI_AWUSER_WIDTH=1,C_" &
|
||||
"SLOT_5_AXI_WUSER_WIDTH=1,C_SLOT_5_AXI_BUSER_WIDTH=1,C_SLOT_5_AXI_ID_WIDTH=AUTO,C_SLOT_5_AXI_DATA_WIDTH=AUTO,C_SLOT_5_AXI_ADDR_WIDTH=AUTO,C_SLOT_5_AXI_PROTOCOL=AXI4,C_SLOT_5_AXIS_TDATA_WIDTH=AUTO,C_SLOT_5_AXIS_TID_WIDTH=AUTO,C_SLOT_5_AXIS_TUSER_WIDTH=AUTO,C_SLOT_5_AXIS_TDEST_WIDTH=AUTO,C_SLOT_6_AXI_ARUSER_WIDTH=1,C_SLOT_6_AXI_RUSER_WIDTH=1,C_SLOT_6_AXI_AWUSER_WIDTH=1,C_SLOT_6_AXI_WUSER_WIDTH=1,C_SLOT_6_AXI_BUSER_WIDTH=1,C_SLOT_6_AXI_ID_WIDTH=AUTO,C_SLOT_6_AXI_DATA_WIDTH=AUTO,C_SLOT_6_AXI_ADDR_WID" &
|
||||
"TH=AUTO,C_SLOT_6_AXI_PROTOCOL=AXI4,C_SLOT_6_AXIS_TDATA_WIDTH=AUTO,C_SLOT_6_AXIS_TID_WIDTH=AUTO,C_SLOT_6_AXIS_TUSER_WIDTH=AUTO,C_SLOT_6_AXIS_TDEST_WIDTH=AUTO,C_SLOT_7_AXI_ARUSER_WIDTH=1,C_SLOT_7_AXI_RUSER_WIDTH=1,C_SLOT_7_AXI_AWUSER_WIDTH=1,C_SLOT_7_AXI_WUSER_WIDTH=1,C_SLOT_7_AXI_BUSER_WIDTH=1,C_SLOT_7_AXI_ID_WIDTH=AUTO,C_SLOT_7_AXI_DATA_WIDTH=AUTO,C_SLOT_7_AXI_ADDR_WIDTH=AUTO,C_SLOT_7_AXI_PROTOCOL=AXI4,C_SLOT_7_AXIS_TDATA_WIDTH=AUTO,C_SLOT_7_AXIS_TID_WIDTH=AUTO,C_SLOT_7_AXIS_TUSER_WIDTH=AUTO,C_S" &
|
||||
"LOT_7_AXIS_TDEST_WIDTH=AUTO,C_SLOT_8_AXI_ARUSER_WIDTH=1,C_SLOT_8_AXI_RUSER_WIDTH=1,C_SLOT_8_AXI_AWUSER_WIDTH=1,C_SLOT_8_AXI_WUSER_WIDTH=1,C_SLOT_8_AXI_BUSER_WIDTH=1,C_SLOT_8_AXI_ID_WIDTH=AUTO,C_SLOT_8_AXI_DATA_WIDTH=AUTO,C_SLOT_8_AXI_ADDR_WIDTH=AUTO,C_SLOT_8_AXI_PROTOCOL=AXI4,C_SLOT_8_AXIS_TDATA_WIDTH=AUTO,C_SLOT_8_AXIS_TID_WIDTH=AUTO,C_SLOT_8_AXIS_TUSER_WIDTH=AUTO,C_SLOT_8_AXIS_TDEST_WIDTH=AUTO,C_SLOT_9_AXI_ARUSER_WIDTH=1,C_SLOT_9_AXI_RUSER_WIDTH=1,C_SLOT_9_AXI_AWUSER_WIDTH=1,C_SLOT_9_AXI_WUSER" &
|
||||
"_WIDTH=1,C_SLOT_9_AXI_BUSER_WIDTH=1,C_SLOT_9_AXI_ID_WIDTH=AUTO,C_SLOT_9_AXI_DATA_WIDTH=AUTO,C_SLOT_9_AXI_ADDR_WIDTH=AUTO,C_SLOT_9_AXI_PROTOCOL=AXI4,C_SLOT_9_AXIS_TDATA_WIDTH=AUTO,C_SLOT_9_AXIS_TID_WIDTH=AUTO,C_SLOT_9_AXIS_TUSER_WIDTH=AUTO,C_SLOT_9_AXIS_TDEST_WIDTH=AUTO,C_SLOT_10_AXI_ARUSER_WIDTH=1,C_SLOT_10_AXI_RUSER_WIDTH=1,C_SLOT_10_AXI_AWUSER_WIDTH=1,C_SLOT_10_AXI_WUSER_WIDTH=1,C_SLOT_10_AXI_BUSER_WIDTH=1,C_SLOT_10_AXI_ID_WIDTH=AUTO,C_SLOT_10_AXI_DATA_WIDTH=AUTO,C_SLOT_10_AXI_ADDR_WIDTH=AUTO," &
|
||||
"C_SLOT_10_AXI_PROTOCOL=AXI4,C_SLOT_10_AXIS_TDATA_WIDTH=AUTO,C_SLOT_10_AXIS_TID_WIDTH=AUTO,C_SLOT_10_AXIS_TUSER_WIDTH=AUTO,C_SLOT_10_AXIS_TDEST_WIDTH=AUTO,C_SLOT_11_AXI_ARUSER_WIDTH=1,C_SLOT_11_AXI_RUSER_WIDTH=1,C_SLOT_11_AXI_AWUSER_WIDTH=1,C_SLOT_11_AXI_WUSER_WIDTH=1,C_SLOT_11_AXI_BUSER_WIDTH=1,C_SLOT_11_AXI_ID_WIDTH=AUTO,C_SLOT_11_AXI_DATA_WIDTH=AUTO,C_SLOT_11_AXI_ADDR_WIDTH=AUTO,C_SLOT_11_AXI_PROTOCOL=AXI4,C_SLOT_11_AXIS_TDATA_WIDTH=AUTO,C_SLOT_11_AXIS_TID_WIDTH=AUTO,C_SLOT_11_AXIS_TUSER_WIDTH" &
|
||||
"=AUTO,C_SLOT_11_AXIS_TDEST_WIDTH=AUTO,C_SLOT_12_AXI_ARUSER_WIDTH=1,C_SLOT_12_AXI_RUSER_WIDTH=1,C_SLOT_12_AXI_AWUSER_WIDTH=1,C_SLOT_12_AXI_WUSER_WIDTH=1,C_SLOT_12_AXI_BUSER_WIDTH=1,C_SLOT_12_AXI_ID_WIDTH=AUTO,C_SLOT_12_AXI_DATA_WIDTH=AUTO,C_SLOT_12_AXI_ADDR_WIDTH=AUTO,C_SLOT_12_AXI_PROTOCOL=AXI4,C_SLOT_12_AXIS_TDATA_WIDTH=AUTO,C_SLOT_12_AXIS_TID_WIDTH=AUTO,C_SLOT_12_AXIS_TUSER_WIDTH=AUTO,C_SLOT_12_AXIS_TDEST_WIDTH=AUTO,C_SLOT_13_AXI_ARUSER_WIDTH=1,C_SLOT_13_AXI_RUSER_WIDTH=1,C_SLOT_13_AXI_AWUSER_" &
|
||||
"WIDTH=1,C_SLOT_13_AXI_WUSER_WIDTH=1,C_SLOT_13_AXI_BUSER_WIDTH=1,C_SLOT_13_AXI_ID_WIDTH=AUTO,C_SLOT_13_AXI_DATA_WIDTH=AUTO,C_SLOT_13_AXI_ADDR_WIDTH=AUTO,C_SLOT_13_AXI_PROTOCOL=AXI4,C_SLOT_13_AXIS_TDATA_WIDTH=AUTO,C_SLOT_13_AXIS_TID_WIDTH=AUTO,C_SLOT_13_AXIS_TUSER_WIDTH=AUTO,C_SLOT_13_AXIS_TDEST_WIDTH=AUTO,C_SLOT_14_AXI_ARUSER_WIDTH=1,C_SLOT_14_AXI_RUSER_WIDTH=1,C_SLOT_14_AXI_AWUSER_WIDTH=1,C_SLOT_14_AXI_WUSER_WIDTH=1,C_SLOT_14_AXI_BUSER_WIDTH=1,C_SLOT_14_AXI_ID_WIDTH=AUTO,C_SLOT_14_AXI_DATA_WIDTH" &
|
||||
"=AUTO,C_SLOT_14_AXI_ADDR_WIDTH=AUTO,C_SLOT_14_AXI_PROTOCOL=AXI4,C_SLOT_14_AXIS_TDATA_WIDTH=AUTO,C_SLOT_14_AXIS_TID_WIDTH=AUTO,C_SLOT_14_AXIS_TUSER_WIDTH=AUTO,C_SLOT_14_AXIS_TDEST_WIDTH=AUTO,C_SLOT_15_AXI_ARUSER_WIDTH=1,C_SLOT_15_AXI_RUSER_WIDTH=1,C_SLOT_15_AXI_AWUSER_WIDTH=1,C_SLOT_15_AXI_WUSER_WIDTH=1,C_SLOT_15_AXI_BUSER_WIDTH=1,C_SLOT_15_AXI_ID_WIDTH=AUTO,C_SLOT_15_AXI_DATA_WIDTH=AUTO,C_SLOT_15_AXI_ADDR_WIDTH=AUTO,C_SLOT_15_AXI_PROTOCOL=AXI4,C_SLOT_15_AXIS_TDATA_WIDTH=AUTO,C_SLOT_15_AXIS_TID_W" &
|
||||
"IDTH=AUTO,C_SLOT_15_AXIS_TUSER_WIDTH=AUTO,C_SLOT_15_AXIS_TDEST_WIDTH=AUTO,C_PROBE_WIDTH_PROPAGATION=AUTO}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_0_AXI_awaddr: SIGNAL IS "XIL_INTERFACENAME SLOT_0_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, R" &
|
||||
"USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_0_AXI_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 SLOT_0_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_1_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_1_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_1_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF SLOT_2_AXIS_tdata: SIGNAL IS "XIL_INTERFACENAME SLOT_2_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF SLOT_2_AXIS_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 SLOT_2_AXIS TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME CLK.clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_f60c_clk, ASSOCIATED_BUSIF SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS, ASSOCIATED_RESET resetn, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME RST.resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.resetn RST";
|
||||
BEGIN
|
||||
U0 : bd_f60c
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
SLOT_0_AXI_awaddr => SLOT_0_AXI_awaddr,
|
||||
SLOT_0_AXI_awprot => SLOT_0_AXI_awprot,
|
||||
SLOT_0_AXI_awvalid => SLOT_0_AXI_awvalid,
|
||||
SLOT_0_AXI_awready => SLOT_0_AXI_awready,
|
||||
SLOT_0_AXI_wdata => SLOT_0_AXI_wdata,
|
||||
SLOT_0_AXI_wstrb => SLOT_0_AXI_wstrb,
|
||||
SLOT_0_AXI_wvalid => SLOT_0_AXI_wvalid,
|
||||
SLOT_0_AXI_wready => SLOT_0_AXI_wready,
|
||||
SLOT_0_AXI_bresp => SLOT_0_AXI_bresp,
|
||||
SLOT_0_AXI_bvalid => SLOT_0_AXI_bvalid,
|
||||
SLOT_0_AXI_bready => SLOT_0_AXI_bready,
|
||||
SLOT_0_AXI_araddr => SLOT_0_AXI_araddr,
|
||||
SLOT_0_AXI_arprot => SLOT_0_AXI_arprot,
|
||||
SLOT_0_AXI_arvalid => SLOT_0_AXI_arvalid,
|
||||
SLOT_0_AXI_arready => SLOT_0_AXI_arready,
|
||||
SLOT_0_AXI_rdata => SLOT_0_AXI_rdata,
|
||||
SLOT_0_AXI_rresp => SLOT_0_AXI_rresp,
|
||||
SLOT_0_AXI_rvalid => SLOT_0_AXI_rvalid,
|
||||
SLOT_0_AXI_rready => SLOT_0_AXI_rready,
|
||||
SLOT_1_AXIS_tdata => SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast => SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tvalid => SLOT_1_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tready => SLOT_1_AXIS_tready,
|
||||
SLOT_2_AXIS_tdata => SLOT_2_AXIS_tdata,
|
||||
SLOT_2_AXIS_tlast => SLOT_2_AXIS_tlast,
|
||||
SLOT_2_AXIS_tvalid => SLOT_2_AXIS_tvalid,
|
||||
SLOT_2_AXIS_tready => SLOT_2_AXIS_tready,
|
||||
resetn => resetn
|
||||
);
|
||||
END design_1_system_ila_0_0_arch;
|
||||
+1
@@ -0,0 +1 @@
|
||||
create_clock -period 8.00 [get_ports clk ];
|
||||
+159
-2
@@ -503,7 +503,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:22 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -511,6 +511,54 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>zybo_audio</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3091947b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:24:54 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3091947b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3091947b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
@@ -523,7 +571,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 00:10:22 UTC 2024</spirit:value>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -531,6 +579,26 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>design_1_zybo_audio_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Sun Nov 10 16:21:50 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:3091947b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
@@ -540,6 +608,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -552,6 +621,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -578,6 +648,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -590,6 +661,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -602,6 +674,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -618,6 +691,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -630,6 +704,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -642,6 +717,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -654,6 +730,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -666,6 +743,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -678,6 +756,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -690,6 +769,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -702,6 +782,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -714,6 +795,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -726,6 +808,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -738,6 +821,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -750,6 +834,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -765,6 +850,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -780,6 +866,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -792,6 +879,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -807,6 +895,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
@@ -876,6 +965,66 @@
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>constrs_1/new/zybo_audio.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/6d0b/sources_1/new/i2c_transmitter.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/6d0b/sources_1/new/i2s_transceiver.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/6d0b/sources_1/new/zybo_audio_i2c_rom.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/6d0b/sources_1/new/zybo_audio.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_zybo_audio_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_zybo_audio_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_zybo_audio_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_zybo_audio_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>design_1_zybo_audio_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -884,6 +1033,14 @@
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/design_1_zybo_audio_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>zybo_audio</spirit:description>
|
||||
<spirit:parameters>
|
||||
|
||||
+3859
File diff suppressed because it is too large
Load Diff
+4864
File diff suppressed because it is too large
Load Diff
+43
@@ -0,0 +1,43 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Sun Nov 10 17:24:54 2024
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.v
|
||||
// Design : design_1_zybo_audio_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "zybo_audio,Vivado 2023.1" *)
|
||||
module design_1_zybo_audio_0_0(clk, axis_pb_data, axis_pb_valid,
|
||||
axis_pb_ready, axis_rec_data, axis_rec_valid, axis_rec_ready, mute, mclk, bclk, pb_dat, pb_lrc,
|
||||
rec_dat, rec_lrc, scl_i, scl_o, scl_t, sda_i, sda_o, sda_t)
|
||||
/* synthesis syn_black_box black_box_pad_pin="axis_pb_data[31:0],axis_pb_valid,axis_pb_ready,axis_rec_data[31:0],axis_rec_valid,axis_rec_ready,mute,mclk,bclk,pb_dat,pb_lrc,rec_dat,rec_lrc,scl_i,scl_o,scl_t,sda_i,sda_o,sda_t" */
|
||||
/* synthesis syn_force_seq_prim="clk" */;
|
||||
input clk /* synthesis syn_isclock = 1 */;
|
||||
input [31:0]axis_pb_data;
|
||||
input axis_pb_valid;
|
||||
output axis_pb_ready;
|
||||
output [31:0]axis_rec_data;
|
||||
output axis_rec_valid;
|
||||
input axis_rec_ready;
|
||||
output mute;
|
||||
output mclk;
|
||||
output bclk;
|
||||
output pb_dat;
|
||||
output pb_lrc;
|
||||
input rec_dat;
|
||||
output rec_lrc;
|
||||
input scl_i;
|
||||
output scl_o;
|
||||
output scl_t;
|
||||
input sda_i;
|
||||
output sda_o;
|
||||
output sda_t;
|
||||
endmodule
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
-- Date : Sun Nov 10 17:24:54 2024
|
||||
-- Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- c:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0_stub.vhdl
|
||||
-- Design : design_1_zybo_audio_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z020clg400-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity design_1_zybo_audio_0_0 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
axis_pb_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_pb_valid : in STD_LOGIC;
|
||||
axis_pb_ready : out STD_LOGIC;
|
||||
axis_rec_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axis_rec_valid : out STD_LOGIC;
|
||||
axis_rec_ready : in STD_LOGIC;
|
||||
mute : out STD_LOGIC;
|
||||
mclk : out STD_LOGIC;
|
||||
bclk : out STD_LOGIC;
|
||||
pb_dat : out STD_LOGIC;
|
||||
pb_lrc : out STD_LOGIC;
|
||||
rec_dat : in STD_LOGIC;
|
||||
rec_lrc : out STD_LOGIC;
|
||||
scl_i : in STD_LOGIC;
|
||||
scl_o : out STD_LOGIC;
|
||||
scl_t : out STD_LOGIC;
|
||||
sda_i : in STD_LOGIC;
|
||||
sda_o : out STD_LOGIC;
|
||||
sda_t : out STD_LOGIC
|
||||
);
|
||||
|
||||
end design_1_zybo_audio_0_0;
|
||||
|
||||
architecture stub of design_1_zybo_audio_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,axis_pb_data[31:0],axis_pb_valid,axis_pb_ready,axis_rec_data[31:0],axis_rec_valid,axis_rec_ready,mute,mclk,bclk,pb_dat,pb_lrc,rec_dat,rec_lrc,scl_i,scl_o,scl_t,sda_i,sda_o,sda_t";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "zybo_audio,Vivado 2023.1";
|
||||
begin
|
||||
end;
|
||||
+174
@@ -0,0 +1,174 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:user:zybo_audio:1.0
|
||||
-- IP Revision: 22
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY design_1_zybo_audio_0_0 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END design_1_zybo_audio_0_0;
|
||||
|
||||
ARCHITECTURE design_1_zybo_audio_0_0_arch OF design_1_zybo_audio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT zybo_audio IS
|
||||
GENERIC (
|
||||
MIC_IN : INTEGER;
|
||||
I2C_CLKDIV : INTEGER;
|
||||
I2S_CLKDIV : INTEGER;
|
||||
HAS_RESET_PIN : BOOLEAN;
|
||||
SRR_70 : STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
resetn : IN STD_LOGIC;
|
||||
axis_pb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_pb_valid : IN STD_LOGIC;
|
||||
axis_pb_ready : OUT STD_LOGIC;
|
||||
axis_rec_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
axis_rec_valid : OUT STD_LOGIC;
|
||||
axis_rec_ready : IN STD_LOGIC;
|
||||
mute : OUT STD_LOGIC;
|
||||
mclk : OUT STD_LOGIC;
|
||||
bclk : OUT STD_LOGIC;
|
||||
pb_dat : OUT STD_LOGIC;
|
||||
pb_lrc : OUT STD_LOGIC;
|
||||
rec_dat : IN STD_LOGIC;
|
||||
rec_lrc : OUT STD_LOGIC;
|
||||
scl_i : IN STD_LOGIC;
|
||||
scl_o : OUT STD_LOGIC;
|
||||
scl_t : OUT STD_LOGIC;
|
||||
sda_i : IN STD_LOGIC;
|
||||
sda_o : OUT STD_LOGIC;
|
||||
sda_t : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT zybo_audio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "zybo_audio,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_zybo_audio_0_0_arch : ARCHITECTURE IS "design_1_zybo_audio_0_0,zybo_audio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "design_1_zybo_audio_0_0,zybo_audio,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zybo_audio,x_ipVersion=1.0,x_ipCoreRevision=22,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,MIC_IN=0,I2C_CLKDIV=9999,I2S_CLKDIV=4,HAS_RESET_PIN=false,SRR_70=00000000}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF design_1_zybo_audio_0_0_arch: ARCHITECTURE IS "package_project";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_pb_data: SIGNAL IS "XIL_INTERFACENAME axis_pb, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_pb_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_pb TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF axis_rec_data: SIGNAL IS "XIL_INTERFACENAME axis_rec, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_data: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_ready: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF axis_rec_valid: SIGNAL IS "xilinx.com:interface:axis:1.0 axis_rec TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF axis_rec:axis_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
BEGIN
|
||||
U0 : zybo_audio
|
||||
GENERIC MAP (
|
||||
MIC_IN => 0,
|
||||
I2C_CLKDIV => 9999,
|
||||
I2S_CLKDIV => 4,
|
||||
HAS_RESET_PIN => false,
|
||||
SRR_70 => B"00000000"
|
||||
)
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
resetn => '1',
|
||||
axis_pb_data => axis_pb_data,
|
||||
axis_pb_valid => axis_pb_valid,
|
||||
axis_pb_ready => axis_pb_ready,
|
||||
axis_rec_data => axis_rec_data,
|
||||
axis_rec_valid => axis_rec_valid,
|
||||
axis_rec_ready => axis_rec_ready,
|
||||
mute => mute,
|
||||
mclk => mclk,
|
||||
bclk => bclk,
|
||||
pb_dat => pb_dat,
|
||||
pb_lrc => pb_lrc,
|
||||
rec_dat => rec_dat,
|
||||
rec_lrc => rec_lrc,
|
||||
scl_i => scl_i,
|
||||
scl_o => scl_o,
|
||||
scl_t => scl_t,
|
||||
sda_i => sda_i,
|
||||
sda_o => sda_o,
|
||||
sda_t => sda_t
|
||||
);
|
||||
END design_1_zybo_audio_0_0_arch;
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define GC_XSDB_MSI_SL_SEL_WIDTH 8 /* Slave Select Width */
|
||||
`define GC_XSDB_MSI_ADDR_WIDTH 17 /* Address Width */
|
||||
`define GC_XSDB_MSI_BRST_WD_LEN_WIDTH 17
|
||||
`define GC_XSDB_MSI_DATA_WIDTH 16 /* Data Width */
|
||||
`define GC_XSDB_MSI_BRST_CNT_WIDTH 16 /* Burst Count Width */
|
||||
`define GC_XSDB_S_IPORT_WIDTH 37 /* Slave Port input interface width */
|
||||
|
||||
`define GC_XSDB_S_OPORT_WIDTH 17 /* Slave Port output interface width */
|
||||
|
||||
`define GC_XSDB_S_ADDR_WIDTH `GC_XSDB_MSI_ADDR_WIDTH /* Slave Addr width */
|
||||
`define GC_XSDB_S_DATA_WIDTH `GC_XSDB_MSI_DATA_WIDTH /* Slave Data width */
|
||||
|
||||
`define GC_IPORT_RST_IDX 0
|
||||
`define GC_IPORT_DCLK_IDX 1
|
||||
`define GC_IPORT_DEN_IDX 2
|
||||
`define GC_IPORT_DWE_IDX 3
|
||||
`define GC_IPORT_DADDR_IDX 4
|
||||
`define GC_IPORT_DI_IDX `GC_IPORT_DADDR_IDX+`GC_XSDB_S_ADDR_WIDTH
|
||||
`define GC_OPORT_RDY_IDX 0
|
||||
`define GC_OPORT_DO_IDX 1
|
||||
|
||||
`define GC_ICN_CTL_WIDTH 36
|
||||
`define GC_ICN_CMD4_WIDTH 3 + `GC_XSDB_MSI_SL_SEL_WIDTH+ `GC_XSDB_MSI_BRST_WD_LEN_WIDTH
|
||||
`define GC_ICN_CMD5_WIDTH 1 + `GC_XSDB_MSI_ADDR_WIDTH
|
||||
`define GC_ICN_CMD6_WIDTH `GC_XSDB_MSI_DATA_WIDTH
|
||||
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX6 "virtex6"
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
+552
@@ -0,0 +1,552 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
IYB6YMUpLRG67Sjv6mvLa0lJDa9M83l3pszRl7mNKDbm3JQq1xub6O3MDaxf4WUUoRlbj6UmK+ls
|
||||
5TT1rZBI42slY2M8d8G/12u9ZwNU0B9Ysw0A9f7H2/gZw+bCFVT2XOufXRtM8469/cgTzPdX6455
|
||||
eehGCOlFNzztUpCCBuo=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
a/7EQ8W4oMyysM5YxqT496V07EUaiHtsiTeMr+xwggjSXDgZBxdH9zS0ZwSbWGNiHwg8nXSCMzIT
|
||||
bUcHpdhYenBbvS6lFHc+OYja/GxpeotPfuhlGtbxN3fXZjw43NjXQI/ojWzEeo5ATyxr94HJ8sHD
|
||||
JA1CsMdglOQT6QZiD9TVY3RkvJVUxzXGEK/4umSz/Fc5dPh6gxxp7cVofeuJ+snpie5VVQQJoj4j
|
||||
tjyBNmGrIhr0Y0IV+3TgWooJ+r24u/VBLLE6lnzKxh0zYnJ5zUjs4eHuQTqInalvOAdYvbUSVqio
|
||||
Lzp5Bj6tb7kmD+A/qe86yLb4GbJzLTehOjcfdg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
Bm8/8qhHbJitBA3cG0BWpho8+cHGNcXoWDJOit3rZ1HeeUrKdPeoNkL9hkzhf9ZUHxLpbdTUCjkz
|
||||
uhVRU8UTRMdIPDzL/7HSIQXCDLdOz1nxeYLnDxwllTKxlZ4aRFdGbB0RXQ/iZNRQW2EmaDTFRcRV
|
||||
v0IjKU+PjNN3ZYIXCkA=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
bOGsLKO2Wjd3RNfQsUHtM5NcPLVbC6ZCRWCjSRRmyvuNhRjavSsIHbXkxLZHDjZnlnBuHdEZ8oea
|
||||
UHHfvapGkuZI0S7deY4irowm1O51aMUIiyYUNQJCaEgTDbqwyEsnkylKzYrQzRU/JO8aErpyMDc+
|
||||
dxDZeGYfZaF3iUzWGpDyEDaQh7d/AMIR890b/cRJ0JPD6S/d68REfiAIau8ZUsXiSCgHP9ot5Why
|
||||
yUKZOeml+FbZ2/zqywrRRADVaEpoSqu6cZux0zJFUOfKwG3rO6e2WYwBKucJSM1O+MXqHqUBqEfl
|
||||
IHl8aYzdxpc89jXiMIYfoqN06f8LwbIAKe3Z+w==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
xyJ+44oGcnu3f/PRr5Q/pt05L20B492JqgiTtcs5oGrsK7nBtr3Jek5JEMvW6gatRMUMnyBEipiF
|
||||
gspt+3c11bhyA0kxxX/8oyNTxGgVhXNyL8HzbkDekMgwRooksQIxmtBQVoCBuyCmgnBOavlrGQRt
|
||||
FtwkHEj4CcUeXXGnFtAt+WOYFScFD17WfS2yPJ5BpD82DvvacbCh7Hbm8sieB2ImG0NiCZXJ2sTF
|
||||
lxRVW8XI4p2q8xA0iSwcF5ZUDD8UmYwHHwFaz9VOXtg3i/iphI/xnKYZ2IQeHkkRf3JRQEAhLQCN
|
||||
mywjCvcVbMSrJkkJ6lHrazZzzBU8tJ9SXhvc1A==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
DKpQGvLhbUl8BJ/8XLn/tPRtGzCl6Z5B9dlBIZ3hIdMpvX5L6qTHJiPL+EPJzvKR3hwn+y3Kf0/e
|
||||
56tD0N9yqf/8HSBzUPN1Wx83eiE7+pWNxuGq7e15dNN7e3+AcR7gjUu0hLG5jSqOt75iiFr0vqqy
|
||||
UPb39HUFrCDaIRNh0fCFdGbydh7zEuizbnn7GRErU0r//wJ+WqhZsjKAuSH/9rkJXt5VJzrFRh2H
|
||||
2zZzduUfRWhphNTH09M8QAQ5RSWmlr7t9fXON4HIIaNpt14zvilBmCZgEfyV1N7+Mbi8zISGSVwM
|
||||
r20FpLJcMjFy8H4kZ7SMF51dIlCCySUMitZhBw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ahGj9cu5vw+TGhDRETTpUmguNUrGkzj4c4HpfbBQWexaOi1CnxDewq4mIuyo2pPRt9bsxMyxinAi
|
||||
yqfZSys3iKpMLTF2rLlaJR5DR+s7MHg3TXo6DwE4YOUz2kUn+kcmB5Oipr2uxn5fY/2OTA6236rk
|
||||
kg96Xfcnb3hsRdNnyl3s8r1r/GO6lcYCfWw2HtuVB73JqZOdMK5WQnRs2nCzyarDak52q8w92CuR
|
||||
jtBAO6iM8C8YYYtdY3bZrNoY2ErKwC2x21gWULEUfsaHyjjhoA1gN+VnA1jThgYsbf0kWw13Grhs
|
||||
2COb8mAkB/0fC26SxfxSy30x8trX0jLDnfntAQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
pM202SIs14RGJlgktq4skB0l7ESlGSPOj1+hAC77mcDHHrczLsAhEpxsiJCrX4tT1I8gJAEoUAhT
|
||||
2AzFczZHKP8ix8wKM9R2i6LZSGPqwG9iMYU/dt/a2tE9vfVY+OxeI0NfGXBvslCOEUGuPq0cQ0cw
|
||||
fSFkfZVVzwr6bhw/htrvJgxFLZKoinkKaocnUwx9C7QHy8rnQ4M8wUbcwoxHDObwJaC6LyVWMmZu
|
||||
kMgZFSpo6p7KOE051S7v8SN2jC64Qu804IoG5zXsnLp60dS4+1fgc7fwF+IiN4mOjBz208J/gcB6
|
||||
0Zjf5PrRbObEBaQt8a9CnelDkWVdP3uTr1rSFz+syFbYPJ/3XU2G/yLmk16QYP9kCQo9CAcIjwxh
|
||||
g41o91RxGZj8PwCpcnZrAoW7se6+/H5h2JrNvoOz8Yr09ZkOhWM0r75h8Rx3OyutUqeqr3BQ1b9B
|
||||
lvB/+l6p6intfTshH8BsTtE0j292jiNGV5cvexC4cczkPuzrIeMxa/xJ
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
eSvh9J2q6NyrGpZqUatGKIA8QDMInI2iwKgziwfCT+i9aojxHhLpFdTm0zLW6vVDbs/IusTTBrYn
|
||||
NVfkcSUH5/jvLRUwLbq9vzH+BhvxZBvdurXPgSJdE/TAka47qAK1KWzgbQ6eoz88SN7MyuoSGGc2
|
||||
6gS0Ba5hhKYx1b8sr66Gjx3DlfaRtcEogEfV8f3DF6j6eL2oGyE6eN3jJQqh8Pb+VBypaE4ia9pR
|
||||
761fYKzcrhd3nvqYI+jRFosC0ZHv3akRZ/GMMOUX9fnkYWn3o4X9t46tehxqU8PXPrS3v/ZJ5wrY
|
||||
YQ/jig9XDE4QndCSZD1niwWxZJrJd1mXs1KKGg==
|
||||
|
||||
`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ff7t8AbFHBpUzmzv37xcV3BaELGXwW2FFoCl9wmbcAMmSLJEeoiYqjiI3XDM4XpMM3cFNM8gQmKz
|
||||
BgEuusWTof+slNUrSsJ5oD354i7b4BucHhOJi1f+LOwqns8ZlfE/Rrpmykq3ApSBIOhbi9mNKfnK
|
||||
0MBBVAY6hK/VLC5VYOy/Nhmbs3uqrr3hY4m+IK3Chy3QTHRdwhQwtRH2hUniNN2nHd1JIS4VwB8x
|
||||
uPCb97uEaIy8cz6h1SApBmWrY9IZKiXvZnBlqAzoVGxsqGB41TtpIISbliL2hGXUFSu0bz8RHT2F
|
||||
fkM9u94uhLFDP/QYjq/SfpByClx8fogg7ejfDA==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
oBc5fYhhP4GDV60D8m6mIIi+6Xspsu6fa6mpRPbQL3lyyZOIW7aY9ehXKE4SewCv0/fpmHMByAsF
|
||||
aFhoGiVGdHT2TtQShdlc5CHrugjHogcTwVhX0awKmb62UeeyTfMrM2krGBcv+KTY+E9Yt4zJZAVM
|
||||
Sf+2Tmup8qb8oKz98yBNuBAlfxqK/VJZfPBeAYq5W5l7vgUBXOhnsiIKqnEuaPcfRrrjrrsrueT9
|
||||
RmvfXIlDjIIC1Vo8LUH+sn4SFtvEa6+9wj+hYFhalOtpexbpZgcDdBcHxxVsqh4fdv9fY6R1msRB
|
||||
ZZFKiIK50d7XvGw4Rs5DAg9ESYyF7BOlcRBOsg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25472)
|
||||
`pragma protect data_block
|
||||
/9vfmgSxR/Rz5jH6WG+Vbr4TobbsOI1owrDDlkeEUmRviechxnb4JeBm0rumqx23QCmYo6p2Q00o
|
||||
BMwgC4UHixTsIVC3K7DTr0QzFajBYbdnkynjCejGnjlIjxdxz5qf12AePggB4LJXEx0Lv/MKJxp9
|
||||
OiAMa6w/YLl34eImd2P3vCX8r2jJnF3nZlOaW53bqZoGq8TzVQyk5lHWgkwIquCYMRUxSmLSrVWD
|
||||
i2/BnIBWZYq2Jo7PGTLaKk9zgjogdKiVWZD48olniusa673x30stQ0i2WLTbpk8wOt1RTSS48DWE
|
||||
cOFtEK7fzyZgIHPXta5+tHQ8HNf6Q6Aydb1F4d8Eidlaetp17hoGLE2Zdli/H8cY4TQmh/pkD13/
|
||||
B8jLAD286BTywt7XCSPGU+GkJH7+zq/qQQuNPKXCFRzahVkJ0vEgZFiCGEE7192SgHZ7hI1eLG+Z
|
||||
vSMhA3qIl8u2dmZoQPqwPsUDSqJU1u9zjHcsoVCj+4jrVqsFZ55jtLH6UIYb/Cq3IIcmS2cO+wvN
|
||||
/MYM02wyZUs3ivY8zw6Y1B4XISjGf5ff3Smo3xLtvu5dnBHnxb2nywTNv4KFzwh0HVB8z/eTLrs1
|
||||
5ACXQdKRPCQefxVeqm1vEigm9zoYQ+3gkByG9RNOdVi7pAOwAtawfcWtvLdinYsKFU9oUoEFF9YZ
|
||||
WEP6gfy4Dd/YNTLVxp7v0721mnHz4gSXuwzPkJ3XAUMCUXMr6PAS3pT3Mdv15Rb/n7fc3PUoodHv
|
||||
/rf2JPX108+tQ14Z6KvF3xxV2W7+T8Qdl0zoGMeBOdhgXcV6DPYK3Gsqi9kolUOu3kWHDh8nci7T
|
||||
0+s30q0sbKeDJVP7x8yaZxIpfVhmak+xMx6A4LOKZSAKYUvnZWN+Au3MIUVU/FP6ZMCy9Gzoxjh3
|
||||
WLFLPqwijIuFmOAxjKa0U8PBKSg2zw8OI4lbAZdVHizkBDHxnb6Y0B+AzWVyBXJUxc0dvWsw4wPc
|
||||
SPEKU/Ms9fJZof3cvJhpYjSnvuDEVT6iqpXm35Pbum1vTzYJk7eRcuAEnuyBcDTYTZ0zh6a/8MzZ
|
||||
cZpleg1Q5M5lyogqAr16SYDpY4B44PxPRvm29ZzlNe/+IuwrCFJt2JVBrfFlZMSlINQT6nlUf0v7
|
||||
YIhFGdSJ1jPt8Th3dj2vfU1BjIzYLz/MtJj2qNqugc4LD72XOIOe/SNUvfVot0iSwwTpD2+pNJA4
|
||||
KA//lDut57qj6Qp9SByw0uzK1L2y33M3w80LdtZZ1KQBQO/rqNeMroByOl75RTxMoHWANj20XDVY
|
||||
ySu3h5pLjn9yoEAOH8jt25g2bP7PuOMmPD0c0sJfHasGOoCeB61S0CwXD4QuHdL5UZo8XV2F2qas
|
||||
qkxAHTv7xl8nkt2ZVvu4Cs1s6n20dYjeA3bJj335j2tDVWaWLiz4fpLSis0ll6Wo36OxgAMkkJsi
|
||||
55jdkfStdz0uyauSYjWsTMOcY96fOu2x21ODosU5R11/3ufFGdh3UBivBnvcYDyA1ZTtspcRo/G/
|
||||
XSvy7ymlpCMVAVk0fBjIoIU6G63yq5rQu7BeiUaO3AojOk28dB5r8ssqaBZW1rtRUXP7CSdLnKxi
|
||||
Zwdkd1z0JS/cYjgCly7diX8FVhqrJDQuxk7QNvS9FOXleGhz1+f03TDtNQssQw8h8l1dABODxxjM
|
||||
w821ixssvKddJvep0fSSrwATJ+sR3JfS24J261LqkxWW2NFTj0E3VdZ/lFDX1t7vm1DCEB9Z6l3Z
|
||||
WoGy86h8p5qJDTC898P70stMbJbutEJ0dixTi4UFLgd/ZwI4ixpfYOxScvzlqv7u/JDSyAwZmU/s
|
||||
2AX55UH5sFkKzCN94FHqiGA3dfbDkULjYEe8XCoLW4f+IbB8XPEJgu2zRxXyyTXDQqwXGj4z7ZJJ
|
||||
itlLST+h1oZTSbj84HcDq9CDGVUN18d3VTI6MGUauS0tulFOirI/cmMm5Nk6j7DNFdQOomvPfMKG
|
||||
a9b0sDf1kT6FzveHYwJZrMAerTfP3HT37k4mkZ2SzsxP2J+CqfabApYFuHlLhBPkxKM/PQ/NW9Hd
|
||||
/JlrMl2tIQI2n3BYIKmjdSvb4DW/gF/6tM8iX6v1xIer3T6ATBJKxx59bSU5RrnnTnGvJ/gtLMJH
|
||||
X8wCB9jm4ss4Pwh7U/VlMIzEHDlM/VxK3kkdJGWqI5JrSy2jvawGTYtFoTaVOhkRcr/VjyG67meY
|
||||
Pg3K1MK84hkugoyPxJjRHQ7eaRwRPRahUqtSkag7Ox+sP+N9DNV+TALDCVCuQPDQXppa1oYSzSDj
|
||||
/0m4eoDT6BeOVS/X70qMbgVjsmaDGwIOHKYE/kbcVuyu4Xx2K7fmnNmQLG9HpfcyrHbnBf34+c/8
|
||||
m5Ae6+kQUlEOpTRNqxYSxxVjF7NzROQj6/FcLsvsE4HQe3+KHju2tvgI8uQ9+7/qZf1nwxBFfheD
|
||||
BtAuJ0R87xHGjcrZMnn3AqR2ZGa4qyuxm4Xpef1I4LyOVFZ5FCj7amjwJhGQDRJDSyCRwWpYGqaK
|
||||
1v6WaOkasx9L9fI7YQMCeZnJKKgW63cda/LHU4QQ4/xYEceKw5EUO6yhAle22avCyfNE/UJ3I9C1
|
||||
yi3ZILaFymOZIPNY7xYHSGoYLlj0f9MO/UuMF2V668rc6Cw5KowtDCvkZIkDfth3nRdl59EnPS3C
|
||||
5Dak+8C6efLlMg58KHI+E9vMaETb1bBmAohKtdviV5glOZURS6REDpWOYMbaPG6cmDGcp6M4tR6j
|
||||
ltG3D/oNX3CGgC3jb07zrW4KperudwEiyslqDRhRkFOZH9SGSzhVl3kRYYhUZ9gpCPGp5J65VYyg
|
||||
moTOqeMnEl3ypsPLnDfrBV1X+5a2oyoL+cnY9daNiWMCTcHL7UvC5vZGUPrmT+CATlaIVR/9B96W
|
||||
RRDWO8KrDgULnBepzGaPvT8D4TZn2B4lFa1ikxt7IOVK5vcosQGJaD98o1QU3/3k+czfDh7zTp7O
|
||||
r/10w2V0gFkMSDhmv+PBfMBPTpeoT11J8AuBFMpGMXkyVlaILF6XuHQBG6TZ41aIKFuofVl8QbWi
|
||||
AI0ILWR2hka/yMuxT6adcNODpDatBBm6vLpungDo6yAIv5ynMozd77ijI0ZaU9rN4J02GIIEOlhB
|
||||
QTSuFeb+4admdrLBKl8q00XDD6JSHPdpU5iz0slxKMDKLWrWqWvJYkXJIq3oVG/zq2h1tHS+suYS
|
||||
f3/mWYOomdjU+AXsG4VUN/Kfe9FRs3nkcwcZxdqn7/iVfppV9CvXKiL6SHuEKmliKf448ofBMVJm
|
||||
geypPXO4XeWp5pMX+yy1PMVcRLTsNbP1QnAIhMjAD70lqLr0DU+E1kkwelqNI4yQEzzfX5fJBzFS
|
||||
hnEfgofzCoVZnWX4Y8i0CSj6Bhz0/+xYfzG/m3ktnjoLH2boDXc6W5FEbcf9exSx7tv1y2244pRG
|
||||
ZoMdioKNkUzCi490LikihaEzHl9yZGlnVIrxie6jaSD2IPcLwZNOQE8fs8d7KLTUx7laVgsvSVmS
|
||||
7/0hoOkQHrbuVISwS44Z04QKuRZCS1cRUBJoCBXIMmbvxvWHDUImbPYFaBt9M7RJxeMzWXXwNacG
|
||||
5CCmpjq1ocKBciQdem/Kh+ZKefJa9wN7XgcGtQlQURTk3UajyTu0Ih+FXkBk+pO7GARRaErkep6C
|
||||
ghxC1ftcXBr/gHFlxlgaYcSZwpjbI2mAoNkhnLiyxiK/fIwWNULAP+HidvCceKgmVbiVw9UzLqlA
|
||||
enbWXSYWNwyK0Ulgo75mfSxcC4PIW0Z8YF+bY1cuRyUJt3JBwWon8gNWg8JpC9NBb8u1d2UxwoYd
|
||||
g8YVI/vct7N5iy7CCldQtUh3XkuJLs1S/UL08Kq8inBLes/7ZAA9+L7yVXNEtLTj2aHeEHtsRy2R
|
||||
NSX8geSmbhRpsz5voKYf1Gse8PsAfXj4pehHVbOd839bO4Li4g4GgG4hozlsPQS+nCFP1zpbspXG
|
||||
QMwSAnpt3AEWk+uokcf0cwgE0vgnpd6LzJNNwz+qXVZmUT/6o+Yb3cymZJuwdlW2iVGMwsaaxekP
|
||||
gJ/uvOhI7joYAY/sdE6lXZhKTR8rN6SwIzln5q6DC2iWIk2qRhlcNRPontFlEztDRQ1hkgDVszyl
|
||||
psJsSsiC626RSiENhEeZweJu6fdsiB9KJuhTjfKcG+0y5shw1Eba7I2oyNFKlyJhNtknKuGnm7iS
|
||||
Jihd+2NSGpgBa5DmLrs2RGzQ61DFJizGuRapUkWEyiHRiybN7JEDNBdO67tJx8AgNKmBc3gDpgmm
|
||||
asINNKRhst+07KFEiBzKx0l0Gsk+D8BZHq5/mLGnHYr3h5ntQBIAfGXFtFmuoqMyMv3fz4KqJQJ5
|
||||
pifEd/zZ691vGAmbd5uVkllTCmK5FlI1QQRaBcjJukdP3jcCX9cUuNr5TR9TG4gh5N3IuVHmrDNR
|
||||
SwcUPCTkm0wz/tTf0kGAIuKUhc1dtn/UiGrsmkBBYPWmpbssZ99UHUpaxTUNR0W2VZ4H/jLbMkPQ
|
||||
8oUgqLbDopQKyYBRyoBRvzxVA2u+djZ54fsQXXVEoflQkf/kWcwV0vzwwPoHNb5NKyd/nnYdSdb/
|
||||
3+YzxJtdlWdNjN5WsWnk2vSwMPYYO0UgyMgBIh8IoLZAcftNfr+cq08pyq3IljiXq+3yEvoVhZF0
|
||||
D2Jag1hmMvSkJVeDPRWB2/Qw6dYsJY9SUkOZW5s0OauPGo3Uw6fr/grcfHWpqH/S6MuAJppl35KN
|
||||
0gzhH+sjJZlyzbK1vPN9PZWN9a03krWoz1cMboFth+zhcIvkWvv9AIxg76pimBHsOXnA8ehv/fph
|
||||
ei/4kDsREuAouVHo/Vfam6nswaJUWUoE1HQz0OPp5F3YkF9l0i/TY5HQRgC1e993D8E0PYx2AZmk
|
||||
o/F+H4ET3dIUKHlbZVmrKfqMuOg7CjW1bMELmFF3M7/K9WV6Spz0dQMLeBWkiQsK1xrMlBeXVnNX
|
||||
2EsZb0usNXk7PBsiDDjNsDGAtLh0MgZE9bSDXmZSu4Tkf7R8yz1124XUkpgcmQMgnNqtIhc3S5Jz
|
||||
G8sC+Wht8bCOHYd/c0J5/S7FQVwydfoKmghRbfpP+5YPnvcrg4NBsSwQpFd/5s31HKSTNDmaVEtg
|
||||
FWsJUbo5NORRKte+4AuLZ3SwjSs74cVy1VEXJkbO9XRPinL2BY5zmDa4DH35B632NEfJvvMpvjfx
|
||||
QpXp2ku83/ztJ8RMdOlPG9/QB+PZsgBIWah88YPZ+uSd9K+NOV0dB1pcrB3qMbL0PEJ2xB1rtglX
|
||||
H5+IzbTdWgLJCHgLE40Yi9UGPGbYY0PDRyOMagAaojUEzDuh8xWXrh61hwuuDyslMwn+hHwVSjpm
|
||||
aFl2mzhodopl/rfNV0lGMQaaeHDa7gImISh+rRCTotJRTe8LOUON3Up5tfslREzPe5c5esk2cq46
|
||||
osYIdTywec7r2ubOjd7Lppn7TL0mFTwnJGDHtlaQOmzjnGYYYLm14V0ze44rs3DVbHRU2Chqc+4Z
|
||||
Y5TS3IiqEvYge/FaINQMdZXu7Ri5giLk3uPXKB6wfa3hKsDkHvWFF1zfAlVYjBV5VCfYmy3Po5Ld
|
||||
naJsdJ0q0XuiSAnO2nrk2nKeUHyZmMkiv9Q/HQE4r6azh1BDUUEyty/CE6JTpQFJJy1pxwO0J0TK
|
||||
BbL57or68AX/kmbnv1uwptQ3RDOdbSGXQposYa68K9MHII8yfCA4nRm1u68DPqVmuW0SnELfks9U
|
||||
xALzrwbBysnNKFGZI/Vzv8fwTbuOdwOo6tJZEXscTXCV/kCtpaNARh94pJvlC7svBr9D0aS/wRja
|
||||
Aznb4BeEEBnNWlgHnskZM1heRvvQes2zTQt4bQ40tj/3ssnFHNNYdrG9utusy2qd6H92rve0UFML
|
||||
8wDlccI00jY5tvdVQyGNt7Un0cnoeIhI+RUZSC8v/QtCWDlJveVWF5naQYMyOwVLPAK2FX16kFC+
|
||||
y153/lSKkG81KuUX5NaonJTb1acO7+97A8KDRgGUQGQnwwQH3/O1bsuUeat5dOv8rwB9eFkIshM2
|
||||
9L88EoQme95l5uidE/YX8rylt5QAvnkplnjldJxaSMGWYDeRWo42LgPZL+NdzcqBV1+w8ZzQxgFl
|
||||
fmhqg6BDA8nehfhbGLQe0VvuR25NhwD+w0qdSL+eazU5VrixFHVTI/78EYGZWea6XH3IIpj79otG
|
||||
3pkkI3bNczsAnMcAnPbeFJYOPfBbg0gJJYgGDkea6zhD4AGLc9hTo2ltNJ3meYVRTyLAR/ZADdmQ
|
||||
h0MG/atBlMkXrL/TcveWmIlKdQR/+qqhLvPEHSiU1CS1p21ELXiCaSwZF/7udhjGqhK33twDFjfP
|
||||
WsOnSaWgudM/nCWvTAjBC/Pa5Dr+O41idUdBEA+mOQ1rbCbbdRHg8JMCJtBaZDbG8KqgHtgGUOuV
|
||||
crjYuvplA9tUG9ZnmeHSuep0OsgG1xVFPkad9P7isy7U1cSZNSDfOCWxsFlazlVuFjxnoE2XXhMr
|
||||
0DdGA86X2Uejs5pyTbWeKc/fHf/Tgar74npUa7CRpQ9dshX+dGHdVKkjPeDi1Oo/x6fpnrvqKtIC
|
||||
iTqP24+EqW+uFmNlll/28E/5rDbNz1tt+wtUEQG3ShM20c+6+4iPOR5bmzx3njJcAhfPaDypJ8O2
|
||||
wiXqfSAJdzO/OTC1HJOLzP07Nc4aQiY1F5coA5lyxhybLoSeuC4Ph7VcTGBFh96uZsisBqMcT0oR
|
||||
TWVefBVV9LjAVgLGEjwDJqGtZTyXe+TKZRczgCKLFt84qWFzO/Wzc6rO6uZyHQKXOMZRTyqBSJw2
|
||||
9tOcNDxZAN2kRPkn+5eIZv/a7+s1S+O0N0t6Gu3DiScfkvhHZnfMePSHHW+Z1NMNdEGJIbjeTS5J
|
||||
D8KakqCs4ui3J/hUpreEGiROr7HLyzr6fmnawneG/JdYgDBWSKBP9Df0PXs9N/ElDWdDPeznXuLQ
|
||||
O7wZRlO6QOsHuVCxygc8UijlxNdQZmvqUYiuTlEhVnJX5u+/umCl0iBn7sF0ihYU9PYX7yePWB97
|
||||
WNBajCaU366RwRDbY8kCCVWV1qNiTnA2WHn/DvEYlUJUQ4QDzvKhQyp25n3DGm9AIKdHArK1KR9h
|
||||
QBRMuLEK3DazpCv451LD5be5epY8NGsO1gt9SuHAFHI7eaRAoX3GTwg/UtNq4bdCJUBCn6EDJ4tP
|
||||
EcEhwTkAo18LchJ7VXe0HUipBN4xgCTHoH3/fVWNXFHn03l9u+sYbbp40vIU4YKgDQoag0b7zHQH
|
||||
SiMxfy3TPipK9/WnoxZ23/nJ9FnWhmIsqytcMQW3aP6m465MfJnMQRlfX4GFOYG/8dtKv8qlyMwB
|
||||
jJgGfYm0qyJPSUoBEloUvbzDj2ALg2sMRqX3wEVuxJrLJ8ZxdzNtgUtOO3T0M1pOPIt+d/uCpQ7a
|
||||
SfDnTSbnoxTCBEucCl01iD8crQZGpk9mhL68tECmRYUti4Np904kOxYYo1HAkpsEqZIzutENLvKL
|
||||
52dfY32dh27NqieDJh/7lovmDa78dt1J0HFlO1HX1DQK+XyQM2jQ5/Qp7AgirbcnPRR/138LEtfP
|
||||
SPYQmGy0JuBlLr2lXlrP0d6c6NgEYzIpM/9TYPgP3u379ab7BwZXIraZ4seQVMW3VGDZXhE40n2D
|
||||
hiTHK6jFAf9vRXX/mZueRyKqYj2AwfvEhtpCrhWzXjqBqxQ9ZiqqRPlspvZnhMJRCUy4ejTnQWkM
|
||||
D7rNeQtDIGmD6L9yRQAAYsUARAYdx/yWzdcUpOmwUUK60Kd7npnsJsewA7zjEmUwWfLpXufLgcpM
|
||||
ZwkQhHhmdaMr9IlihF31LyybNRpulaley3ZsRHVMQ1afdAHoo3Np+Fy+pdAA+pH+IF8hFK5AzcmZ
|
||||
0HqOnyaF21BkQf02bKF2avNGba7eeiQzsTwRUqazPh8GCNAv6D6oRJCgIopSkDDCwFzkF6qS/TWU
|
||||
zNoHM8yw1v5f+PeA1GKriIUBQ6RB9q4MigT2eD//stUsvLQ5/GeVNZuogDEuiaRW6EELuZJBKSz6
|
||||
0OqPcX3X3X5j4W/vfSjPZxUfQKc6yRPnV7rr7QXxHRqoWA2231j4SztCl5odeD6JytpjCFud13A5
|
||||
c/T++hF2gtMCvxkGrVywz/eQy5UzNm5Hq6+UvHMtzazR3c6qYvvEiuADpU8Ivadm+QdOkzUNwjYt
|
||||
58HsdYvx8XRxf8/oQ0cLzIS5MNU/nuqdGg/sjQo5cjEbXwgB7tryGNoXlrCy1TRotiTTU8MfkEI6
|
||||
4pj2c516eELz4KUjFpEu1DapI8oV7MMxXClCUN2v0u+urhALH2bxSTS9noidxABwKzug/56LLT6w
|
||||
UdBJ5fJ4hWLvb6RhSdInxkIg1esSn2vZFyoAEV2EXTAsRucGi/MThpQZdAaDEhRJo31i84aUEX/H
|
||||
/cr2+gNwZPH7LkqdhdTTy7EdrrqjaulBIkSMH6WXCwU/ut7CeH/VXISGub7FsABYC8K8oIfD+Yzt
|
||||
007rKBoCBpIWnZIM7lTN6XvoWsqfncm70h/V9sid0x9bZ6qiD0Dj17GKKyz7nXWfzqFLdhAyxz+M
|
||||
eoT7bFe36+oKu4WQfbNySd4owxwu30ab2uLDO8UYvkjbftjy7x1cUNDJFfge4vQNy5SRql4oWGRB
|
||||
hHdTFk/3mHhKZviOL76shcXzZ1hS43LcPwBfp5XD5YULAklBWNELyq7M4Qrl7h6/0Xs6KhCCK/kJ
|
||||
XPT3sxrjvGbclsTdGvBh6/MylP0lrs3tQ2QkTbG87/+cgQxDLuwQnHLb/Lb0pZXHe7KGe/hTwaFz
|
||||
pYDIctz6+nazztZPYHIPZVxSy09Wml1YykE6CFqjmpk7+hredaV3vQvOYCBv+dQ88iL3ODrPQ92C
|
||||
m5BVza3//bPervksmHwhktd5gB+vHNCUdkm9mF3jWG6lIZO4CCrTg11VUZW+33YxzCDYX4Pb5+q0
|
||||
KTS/fjbxqo0qCpqvvh5PrQJA6epVBeyK3fDy596e5ae+y5BHE5/+ElI7ceSYe0bzGPpFxAB01kwu
|
||||
ICm8A7AOzjunXfe1FqdFQVE8wGmjCO0Yuzq07B4Wues/149PtaNvO6576IQ8AoOZGlRAhWK2jHja
|
||||
rVRQfNBW2flZk2vWCtlfau42tGO3rMbkzrMjgPuQHQAeNRFKNCaIKk6A3/hUFZ5ZAoXGoXn6EL3P
|
||||
oDNDNn8nO219zOxsR2ymYdQtsZfQ/TBjZRf9aEFsZr+qN1PzTT/6j++7Fy4uyaAtzM4IqoICZu9s
|
||||
2iuUyOgSKmeBzQq/IZiFr9I0JoROilK7NEKoLJVE3Y0K3kNTskjqOqwu6ynJzqEdzK75MyMXZyPg
|
||||
rrEV66anmAgwYftruqHWZRFjTTez86pbFsEsi82SgA8CYneHDey1boQSA+iN6rwY2LqRQESmrPb2
|
||||
waLxYSlwKWgH4yYdxwNlB2/56hOMvz1ZcqVnYKbSjxRyZdQjaec08gcVZg1Iwkn0MCxlwlekWM/d
|
||||
wLdM4FI4fy/T5+x9lyfkoK25dPKXXCQvZWAfAbB0pEsk5CLcdPakUlyVTmtt2Tcj6U9e0sBsyios
|
||||
EOqO1N5vSDMgOUkip2LfK8hWHlQRuPt4Mg25cVBKk3Qhz9KICh2PBsBBubS+znAGuNBatg9fcM9N
|
||||
VLWAyYnzJ0msy2AzXonSPxPkn50W4VALj86Oh3cKqGIIhhv4z3dt2/YVmpT+/KTP0nKxLEIruR9V
|
||||
Din4ljqNY3h7LPUuHVkg5S6XL4bn+i0JI3FPsfGePaeaa3y/mES2R4mst123JZMMosnsO91kJXge
|
||||
InfQfClDOF/+Hk+K8WVxNvYjyrzQjJRQM7O0evueJZetmPlab91PgQZrOfhZHxNgfsZj/lSh7Ev5
|
||||
9Pk0BJZZN3MGNzH+N5pjgOWswOC0FAG+e7XWGMhtReflZdwc/1Gn1jv9vKrs1li1ZaZ4fvpCctVF
|
||||
Vt8yd6Dn4vR9o4ezzNPj25RPAwzSbdfzVxbpWbbg67pSbS4DLrQ1omRVgZ61yYUm5tdY8TXcs12e
|
||||
bJ5SEIRgHpQpW7e9kAZ4qJtjrKCbQw+BomKYeDRnQINhfbkdoYzDmH/S6XCQ0Rebo3/qUigrgfMp
|
||||
36mzNMFuDrnKtIYwqn0gJAGX6ynmWqD3U4njQUmUWB/xw/6wAcTJOCeSitilVY9MGneUKKu/eQuw
|
||||
kdYdkmaX9UBJPP5S10PyItPh5X0grxIuHqScdV/Xx+yc24r3+ffrlcy3SB60uzl/1OmbPUoSDFGF
|
||||
8b0dWRsECwOguwGWM8SufyZcajCVuHzUgi0I4fJ77RyEtdPCKW9MD5D6vc+N24DF8pwJb5qU1XUi
|
||||
Afk8bkaozSQCmJMf1J35ZPqrFm17PptUhGi/pBjLcC62OG8zHppLcZPs47BZADoEfW/r9Vt9ApJ8
|
||||
X8VnNV0kbdW7+W4yyEPAfV/PYUdsDnF51FHK3R5Tnz2UHEb40uoGXheVdi8ssSDRSFgip4VTYvCk
|
||||
NTSUjP0zOzuHAvvdvQsL1xjLWknGNKplMhhkJhsNDHKRBusJehzvXUH7l79xXR+uliaEftf+lB74
|
||||
wVSiZvcTSs05axnoT3Nqnrmtipt1JrHWBczPIrvZ0ZQmOsErmrFE7U7LHo039OfM+wzADqOoxt69
|
||||
/kwRDa+B7MBuXE463NJcNTXcD7m5HlTtApa2p51GvU4ihwsSf/11vGwpxTWxtw1rSqQ98EJoczTy
|
||||
kFaBLJpbCqienoYoqxioVIhlAL2QOYgHV7ja3dOQneL+VkPD3xfEdIoeJM3+jS+B0L7XXVwem16j
|
||||
GT+rjfk8YmAoVygEHrCCr2j24lc5L4+PrQQ91djTuytDbQlx1sIwNRhpo1s5rNxIpduCdZyKgA+e
|
||||
E2qvW1RBojbjXkKjm20YvLGtKYkAC6d7Un84UvKKaQoUXqabgB9nUtvsX2CI1LgXerWbJaR6F6wN
|
||||
0nNGaOahBKpwdRuYBnSunK1VGhIMbk+5xo80QfULA7FLqSLR/R5BxjwY4p6thirGJzbILf0SqVKl
|
||||
f8TFkhA0H5f63DloUf+3rvdYFfT9O6+MKTME8xIAllSurZ/KeZuFXCMRiBCDyjuCJ/xhIFKa2poL
|
||||
4cFYK8mE/WMVScnMWuVP69H5r5Tl0WUxCJe08K9QPEjq07KPuDE2cQsB+5L1DS3iAcJ70PD5kmSc
|
||||
r6eTQMn+fL5Wda6Qlm11ym2Ji+NOXXnT5GE5lQdnh29wzf5LE7+2W+gzOSvu2dZdUskz3zgrCOKh
|
||||
Oki7K7QWq5TYe8u/797FiNoYC+GCT6vQP/vu8TP40csnf+YLeeZ6n03l3tqWts5eDEe6H/6uP2oa
|
||||
y46CS99RQpl6ofgy8dyJ339Kdtc4OJBgp6w/wK8RbFGZ93A7x1g/rXgsmEXnbWHArP7DmEHj3lKV
|
||||
crzhDXGe4qCC7yT2ZDBl3tC0O2ftRHrCncNp6rmRvEaj4YVL7+gNx+sWQP7OPMfISxrDqGwjoIC3
|
||||
4gQ0RxIAw6CIVYUiDmCENpEMZe9i4U+i6IqefER38XkIQ7HDF8B37wPrB7WkB8FOZKOZ1u2e2i9y
|
||||
VJQhlOPZla7rOOqGoRHJlCYLfw/s2Q9UMSY50RbgYDh06Y88YDZwC5ja0PGpB2sKkcY1bBxhkPQT
|
||||
1al55HLECEBbL2U203z3poH1o2mtc+gq76bA2kuGXhqn681ILDsWaNqCa8wGTiDMTlQr8oTvKrIn
|
||||
cyRa8WSGZAZDplqbPY7BcT+3QZi1jxtTS82xXcWrG2qJZ4ptHEMMQ3GBKoL9jSOOR9kOipwUCnd3
|
||||
R9Umd9yZ1o0ntpA30EvaQiFl69Lbay/WBRvF23TLjLRA9kXjKGBKv8ZvqffINkLEGUx/Qe21w7s9
|
||||
PvBYGUhJzOOhgh5b84SSzMVmZijq4cvMOkFEitFd8MjqVV8R2bTX97Hn1omHb7j5qQrn8Zn6ZV6X
|
||||
ENbIVzSAkT9CPY/h0rsN8jyefivaHMb7DhXl1ARniYUnUY3EtkGclt30FTomj7GDWbUN8jfcBzMm
|
||||
6zdUzUhYHNsWlrVeKmsZYLtVHHiU15Dm6KwEeqQDB5BQ7UJiMyY89pZu7KJ/p80WN1EFnF0sHDcG
|
||||
flNURi6OgyQliEdLzK3EtAkMY1CNt+NbeQwKF3oxXHY5M5TYcJXXVTCOQjel/kkvtqU5C/K3FRGM
|
||||
XKK0wRV0dmG3rQIzvXfJhbcIQNsRuqwIbMCahzVh5hLCnU7UQGeNbJD3AdZsDSZVbwvpaKz0/SUx
|
||||
bRGrMZpRpTIJZAEVN8eV2Bn4QAAgPR7Qfcn7VlEkfjx+EdszzvxHTEK0QFgzcd9jNDRRRSDD+5rL
|
||||
Ry9mtnMXZvKg5xKTVUTSqdSrhLGfyUuj0ZrZFiiflJz6EucrIrBSuFwJgwpk6WDtMq/42FVveyzw
|
||||
LvoJ5Kp41W+lasEf1YYV1Z18JCNqQ6PO3/07Xd9AVBllgJlh66PUtYRros/h/D0wuQTBt5VQC1vH
|
||||
JmBBxvbFd1jpX1O+Yp8OAEPgCn+7sG5NPzTwc81cO955fwGGAWVASnYZOfMlV8/CA/80YYW1nfJZ
|
||||
jWjlLtaesaqELRt1/L3ffBYuRWupKsE0hbVaxD3Cxlt+xiDI8IXPRijZFUEgrcpM86M9yjrZRK4u
|
||||
dVq7eIeoXR1mMqEhyid8vy8GK1THMe0fwYMI8LXg6zqPxA57CN6r8ieDe3IQlnkt65UWnDiSa0Sf
|
||||
p/9hRwpMI512WMZ5M1+fVz0YlTJ8Cd1Cx8rqD3jVRL6P+UXGoKwyaltuFLZ+HrGKAeyKSNQHDxNi
|
||||
Qs+U5KuUdiYJ4dEjegj6ykLIY194jLgfx1YoH59IlezRFEBn04K6423lNYgnvr0kLq9XkMEywqzj
|
||||
h2JhcjSD5YyLeOXfw4bLvhKuzrWA9ru91Zj36MunxEXsQLf6IHp9r2wwyVozOH0ZTyGGVOWnqXLT
|
||||
hpANzq0vFacpGoDWj2UZqSstiryX3eZUpUCBrwl1RBRs92I7MWIijjG6TFC5MScRbQradLW+w+jl
|
||||
MUg7xwpoJbRfWsBnyvNSAjH4mcelwdBal/cdBbOqzGim5o4mbWZBqeRCKpnWCWrx5Nsgf3bz+2qM
|
||||
yEgBg2hC6olUirlx4TpHfQr1oYpNw20ay6wgifzWLLMrS5GR29GvPp1TwUOwi8Lie8mptnk9mhRb
|
||||
p7pjaJCsgxH/GQGR8yvfcMAoFv/JCRDuN7vupT14an00C43zz/GicVkUQFT/sAya/SVi5VeQDxID
|
||||
yms8D5XhvviCunMYZIw/wA8q1vUuOIif00J3tJbRyhzJqJQHuPEmawKkmLrLLPREWKUrBtVTyKx5
|
||||
DVYdnnxT5++60oxOJjG+cTL35QgNspr0PfCkv2V675HDV9t+bhkA2AxeitytMebVmE3rCU9gKT/D
|
||||
oCGP+yItGnKKagYXymFzmQu9/HB/XkQeH49TQKDgbSw4kCsm31mOsN/6veprQQFqy9tlVApP4icg
|
||||
IQtUF0KEmvT7KfRBgdyBk9bzmM9Z/n80xTofqrfi29ZtFtrOvDnUMQsMlKoBkluqPhaVRsSdO9nG
|
||||
/Bj+o72s9SVIZFqpolUuznHEaQlLjhRw9HS1B8XtHChe4wb6BYVWpqkXkAq2UGclV5fXGLtaC15F
|
||||
hl7LBCnRfuaqNDz1g6pWyu4UKF1tvQF97fvJRf33WayqJq9KRsRWmvrLAdWNcWEfyvpQBEktGEKt
|
||||
S+3BD2X9BaOAXrNcP6516IhH47NhNkMo0XEq/dz0Uz8RsLndDsEEkn6zoej+jQ08CffA9Ol+RrdW
|
||||
bZF/2GRNo37LZIo+uo13zviXZQlQkwd0QG4/GocpYzzsjpWvCvVeIYP97GBWhaahy68PDGGyXgax
|
||||
X8pmbg23AVQLQvszgxioB9SIffbVnmwymXdpJPkoa4BJyVeZOxX6RQDRIP2rcgj/vJ8nOGFJha4C
|
||||
RncUaThshBc9YV/68dhKuVkG65MBaRtA2MupxxYw+IPkP5YNlkm22EPFy9YHuwwPTZseLFwNym3p
|
||||
dBsgH7MyEYRqB/JlGiw55toVSTqVrc504Sg7GLgJ25pwVPVKUM3e6GeZjw5tlD51hSy/hcVe0/W8
|
||||
EToBgOUIBbxX59habmlbHU1FFN0mfNZEqDGpzgjJfUYohajDEk42i+7u6iPU2NVB3l1l6idNd7XO
|
||||
yyoX9IBmJTcbd3ZUQ+sXt19nShdE81jBN3lQdIwFilkR8DSR7RlNL+i2LvBE/yiAkPUvgw97KL5e
|
||||
I6YO6YZMCQtKfeASO4Bc4+kHnWzm4LbS7RMdlsgYaa02doDo9C7DKQ8jO8NmldBSitnQEyFHjKo2
|
||||
s1qSvjbFjx0lhUIlEkfCgztexWAOvSVade9ch3Jq5Ss3CIZ//2tR9z6yDDgdLEO+jOvObriv5iZg
|
||||
vGdzou4QzszGYHYB87R7isyQss3AMTEIgv2pMrX/uiSYwRhYum/lnkZ9otuuG+VhCQsRAKGq4QtY
|
||||
3zZB/gNEdMOpDTgjIA/1g4aFfmR9LXnqJTBkd1B/RNITy0noH6Kt0aepMDs6b5SNxbPxuWpuxh0O
|
||||
pDwgItE9kM8xUdNvWH7SDjBw+Pk/xvKCgWlAQ5bVpZhmbkzKWGaaPursaHE4+I+c/Z6PH0tvq/i7
|
||||
DzJzshRcZfmFxk2e8c88CwBFaIQfY8PesNRT5ME5Y0s2Ok6Pt+nfpSvpm4kXaFre36eiua+sUa6R
|
||||
r+e262BrVV+I1wRjdAKif56NmB2PJOv29O2wEbZ0LAaM50nHOOz/853ysGDyBhwQlTYzs3aFy0Qg
|
||||
5EDl2KN+4E+fh0NL3M5SBVX9u3NWj4jGmD8mydGpBUYu7znp9+AwrYhjpm9TLnT0l+rUVdECfz9b
|
||||
QQoXg3Viq+B2GaBfsBlM2IX+G7JqmLZ7QTI9DKjYVQBXufyN2oom+GlqfZ1K8bcgAKsT0ksXh4/h
|
||||
P37+/s0i1+Ox55gY7aJ4vWHqQlwblRdbL3DY5NgDgJGX6wHb/IvK7KKEbISW2W5Y5cTw+OT7TaNI
|
||||
39gH2kfZ5Ribev5hjJN7t0CW0e8OnYaaSCE5NhRKYjwPgQyppiuZNW5emIJtNul+HDmRivmeFKs9
|
||||
59qn2j0IvgFNv1EsnFPmVisH1/4qwn2/jbYmVyTV+EJF4Wa97XlPw6S3lhhqqEMpPnnH54snxHCe
|
||||
yTDVW0zKekWN9Kh7aVdHDB8vPvCdIzQooCdUjWvNqypdySReI5ejaxXOWYs53obrZS//tPLfhWUQ
|
||||
/fJtj1u1A84ziJJ26UsR0IYC76G8uRtLdO4E4owk3ODAYTpmtmetiGjudzIzFQ/klAQTolgwOnlx
|
||||
QnLzpR2XQ6d7HZJ3e5htFLZL31ervvva2n3MRW3986KteFOJ3Qel44tIsfhUOOQup/B2JjWe0Y21
|
||||
Wjbnj/YMbGFHj9D8WULQPo/FOdNBLCmY3KIbOzm+nKfMin3CXbgW2F/h7JHLr9C9uduG1CCGBeFY
|
||||
vnCIBbrXIXZXuiDuLO/crPWW5u+OE6/r3zEhpV6Jjx+LRyrbXdw8v8qH9yxLa37ynV7zShuVIGfb
|
||||
xlvPklve2ctuXZ8LpAPgiZRRgPzLL0WZJP7FPuDn/HKGtnocz2eas60+4yz+bprwgiYSC1rVGFYn
|
||||
sjMf7wpoCxP9uGWXCKXG9RiaBNFst5EOLuZ+x8ppt4TXGC55EC4oHu2Pps6vj2TaklrzPSabuaZf
|
||||
YBx8HYnHYOaQ4aTwCMVFf575uIj50wCXOAxKA/8vU1bMK6DBFpVrM2PO8ElS8GSD52C5UUMBAv9z
|
||||
I6L6P32RrCTYQSvgulOYP6l7JCE8uKregfh2N/0zikL634M/2za4R+15tTxVrvlxykq9SI1ewyDk
|
||||
oXQ9wcn+2vSHMRcosNXvhEoA3S7SxMVJdRFxRZrOxoet276plDxwnL9ML33YOpJsYjEXAu9N6cF4
|
||||
pv0Zwd0hC/UJUCmosVo7Tnk/W6FexewqFslYLvwllLYpirPWqXVAm4hV9AKVsmP3tOUs/7pUzb0g
|
||||
Eg7UvsPO+IU/JdjJvnUJIeDAgOU5SViJv2iVrxlSAxG/2tZiKf8BRpDCbLAMu7mcankt4ESENcpV
|
||||
C1w1A6zYfarQ5n5eiWvZ2xMjHGPo6ji15umCPXCgUhcvzAWEadBwPjWbeblaDOFoZq5zH345j2Sx
|
||||
81go3IkuyWPe2cHoj7yb9weKueYBcbTBWu+0cOwUFOLHPtb25DxaVrGYh1bOnJGY/ymdUTtQfTEb
|
||||
KZUpGUIvHU04HzZOVBpp+E1U4JN3/pKxoUMZyU1DgG0FN33x9wWJlytGYSZU9l+qMRPZhcxKpKaM
|
||||
BAw8QQGKnDI+EXXiBeKA1lYh9jRVVta8HiaEC6ZyRTDp7cEyDufuimkDf2ahnShEE+c2j4MevsKN
|
||||
HvY0/w/opMFvQN8Y+0LWpJ5hr9n69fQMYz19lqAx0Va4rX0O7NQVnWOtSgHJ6aW5PRSNJPa9Nt/2
|
||||
r1VqpjMxlWfNGzi/R2OrfuBAK+jH/dwHNlYetkk7QkdZqh5VVr4ifTZylZY074kE+3wA6YL49ZWo
|
||||
5Y3oQVlyx8MeTYIhTwVX72xjlzVfMgYbIuKzjrsQ8KdUU+9lqQ4KlEYFxMUfGYeusudwo5yPn8Nh
|
||||
Dw7UF5oIPmnys24AY+tvpZYpTz81ZyU6l+1+RmcjKF2HZgEmjTBZS8vToSfhoBHACgoN/ZZbKBGN
|
||||
njV5YcKGuoK36AGJSee4sIh8EPy3KTBC1ToCuCpQhArM2LIUBtidx/+F/EBy8xYpNW3MEuwofunT
|
||||
sOqzoaCOt7zs7iK4I7vYOcpLKPk4MNe5tFoKHDvDcsV/GWMaEmJoeJW8Wx416idOAF3bHef+T7cx
|
||||
T44wXs3iUDYO9Wem9NcphX6NXDML6sPrXZQdvnWTU/uuoNNHiggXCSCOpirMQ8vJmVDfC8ey8Jfa
|
||||
AMNC7KcrIYsVH73KKu5VeFl03Ge2SoRGqSdR64oyryCpriGrqm7d+sM479p2GPzYEG9xYEYuvh3G
|
||||
pD+pwEeB8jErK9V/4l8DHa5+O2aG+mVNoVPESA42YPSmpSlc6dSTXRg86QgaEMCd+kxkd9V3qqcO
|
||||
7u0BFcEEvejHTuDoDSxLkhaA3FxaqsPNeSydZWNVh/dR6MgZjaPhQEbKCKWJqLxAy5zsfQI7VIUd
|
||||
rzgq6kv3yrGD4XbYOc3uHT/GM/OL3AWJmEoBFKCACsdQlhv2wR3yY8YVtfZVPGjClsPbsBVCegMP
|
||||
WnZ4eQT6UxZfoCJLXpfeHhUUZ1sybRzVi2EP2w91b6IHxXBBF4AYjVVSrOqa10EG53zEfxfXDKdb
|
||||
EFU+WLv4+/x9USIU02znLKiZxulnW+bOHEJJx93aobuNRpXGbTWQsR0Cs7MeJpfiYKtcNn6EHltQ
|
||||
ezD4iqExeAIbbMNyeH8A5uEO6ALXlSrRVM5zkX9BzDqG0yR3hvfSse8PmKrD3K2QCH821M/85qfH
|
||||
DrPZh4hBsdCn3IYfssbUbzkMiL+iP/ZfxYoNkguFvEbMUUxB2XtN65j4m+WXlLFGqQIShHpYQFyK
|
||||
VSi93+dLBuutihqkKXh2ouhRVhvfwxHu46anA+r3Fk/SsTDrJsOTX6Ockv/GjAvpHcVdHdzKHSqG
|
||||
2yx14wUTpMthSyVn493JRqPjpKzuA7gOtgFrDwfKtpv9T+JkvHUvWDnXxzlXjD5HecyWXWUfU1Sl
|
||||
P6u/18KQtIvd3M5GHYCWTL9Zt6LfLIWbBTBT3nVd1X8fnC0LtIu3QmMzWx0PEOkqmFsdo7BM6m2z
|
||||
Zj3eVD3ElMDjrh/wyCrCJlp16GMpU2KMIx8+qC5rS4x7Zf3ZyHtrVf/HhwMxW28COyFFGhcc/V2t
|
||||
jkEfNywd23oJLHp3weTpu+ULYIu2qvKtOkXV28z58k7VytMTTbujHZ/V41pH6NjjY9kHxcPOjS0i
|
||||
c/r4k9zHVfQsYJhOKNbBXyplYHN0T0aWor2XbrX54u5c2WL+0AFBPeVhyB7rZxRB++ltwVbkYBML
|
||||
Icl5rTPmYKr1Z13MW1N7abLir+rYEklMtzdd66nVEnqQbubIDhxxosZi3fCMg7u/PS/8Dk1+Wp48
|
||||
1ynZ3dCaK5JTB+jSOy3l9UAXsZQzhGps7Dv9c8vdSHazuANE9xDwvx5HJ9UcZdfyKRW189ALf6uG
|
||||
upUlc1DkNvwVxJnYPJTlhyCZrPqgpCtxd9OqIqy7MxGHlUwuz14XmPir9I9ohhirru+v1tjNZc0S
|
||||
QHtQjYT2VRC4dPP7kaF7QaFbQxwL7slrYPxxyYn7anxxLNLrHb4aSO/zk6MFpL5I/r1dvR8hbrDc
|
||||
eDbgGWZNj7jvGENVfpmAQ4hzHOZeUIh8dx9SFUlGV2J2UO3IXliI+ifwHvpO3PFYY80KFQDOnOTU
|
||||
O5dieSVdm2j7POckKUIBXA8lYI6/5ZRrLLoVmyQt6pBUCg+CQltV0WD6nYPR9UewMYjglEs+4sIv
|
||||
bXVBffRUydAziGm3UWZH+Ebj/q3sKB+d7XvYW3TNEYRgV0zCAtdOF/5aWawZC4nIiWu6yULBS2FV
|
||||
uGvaU741tXPTTLGSdk1tRM7eO2HnxL8A3ucyptZkGTYjjCqHcGncLSpMcFBplIP/dx9VYHxYEpaT
|
||||
VLdDl7XK6q9/CNWKU/4bxw+iAK+8EHrvcJTEvYYob4jBoUMax+e4dNw3MJyuRHkWoLEA6qw/bctA
|
||||
AHbpxMsFJNbCCKHxSKplS6JP+pHWi3Kyp/9fX+gSYMyc9hM3nNDRahJ89t58eX6SNI+4Qzglszrc
|
||||
CXKHJGMSn3OjoiMBy28gLvH9vz5Fs8BFud0u4e5r9327YOCIOLlBO/F2ttEXxoPoI6gib/EpfUVY
|
||||
8v6YuSzF9EYeh1A+BqwIClfRbHxR7OczR8H3So6aK1iVa1tHiNXCg4rLTR+ET6TC6AzZJQ6x5Tfj
|
||||
9JKNqmcZOeT2fzjv3XSWFmljEwjyiUhENW2eCFlL1+GIWJfT3vEeBV11GWqFhYbUeoUsbUYec+d6
|
||||
XCdNOgqMqqdO1WtM5r/mudgwcS0vd2YOFoSwSm2uU/kDBDIUVtGPYthNHj3omLbTo+57YQ3jGcQ8
|
||||
7MPEwgn+JGjZJ+zl71EBQQPVt6kxf71Zm6uSeral6d78WyCG+VzT1A7XSUBUiSj+bPNC23/JCOWo
|
||||
+7qft4IW4sCVsk8fFMh4uLFtKgpy/iMCt51Vrm2JEHyImdLr7Vwg6MNEpSfdJEJDt6PGKrgrmEBP
|
||||
8D2NJkpnyxa4IKwFqjuqolupfeLygGFewNlw97ZcTuov9PlSQUwnDCiqaA5SIDedRDDy6cZJsmgj
|
||||
gKLPsem73bsQbBy/ZcSyxkt6U9fQ2Dd1NnHh4dRLu7btPM2VzA56qi6BhNaOS13sLOqy2op8Yfhu
|
||||
0lvKNn7AXPwdAyvRle3IHe7nMls173UAQUduBfbEoVRi+xvWblIYOFcKESxMHpWTpRMnrOe4f9uG
|
||||
OvEHeRWS/SPgoQTpKgkaAruYokEt47yWVSo90xVgsfJDgDOoZfH9kgXd7TWOipouzOrzUAoV24Nr
|
||||
IHHfBZYUeHGUztkSMtE4Bz3zYPMeWcDdOstGQzR+0G8/GSCVpfyA/MjcacNg7ootnpteUf7nC5k5
|
||||
VdNMlHZ1O9m0fPDSDynKKzuQgLmPIHyJVmN9NCGoDPo06NQJPKG4yb3jJyecdICauMd+ixIOjUIl
|
||||
HDCXyPrfTcvg0miOGtUUlkHP/ht0dVIJ9TKV8QC9+Fozb+gJH3OPvDaATRAX19IAALXFzZSewYcF
|
||||
nu7dNdea4FdaFxPKbR03CXsR2zDNPqphvEnf+iQ+6Tl6FoDMLnKxSs9NlLK76rTvneT/CHgBuE23
|
||||
0mYouQXjo1LsLb6LTvBq/W0Xs0jj9HsexxAK4RMTFM31GHdCHdjOWWgsfUbrYSJw1iQsggLLEicc
|
||||
bYSSnGoCkjqcd/I9K2Pbae7FguIxmqcy3Y6P4M490xcPMnvPRbTzN0fzr9y5c8ugAhkaPwkcJn7P
|
||||
4V8iBbVy0E4eDhRDpLjFGG895LO+UOM8GMq/CXxefzVV+Oe+Ty8yFQ1kvUMZh3cmPEhohxgcOkcN
|
||||
RxV715U0bd/AAQGE2PHETeAWbdxgMlBrBRvgWk4ZNVDj8appJbzYfcmyLc8IIBy9Cn/4Y1hE89ym
|
||||
qbKHnH2AAfSDtg0xzez9VgKjPpUahrODiihgWZTRkEi+vJCAe7l9Fq/aVeEg7G3MPOmQ08QQVPBr
|
||||
J0lKLggljJ2S4baWOxyKBxYs8RiB/KmihMcjdbfmepnhuIeNL/4n/iYClkKsAzagAZ+VrW1ScbIw
|
||||
rtc7KmJelkGuTNLVDh+D0dA+OJ/NYDWITql8tCnzTKhQCqrhA5AdWlZ/vnXaqBbV/KrUawEEIREN
|
||||
QUNiqLNSWyhIQMYYYndRI9V9aeBLaTdbRLD2AcHi1ZYqkY81j6vL+3JBBzVBkxub7a7wPnjRImrz
|
||||
NTaIYuoR9hapCMpZsZyPIK6+k3bPE4CF0fvbHWI1v3menl2055VUcMvbyAVcmCNqh/2xeReSLhHk
|
||||
Wl3VWUMlFkFGCV20yCYMSF2sxWo/jwMhGvXya1BivYnEl3I4yyBmgTtEJ554f3K41tKf0lO2rFXp
|
||||
VppFb8MZTn8gWc+9w0H9BWiMV2F53pD7z5+AYAN4J4l5Fgq75oGyNryAPHfM/vmIr0xRrRrTZpFb
|
||||
UxZ1mYL30DlD5sGxwpYR7CLDRdR366zzsP/2S190+o2MZrdb6a9WPbtMlvmPDMNvYg3aDdZz0Ovh
|
||||
y9QQOfD+pczjAgTfzA62XIallNUH9JgH2Uahe92A4yfDRpigntqOiJbIjiY+vOD7fyG1UZkVrx5m
|
||||
ILT2Mfrm9dlk+6jCOA1ziwbtKORq1MGzVTllCCjbHHws560NN1CJFVubjqRXyxr8wWUkDmufrxfg
|
||||
HFiTzGhcVH24CpqLSw2I9xO19g7JVs7qNIn0HPfMAiMlVnhKhG3JPdke3h0615nOM1l6KzIN7Fg9
|
||||
fO3d23DgwoaIJ7U/ec+Ela+uL+FUOkQntQ0hO7YkUE2OMcx2HGd5WQBHk8icpAH8+nHEnhiaL/iI
|
||||
fTxFO0UBg0HielOm3RAWlCtvY3GcifzvkFGoZKTR6cRfovAlCcOUwC8RGBdDPQgWFJttsVjIrvz4
|
||||
/cpmVSt4mFiZ1qFlfZ47yqgQFB+xfKvBovlAHbtmYMMVMm9JNDILUQ4FcrdxJQGUrhBpUMnfqRL8
|
||||
QiUEakAocYWbHITmhl9jD2PwM2h94ufka8nB8RNfJ9nitKtB3pl4ZguTgNEbiUhNWDG2kx78Ezhy
|
||||
QMaLLD5/dJDsHTCOColJlHnzXvK6L80NjtCgtyLheRh1/Xgn+0uS4umXtQpuYhh7rup96++zUVbu
|
||||
wnSW6kuUYj4YTc8ddPH//QNETUGzHxFzRMcPutUeC5adgIqAVmgH9lNKNvX0wnlWUWcbv2Na7HWj
|
||||
QYgUaNF0sX50k5j/DGPBU3Govj7dxlsDdBOrY7hX7bgVOVbpTJXhvUWKGIVkHZ983kklQppdsch6
|
||||
RYn5KZzlPnwnmjw+bmhHcgorWJPRs5Ivn+SODaV80h9OkefkSHwdV3NrJxMc8Bqeugk4YL8LXyot
|
||||
tSOdOgRgToebSirtm7/nGUHpYeoMBpXoKLbuBrCLBYKcJ12dgFZZB/NRxsg6Xa/u9AzeamSA72zd
|
||||
ZW54CRc6asJDaHaPhCJikE65rLbHrVp884+QVQ5q8wkdV6+j7YYx/dgHdCRYK+CL255yAxUCNFTu
|
||||
pKp2r6sMfI07/CZa+FDymxwZbQatIr1tVmH1QXaXgJWTFWiZqkq8VdaKMSa91nSbteuzAaLbh2p/
|
||||
EtKIhRxgLpR1uLm4Gr6KZeqhFy60u8lnh7fSXsOswJ3ltIV5pKQ30Rj5PdQWsiK/zpok0d9gZ7Kk
|
||||
zH+OiugwItoK6gLCXiqnRtBUEjcc3Ru2cH8RlCCts4zqq7sq9tGAQm83zltyI8Pvlbf/jR4IPJiw
|
||||
bzSyqT/hItXYlEqwjQRjzMRIncWVdbcF06924gJktAKHLuyGCEEMMB9lWKDFMdCvo4jmL/jpfIVE
|
||||
iEoOAhlHzoHoVzBywB0oXZ+McW4HKP3OUNj6zDMFxNaNypFGfkC6KVGSkoL0nB1vNaINWnokIjCT
|
||||
3pDEeXDV83/14CXBPby/vxc3Y/hoWcoEDMb8cLcGI3z6lrpB8O+bzp2Eath30gNHKbMeI7lxJ0by
|
||||
0Qh72Nn9lI0rQo5cLulk+wgPCwVbNQVVNQUmik/e0lSUQADAE5vMrS06Ouf6FxoEViOOWwoa8jZ8
|
||||
ZeCYLaI4LRgILgVRDtUPCknHZ4LmNuYHpT3EjJMqL7ixDAeSigBGU9+vULdGYOwMQBnkDqV7o5CI
|
||||
QbnxRzzyknt6Pd/HCQ91x56RtIVO1cu0W/qk3PiFj0Bdwt4EQ52MgozRzs+YykA5bEVWYjRI8cgW
|
||||
vWAWO/WSPl9ZBEqEMZ0O7g3+lC27oXlQti24ltH7AML8h8RBK2fYYNBomrrdL09DnUjq4yAqoXoC
|
||||
Vo3aJv1hbk9/l6zY1l35YYs3Q9aIousruurKaozKOHHwvyVaMrAuSl/TT6eEIKTkA+BdO7OECgEL
|
||||
typWP3jB4ouv533v8Nf+fDuUlRKQXBfvDyUoJ2hfl7G8swq7+E27wqP84B19dklsVkz0/2NAiVE1
|
||||
0ONWk5d6WRtv7vZsqwlzcgn/9Q7DKY0voNI09Fp//hpIrEbqHDsOZSVi6aqDBOih4UKcHDMcQzqy
|
||||
Ph3dcPEVhY2XAUl+DFQDI2bH2N1zgwa6lP3gKOXAZHJOhQLFy0XDI9zt35PbnExKPCZHpJQi9iFX
|
||||
63FOJfw3b+PUSGOWVLF1exQnQV1r30EVTLtndvnuNYvQ3qtH+7mMMSdx0Inyoy56vBpWKOgZ1d//
|
||||
uAi/0ysi0lQLOFK2A8YsKmwnDqA0TrW2/O3wZVFkhieaApn2nvInBKpsfjtS3hJc0nV9PhLJmyE2
|
||||
Bn8j52aWS/1JoRQaMKYg0OTPwF6ZuVWVk+6YHOuWtK2n4/YTC0h/7qugjfZ4DpHBMhgusMH74OKh
|
||||
fk7vt/5cSNyGCeaBR47E9Zvdv+e9DuhWTQWsfRXrRDP6nJdCs2hhhzWRmgzfUtxgcMu7BoqwnwyR
|
||||
Gsh8GDIZ/uxHOoefus5Zxn7DkFn391OgCjuf0AZtonvNi9MQ8qut0GvHhHKNggcq9oQY53J/pxc7
|
||||
YDqDPAlteIcqfjQ28u5TBhCJC49PvpkDAQL4jqadIoVXPLTYDID+9ZLxD5A71FsvusO1GChzu6OS
|
||||
MMBEIPjkWkOJ69hLfoEcDUEHmRbDsnnhYNUsljbJvdL7fRzYD+8VuaPLs3z1UiwzELjbFYkRjSG+
|
||||
8j6xNVVIhkkOw0BEJM5Mn6HZGVdebpUWY7/Sm7rv38+j9stbRVKNMLDSC5IPBwtpiLKNpBLCzHnN
|
||||
RKqy3gFUtzDngniw6LuL8NxE1ewO8bccvYFnLhZwDTdAEEJonSOcr4gr6NuT1+XStbmsHRDtIEpF
|
||||
P2vIYMPHZdHjx8qA/eQ9HcPdhBwpLOudG2E80/0156TMMFaD3gN/+QInfhXyK6BtdMIH/38mDEZX
|
||||
ilLPqOFLkwZAMzvTcO9GdevvdvhvdDwt8O2/7/JU6HUic99qKdFdYiU3I22MPlhGTmPlqd0QGRd1
|
||||
4oTEiwuPuYjv7TtpE7XmWEH3BxwRCiLmYADyX6XxyQJzGgXFbNGC6DN7nZgASOyboWEOB92pbOGf
|
||||
I/AoMiTgRlLnqxRKcp2Jrlj956QAUj+H0l4nEuwE3XJP6y6i2PVeUgs9CWyMUuvoLOrb1iGSNzlI
|
||||
UXvWQUB8fRIWX7xIUpf395lDDKxxsZy47NHvyE8M7KRpwTL4GKfa2D9wWx3DbcBopobNTjLirUtW
|
||||
IVUz8X2QTfqaoMblOutq3xDSRMankvYxOoyCt+dNOrLTbUDBT9XsVccexoIWWAtqi+i+ycX5G8EM
|
||||
NV5n3uX5BzdawsWHixmGyTbph2oVGlrGhjsbHGEd6ubrKvazdSgzfj2IGJjBnELliHmaOm0JjP8a
|
||||
3ciQX6t7zj9ZTnF9ticxXBZZZuqDndguiPXyIHNhAXMQVVouMg56eoskyz7x/92P84YJ0vxk92j3
|
||||
RtTUv2P3FCB93cmnT85IVtX3dSrmjdQx2QyEEov2VYv8TcfAVWf4LNonD9rEG2NEU5Da4O7pWXJm
|
||||
01SnrE64dTJfUo7ie8ubS5AiPwMKwqSx6OqjZQ8f6S3VQiJ4MmuWcmxtTjSs8eC6w7+FQYsBnFcv
|
||||
o+YRHlnELKVTZZaITy8LlkHHCIgudRBdKBHZ/u9AtFY7HGsEzpw1Og42J06gUmCSGNNt/5VXlNuE
|
||||
fac7rAQ74JGDakPu780un5YyyNBP/N87zKNTNmXjqQWh9607Cv6SeVKuQAOHdLKf3+4gH0qEYBNS
|
||||
JwxfvpBelIE55YDLbAdzMM5amEwCzLZd0sfqXcBYJh+mtdYBH+UGRGxgfYwAy2pXQcONjr3+H15i
|
||||
IuDvrmqEs47Q+aBQ0AMv6G31ZF7wm869TZHevzpn6SuuzwxTb+xAgWsD069hFFp+kexuVKSSh+4F
|
||||
SEMx0tlm8MDrn5UltgVLdorJH1eaYXbCbyWcsTglDBYgIGwK+Mano8ECAjbbXgE42jZ6DN/+JK25
|
||||
4oeUQbhqPoWYpN4Bu6Sx3+n01mZwNYV3fNi/YkWVCG16MJr/rCAGvIvXKfN88qoaNfjF2+wveL6T
|
||||
6m7XYRCfkfpIzlc5HR3urwDEeayDFuF4HGdnM0XzmAN5eo7EGLWuy/1apLvKuj5qLS/Grqe8TBBQ
|
||||
c59yogKB6IDdo43RnTXKbQ+V/3W5sYOnblZL3jmgl+/x+YbJvf2/u2SxwJJyT6iPZRaVstelkTgI
|
||||
dr6gXgB9VOR/E08VQ7lcpL1jmXvxFa5jZ6LuEyhyDbQoJ5oE4VWnIcRRw0Vl1Xu8Jrt08quizhtC
|
||||
X8+NL/ynoCLItdiD/D4SjebHQ8eggYkjL+nFX2ffgTn7nCW8+6jn6fnbQqJuAxoTmooqvX1lTT1t
|
||||
sw/w0GGHEay0jN52zN7ak3RFa5TSijiZwOqb8FqCfzZn0jFzTO92SJb+WN9T3GVTm8uc7wJWGlEl
|
||||
Fr/BndSMnKNgGRkeOAp0J9xkibt8Ab8SIVPIbkZfstBBqVizGxOXelKieBnwS+ImTS5MWWC9AIkB
|
||||
3J2k9ipDe+jTokKcKKVK8Xbh3UusEIXDJgtfVHJ7y12g/rd8uY+hjxVmcn2vHI3BJeFc7C0/ijmt
|
||||
qhz5MS+abRXYQQe/yFkcRMxf+phCcJCTtaD0aeIzPtXiHooioOJDPrLOzhFIzy3cj3x1UMWo/jg3
|
||||
V7oul2j4kqXLN1HR9oADjWo3+6C1eT3iAf+u/0yzxxn+mVd0hDe/LiHcluPG0WUbp6AnYpEYRc0D
|
||||
edmUCPwpZophDQOrn84N8PsdTnRj+HUyLUWxGxKySd6co0Q3Ulg5HGJQLWhkUzkGXy9wo0QH8xvk
|
||||
aI09b6lQ4YrxkeY3UddldnfdETLpo4zbulkEEWYDvTdEZRdXv3J79TYMK597CD89GePgFhI4jnd1
|
||||
J0PuLhho47cCEElfH1gUZdog8X7iF60G6G2DgXjSnc1tUWrbduTRgbkmvQqGXOwrQR1IGKVVMKGH
|
||||
eYhhEwUFScf9SNA3DnNxkq4zY7w1XYDekkOcrpwuE0y44fUREynd1eNcrVMTdUXhTS6DKvuBt5+u
|
||||
/OVGv5YqyOoXuQ5QRk0GV7XJTvZQFqNp5jhWFOPwIg9yf/7JVwGsdGJ5hubjz6DcoSqHXJ5qRBu3
|
||||
pzLIKjTASTMIk3lAbTaAiH+C0hF9qmmR+J+q3viySl3OmnvkmueJUN7HKfnaLgFO20aiQtWE90uz
|
||||
AMH04k8yy3KI9UpBCPX9KyftDytxUuZ4H/tn5bdhLSHPU0dCkZcoQoEanQ1XLkCzntNQvdO7Qzr1
|
||||
Ukurm2yCK1x6vzJjOiGJ/RLC6/XBh/rjiMgNjMApWnq9u6WIm7IaP1lkGibs6UZKQepNiZrImHod
|
||||
REJ3RLVxFBjiXvZcb5dHk2r0OnNaO0fu8CHPqXO5hD9iT9rPMy55lfDVX1XCXarGag9FGrLIo9Qg
|
||||
ypaglNRZAPmhfsrC0g2Clf6CaBR0/sC7ppdCZl7sp3OwzGmB9vsbBwRGDQtBjK8TXQ+c2r0r9P+w
|
||||
P9R2972D9FMON7rQJCxANjWjoQsIe9L9Bv9bENphONwq/scl2F1yR0KE5GnJDHQgJ6Rz+PEJ46AI
|
||||
81ITG9blLykiLM1NOT86xr6OsuF6Hp3OFbGQKj/nV+qShyk9TrpOcifVZRFfXW4+nwatOHtfcr24
|
||||
0yDbDQKHckQj9YdQF9Tiy9zqBftaT7iJEn6KrEWgXwvENuYqQsCwckcja2VCJPRC/c3MfyrcC3rA
|
||||
E00DkEyzHkYoQm6tQeVo6GpTkrciD9fD3EST1eQEHfGjJyjh8idNN2aY5+wy9RDVAe3/ZP3jOo0k
|
||||
f38xtUYfqspisKaIwQQWqJZG9GQmbEaDpPMtOsiRMWTYus/ggUSvS/LrC73P+Efbv77HstnitsHV
|
||||
Xc9IFZ+U2ye3uRmB1tTihSe9q8kHEbrPS89Nvd5ZMWPEmhfbfWEn/hI3uS4iUNQFGY6MdcZF4Y5F
|
||||
a2FJszb6ulEls8ewxaCv2JQtoeXJnb3AD4JBcpHoSdaBsFShqNL06rjbS2XObM5VSWnrNiEpBhjB
|
||||
MehdV1Ci9Tj0rdcG6iCD4WYEWpiVB0mNwqPQUhm3TBt9uWcuT01H8pM3uNzVxadA3WZZ8na/s6jo
|
||||
6xHi2SDboCXZRBpycZmIxRqDn7/G8duX9jcbYx00vCEDWlrf0Q3Kq9knZoyfl6V14zkvWyj9iAVf
|
||||
wxtdZjshiBTZw3VO/Kt+noLMuHCoJ/qm1/Ven2E93AAzh9+G1X32mMwVN0iGtD3D0oX8NBxgDT85
|
||||
q35EdCrH4ZFf36TSx/gazsNsYObHSujWDBuD1mgjGx1rLbEg9Jeblm5E+umWhOLeF1JlO3Z/GCjg
|
||||
JL7hKFARi9pucB+LKsrWp7iypFaYnyllRjVxMUReCwPK0SwuKLZdYtQbcs+X6vwWTiz/MQiiGOl0
|
||||
UxUHG9Q2isvZpvIdmTjGRvUXntvQVU5IxI99XzUIuHc4XlelnlaZuVVfxQCuBRlFTlJ4eZVTLQUF
|
||||
618F2GusQU4eWSSw6CLsL/9yBMXtXS1ELUdP0w3ewJ0s5+x6dbyENk9jEt9AH0sGAtw+xy/qcWpX
|
||||
Q56ybowSsrNFa0NIdsS1Rh6dDWDH33v64q+moXr3f7wQjE2idLBSXCl3Jqvr/5NdmiNqhYb7bH0m
|
||||
P28YAyNS73EEWNKSXoKSgiiDyT3ckjhqZWqlw1BHB4NCbf8zxHdxM8RtNvxPAPfVynky9ttNlrIO
|
||||
oI11n1MjlwJT4U3Qw9TlW34fSREcvWKFun06X1YDqpMiQStLB71UEGjIWA2ejHegusSm6Cgy4ii1
|
||||
T0BtGpRt77NFogIRh/EzaBSgsNLUjuyh4pYUgpIGHsuRzJfbKGnpBBkxpXw32M6pf0UoXF8u4zyh
|
||||
gOtJ7A3E4drj/q9x6NOWvRI8iwjcjhBj9mPTwbUmBA3h+PCf7TIP4ev+zsJ5JbRGXK9A1qpKKOqM
|
||||
dsI5y7+763Uj3LrH22OO4fMOSqwpF1RgpqYFUYmdqXJ5lMa8kDCJ0CxoRFNsg32OaZYyqIRK3EWP
|
||||
VBweSjkg30NscucypO5W1TrzN+ULRfPwjSKjelkZndVuy1DZtSg4S6ZdW0KRvj6Uu6hBZoy9YLos
|
||||
7IpgZVxwtZW4rpMI7vRqF5tDBuDgVhVPCOYkjvdYzNDo+I5v1BD7zT0HwxJ5UBgMsrlQO1NMe0tF
|
||||
YnfXqovlb0PJ9l2NXgC8py1OcflT1jYSduEdjlW/cOHew4hsjqF6JVxt7vpPDn9IYKWyC1+n2C4p
|
||||
TwdYPu0DWErT5Cp8x2VHVE7POgiiPtIDKz2BPnZR3kIii9QtNNoOxd0YOMqhdbHLIAgOZD96ScbZ
|
||||
bKEkpMJkbEp7HqgXSrka7NN7S6KCT3rbWEERaOWjNjFy4iN1RmgUl7pkIfK/1ye7WBBTUcPAcl+l
|
||||
2qfaqzuSY9b7ceu9M71sC0k7NW8XID6HTC+5LxcxrWThSGne6Y3boTA0qeJfNMVNb3JGpWiJuXal
|
||||
ZFAj6dAqZa2RQjsB7vKLzRv+BFpdc3XdnNlVuEN1+rdcECmrHDkknBJRxcB82/GjaM0xtIVbnmZq
|
||||
bfULH8lSYXKgeukj7hawyD3moShQIjyZnp4AgbSUh+5gEoVj/EHwsYqqFBqV6oxE9HIVaNlTM6pW
|
||||
G7i7eeskYGNSG/3dB48DlnvEFgBDqyXTKUWA2IsrbASAmt8ZK1GZuzslXHE47pDrdEvUzZJdEux9
|
||||
lj2Idx4w4Bejm1qJ4mRYAwqWTyGD/fARXmKjsRlMdCjZZ2HbqjsCQKFaiv8PuNk43SOlBD/0BN0b
|
||||
LwdqFmc8jKO1Gepn5A2CPtw5sS947eGIhKIFqtv7+1xpLxs89KQmb5Vf2Pxrxxr0fH80lrYQorU1
|
||||
4DBtJ3lRDz99AvEcgY67VKvQ0bOMJ1jyVPEpkqw4yieJ/bhIYUwzQo0eyNFyPE+jHZk69UF0vq5y
|
||||
Ivms9+enZcKPmcRPtm76ZgT/Baw57HE7LmXL3TKincwwZ+KqJnX9xcxuoa1Tp5xavR4jB7Lzwvj0
|
||||
S7wXkaAbc3HdDRDze4BAi+lj6tB1gbC/qn8F8tkVSXeHZ+11q5LELeS8mbUgMsJVRLUVB+E1Kcuu
|
||||
HjFK/l55G74F7idJyYfzOvyoLdpcrx44uDp4QOKjqytCR0mdxBR2UEVwJP38nbfxUUijt2BdP4HJ
|
||||
i1t12e8mDZU4t2R973LAt2/tbl8OvkuF4U3+FXmEDX/qFqPYkwEcWRhhR7HKBA7LK7whhtI6M96d
|
||||
RLK/wSSfW9lLQsfew8orDu+ERKV5HlAT83gTf27G2Aj9W3FgIipwDccwhK0CKACG98b1T+Hm2ZZn
|
||||
YlianvdBSIG19lVKIJAFS+OHlfhatCKPCsB/+pK1cEK2aIEtTUeRmHyx3JzX5d2VkP04kBPkLYb8
|
||||
ZEC6rbxekgrG0nWGmiSHs64dGUrK4/TeB2W2So1KxdwIIiZavLli2e8jPb/F36kdEYr4k16e1WDl
|
||||
tN7Qw5D7oCuLZZOx57AaA1VsSzv33qIlUAv0WSGXE2xRj+p9IQzVgUbcLTJjUuTEy9aKtdBCzFIa
|
||||
pYuQyHR9Pm2YVb7dneBuYeGiiz/jOG5ScW3Vqgey0tEHSZaWvizmh9Z6HOpWtm7gpgMHWTLklgNw
|
||||
Zg7w9DtYowH+5DayQWnPWs75DMwCFSckGcUyPSmCMq0inVM5Tqb4YNR/HHCQYY7DxDCaJ6nDdlaU
|
||||
Vno4dOYR7j+ggxFx8SOdS8ZiOUipgNOmtMiQQdGybdXWrjA/goRyCvS3UFhyDvxvGxPuVgE2hqKD
|
||||
W3oMIbMc8J4hmuZNGw3NIY+eB5TRRl+/5KVG2mSUZGEs4zAyjr7r7aOz7/XFrp0bIWtPR1TcfpWe
|
||||
UXLU35buaXGA8H1nIWRGm/WbCw8iiLXlzW7q1X+bMCtJRZAt1kYNvkkS9wdaU1JQ/S5KJJg0R80H
|
||||
lFZGPAdVwFZHwuxFRx6wBIFNO+EN2Dnm/T2fT/AU/CM6IVBbWuwg1mfSr3rkfugDZ6/NdeOI2slE
|
||||
Fz7NLD/AcJ5KWCjjnp62PwSMSCo1Mf5hPPlvLSqFPNAy/OqJzqNRB7w5ygvU0bKTvkavspJXJ2Ic
|
||||
Cqmq0fwTVm9JR3dJi7E0/JN3WxmMcIt/dS597bIDwhH40XQe74/tuG0lyfxwIyX61wLuLqDQKTZO
|
||||
dXvGorweqWqpLPunjMTMvcos4GPDJv/oze8d8TnWWIShTM3TDbUdLMtS1ZENVTTgiJOMlZUYpQwh
|
||||
QsLtTVCakE0X2Fd+ndlLOaNQ5Hs0AfVEchJi3BPsclMlaeMMloFTpWEOxh4dKtr4b8omj/4Isv0v
|
||||
YuNPh8hTSNNwHuFOxhThNWP9xty6OLGAGE/DpyV4fugyhS6bJa1SAhw2PJLBS1KbuNa43nyed+dB
|
||||
pxzfkgUlD/Z3fzgalS5187HZ2gqyuDzwSCIsT4Fbd/xM5fs63Q8vRA6LK3Uq3KhT5Cc0IHcCIVbb
|
||||
Kwa2RBpN0ZePJz9yjIt1vnjefVoKHfXpYBU/WpCRD1qgPSsiJlDiBENnt2Kq32puuR9zSNIF2qNK
|
||||
668tQ5Y+su5TnPgkz02loLKJTMskO+xJyxsd1ImVyRv/inwYvSPUMOJ0p9QOJK8MubSrK7BI6CkG
|
||||
8MGne2ScqnRQD7y6UD+XFOBrwm0EewYVf4JmqdskW7XqsZY0hm5r9XVC1qLTlraQs0eOpjc1Pq6C
|
||||
srrj2s1e1B8T1JBPWy3WF2dUhr1srf4W5giere64zBRF7RTTaLyWSQuzma34CSUzbnsj4b/LGAq6
|
||||
QsTdgZ2bCrZ9S5myyLQaEVb/YR2QW56vyeZFpctdXPvT5roUO+122FmPoe5LA+h2330ZvEh994fJ
|
||||
KmQK4T9pB4xbev7+9+mKXycec4sjzOAA/KRF/63kwF+YnRWWU8tO6kNeud2YyJULasSulFJoXiDW
|
||||
BhwBbcGmIc67l9UWmqC3M/ziy81BwWUkLi9GpI9gMT2Po0lbRVskqyzl/JktH/ztr+mJBR5qEI4e
|
||||
iwrAW1z9wxjGFN6zN4IU4SVdC/QiIbsoAbCxz60B6SP/USxzv27yGOKx9qc9w+L0cgfnATCgKqXz
|
||||
hjrIS/e6xjYx+S2oaJp2yBtrEvsxQLtS4arpZQOuxnvsBTtz3GM95iMTH2UQmSI+Fs7KeWPaM8Gn
|
||||
kbOreE33M6ag5jVt+wLYRVdlfQvhvN/m7FHkQzDRSBBi/ErSm/quYqIBtPfklveI7T2GG0e4d2jg
|
||||
ndAQkjOj17Wl8GqFLrni/sCFaMw+PBkR1LT17fHnWaBTAYNZhx4NMzHXarCEibSziJZGVOuXSMjA
|
||||
4DCfxn4OcuUiCwMN3h+AuoYFvlNm46j3NOL1JDw6g3TggBeCsNPVzeIgh4hhKZip9rVby5etvxL/
|
||||
wExla/TKwsVoNZuarQFRQuJRf9ry7tJJEelOdYUO/+v7Rq8EPaJHcwh8aOgmHDeqVY0U1GsiU53X
|
||||
XweejELtZProBRRy7YasoxXjCigFNjOEF0AF4MsyFy0b6J8e+HR6+ncAs+rDNN9oXMZel7laUuAy
|
||||
XD8iU834dMgHOkcBEhbaZjf5VZ8zmXSXh3lJZ9zAqudOK0tBq/I+MWPKx5rvMqv+IOOVPqeY+QCO
|
||||
lMWloSrmK+qIIsXipXom9wuMlI3dXWkZCKGNgye6v6AbkUAcfaqzARGqiakKyEYW7fSvrSDxvYVM
|
||||
dlIryOIRdEwKS7U2TJsrnc6GCGKKnxHh1NHhdKp2Yo6xHhswvsAenjGAEkxrPUX0ppvAkYVX9qDh
|
||||
jwBD0RjaCpRcwxx9oPjo8nN8tVf8WYJxOB0QcXLWpS51AXfEAbfwoLJS63mdLOAMjVGwxW5vqzcb
|
||||
HLCTw0ZPrPjbwFkMJbz67B/XpMPZy2maf2nwdg6cdHgsNb+5Ut3Y9ng0MMoxNzzNzQS103y4OyBA
|
||||
8JYyLgaLHOoKmIMRGODMQtwLZ/jHYSf44X129Eq4ZSU+cv/d3Wgygmwd5OZ3f/Qkhdk8IWCt+HNz
|
||||
eprrM9DQjWQZbjyqkujHXlp1CauZwE6omxJ1z2oSAa8ZUOcbNEi4BrIH+Dk81cnnU+ZteIKstGCX
|
||||
n3nvhsz2cCLSPc+E/R1fJDJiUeSTcpHwIDxkV2vcZT59En2OkNdIy9J7DCmP91elMjOu4nf6Pi7T
|
||||
XcRX0n5IlkKhR/kPtGyFu5jhLnRnBfIAHIYbAAo9b57/4cmlaMykL0VKMIS7Ee8LaYLjnuczc5EX
|
||||
Xtkem30IXGBbDtBCi7SBQ3f9hKZqP77iv8P6mwM93hjh7s+gZVyAHmFuuoEE2M9Q+rI/CSnCMGuy
|
||||
GTEbsmICQKOxqW2t1F/wufELT+Tz72Tc13g8Hqp0ES46cqzBf4/HvdsHjbXShBuYUirIIkWyBtyn
|
||||
m+jWaJBF84xa2GzA3KrjG8JsqGeu3Ftqa8ui/sD/gG5HPsLcr2o1rJM7TfIgbWBFq+tU3SDDabBx
|
||||
kd8FaOg3evZuBQE99GNLVgaozPOTt7d4NeqlfsWnyCtgWaEO83LqAzxZpq23XwGdI7IgjQGt5i+l
|
||||
x025q6WnJBixe+KH/VkoOOuFNOyAPWZzw4Ecfyvb20rs4d4IbPfONNjnd9Gq70rqJvsD8mtm9MJV
|
||||
2T3n+IouDmtQ/9SZW0OQynFv/gOOIfZLCHIoG8Gjxwci/5om15c+coE8MLzjvkvWibVAH2cCSccP
|
||||
HyTNHT44r/NEs04DgTuxluhivbtevtVSEBinQNtTYyXk/AoUHIywHHe3M4hs9Z+VUZsjvoTaqrBb
|
||||
wKw55iU76pnbjuyT/YKBsR6cXrIuYV4/Y3DELxe61XYeLhrx1P9BOGPy+ZLGBkcmsPKYCyNMFteN
|
||||
DznfH/+dGN3z2HhnatAuS/tTtrZncMBX6OHfAH9+8NE66XrjCoHNXykVbNsyEyx77a+jNVaH2NtN
|
||||
Kv9YB8etHxHw/3e71djAYtdelBoicgTw6ChsxOoxsGCCnLAo5QRKTUA5/C12vbOjzAh0urBOQxCN
|
||||
8oe7kK9UnYCLr8ugczWLu2p+TE5DxeBQlAwVL6NKw8UWxYH/A4fI1F1EHdrzC59GIgNz2gRvySd3
|
||||
QGA1UWFpiQDE0xtfs62NXptvYs/aowduC6J9xsMFR0LcPnW5WjEJ+/c4oPasc550I+P3Ofm66eUB
|
||||
g+/PvsOD733Sl1vOOPFY36kxaMUYO9y8rYScVMIz4Av1BaDG932/6z/osEdTQp9+PnwpMPpxHmRV
|
||||
z6PRFNC0mfZ3O1lp3pF7rqLzgs8tN2ACEBMa8U31TJNKhhklqaPSj/vSLseMsJe0V2P2aGb+7oY0
|
||||
eF4emSMNuWzBIZ1Olgkp+EvKL+Dden6p18IBZd98jJirI0U2GSyrdeL9ohIbxP5ImtFAZOZp8cTx
|
||||
Q8i1KPajU2BEaBJHKUv1tR6wfAchC78OObJmF7n5Snuix0MLEEUa3TZqbDL4K8uMe31BN2sFKpgS
|
||||
5C85szOfpXCr2U/Vih7ThHlJZC07kmA0581318a2X2dqzIkNSttCbxB6T0jf7B7K4wpUzVKXZ3BE
|
||||
O10NYQj4jofrk02aRI0n06aHWSHsFZQFSPlGhk0jbKT0x7fxocqrw5QzDLNkhkAJ2b6m/poatPhK
|
||||
w2M45oehah5+KDQE22hkjBaxuuypkzSOs4/jeFChzPlP6JCEjNLc71YiPTuNxoySYmGTmU6+ro7l
|
||||
Q8vD89Onzfa3xTEaI6W6VW4vHy2mmeHgEN1aycOt57wXkTdADXvlJ4HJo5Rxph+1AuyDFe6/8K0F
|
||||
LG5+lQQim5YjFG7/ujR/DJ1h+5Xz3pOez/BZ4NjY23MHX0Og4izbffcyFu2MjnKDR6Ym1a5rizdZ
|
||||
BmNQaXzv5G+ljGQxMl+dn3U4cH06Ytqh8uKMuEOX/fqiMmqMQVSOofYKzJ44NFyM+iO2AZFUSilL
|
||||
BgOfSCuc6XZklqDE+JuC9kwIcWXGQXANzqpyJbU2vczZEM1DvFCrW5z1lWzIAMjpWyYZ1BiC4fBv
|
||||
l8kwOrcYzPOzTOhO5bMYZpUoWrpQZNRf8T4Gkq+GwAFNDhJ9/mk7ywAJIMAQCXE1mQR6LsTrdyI0
|
||||
F6+hJAizIG48Z3Ee/uvTIpzYJX0wEAuVrjTZRSzbyx2BDUxz5921JjCV3WrFR8oc9fH81SRz5JsW
|
||||
zD9Y4/OIbfLInO4N5NFAsM+Yxmk2CGs+KexqYUuF1MZhPrOWYGWJe9FiIMTd+Nejk9hvXeIbvtYW
|
||||
Er2q+oOvXC+TGzgkl37AQRurGOGT3RLcAqlq8woGTOA5QrX5ra8XyeAyByZQHIQjs6x24pqrfD5W
|
||||
2VvYA12K4/CDdrODVFkeU7iZOvCyWcoSgjy/NuWaFXLIGh95dn/WrbI9XVh4VRLc5zpvvA5lgjW1
|
||||
QX0imhzqlaxtnb8uFddGJZUBZe9DTG/ZuEDVknVqv6P/hgUGLMDZK+3nv+hBdVJKfUDOtg6iYmAA
|
||||
6QrgZDu16PWp2buBRAMUj4ktBh//jSl6h4BwKUHR3kiNh1/4Cnd9/wINx7cDK4lUtcg=
|
||||
`pragma protect end_protected
|
||||
+1241
File diff suppressed because it is too large
Load Diff
+104
@@ -0,0 +1,104 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2011/04/26
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* General functions used by other Labtools IP cores. Functions will
|
||||
* be added as needed.
|
||||
*
|
||||
*Notes:
|
||||
* Include the file inside the Verilog module after the module and port
|
||||
* section. Do not include at the top of the module.
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
`include "ltlib_v1_0_0_ver.vh"
|
||||
|
||||
function integer clogb2;
|
||||
input integer depth;
|
||||
integer d;
|
||||
begin
|
||||
if (depth == 0)
|
||||
clogb2 = 1;
|
||||
else
|
||||
begin
|
||||
d = depth;
|
||||
for (clogb2=0; d > 0; clogb2 = clogb2+1)
|
||||
d = d >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function string_contains;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] familyName;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] expectedName;
|
||||
input integer expectedLength;
|
||||
integer i;
|
||||
integer j;
|
||||
reg temp_contain;
|
||||
begin
|
||||
string_contains = 1;
|
||||
temp_contain = 0;
|
||||
for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)
|
||||
begin
|
||||
if (familyName[(8*i)+:8] == expectedName[0+:8])
|
||||
begin
|
||||
temp_contain = 1;
|
||||
for (j=0; j<expectedLength; j=j+1)
|
||||
begin
|
||||
if (familyName[((8*i)+(8*j))+:8] != expectedName[(8*j)+:8])
|
||||
begin
|
||||
temp_contain = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if (temp_contain == 1)
|
||||
begin
|
||||
string_contains = 1;
|
||||
i = `FAMILY_NAME_LENGTH;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_bscane2;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_bscane2 = 1;
|
||||
else
|
||||
supports_bscane2 = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_bufr;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_bufr = 1;
|
||||
else
|
||||
supports_series7_bufr = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_startup;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_startup = 1;
|
||||
else
|
||||
supports_series7_startup = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
+7910
File diff suppressed because it is too large
Load Diff
+1045
File diff suppressed because it is too large
Load Diff
+124
@@ -0,0 +1,124 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*******************************************************************************
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2011/10/14
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Verilog functions required by ila_lib
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
function integer size_of_data;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
integer i;
|
||||
begin
|
||||
size_of_data = match_width_string[0+:16]+1;
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
if (match_tpid_string[(16*(i))+:16] > match_tpid_string[(16*(i-1))+:16])
|
||||
size_of_data = size_of_data + match_width_string[(match_tpid_string[(i*`GC_TRIG_TYPEID_VEC_W)+:16]*16)+:16]+1;
|
||||
end
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
function integer match_units_count;
|
||||
input integer num_probes;
|
||||
input [`GC_MU_CNT_VEC_ARRAY_W-1:0] match_cnt_string;
|
||||
integer i;
|
||||
begin
|
||||
match_units_count = match_cnt_string[0+:4]+1;
|
||||
for (i=1; i<num_probes; i=i+1)
|
||||
begin
|
||||
match_units_count = match_units_count + match_cnt_string[(4*i)+:4]+1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [255:0] match_tpid;
|
||||
// Cast as bit16. Replace with null_value if not qualified.
|
||||
input [15:0] arg_ddr;
|
||||
input [15:0] arg;
|
||||
input qual;
|
||||
input [15:0] val;
|
||||
integer i;
|
||||
integer j;
|
||||
integer arg_temp;
|
||||
begin
|
||||
arg_temp = qual ? arg_ddr : arg;
|
||||
|
||||
for (i=0; i<arg_temp; i=i+1)
|
||||
begin
|
||||
match_tpid[i*16+:16] = val[15:0];
|
||||
end
|
||||
for (j=arg_temp; j<16; j=j+1)
|
||||
begin
|
||||
match_tpid[j*16+:16] = 16'h0000;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer match_units_count_en;
|
||||
input integer num_mu;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
//match_units_count = match_cnt_string[0+:2]+1;
|
||||
match_units_count_en = 0;
|
||||
for (i=0; i<num_mu; i=i+1)
|
||||
begin
|
||||
if (is_string[i] == 1'b1) begin
|
||||
match_units_count_en = match_units_count_en + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer size_of_data_less;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
if (is_string[0] == 1'b1) begin
|
||||
size_of_data_less = match_width_string[0+:16]+1;
|
||||
end else begin
|
||||
size_of_data_less = 0 ;
|
||||
end
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
if (is_string[i] == 1'b1) begin
|
||||
size_of_data_less = size_of_data_less + match_width_string[i*16+:16]+1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer size_of_data_full;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
size_of_data_full = match_width_string[0+:16]+1;
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
size_of_data_full = size_of_data_full + match_width_string[i*16+:16]+1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
+8410
File diff suppressed because it is too large
Load Diff
+3148
File diff suppressed because it is too large
Load Diff
+122
@@ -0,0 +1,122 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*******************************************************************************
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2001/08/10
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* ILA constant values library
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
//--
|
||||
//-- ILA Pro command types:
|
||||
//--
|
||||
//-- These command values match those found in the documentation. The
|
||||
//-- CONTROL bus bit offset can be derived by adding CONTROL_OFFSET to
|
||||
//-- these values.
|
||||
//--
|
||||
`define READ_STATIC_STAT_CMD 0
|
||||
`define READ_DYNAMIC_STAT_CMD 1
|
||||
`define READ_DATA_CMD 2
|
||||
`define READ_TSTAMP_CMD 3
|
||||
`define WRITE_TRIG_SETUP_CMD 4
|
||||
`define WRITE_CAP_CTRL_SETUP_CMD 5
|
||||
`define WRITE_ENABLE_EXTCAP_CMD 6
|
||||
`define WRITE_DISABLE_EXTCAP_CMD 7
|
||||
`define WRITE_ARM_CMD 8
|
||||
`define WRITE_HALT_CMD 9
|
||||
`define WRITE_RESET_CMD 10
|
||||
`define WRITE_RESET_DCM_CMD 11
|
||||
`define RESERVED_0C_CMD 12
|
||||
`define RESERVED_0D_CMD 13
|
||||
`define RESERVED_0E_CMD 14
|
||||
`define WRITE_TSEQ_TRIGOUT 15
|
||||
`define WRITE_M0_SETUP_CMD 16
|
||||
`define WRITE_M1_SETUP_CMD 17
|
||||
`define WRITE_M2_SETUP_CMD 18
|
||||
`define WRITE_M3_SETUP_CMD 19
|
||||
`define WRITE_M4_SETUP_CMD 20
|
||||
`define WRITE_M5_SETUP_CMD 21
|
||||
`define WRITE_M6_SETUP_CMD 22
|
||||
`define WRITE_M7_SETUP_CMD 23
|
||||
`define WRITE_M8_SETUP_CMD 24
|
||||
`define WRITE_M9_SETUP_CMD 25
|
||||
`define WRITE_M10_SETUP_CMD 26
|
||||
`define WRITE_M11_SETUP_CMD 27
|
||||
`define WRITE_M12_SETUP_CMD 28
|
||||
`define WRITE_M13_SETUP_CMD 29
|
||||
`define WRITE_M14_SETUP_CMD 30
|
||||
`define WRITE_M15_SETUP_CMD 31
|
||||
|
||||
`define CONTROL_CMD_OFFSET 3
|
||||
|
||||
`define CFG_CLK_BIT 0
|
||||
`define CFG_DIN_BIT 1
|
||||
`define UNUSED_BIT 2
|
||||
`define CFG_DOUT_BIT 3
|
||||
`define READ_STATIC_STAT_CMD_BIT `READ_STATIC_STAT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_DYNAMIC_STAT_CMD_BIT `READ_DYNAMIC_STAT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_DATA_CMD_BIT `READ_DATA_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_TSTAMP_CMD_BIT `READ_TSTAMP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_TRIG_SETUP_CMD_BIT `WRITE_TRIG_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_CAP_CTRL_SETUP_CMD_BIT `WRITE_CAP_CTRL_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_ENABLE_EXTCAP_CMD_BIT `WRITE_ENABLE_EXTCAP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_DISABLE_EXTCAP_CMD_BIT `WRITE_DISABLE_EXTCAP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_ARM_CMD_BIT `WRITE_ARM_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_HALT_CMD_BIT `WRITE_HALT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_RESET_CMD_BIT `WRITE_RESET_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_RESET_DCM_CMD_BIT `WRITE_RESET_DCM_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0C_CMD_BIT `RESERVED_0C_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0D_CMD_BIT `RESERVED_0D_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0E_CMD_BIT `RESERVED_0E_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_TSEQ_TRIGOUT_BIT `WRITE_TSEQ_TRIGOUT + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M0_SETUP_CMD_BIT `WRITE_M0_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M1_SETUP_CMD_BIT `WRITE_M1_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M2_SETUP_CMD_BIT `WRITE_M2_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M3_SETUP_CMD_BIT `WRITE_M3_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M4_SETUP_CMD_BIT `WRITE_M4_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M5_SETUP_CMD_BIT `WRITE_M5_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M6_SETUP_CMD_BIT `WRITE_M6_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M7_SETUP_CMD_BIT `WRITE_M7_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M8_SETUP_CMD_BIT `WRITE_M8_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M9_SETUP_CMD_BIT `WRITE_M9_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M10_SETUP_CMD_BIT `WRITE_M10_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M11_SETUP_CMD_BIT `WRITE_M11_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M12_SETUP_CMD_BIT `WRITE_M12_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M13_SETUP_CMD_BIT `WRITE_M13_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M14_SETUP_CMD_BIT `WRITE_M14_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M15_SETUP_CMD_BIT `WRITE_M15_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
|
||||
//--
|
||||
//-- Delay of data due to trigger delay
|
||||
//--
|
||||
`define ILA_PRO_DATA_DELAY 9
|
||||
//--constant ILA_PRO_DATA_DELAY : integer := 8;
|
||||
|
||||
//-- Width of vector used to encode each Trigger Width value (see ila_core)
|
||||
`define GC_MAX_NUM_MU 1024
|
||||
`define GC_TRIG_WIDTH_VEC_W 16
|
||||
`define GC_TRIG_WIDTH_VEC_ARRAY_W `GC_TRIG_WIDTH_VEC_W*`GC_MAX_NUM_MU
|
||||
`define GC_TRIG_TYPEID_VEC_W 16
|
||||
`define GC_TRIG_TYPEID_VEC_ARRAY_W `GC_TRIG_TYPEID_VEC_W*`GC_MAX_NUM_MU
|
||||
`define GC_MU_CNT_VEC_W 4
|
||||
`define GC_MU_CNT_VEC_ARRAY_W `GC_MU_CNT_VEC_W*`GC_MAX_NUM_MU
|
||||
|
||||
//-- Width of vector used to encode each Trigger Width value (see ila_core)
|
||||
`define GC_TRIG_TYPE_ID_W 15
|
||||
|
||||
|
||||
//-- Static Status Width
|
||||
`define GC_STATIC_STAT_W 672
|
||||
|
||||
|
||||
+193171
File diff suppressed because it is too large
Load Diff
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+491
@@ -0,0 +1,491 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_15[31:0],bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
|
||||
+638
@@ -0,0 +1,638 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output update_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output capture_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output reset_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output runtest_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tms_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tck_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tdi_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output sel_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output shift_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output drck_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)input tdo_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output update_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output capture_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output reset_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output runtest_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tms_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tck_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tdi_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output sel_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output shift_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output drck_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)input tdo_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output update_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output capture_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output reset_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output runtest_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tms_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tck_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tdi_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output sel_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output shift_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output drck_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)input tdo_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output update_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output capture_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output reset_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output runtest_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tms_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tck_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tdi_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output sel_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output shift_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output drck_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)input tdo_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output update_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output capture_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output reset_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output runtest_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tms_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tck_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tdi_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output sel_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output shift_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output drck_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)input tdo_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output update_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output capture_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output reset_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output runtest_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tms_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tck_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tdi_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output sel_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output shift_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output drck_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)input tdo_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output update_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output capture_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output reset_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output runtest_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tms_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tck_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tdi_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output sel_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output shift_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output drck_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)input tdo_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output update_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output capture_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output reset_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output runtest_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tms_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tck_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tdi_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output sel_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output shift_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output drck_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)input tdo_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output update_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output capture_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output reset_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output runtest_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tms_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tck_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tdi_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output sel_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output shift_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output drck_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)input tdo_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output update_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output capture_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output reset_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output runtest_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tms_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tck_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tdi_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output sel_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output shift_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output drck_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)input tdo_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output update_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output capture_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output reset_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output runtest_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tms_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tck_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tdi_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output sel_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output shift_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output drck_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)input tdo_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output update_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output capture_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output reset_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output runtest_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tms_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tck_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tdi_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output sel_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output shift_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output drck_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)input tdo_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output update_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output capture_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output reset_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output runtest_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tms_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tck_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tdi_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output sel_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output shift_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output drck_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)input tdo_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output update_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output capture_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output reset_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output runtest_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tms_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tck_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tdi_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output sel_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output shift_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output drck_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)input tdo_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output update_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output capture_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output reset_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output runtest_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tms_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tck_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tdi_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output sel_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output shift_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output drck_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)input tdo_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output update_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output capture_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output reset_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output runtest_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tms_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tck_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tdi_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output sel_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output shift_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output drck_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)input tdo_15,
|
||||
+491
@@ -0,0 +1,491 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_15[31:0],bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output bscanid_en_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output bscanid_en_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output bscanid_en_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output bscanid_en_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output bscanid_en_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output bscanid_en_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output bscanid_en_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output bscanid_en_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output bscanid_en_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output bscanid_en_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output bscanid_en_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output bscanid_en_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output bscanid_en_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output bscanid_en_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output bscanid_en_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output bscanid_en_15,
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)input [31:0] bscanid_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)input [31:0] bscanid_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)input [31:0] bscanid_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)input [31:0] bscanid_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)input [31:0] bscanid_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)input [31:0] bscanid_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)input [31:0] bscanid_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)input [31:0] bscanid_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)input [31:0] bscanid_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)input [31:0] bscanid_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)input [31:0] bscanid_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)input [31:0] bscanid_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)input [31:0] bscanid_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)input [31:0] bscanid_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)input [31:0] bscanid_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)input [31:0] bscanid_15,
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define GC_XSDB_MSI_SL_SEL_WIDTH 8 /* Slave Select Width */
|
||||
`define GC_XSDB_MSI_ADDR_WIDTH 17 /* Address Width */
|
||||
`define GC_XSDB_MSI_BRST_WD_LEN_WIDTH 17
|
||||
`define GC_XSDB_MSI_DATA_WIDTH 16 /* Data Width */
|
||||
`define GC_XSDB_MSI_BRST_CNT_WIDTH 16 /* Burst Count Width */
|
||||
`define GC_XSDB_S_IPORT_WIDTH 37 /* Slave Port input interface width */
|
||||
|
||||
`define GC_XSDB_S_OPORT_WIDTH 17 /* Slave Port output interface width */
|
||||
|
||||
`define GC_XSDB_S_ADDR_WIDTH `GC_XSDB_MSI_ADDR_WIDTH /* Slave Addr width */
|
||||
`define GC_XSDB_S_DATA_WIDTH `GC_XSDB_MSI_DATA_WIDTH /* Slave Data width */
|
||||
|
||||
`define GC_IPORT_RST_IDX 0
|
||||
`define GC_IPORT_DCLK_IDX 1
|
||||
`define GC_IPORT_DEN_IDX 2
|
||||
`define GC_IPORT_DWE_IDX 3
|
||||
`define GC_IPORT_DADDR_IDX 4
|
||||
`define GC_IPORT_DI_IDX `GC_IPORT_DADDR_IDX+`GC_XSDB_S_ADDR_WIDTH
|
||||
`define GC_OPORT_RDY_IDX 0
|
||||
`define GC_OPORT_DO_IDX 1
|
||||
|
||||
`define GC_ICN_CTL_WIDTH 36
|
||||
`define GC_ICN_CMD4_WIDTH 3 + `GC_XSDB_MSI_SL_SEL_WIDTH+ `GC_XSDB_MSI_BRST_WD_LEN_WIDTH
|
||||
`define GC_ICN_CMD5_WIDTH 1 + `GC_XSDB_MSI_ADDR_WIDTH
|
||||
`define GC_ICN_CMD6_WIDTH `GC_XSDB_MSI_DATA_WIDTH
|
||||
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define TARGET_HIGH_INDEX 15
|
||||
`define TARGET_CORE_ID_HIGH_INDEX 15
|
||||
`define TARGET_CORE_ID_LOW_INDEX 12
|
||||
`define TARGET_COMMAND_HIGH_INDEX 11
|
||||
`define TARGET_COMMAND_LOW_INDEX 8
|
||||
`define TARGET_COMMAND_GROUP_HIGH_INDEX 7
|
||||
`define TARGET_COMMAND_GROUP_LOW_INDEX 6
|
||||
`define TARGET_LOW_INDEX 6
|
||||
|
||||
`define TARGET_CORE_ID_WIDTH `TARGET_CORE_ID_HIGH_INDEX - `TARGET_CORE_ID_LOW_INDEX + 1
|
||||
`define TARGET_COMMAND_WIDTH `TARGET_COMMAND_HIGH_INDEX - `TARGET_COMMAND_LOW_INDEX + 1
|
||||
|
||||
`define ICON_READ_STAT_CMD 0
|
||||
|
||||
|
||||
+192
@@ -0,0 +1,192 @@
|
||||
.update_0 (update_0),
|
||||
.capture_0 (capture_0),
|
||||
.reset_0 (reset_0),
|
||||
.runtest_0 (runtest_0),
|
||||
.tms_0 (tms_0),
|
||||
.tck_0 (tck_0),
|
||||
.tdi_0 (tdi_0),
|
||||
.sel_0 (sel_0),
|
||||
.shift_0 (shift_0),
|
||||
.drck_0 (drck_0),
|
||||
.tdo_0 (tdo_0),
|
||||
.bscanid_en_0 (bscanid_en_0),
|
||||
.update_1 (update_1),
|
||||
.capture_1 (capture_1),
|
||||
.reset_1 (reset_1),
|
||||
.runtest_1 (runtest_1),
|
||||
.tms_1 (tms_1),
|
||||
.tck_1 (tck_1),
|
||||
.tdi_1 (tdi_1),
|
||||
.sel_1 (sel_1),
|
||||
.shift_1 (shift_1),
|
||||
.drck_1 (drck_1),
|
||||
.tdo_1 (tdo_1),
|
||||
.bscanid_en_1 (bscanid_en_1),
|
||||
.update_2 (update_2),
|
||||
.capture_2 (capture_2),
|
||||
.reset_2 (reset_2),
|
||||
.runtest_2 (runtest_2),
|
||||
.tms_2 (tms_2),
|
||||
.tck_2 (tck_2),
|
||||
.tdi_2 (tdi_2),
|
||||
.sel_2 (sel_2),
|
||||
.shift_2 (shift_2),
|
||||
.drck_2 (drck_2),
|
||||
.tdo_2 (tdo_2),
|
||||
.bscanid_en_2 (bscanid_en_2),
|
||||
.update_3 (update_3),
|
||||
.capture_3 (capture_3),
|
||||
.reset_3 (reset_3),
|
||||
.runtest_3 (runtest_3),
|
||||
.tms_3 (tms_3),
|
||||
.tck_3 (tck_3),
|
||||
.tdi_3 (tdi_3),
|
||||
.sel_3 (sel_3),
|
||||
.shift_3 (shift_3),
|
||||
.drck_3 (drck_3),
|
||||
.tdo_3 (tdo_3),
|
||||
.bscanid_en_3 (bscanid_en_3),
|
||||
.update_4 (update_4),
|
||||
.capture_4 (capture_4),
|
||||
.reset_4 (reset_4),
|
||||
.runtest_4 (runtest_4),
|
||||
.tms_4 (tms_4),
|
||||
.tck_4 (tck_4),
|
||||
.tdi_4 (tdi_4),
|
||||
.sel_4 (sel_4),
|
||||
.shift_4 (shift_4),
|
||||
.drck_4 (drck_4),
|
||||
.tdo_4 (tdo_4),
|
||||
.bscanid_en_4 (bscanid_en_4),
|
||||
.update_5 (update_5),
|
||||
.capture_5 (capture_5),
|
||||
.reset_5 (reset_5),
|
||||
.runtest_5 (runtest_5),
|
||||
.tms_5 (tms_5),
|
||||
.tck_5 (tck_5),
|
||||
.tdi_5 (tdi_5),
|
||||
.sel_5 (sel_5),
|
||||
.shift_5 (shift_5),
|
||||
.drck_5 (drck_5),
|
||||
.tdo_5 (tdo_5),
|
||||
.bscanid_en_5 (bscanid_en_5),
|
||||
.update_6 (update_6),
|
||||
.capture_6 (capture_6),
|
||||
.reset_6 (reset_6),
|
||||
.runtest_6 (runtest_6),
|
||||
.tms_6 (tms_6),
|
||||
.tck_6 (tck_6),
|
||||
.tdi_6 (tdi_6),
|
||||
.sel_6 (sel_6),
|
||||
.shift_6 (shift_6),
|
||||
.drck_6 (drck_6),
|
||||
.tdo_6 (tdo_6),
|
||||
.bscanid_en_6 (bscanid_en_6),
|
||||
.update_7 (update_7),
|
||||
.capture_7 (capture_7),
|
||||
.reset_7 (reset_7),
|
||||
.runtest_7 (runtest_7),
|
||||
.tms_7 (tms_7),
|
||||
.tck_7 (tck_7),
|
||||
.tdi_7 (tdi_7),
|
||||
.sel_7 (sel_7),
|
||||
.shift_7 (shift_7),
|
||||
.drck_7 (drck_7),
|
||||
.tdo_7 (tdo_7),
|
||||
.bscanid_en_7 (bscanid_en_7),
|
||||
.update_8 (update_8),
|
||||
.capture_8 (capture_8),
|
||||
.reset_8 (reset_8),
|
||||
.runtest_8 (runtest_8),
|
||||
.tms_8 (tms_8),
|
||||
.tck_8 (tck_8),
|
||||
.tdi_8 (tdi_8),
|
||||
.sel_8 (sel_8),
|
||||
.shift_8 (shift_8),
|
||||
.drck_8 (drck_8),
|
||||
.tdo_8 (tdo_8),
|
||||
.bscanid_en_8 (bscanid_en_8),
|
||||
.update_9 (update_9),
|
||||
.capture_9 (capture_9),
|
||||
.reset_9 (reset_9),
|
||||
.runtest_9 (runtest_9),
|
||||
.tms_9 (tms_9),
|
||||
.tck_9 (tck_9),
|
||||
.tdi_9 (tdi_9),
|
||||
.sel_9 (sel_9),
|
||||
.shift_9 (shift_9),
|
||||
.drck_9 (drck_9),
|
||||
.tdo_9 (tdo_9),
|
||||
.bscanid_en_9 (bscanid_en_9),
|
||||
.update_10 (update_10),
|
||||
.capture_10 (capture_10),
|
||||
.reset_10 (reset_10),
|
||||
.runtest_10 (runtest_10),
|
||||
.tms_10 (tms_10),
|
||||
.tck_10 (tck_10),
|
||||
.tdi_10 (tdi_10),
|
||||
.sel_10 (sel_10),
|
||||
.shift_10 (shift_10),
|
||||
.drck_10 (drck_10),
|
||||
.tdo_10 (tdo_10),
|
||||
.bscanid_en_10 (bscanid_en_10),
|
||||
.update_11 (update_11),
|
||||
.capture_11 (capture_11),
|
||||
.reset_11 (reset_11),
|
||||
.runtest_11 (runtest_11),
|
||||
.tms_11 (tms_11),
|
||||
.tck_11 (tck_11),
|
||||
.tdi_11 (tdi_11),
|
||||
.sel_11 (sel_11),
|
||||
.shift_11 (shift_11),
|
||||
.drck_11 (drck_11),
|
||||
.tdo_11 (tdo_11),
|
||||
.bscanid_en_11 (bscanid_en_11),
|
||||
.update_12 (update_12),
|
||||
.capture_12 (capture_12),
|
||||
.reset_12 (reset_12),
|
||||
.runtest_12 (runtest_12),
|
||||
.tms_12 (tms_12),
|
||||
.tck_12 (tck_12),
|
||||
.tdi_12 (tdi_12),
|
||||
.sel_12 (sel_12),
|
||||
.shift_12 (shift_12),
|
||||
.drck_12 (drck_12),
|
||||
.tdo_12 (tdo_12),
|
||||
.bscanid_en_12 (bscanid_en_12),
|
||||
.update_13 (update_13),
|
||||
.capture_13 (capture_13),
|
||||
.reset_13 (reset_13),
|
||||
.runtest_13 (runtest_13),
|
||||
.tms_13 (tms_13),
|
||||
.tck_13 (tck_13),
|
||||
.tdi_13 (tdi_13),
|
||||
.sel_13 (sel_13),
|
||||
.shift_13 (shift_13),
|
||||
.drck_13 (drck_13),
|
||||
.tdo_13 (tdo_13),
|
||||
.bscanid_en_13 (bscanid_en_13),
|
||||
.update_14 (update_14),
|
||||
.capture_14 (capture_14),
|
||||
.reset_14 (reset_14),
|
||||
.runtest_14 (runtest_14),
|
||||
.tms_14 (tms_14),
|
||||
.tck_14 (tck_14),
|
||||
.tdi_14 (tdi_14),
|
||||
.sel_14 (sel_14),
|
||||
.shift_14 (shift_14),
|
||||
.drck_14 (drck_14),
|
||||
.tdo_14 (tdo_14),
|
||||
.bscanid_en_14 (bscanid_en_14),
|
||||
.update_15 (update_15),
|
||||
.capture_15 (capture_15),
|
||||
.reset_15 (reset_15),
|
||||
.runtest_15 (runtest_15),
|
||||
.tms_15 (tms_15),
|
||||
.tck_15 (tck_15),
|
||||
.tdi_15 (tdi_15),
|
||||
.sel_15 (sel_15),
|
||||
.shift_15 (shift_15),
|
||||
.drck_15 (drck_15),
|
||||
.tdo_15 (tdo_15),
|
||||
.bscanid_en_15 (bscanid_en_15),
|
||||
+192
@@ -0,0 +1,192 @@
|
||||
.update_0 (update_0),
|
||||
.capture_0 (capture_0),
|
||||
.reset_0 (reset_0),
|
||||
.runtest_0 (runtest_0),
|
||||
.tms_0 (tms_0),
|
||||
.tck_0 (tck_0),
|
||||
.tdi_0 (tdi_0),
|
||||
.sel_0 (sel_0),
|
||||
.shift_0 (shift_0),
|
||||
.drck_0 (drck_0),
|
||||
.tdo_0 (tdo_0),
|
||||
.bscanid_0 (bscanid_0),
|
||||
.update_1 (update_1),
|
||||
.capture_1 (capture_1),
|
||||
.reset_1 (reset_1),
|
||||
.runtest_1 (runtest_1),
|
||||
.tms_1 (tms_1),
|
||||
.tck_1 (tck_1),
|
||||
.tdi_1 (tdi_1),
|
||||
.sel_1 (sel_1),
|
||||
.shift_1 (shift_1),
|
||||
.drck_1 (drck_1),
|
||||
.tdo_1 (tdo_1),
|
||||
.bscanid_1 (bscanid_1),
|
||||
.update_2 (update_2),
|
||||
.capture_2 (capture_2),
|
||||
.reset_2 (reset_2),
|
||||
.runtest_2 (runtest_2),
|
||||
.tms_2 (tms_2),
|
||||
.tck_2 (tck_2),
|
||||
.tdi_2 (tdi_2),
|
||||
.sel_2 (sel_2),
|
||||
.shift_2 (shift_2),
|
||||
.drck_2 (drck_2),
|
||||
.tdo_2 (tdo_2),
|
||||
.bscanid_2 (bscanid_2),
|
||||
.update_3 (update_3),
|
||||
.capture_3 (capture_3),
|
||||
.reset_3 (reset_3),
|
||||
.runtest_3 (runtest_3),
|
||||
.tms_3 (tms_3),
|
||||
.tck_3 (tck_3),
|
||||
.tdi_3 (tdi_3),
|
||||
.sel_3 (sel_3),
|
||||
.shift_3 (shift_3),
|
||||
.drck_3 (drck_3),
|
||||
.tdo_3 (tdo_3),
|
||||
.bscanid_3 (bscanid_3),
|
||||
.update_4 (update_4),
|
||||
.capture_4 (capture_4),
|
||||
.reset_4 (reset_4),
|
||||
.runtest_4 (runtest_4),
|
||||
.tms_4 (tms_4),
|
||||
.tck_4 (tck_4),
|
||||
.tdi_4 (tdi_4),
|
||||
.sel_4 (sel_4),
|
||||
.shift_4 (shift_4),
|
||||
.drck_4 (drck_4),
|
||||
.tdo_4 (tdo_4),
|
||||
.bscanid_4 (bscanid_4),
|
||||
.update_5 (update_5),
|
||||
.capture_5 (capture_5),
|
||||
.reset_5 (reset_5),
|
||||
.runtest_5 (runtest_5),
|
||||
.tms_5 (tms_5),
|
||||
.tck_5 (tck_5),
|
||||
.tdi_5 (tdi_5),
|
||||
.sel_5 (sel_5),
|
||||
.shift_5 (shift_5),
|
||||
.drck_5 (drck_5),
|
||||
.tdo_5 (tdo_5),
|
||||
.bscanid_5 (bscanid_5),
|
||||
.update_6 (update_6),
|
||||
.capture_6 (capture_6),
|
||||
.reset_6 (reset_6),
|
||||
.runtest_6 (runtest_6),
|
||||
.tms_6 (tms_6),
|
||||
.tck_6 (tck_6),
|
||||
.tdi_6 (tdi_6),
|
||||
.sel_6 (sel_6),
|
||||
.shift_6 (shift_6),
|
||||
.drck_6 (drck_6),
|
||||
.tdo_6 (tdo_6),
|
||||
.bscanid_6 (bscanid_6),
|
||||
.update_7 (update_7),
|
||||
.capture_7 (capture_7),
|
||||
.reset_7 (reset_7),
|
||||
.runtest_7 (runtest_7),
|
||||
.tms_7 (tms_7),
|
||||
.tck_7 (tck_7),
|
||||
.tdi_7 (tdi_7),
|
||||
.sel_7 (sel_7),
|
||||
.shift_7 (shift_7),
|
||||
.drck_7 (drck_7),
|
||||
.tdo_7 (tdo_7),
|
||||
.bscanid_7 (bscanid_7),
|
||||
.update_8 (update_8),
|
||||
.capture_8 (capture_8),
|
||||
.reset_8 (reset_8),
|
||||
.runtest_8 (runtest_8),
|
||||
.tms_8 (tms_8),
|
||||
.tck_8 (tck_8),
|
||||
.tdi_8 (tdi_8),
|
||||
.sel_8 (sel_8),
|
||||
.shift_8 (shift_8),
|
||||
.drck_8 (drck_8),
|
||||
.tdo_8 (tdo_8),
|
||||
.bscanid_8 (bscanid_8),
|
||||
.update_9 (update_9),
|
||||
.capture_9 (capture_9),
|
||||
.reset_9 (reset_9),
|
||||
.runtest_9 (runtest_9),
|
||||
.tms_9 (tms_9),
|
||||
.tck_9 (tck_9),
|
||||
.tdi_9 (tdi_9),
|
||||
.sel_9 (sel_9),
|
||||
.shift_9 (shift_9),
|
||||
.drck_9 (drck_9),
|
||||
.tdo_9 (tdo_9),
|
||||
.bscanid_9 (bscanid_9),
|
||||
.update_10 (update_10),
|
||||
.capture_10 (capture_10),
|
||||
.reset_10 (reset_10),
|
||||
.runtest_10 (runtest_10),
|
||||
.tms_10 (tms_10),
|
||||
.tck_10 (tck_10),
|
||||
.tdi_10 (tdi_10),
|
||||
.sel_10 (sel_10),
|
||||
.shift_10 (shift_10),
|
||||
.drck_10 (drck_10),
|
||||
.tdo_10 (tdo_10),
|
||||
.bscanid_10 (bscanid_10),
|
||||
.update_11 (update_11),
|
||||
.capture_11 (capture_11),
|
||||
.reset_11 (reset_11),
|
||||
.runtest_11 (runtest_11),
|
||||
.tms_11 (tms_11),
|
||||
.tck_11 (tck_11),
|
||||
.tdi_11 (tdi_11),
|
||||
.sel_11 (sel_11),
|
||||
.shift_11 (shift_11),
|
||||
.drck_11 (drck_11),
|
||||
.tdo_11 (tdo_11),
|
||||
.bscanid_11 (bscanid_11),
|
||||
.update_12 (update_12),
|
||||
.capture_12 (capture_12),
|
||||
.reset_12 (reset_12),
|
||||
.runtest_12 (runtest_12),
|
||||
.tms_12 (tms_12),
|
||||
.tck_12 (tck_12),
|
||||
.tdi_12 (tdi_12),
|
||||
.sel_12 (sel_12),
|
||||
.shift_12 (shift_12),
|
||||
.drck_12 (drck_12),
|
||||
.tdo_12 (tdo_12),
|
||||
.bscanid_12 (bscanid_12),
|
||||
.update_13 (update_13),
|
||||
.capture_13 (capture_13),
|
||||
.reset_13 (reset_13),
|
||||
.runtest_13 (runtest_13),
|
||||
.tms_13 (tms_13),
|
||||
.tck_13 (tck_13),
|
||||
.tdi_13 (tdi_13),
|
||||
.sel_13 (sel_13),
|
||||
.shift_13 (shift_13),
|
||||
.drck_13 (drck_13),
|
||||
.tdo_13 (tdo_13),
|
||||
.bscanid_13 (bscanid_13),
|
||||
.update_14 (update_14),
|
||||
.capture_14 (capture_14),
|
||||
.reset_14 (reset_14),
|
||||
.runtest_14 (runtest_14),
|
||||
.tms_14 (tms_14),
|
||||
.tck_14 (tck_14),
|
||||
.tdi_14 (tdi_14),
|
||||
.sel_14 (sel_14),
|
||||
.shift_14 (shift_14),
|
||||
.drck_14 (drck_14),
|
||||
.tdo_14 (tdo_14),
|
||||
.bscanid_14 (bscanid_14),
|
||||
.update_15 (update_15),
|
||||
.capture_15 (capture_15),
|
||||
.reset_15 (reset_15),
|
||||
.runtest_15 (runtest_15),
|
||||
.tms_15 (tms_15),
|
||||
.tck_15 (tck_15),
|
||||
.tdi_15 (tdi_15),
|
||||
.sel_15 (sel_15),
|
||||
.shift_15 (shift_15),
|
||||
.drck_15 (drck_15),
|
||||
.tdo_15 (tdo_15),
|
||||
.bscanid_15 (bscanid_15),
|
||||
+117
@@ -0,0 +1,117 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX6 "virtex6"
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
`define FAMILY_KINTEXU "kintexu"
|
||||
`define FAMILY_KINTEXUPLUS "kintexuplus"
|
||||
`define FAMILY_ARTIXUPLUS "artixuplus"
|
||||
`define FAMILY_AARTIXUPLUS "aartixuplus"
|
||||
`define FAMILY_VIRTEXU "virtexu"
|
||||
`define FAMILY_VIRTEXUPLUS "virtexuplus"
|
||||
`define FAMILY_VIRTEXUPLUSHBM "virtexuplusHBM"
|
||||
`define FAMILY_VIRTEXUPLUS58G "virtexuplus58g"
|
||||
`define FAMILY_ZYNQUPLUS "zynquplus"
|
||||
`define FAMILY_ZYNQUPLUSRFSOC "zynquplusRFSOC"
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
+512
@@ -0,0 +1,512 @@
|
||||
.sl_iport0_o (sl_iport0_o),
|
||||
.sl_iport1_o (sl_iport1_o),
|
||||
.sl_iport2_o (sl_iport2_o),
|
||||
.sl_iport3_o (sl_iport3_o),
|
||||
.sl_iport4_o (sl_iport4_o),
|
||||
.sl_iport5_o (sl_iport5_o),
|
||||
.sl_iport6_o (sl_iport6_o),
|
||||
.sl_iport7_o (sl_iport7_o),
|
||||
.sl_iport8_o (sl_iport8_o),
|
||||
.sl_iport9_o (sl_iport9_o),
|
||||
.sl_iport10_o (sl_iport10_o),
|
||||
.sl_iport11_o (sl_iport11_o),
|
||||
.sl_iport12_o (sl_iport12_o),
|
||||
.sl_iport13_o (sl_iport13_o),
|
||||
.sl_iport14_o (sl_iport14_o),
|
||||
.sl_iport15_o (sl_iport15_o),
|
||||
.sl_iport16_o (sl_iport16_o),
|
||||
.sl_iport17_o (sl_iport17_o),
|
||||
.sl_iport18_o (sl_iport18_o),
|
||||
.sl_iport19_o (sl_iport19_o),
|
||||
.sl_iport20_o (sl_iport20_o),
|
||||
.sl_iport21_o (sl_iport21_o),
|
||||
.sl_iport22_o (sl_iport22_o),
|
||||
.sl_iport23_o (sl_iport23_o),
|
||||
.sl_iport24_o (sl_iport24_o),
|
||||
.sl_iport25_o (sl_iport25_o),
|
||||
.sl_iport26_o (sl_iport26_o),
|
||||
.sl_iport27_o (sl_iport27_o),
|
||||
.sl_iport28_o (sl_iport28_o),
|
||||
.sl_iport29_o (sl_iport29_o),
|
||||
.sl_iport30_o (sl_iport30_o),
|
||||
.sl_iport31_o (sl_iport31_o),
|
||||
.sl_iport32_o (sl_iport32_o),
|
||||
.sl_iport33_o (sl_iport33_o),
|
||||
.sl_iport34_o (sl_iport34_o),
|
||||
.sl_iport35_o (sl_iport35_o),
|
||||
.sl_iport36_o (sl_iport36_o),
|
||||
.sl_iport37_o (sl_iport37_o),
|
||||
.sl_iport38_o (sl_iport38_o),
|
||||
.sl_iport39_o (sl_iport39_o),
|
||||
.sl_iport40_o (sl_iport40_o),
|
||||
.sl_iport41_o (sl_iport41_o),
|
||||
.sl_iport42_o (sl_iport42_o),
|
||||
.sl_iport43_o (sl_iport43_o),
|
||||
.sl_iport44_o (sl_iport44_o),
|
||||
.sl_iport45_o (sl_iport45_o),
|
||||
.sl_iport46_o (sl_iport46_o),
|
||||
.sl_iport47_o (sl_iport47_o),
|
||||
.sl_iport48_o (sl_iport48_o),
|
||||
.sl_iport49_o (sl_iport49_o),
|
||||
.sl_iport50_o (sl_iport50_o),
|
||||
.sl_iport51_o (sl_iport51_o),
|
||||
.sl_iport52_o (sl_iport52_o),
|
||||
.sl_iport53_o (sl_iport53_o),
|
||||
.sl_iport54_o (sl_iport54_o),
|
||||
.sl_iport55_o (sl_iport55_o),
|
||||
.sl_iport56_o (sl_iport56_o),
|
||||
.sl_iport57_o (sl_iport57_o),
|
||||
.sl_iport58_o (sl_iport58_o),
|
||||
.sl_iport59_o (sl_iport59_o),
|
||||
.sl_iport60_o (sl_iport60_o),
|
||||
.sl_iport61_o (sl_iport61_o),
|
||||
.sl_iport62_o (sl_iport62_o),
|
||||
.sl_iport63_o (sl_iport63_o),
|
||||
.sl_iport64_o (sl_iport64_o),
|
||||
.sl_iport65_o (sl_iport65_o),
|
||||
.sl_iport66_o (sl_iport66_o),
|
||||
.sl_iport67_o (sl_iport67_o),
|
||||
.sl_iport68_o (sl_iport68_o),
|
||||
.sl_iport69_o (sl_iport69_o),
|
||||
.sl_iport70_o (sl_iport70_o),
|
||||
.sl_iport71_o (sl_iport71_o),
|
||||
.sl_iport72_o (sl_iport72_o),
|
||||
.sl_iport73_o (sl_iport73_o),
|
||||
.sl_iport74_o (sl_iport74_o),
|
||||
.sl_iport75_o (sl_iport75_o),
|
||||
.sl_iport76_o (sl_iport76_o),
|
||||
.sl_iport77_o (sl_iport77_o),
|
||||
.sl_iport78_o (sl_iport78_o),
|
||||
.sl_iport79_o (sl_iport79_o),
|
||||
.sl_iport80_o (sl_iport80_o),
|
||||
.sl_iport81_o (sl_iport81_o),
|
||||
.sl_iport82_o (sl_iport82_o),
|
||||
.sl_iport83_o (sl_iport83_o),
|
||||
.sl_iport84_o (sl_iport84_o),
|
||||
.sl_iport85_o (sl_iport85_o),
|
||||
.sl_iport86_o (sl_iport86_o),
|
||||
.sl_iport87_o (sl_iport87_o),
|
||||
.sl_iport88_o (sl_iport88_o),
|
||||
.sl_iport89_o (sl_iport89_o),
|
||||
.sl_iport90_o (sl_iport90_o),
|
||||
.sl_iport91_o (sl_iport91_o),
|
||||
.sl_iport92_o (sl_iport92_o),
|
||||
.sl_iport93_o (sl_iport93_o),
|
||||
.sl_iport94_o (sl_iport94_o),
|
||||
.sl_iport95_o (sl_iport95_o),
|
||||
.sl_iport96_o (sl_iport96_o),
|
||||
.sl_iport97_o (sl_iport97_o),
|
||||
.sl_iport98_o (sl_iport98_o),
|
||||
.sl_iport99_o (sl_iport99_o),
|
||||
.sl_iport100_o (sl_iport100_o),
|
||||
.sl_iport101_o (sl_iport101_o),
|
||||
.sl_iport102_o (sl_iport102_o),
|
||||
.sl_iport103_o (sl_iport103_o),
|
||||
.sl_iport104_o (sl_iport104_o),
|
||||
.sl_iport105_o (sl_iport105_o),
|
||||
.sl_iport106_o (sl_iport106_o),
|
||||
.sl_iport107_o (sl_iport107_o),
|
||||
.sl_iport108_o (sl_iport108_o),
|
||||
.sl_iport109_o (sl_iport109_o),
|
||||
.sl_iport110_o (sl_iport110_o),
|
||||
.sl_iport111_o (sl_iport111_o),
|
||||
.sl_iport112_o (sl_iport112_o),
|
||||
.sl_iport113_o (sl_iport113_o),
|
||||
.sl_iport114_o (sl_iport114_o),
|
||||
.sl_iport115_o (sl_iport115_o),
|
||||
.sl_iport116_o (sl_iport116_o),
|
||||
.sl_iport117_o (sl_iport117_o),
|
||||
.sl_iport118_o (sl_iport118_o),
|
||||
.sl_iport119_o (sl_iport119_o),
|
||||
.sl_iport120_o (sl_iport120_o),
|
||||
.sl_iport121_o (sl_iport121_o),
|
||||
.sl_iport122_o (sl_iport122_o),
|
||||
.sl_iport123_o (sl_iport123_o),
|
||||
.sl_iport124_o (sl_iport124_o),
|
||||
.sl_iport125_o (sl_iport125_o),
|
||||
.sl_iport126_o (sl_iport126_o),
|
||||
.sl_iport127_o (sl_iport127_o),
|
||||
.sl_iport128_o (sl_iport128_o),
|
||||
.sl_iport129_o (sl_iport129_o),
|
||||
.sl_iport130_o (sl_iport130_o),
|
||||
.sl_iport131_o (sl_iport131_o),
|
||||
.sl_iport132_o (sl_iport132_o),
|
||||
.sl_iport133_o (sl_iport133_o),
|
||||
.sl_iport134_o (sl_iport134_o),
|
||||
.sl_iport135_o (sl_iport135_o),
|
||||
.sl_iport136_o (sl_iport136_o),
|
||||
.sl_iport137_o (sl_iport137_o),
|
||||
.sl_iport138_o (sl_iport138_o),
|
||||
.sl_iport139_o (sl_iport139_o),
|
||||
.sl_iport140_o (sl_iport140_o),
|
||||
.sl_iport141_o (sl_iport141_o),
|
||||
.sl_iport142_o (sl_iport142_o),
|
||||
.sl_iport143_o (sl_iport143_o),
|
||||
.sl_iport144_o (sl_iport144_o),
|
||||
.sl_iport145_o (sl_iport145_o),
|
||||
.sl_iport146_o (sl_iport146_o),
|
||||
.sl_iport147_o (sl_iport147_o),
|
||||
.sl_iport148_o (sl_iport148_o),
|
||||
.sl_iport149_o (sl_iport149_o),
|
||||
.sl_iport150_o (sl_iport150_o),
|
||||
.sl_iport151_o (sl_iport151_o),
|
||||
.sl_iport152_o (sl_iport152_o),
|
||||
.sl_iport153_o (sl_iport153_o),
|
||||
.sl_iport154_o (sl_iport154_o),
|
||||
.sl_iport155_o (sl_iport155_o),
|
||||
.sl_iport156_o (sl_iport156_o),
|
||||
.sl_iport157_o (sl_iport157_o),
|
||||
.sl_iport158_o (sl_iport158_o),
|
||||
.sl_iport159_o (sl_iport159_o),
|
||||
.sl_iport160_o (sl_iport160_o),
|
||||
.sl_iport161_o (sl_iport161_o),
|
||||
.sl_iport162_o (sl_iport162_o),
|
||||
.sl_iport163_o (sl_iport163_o),
|
||||
.sl_iport164_o (sl_iport164_o),
|
||||
.sl_iport165_o (sl_iport165_o),
|
||||
.sl_iport166_o (sl_iport166_o),
|
||||
.sl_iport167_o (sl_iport167_o),
|
||||
.sl_iport168_o (sl_iport168_o),
|
||||
.sl_iport169_o (sl_iport169_o),
|
||||
.sl_iport170_o (sl_iport170_o),
|
||||
.sl_iport171_o (sl_iport171_o),
|
||||
.sl_iport172_o (sl_iport172_o),
|
||||
.sl_iport173_o (sl_iport173_o),
|
||||
.sl_iport174_o (sl_iport174_o),
|
||||
.sl_iport175_o (sl_iport175_o),
|
||||
.sl_iport176_o (sl_iport176_o),
|
||||
.sl_iport177_o (sl_iport177_o),
|
||||
.sl_iport178_o (sl_iport178_o),
|
||||
.sl_iport179_o (sl_iport179_o),
|
||||
.sl_iport180_o (sl_iport180_o),
|
||||
.sl_iport181_o (sl_iport181_o),
|
||||
.sl_iport182_o (sl_iport182_o),
|
||||
.sl_iport183_o (sl_iport183_o),
|
||||
.sl_iport184_o (sl_iport184_o),
|
||||
.sl_iport185_o (sl_iport185_o),
|
||||
.sl_iport186_o (sl_iport186_o),
|
||||
.sl_iport187_o (sl_iport187_o),
|
||||
.sl_iport188_o (sl_iport188_o),
|
||||
.sl_iport189_o (sl_iport189_o),
|
||||
.sl_iport190_o (sl_iport190_o),
|
||||
.sl_iport191_o (sl_iport191_o),
|
||||
.sl_iport192_o (sl_iport192_o),
|
||||
.sl_iport193_o (sl_iport193_o),
|
||||
.sl_iport194_o (sl_iport194_o),
|
||||
.sl_iport195_o (sl_iport195_o),
|
||||
.sl_iport196_o (sl_iport196_o),
|
||||
.sl_iport197_o (sl_iport197_o),
|
||||
.sl_iport198_o (sl_iport198_o),
|
||||
.sl_iport199_o (sl_iport199_o),
|
||||
.sl_iport200_o (sl_iport200_o),
|
||||
.sl_iport201_o (sl_iport201_o),
|
||||
.sl_iport202_o (sl_iport202_o),
|
||||
.sl_iport203_o (sl_iport203_o),
|
||||
.sl_iport204_o (sl_iport204_o),
|
||||
.sl_iport205_o (sl_iport205_o),
|
||||
.sl_iport206_o (sl_iport206_o),
|
||||
.sl_iport207_o (sl_iport207_o),
|
||||
.sl_iport208_o (sl_iport208_o),
|
||||
.sl_iport209_o (sl_iport209_o),
|
||||
.sl_iport210_o (sl_iport210_o),
|
||||
.sl_iport211_o (sl_iport211_o),
|
||||
.sl_iport212_o (sl_iport212_o),
|
||||
.sl_iport213_o (sl_iport213_o),
|
||||
.sl_iport214_o (sl_iport214_o),
|
||||
.sl_iport215_o (sl_iport215_o),
|
||||
.sl_iport216_o (sl_iport216_o),
|
||||
.sl_iport217_o (sl_iport217_o),
|
||||
.sl_iport218_o (sl_iport218_o),
|
||||
.sl_iport219_o (sl_iport219_o),
|
||||
.sl_iport220_o (sl_iport220_o),
|
||||
.sl_iport221_o (sl_iport221_o),
|
||||
.sl_iport222_o (sl_iport222_o),
|
||||
.sl_iport223_o (sl_iport223_o),
|
||||
.sl_iport224_o (sl_iport224_o),
|
||||
.sl_iport225_o (sl_iport225_o),
|
||||
.sl_iport226_o (sl_iport226_o),
|
||||
.sl_iport227_o (sl_iport227_o),
|
||||
.sl_iport228_o (sl_iport228_o),
|
||||
.sl_iport229_o (sl_iport229_o),
|
||||
.sl_iport230_o (sl_iport230_o),
|
||||
.sl_iport231_o (sl_iport231_o),
|
||||
.sl_iport232_o (sl_iport232_o),
|
||||
.sl_iport233_o (sl_iport233_o),
|
||||
.sl_iport234_o (sl_iport234_o),
|
||||
.sl_iport235_o (sl_iport235_o),
|
||||
.sl_iport236_o (sl_iport236_o),
|
||||
.sl_iport237_o (sl_iport237_o),
|
||||
.sl_iport238_o (sl_iport238_o),
|
||||
.sl_iport239_o (sl_iport239_o),
|
||||
.sl_iport240_o (sl_iport240_o),
|
||||
.sl_iport241_o (sl_iport241_o),
|
||||
.sl_iport242_o (sl_iport242_o),
|
||||
.sl_iport243_o (sl_iport243_o),
|
||||
.sl_iport244_o (sl_iport244_o),
|
||||
.sl_iport245_o (sl_iport245_o),
|
||||
.sl_iport246_o (sl_iport246_o),
|
||||
.sl_iport247_o (sl_iport247_o),
|
||||
.sl_iport248_o (sl_iport248_o),
|
||||
.sl_iport249_o (sl_iport249_o),
|
||||
.sl_iport250_o (sl_iport250_o),
|
||||
.sl_iport251_o (sl_iport251_o),
|
||||
.sl_iport252_o (sl_iport252_o),
|
||||
.sl_iport253_o (sl_iport253_o),
|
||||
.sl_iport254_o (sl_iport254_o),
|
||||
.sl_iport255_o (sl_iport255_o),
|
||||
.sl_oport0_i (sl_oport0_i),
|
||||
.sl_oport1_i (sl_oport1_i),
|
||||
.sl_oport2_i (sl_oport2_i),
|
||||
.sl_oport3_i (sl_oport3_i),
|
||||
.sl_oport4_i (sl_oport4_i),
|
||||
.sl_oport5_i (sl_oport5_i),
|
||||
.sl_oport6_i (sl_oport6_i),
|
||||
.sl_oport7_i (sl_oport7_i),
|
||||
.sl_oport8_i (sl_oport8_i),
|
||||
.sl_oport9_i (sl_oport9_i),
|
||||
.sl_oport10_i (sl_oport10_i),
|
||||
.sl_oport11_i (sl_oport11_i),
|
||||
.sl_oport12_i (sl_oport12_i),
|
||||
.sl_oport13_i (sl_oport13_i),
|
||||
.sl_oport14_i (sl_oport14_i),
|
||||
.sl_oport15_i (sl_oport15_i),
|
||||
.sl_oport16_i (sl_oport16_i),
|
||||
.sl_oport17_i (sl_oport17_i),
|
||||
.sl_oport18_i (sl_oport18_i),
|
||||
.sl_oport19_i (sl_oport19_i),
|
||||
.sl_oport20_i (sl_oport20_i),
|
||||
.sl_oport21_i (sl_oport21_i),
|
||||
.sl_oport22_i (sl_oport22_i),
|
||||
.sl_oport23_i (sl_oport23_i),
|
||||
.sl_oport24_i (sl_oport24_i),
|
||||
.sl_oport25_i (sl_oport25_i),
|
||||
.sl_oport26_i (sl_oport26_i),
|
||||
.sl_oport27_i (sl_oport27_i),
|
||||
.sl_oport28_i (sl_oport28_i),
|
||||
.sl_oport29_i (sl_oport29_i),
|
||||
.sl_oport30_i (sl_oport30_i),
|
||||
.sl_oport31_i (sl_oport31_i),
|
||||
.sl_oport32_i (sl_oport32_i),
|
||||
.sl_oport33_i (sl_oport33_i),
|
||||
.sl_oport34_i (sl_oport34_i),
|
||||
.sl_oport35_i (sl_oport35_i),
|
||||
.sl_oport36_i (sl_oport36_i),
|
||||
.sl_oport37_i (sl_oport37_i),
|
||||
.sl_oport38_i (sl_oport38_i),
|
||||
.sl_oport39_i (sl_oport39_i),
|
||||
.sl_oport40_i (sl_oport40_i),
|
||||
.sl_oport41_i (sl_oport41_i),
|
||||
.sl_oport42_i (sl_oport42_i),
|
||||
.sl_oport43_i (sl_oport43_i),
|
||||
.sl_oport44_i (sl_oport44_i),
|
||||
.sl_oport45_i (sl_oport45_i),
|
||||
.sl_oport46_i (sl_oport46_i),
|
||||
.sl_oport47_i (sl_oport47_i),
|
||||
.sl_oport48_i (sl_oport48_i),
|
||||
.sl_oport49_i (sl_oport49_i),
|
||||
.sl_oport50_i (sl_oport50_i),
|
||||
.sl_oport51_i (sl_oport51_i),
|
||||
.sl_oport52_i (sl_oport52_i),
|
||||
.sl_oport53_i (sl_oport53_i),
|
||||
.sl_oport54_i (sl_oport54_i),
|
||||
.sl_oport55_i (sl_oport55_i),
|
||||
.sl_oport56_i (sl_oport56_i),
|
||||
.sl_oport57_i (sl_oport57_i),
|
||||
.sl_oport58_i (sl_oport58_i),
|
||||
.sl_oport59_i (sl_oport59_i),
|
||||
.sl_oport60_i (sl_oport60_i),
|
||||
.sl_oport61_i (sl_oport61_i),
|
||||
.sl_oport62_i (sl_oport62_i),
|
||||
.sl_oport63_i (sl_oport63_i),
|
||||
.sl_oport64_i (sl_oport64_i),
|
||||
.sl_oport65_i (sl_oport65_i),
|
||||
.sl_oport66_i (sl_oport66_i),
|
||||
.sl_oport67_i (sl_oport67_i),
|
||||
.sl_oport68_i (sl_oport68_i),
|
||||
.sl_oport69_i (sl_oport69_i),
|
||||
.sl_oport70_i (sl_oport70_i),
|
||||
.sl_oport71_i (sl_oport71_i),
|
||||
.sl_oport72_i (sl_oport72_i),
|
||||
.sl_oport73_i (sl_oport73_i),
|
||||
.sl_oport74_i (sl_oport74_i),
|
||||
.sl_oport75_i (sl_oport75_i),
|
||||
.sl_oport76_i (sl_oport76_i),
|
||||
.sl_oport77_i (sl_oport77_i),
|
||||
.sl_oport78_i (sl_oport78_i),
|
||||
.sl_oport79_i (sl_oport79_i),
|
||||
.sl_oport80_i (sl_oport80_i),
|
||||
.sl_oport81_i (sl_oport81_i),
|
||||
.sl_oport82_i (sl_oport82_i),
|
||||
.sl_oport83_i (sl_oport83_i),
|
||||
.sl_oport84_i (sl_oport84_i),
|
||||
.sl_oport85_i (sl_oport85_i),
|
||||
.sl_oport86_i (sl_oport86_i),
|
||||
.sl_oport87_i (sl_oport87_i),
|
||||
.sl_oport88_i (sl_oport88_i),
|
||||
.sl_oport89_i (sl_oport89_i),
|
||||
.sl_oport90_i (sl_oport90_i),
|
||||
.sl_oport91_i (sl_oport91_i),
|
||||
.sl_oport92_i (sl_oport92_i),
|
||||
.sl_oport93_i (sl_oport93_i),
|
||||
.sl_oport94_i (sl_oport94_i),
|
||||
.sl_oport95_i (sl_oport95_i),
|
||||
.sl_oport96_i (sl_oport96_i),
|
||||
.sl_oport97_i (sl_oport97_i),
|
||||
.sl_oport98_i (sl_oport98_i),
|
||||
.sl_oport99_i (sl_oport99_i),
|
||||
.sl_oport100_i (sl_oport100_i),
|
||||
.sl_oport101_i (sl_oport101_i),
|
||||
.sl_oport102_i (sl_oport102_i),
|
||||
.sl_oport103_i (sl_oport103_i),
|
||||
.sl_oport104_i (sl_oport104_i),
|
||||
.sl_oport105_i (sl_oport105_i),
|
||||
.sl_oport106_i (sl_oport106_i),
|
||||
.sl_oport107_i (sl_oport107_i),
|
||||
.sl_oport108_i (sl_oport108_i),
|
||||
.sl_oport109_i (sl_oport109_i),
|
||||
.sl_oport110_i (sl_oport110_i),
|
||||
.sl_oport111_i (sl_oport111_i),
|
||||
.sl_oport112_i (sl_oport112_i),
|
||||
.sl_oport113_i (sl_oport113_i),
|
||||
.sl_oport114_i (sl_oport114_i),
|
||||
.sl_oport115_i (sl_oport115_i),
|
||||
.sl_oport116_i (sl_oport116_i),
|
||||
.sl_oport117_i (sl_oport117_i),
|
||||
.sl_oport118_i (sl_oport118_i),
|
||||
.sl_oport119_i (sl_oport119_i),
|
||||
.sl_oport120_i (sl_oport120_i),
|
||||
.sl_oport121_i (sl_oport121_i),
|
||||
.sl_oport122_i (sl_oport122_i),
|
||||
.sl_oport123_i (sl_oport123_i),
|
||||
.sl_oport124_i (sl_oport124_i),
|
||||
.sl_oport125_i (sl_oport125_i),
|
||||
.sl_oport126_i (sl_oport126_i),
|
||||
.sl_oport127_i (sl_oport127_i),
|
||||
.sl_oport128_i (sl_oport128_i),
|
||||
.sl_oport129_i (sl_oport129_i),
|
||||
.sl_oport130_i (sl_oport130_i),
|
||||
.sl_oport131_i (sl_oport131_i),
|
||||
.sl_oport132_i (sl_oport132_i),
|
||||
.sl_oport133_i (sl_oport133_i),
|
||||
.sl_oport134_i (sl_oport134_i),
|
||||
.sl_oport135_i (sl_oport135_i),
|
||||
.sl_oport136_i (sl_oport136_i),
|
||||
.sl_oport137_i (sl_oport137_i),
|
||||
.sl_oport138_i (sl_oport138_i),
|
||||
.sl_oport139_i (sl_oport139_i),
|
||||
.sl_oport140_i (sl_oport140_i),
|
||||
.sl_oport141_i (sl_oport141_i),
|
||||
.sl_oport142_i (sl_oport142_i),
|
||||
.sl_oport143_i (sl_oport143_i),
|
||||
.sl_oport144_i (sl_oport144_i),
|
||||
.sl_oport145_i (sl_oport145_i),
|
||||
.sl_oport146_i (sl_oport146_i),
|
||||
.sl_oport147_i (sl_oport147_i),
|
||||
.sl_oport148_i (sl_oport148_i),
|
||||
.sl_oport149_i (sl_oport149_i),
|
||||
.sl_oport150_i (sl_oport150_i),
|
||||
.sl_oport151_i (sl_oport151_i),
|
||||
.sl_oport152_i (sl_oport152_i),
|
||||
.sl_oport153_i (sl_oport153_i),
|
||||
.sl_oport154_i (sl_oport154_i),
|
||||
.sl_oport155_i (sl_oport155_i),
|
||||
.sl_oport156_i (sl_oport156_i),
|
||||
.sl_oport157_i (sl_oport157_i),
|
||||
.sl_oport158_i (sl_oport158_i),
|
||||
.sl_oport159_i (sl_oport159_i),
|
||||
.sl_oport160_i (sl_oport160_i),
|
||||
.sl_oport161_i (sl_oport161_i),
|
||||
.sl_oport162_i (sl_oport162_i),
|
||||
.sl_oport163_i (sl_oport163_i),
|
||||
.sl_oport164_i (sl_oport164_i),
|
||||
.sl_oport165_i (sl_oport165_i),
|
||||
.sl_oport166_i (sl_oport166_i),
|
||||
.sl_oport167_i (sl_oport167_i),
|
||||
.sl_oport168_i (sl_oport168_i),
|
||||
.sl_oport169_i (sl_oport169_i),
|
||||
.sl_oport170_i (sl_oport170_i),
|
||||
.sl_oport171_i (sl_oport171_i),
|
||||
.sl_oport172_i (sl_oport172_i),
|
||||
.sl_oport173_i (sl_oport173_i),
|
||||
.sl_oport174_i (sl_oport174_i),
|
||||
.sl_oport175_i (sl_oport175_i),
|
||||
.sl_oport176_i (sl_oport176_i),
|
||||
.sl_oport177_i (sl_oport177_i),
|
||||
.sl_oport178_i (sl_oport178_i),
|
||||
.sl_oport179_i (sl_oport179_i),
|
||||
.sl_oport180_i (sl_oport180_i),
|
||||
.sl_oport181_i (sl_oport181_i),
|
||||
.sl_oport182_i (sl_oport182_i),
|
||||
.sl_oport183_i (sl_oport183_i),
|
||||
.sl_oport184_i (sl_oport184_i),
|
||||
.sl_oport185_i (sl_oport185_i),
|
||||
.sl_oport186_i (sl_oport186_i),
|
||||
.sl_oport187_i (sl_oport187_i),
|
||||
.sl_oport188_i (sl_oport188_i),
|
||||
.sl_oport189_i (sl_oport189_i),
|
||||
.sl_oport190_i (sl_oport190_i),
|
||||
.sl_oport191_i (sl_oport191_i),
|
||||
.sl_oport192_i (sl_oport192_i),
|
||||
.sl_oport193_i (sl_oport193_i),
|
||||
.sl_oport194_i (sl_oport194_i),
|
||||
.sl_oport195_i (sl_oport195_i),
|
||||
.sl_oport196_i (sl_oport196_i),
|
||||
.sl_oport197_i (sl_oport197_i),
|
||||
.sl_oport198_i (sl_oport198_i),
|
||||
.sl_oport199_i (sl_oport199_i),
|
||||
.sl_oport200_i (sl_oport200_i),
|
||||
.sl_oport201_i (sl_oport201_i),
|
||||
.sl_oport202_i (sl_oport202_i),
|
||||
.sl_oport203_i (sl_oport203_i),
|
||||
.sl_oport204_i (sl_oport204_i),
|
||||
.sl_oport205_i (sl_oport205_i),
|
||||
.sl_oport206_i (sl_oport206_i),
|
||||
.sl_oport207_i (sl_oport207_i),
|
||||
.sl_oport208_i (sl_oport208_i),
|
||||
.sl_oport209_i (sl_oport209_i),
|
||||
.sl_oport210_i (sl_oport210_i),
|
||||
.sl_oport211_i (sl_oport211_i),
|
||||
.sl_oport212_i (sl_oport212_i),
|
||||
.sl_oport213_i (sl_oport213_i),
|
||||
.sl_oport214_i (sl_oport214_i),
|
||||
.sl_oport215_i (sl_oport215_i),
|
||||
.sl_oport216_i (sl_oport216_i),
|
||||
.sl_oport217_i (sl_oport217_i),
|
||||
.sl_oport218_i (sl_oport218_i),
|
||||
.sl_oport219_i (sl_oport219_i),
|
||||
.sl_oport220_i (sl_oport220_i),
|
||||
.sl_oport221_i (sl_oport221_i),
|
||||
.sl_oport222_i (sl_oport222_i),
|
||||
.sl_oport223_i (sl_oport223_i),
|
||||
.sl_oport224_i (sl_oport224_i),
|
||||
.sl_oport225_i (sl_oport225_i),
|
||||
.sl_oport226_i (sl_oport226_i),
|
||||
.sl_oport227_i (sl_oport227_i),
|
||||
.sl_oport228_i (sl_oport228_i),
|
||||
.sl_oport229_i (sl_oport229_i),
|
||||
.sl_oport230_i (sl_oport230_i),
|
||||
.sl_oport231_i (sl_oport231_i),
|
||||
.sl_oport232_i (sl_oport232_i),
|
||||
.sl_oport233_i (sl_oport233_i),
|
||||
.sl_oport234_i (sl_oport234_i),
|
||||
.sl_oport235_i (sl_oport235_i),
|
||||
.sl_oport236_i (sl_oport236_i),
|
||||
.sl_oport237_i (sl_oport237_i),
|
||||
.sl_oport238_i (sl_oport238_i),
|
||||
.sl_oport239_i (sl_oport239_i),
|
||||
.sl_oport240_i (sl_oport240_i),
|
||||
.sl_oport241_i (sl_oport241_i),
|
||||
.sl_oport242_i (sl_oport242_i),
|
||||
.sl_oport243_i (sl_oport243_i),
|
||||
.sl_oport244_i (sl_oport244_i),
|
||||
.sl_oport245_i (sl_oport245_i),
|
||||
.sl_oport246_i (sl_oport246_i),
|
||||
.sl_oport247_i (sl_oport247_i),
|
||||
.sl_oport248_i (sl_oport248_i),
|
||||
.sl_oport249_i (sl_oport249_i),
|
||||
.sl_oport250_i (sl_oport250_i),
|
||||
.sl_oport251_i (sl_oport251_i),
|
||||
.sl_oport252_i (sl_oport252_i),
|
||||
.sl_oport253_i (sl_oport253_i),
|
||||
.sl_oport254_i (sl_oport254_i),
|
||||
.sl_oport255_i (sl_oport255_i),
|
||||
+8826
File diff suppressed because it is too large
Load Diff
+193219
File diff suppressed because it is too large
Load Diff
+31647
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Nov 10 16:55:43 2024
|
||||
--Date : Sun Nov 10 17:21:43 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
@@ -185,86 +185,113 @@ architecture STRUCTURE of design_1 is
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DONT_TOUCH : boolean;
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
attribute DEBUG : string;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWADDR";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WSTRB";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TLAST";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
@@ -286,12 +313,12 @@ architecture STRUCTURE of design_1 is
|
||||
signal zybo_audio_0_pb_lrc : STD_LOGIC;
|
||||
signal zybo_audio_0_rec_lrc : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
begin
|
||||
bclk <= zybo_audio_0_bclk;
|
||||
clk_1 <= clk;
|
||||
|
||||
Binary file not shown.
+61
-34
@@ -2,7 +2,7 @@
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Sun Nov 10 16:55:42 2024
|
||||
--Date : Sun Nov 10 17:21:43 2024
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target design_1.bd
|
||||
--Design : design_1
|
||||
@@ -185,86 +185,113 @@ architecture STRUCTURE of design_1 is
|
||||
signal axil_master_with_rom_0_M_AXIL_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO : string;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARADDR";
|
||||
attribute DONT_TOUCH : boolean;
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
attribute DEBUG : string;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is "true";
|
||||
attribute MARK_DEBUG : boolean;
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_ARVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE ARVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_ARVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWADDR";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWADDR : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWPROT";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWPROT : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_AWVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE AWVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_AWVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_BVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_BVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE BVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_BVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RRESP : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RRESP";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RRESP : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_RVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_RVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE RVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_RVALID : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WDATA : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WDATA";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WDATA : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WREADY : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WREADY";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WREADY : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WSTRB";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WSTRB : signal is std.standard.true;
|
||||
signal axil_master_with_rom_0_M_AXIL_WVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axil_master_with_rom_0_M_AXIL_WVALID : signal is "axil_master_with_rom_0_M_AXIL xilinx.com:interface:aximm:1.0 AXI4LITE WVALID";
|
||||
attribute DONT_TOUCH of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axil_master_with_rom_0_M_AXIL_WVALID : signal is std.standard.true;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "axis_audio_stereo2mo_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_audio_stereo2mo_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TDATA";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TDATA : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TLAST : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TLAST";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TLAST : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TREADY";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TREADY : signal is std.standard.true;
|
||||
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
|
||||
attribute CONN_BUS_INFO of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "axis_prog_audio_filt_0_M_AXIS xilinx.com:interface:axis:1.0 None TVALID";
|
||||
attribute DONT_TOUCH of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
attribute DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is "true";
|
||||
attribute MARK_DEBUG of axis_prog_audio_filt_0_M_AXIS_TVALID : signal is std.standard.true;
|
||||
signal clk_1 : STD_LOGIC;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
@@ -286,12 +313,12 @@ architecture STRUCTURE of design_1 is
|
||||
signal zybo_audio_0_pb_lrc : STD_LOGIC;
|
||||
signal zybo_audio_0_rec_lrc : STD_LOGIC;
|
||||
attribute X_INTERFACE_INFO : string;
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c ";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_i : signal is "xilinx.com:interface:iic:1.0 i2c SCL_I";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_o : signal is "xilinx.com:interface:iic:1.0 i2c SCL_O";
|
||||
attribute X_INTERFACE_INFO of i2c_scl_t : signal is "xilinx.com:interface:iic:1.0 i2c SCL_T";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_i : signal is "xilinx.com:interface:iic:1.0 i2c SDA_I";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_o : signal is "xilinx.com:interface:iic:1.0 i2c SDA_O";
|
||||
attribute X_INTERFACE_INFO of i2c_sda_t : signal is "xilinx.com:interface:iic:1.0 i2c SDA_T";
|
||||
begin
|
||||
bclk <= zybo_audio_0_bclk;
|
||||
clk_1 <= clk;
|
||||
|
||||
+1
-1
@@ -855,7 +855,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2024-11-09T23:36:52Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2024-11-10T16:10:21Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
@@ -513,7 +513,15 @@
|
||||
"axil_master_with_rom_0/M_AXIL",
|
||||
"axis_prog_audio_filt_0/S_AXIL",
|
||||
"system_ila_0/SLOT_0_AXI"
|
||||
]
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_audio_mono2ster_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
@@ -526,14 +534,30 @@
|
||||
"axis_audio_stereo2mo_0/M_AXIS",
|
||||
"axis_prog_audio_filt_0/S_AXIS",
|
||||
"system_ila_0/SLOT_1_AXIS"
|
||||
]
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axis_prog_audio_filt_0_M_AXIS": {
|
||||
"interface_ports": [
|
||||
"axis_prog_audio_filt_0/M_AXIS",
|
||||
"axis_audio_mono2ster_0/S_AXIS",
|
||||
"system_ila_0/SLOT_2_AXIS"
|
||||
]
|
||||
],
|
||||
"hdl_attributes": {
|
||||
"DEBUG": {
|
||||
"value": "true"
|
||||
},
|
||||
"MARK_DEBUG": {
|
||||
"value": "true"
|
||||
}
|
||||
}
|
||||
},
|
||||
"zybo_audio_0_axis_rec": {
|
||||
"interface_ports": [
|
||||
|
||||
+19
-19
@@ -137,26 +137,26 @@
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXIL",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
@@ -1,10 +1,11 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.85789",
|
||||
"Default View_TopLeft":"813,-59",
|
||||
"Default View_ScaleFactor":"1.42004",
|
||||
"Default View_TopLeft":"49,-254",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
preplace port i2c -pg 1 -lvl 6 -x 1270 -y 80 -defaultsOSRD
|
||||
preplace port port-id_clk -pg 1 -lvl 0 -x -240 -y -40 -defaultsOSRD
|
||||
preplace port port-id_resez -pg 1 -lvl 0 -x -240 -y 0 -defaultsOSRD
|
||||
preplace port port-id_rec_dat -pg 1 -lvl 0 -x -240 -y 200 -defaultsOSRD
|
||||
@@ -14,7 +15,6 @@ preplace port port-id_bclk -pg 1 -lvl 6 -x 1270 -y 260 -defaultsOSRD
|
||||
preplace port port-id_pb_dat -pg 1 -lvl 6 -x 1270 -y 40 -defaultsOSRD
|
||||
preplace port port-id_pb_lrc -pg 1 -lvl 6 -x 1270 -y 300 -defaultsOSRD
|
||||
preplace port port-id_rec_lrc -pg 1 -lvl 6 -x 1270 -y 190 -defaultsOSRD
|
||||
preplace port i2c -pg 1 -lvl 6 -x 1270 -y 80 -defaultsOSRD
|
||||
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 600 -y -110 -defaultsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x -20 -y 0 -defaultsOSRD
|
||||
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 2 -x 320 -y -90 -defaultsOSRD
|
||||
@@ -23,7 +23,7 @@ preplace inst system_ila_0 -pg 1 -lvl 4 -x 860 -y -170 -defaultsOSRD
|
||||
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 860 -y 110 -defaultsOSRD
|
||||
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1100 -y 130 -defaultsOSRD
|
||||
preplace netloc clk_1 1 0 1 -220 -40n
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 460 0 740 190 970
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 460 0 740 180 970
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 470 -20 750
|
||||
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 980
|
||||
preplace netloc resez_1 1 0 1 N 0
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user