Milestone 2 getestet abgeschlossen
This commit is contained in:
Sebastian Meyer
@@ -4,7 +4,7 @@
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||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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||||
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/Users/matth/OneDrive/Dokumente/Studium/05_WS_24/ETS_Elektronische_Systeme/Praktikum/es-praktikum/Milestone1/es-milestone1/es-milestone1.xpr">
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||||
<Project Product="Vivado" Version="7" Minor="63" Path="C:/es-praktikum/Milestone1/es-milestone1/es-milestone1.xpr">
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||||
<DefaultLaunch Dir="$PRUNDIR"/>
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||||
<Configuration>
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||||
<Option Name="Id" Val="73895a82e9554b79a821ba26ed366349"/>
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||||
@@ -44,7 +44,7 @@
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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||||
<Option Name="TargetLanguage" Val="VHDL"/>
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||||
<Option Name="BoardPart" Val="digilentinc.com:zybo-z7-20:part0:1.2"/>
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||||
<Option Name="BoardPart" Val=""/>
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||||
<Option Name="ActiveSimSet" Val="sim_1"/>
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||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
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||||
<Option Name="ProjectType" Val="Default"/>
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||||
@@ -158,14 +158,6 @@
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</FileSet>
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||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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||||
<Filter Type="Utils"/>
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||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/spi2display.dcp">
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<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedInSteps" Val="synth_1"/>
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||||
<Attr Name="AutoDcp" Val="1"/>
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||||
</FileInfo>
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||||
</File>
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||||
<Config>
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||||
<Option Name="TopAutoSet" Val="TRUE"/>
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||||
</Config>
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||||
@@ -190,7 +182,7 @@
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</Simulator>
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||||
</Simulators>
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||||
<Runs Version="1" Minor="20">
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||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/spi2display.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
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<Step Id="synth_design"/>
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@@ -200,7 +192,7 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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||||
<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
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||||
<Step Id="init_design"/>
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||||
@@ -219,9 +211,7 @@
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<RQSFiles/>
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||||
</Run>
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||||
</Runs>
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||||
<Board>
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||||
<Jumpers/>
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||||
</Board>
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||||
<Board/>
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||||
<DashboardSummary Version="1" Minor="0">
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||||
<Dashboards>
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||||
<Dashboard Name="default_dashboard">
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||||
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||||
-429
@@ -1,429 +0,0 @@
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{
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||||
"design": {
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||||
"design_info": {
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||||
"boundary_crc": "0x14BE19C5147B5D81",
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||||
"design_src": "SBD",
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||||
"device": "xc7z020clg400-1",
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||||
"name": "bd_3e86",
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||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
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||||
"scoped": "true",
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||||
"synth_flow_mode": "None",
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||||
"tool_version": "2023.1",
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||||
"validated": "true"
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||||
},
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||||
"design_tree": {
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||||
"ila_lib": "",
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||||
"g_inst": ""
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||||
},
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||||
"interface_ports": {
|
||||
"SLOT_0_AXIS": {
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||||
"mode": "Monitor",
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||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
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||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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||||
"parameters": {
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||||
"CLK_DOMAIN": {
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||||
"value": "bd_3e86_clk",
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||||
"value_src": "default"
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||||
},
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||||
"FREQ_HZ": {
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||||
"value": "100000000",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TKEEP": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TLAST": {
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||||
"value": "1",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TREADY": {
|
||||
"value": "1",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TSTRB": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"INSERT_VIP": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
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||||
"LAYERED_METADATA": {
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||||
"value": "undef",
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||||
"value_src": "default"
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||||
},
|
||||
"PHASE": {
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||||
"value": "0.0",
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||||
"value_src": "default"
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||||
},
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||||
"TDATA_NUM_BYTES": {
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||||
"value": "2",
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||||
"value_src": "default"
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||||
},
|
||||
"TDEST_WIDTH": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
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||||
"TID_WIDTH": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"TUSER_WIDTH": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
}
|
||||
}
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"parameters": {
|
||||
"CLK_DOMAIN": {
|
||||
"value": "bd_3e86_clk",
|
||||
"value_src": "default"
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||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
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||||
"value_src": "default"
|
||||
},
|
||||
"HAS_TKEEP": {
|
||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TLAST": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TREADY": {
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||||
"value": "1",
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||||
"value_src": "default"
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||||
},
|
||||
"HAS_TSTRB": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"INSERT_VIP": {
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||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"LAYERED_METADATA": {
|
||||
"value": "undef",
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||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
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||||
"value_src": "default"
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||||
},
|
||||
"TDATA_NUM_BYTES": {
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||||
"value": "2",
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||||
"value_src": "default"
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||||
},
|
||||
"TDEST_WIDTH": {
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||||
"value": "0",
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||||
"value_src": "default"
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||||
},
|
||||
"TID_WIDTH": {
|
||||
"value": "0",
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||||
"value_src": "default"
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||||
},
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||||
"TUSER_WIDTH": {
|
||||
"value": "0",
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||||
"value_src": "default"
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||||
}
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||||
}
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||||
}
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||||
},
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||||
"ports": {
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||||
"clk": {
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||||
"type": "clk",
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||||
"direction": "I",
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||||
"parameters": {
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||||
"ASSOCIATED_BUSIF": {
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||||
"value": "SLOT_0_AXIS:SLOT_1_AXIS"
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||||
},
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||||
"ASSOCIATED_RESET": {
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||||
"value": "resetn"
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||||
},
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||||
"CLK_DOMAIN": {
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||||
"value": "bd_3e86_clk",
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||||
"value_src": "default_prop"
|
||||
},
|
||||
"FREQ_HZ": {
|
||||
"value": "100000000",
|
||||
"value_src": "default"
|
||||
},
|
||||
"FREQ_TOLERANCE_HZ": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"PHASE": {
|
||||
"value": "0.0",
|
||||
"value_src": "default"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
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||||
"direction": "I",
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||||
"parameters": {
|
||||
"INSERT_VIP": {
|
||||
"value": "0",
|
||||
"value_src": "default"
|
||||
},
|
||||
"POLARITY": {
|
||||
"value": "ACTIVE_LOW",
|
||||
"value_src": "constant"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"ila_lib": {
|
||||
"vlnv": "xilinx.com:ip:ila:6.2",
|
||||
"xci_name": "bd_3e86_ila_lib_0",
|
||||
"xci_path": "ip\\ip_0\\bd_3e86_ila_lib_0.xci",
|
||||
"inst_hier_path": "ila_lib",
|
||||
"parameters": {
|
||||
"ALL_PROBE_SAME_MU": {
|
||||
"value": "TRUE"
|
||||
},
|
||||
"ALL_PROBE_SAME_MU_CNT": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_ADV_TRIGGER": {
|
||||
"value": "FALSE"
|
||||
},
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "1024"
|
||||
},
|
||||
"C_EN_STRG_QUAL": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_ILA_CLK_FREQ": {
|
||||
"value": "100000000"
|
||||
},
|
||||
"C_INPUT_PIPE_STAGES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_MONITOR_TYPE": {
|
||||
"value": "Native"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "8"
|
||||
},
|
||||
"C_PROBE0_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE0_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE1_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE1_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE2_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE2_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE3_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE3_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE4_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE4_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_PROBE5_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE5_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE6_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE6_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_PROBE7_TYPE": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_PROBE7_WIDTH": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_TRIGIN_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_TRIGOUT_EN": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_XLNX_HW_PROBE_INFO": {
|
||||
"value": "DEFAULT"
|
||||
}
|
||||
}
|
||||
},
|
||||
"g_inst": {
|
||||
"vlnv": "xilinx.com:ip:gigantic_mux:1.0",
|
||||
"xci_name": "bd_3e86_g_inst_0",
|
||||
"xci_path": "ip\\ip_1\\bd_3e86_g_inst_0.xci",
|
||||
"inst_hier_path": "g_inst",
|
||||
"parameters": {
|
||||
"C_EN_GIGAMUX": {
|
||||
"value": "false"
|
||||
},
|
||||
"C_NUM_MONITOR_SLOTS": {
|
||||
"value": "2"
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_0_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_0_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_0_MON_MODE": {
|
||||
"value": "FT"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDATA_WIDTH": {
|
||||
"value": "16"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TDEST_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TID_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXIS_TUSER_WIDTH": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_AXI_PROTOCOL": {
|
||||
"value": "AXI4S"
|
||||
},
|
||||
"C_SLOT_1_HAS_TKEEP": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_HAS_TREADY": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_SLOT_1_HAS_TSTRB": {
|
||||
"value": "0"
|
||||
},
|
||||
"C_SLOT_1_MON_MODE": {
|
||||
"value": "FT"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn": {
|
||||
"interface_ports": [
|
||||
"SLOT_0_AXIS",
|
||||
"g_inst/slot_0_axis"
|
||||
]
|
||||
},
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"SLOT_1_AXIS",
|
||||
"g_inst/slot_1_axis"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"clk_1": {
|
||||
"ports": [
|
||||
"clk",
|
||||
"ila_lib/clk",
|
||||
"g_inst/aclk"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tdata",
|
||||
"ila_lib/probe0"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tlast",
|
||||
"ila_lib/probe3"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tready",
|
||||
"ila_lib/probe2"
|
||||
]
|
||||
},
|
||||
"net_slot_0_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_0_axis_tvalid",
|
||||
"ila_lib/probe1"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tdata": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tdata",
|
||||
"ila_lib/probe4"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tlast": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tlast",
|
||||
"ila_lib/probe7"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tready": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tready",
|
||||
"ila_lib/probe6"
|
||||
]
|
||||
},
|
||||
"net_slot_1_axis_tvalid": {
|
||||
"ports": [
|
||||
"g_inst/m_slot_1_axis_tvalid",
|
||||
"ila_lib/probe5"
|
||||
]
|
||||
},
|
||||
"resetn_1": {
|
||||
"ports": [
|
||||
"resetn",
|
||||
"g_inst/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-51
@@ -1,51 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_3e86" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1730149476"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1730149476"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1730149476"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1730149476"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\bd_3e86.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_3e86.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="bd_3e86_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\design_1_syn_system_ila_0_2.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\design_1_syn_system_ila_0_2.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\bd_3e86.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
-11
@@ -1,11 +0,0 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
-54
@@ -1,54 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86_wrapper.bd
|
||||
//Design : bd_3e86_wrapper
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module bd_3e86_wrapper
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
input [15:0]SLOT_0_AXIS_tdata;
|
||||
input SLOT_0_AXIS_tlast;
|
||||
input SLOT_0_AXIS_tready;
|
||||
input SLOT_0_AXIS_tvalid;
|
||||
input [15:0]SLOT_1_AXIS_tdata;
|
||||
input SLOT_1_AXIS_tlast;
|
||||
input SLOT_1_AXIS_tready;
|
||||
input SLOT_1_AXIS_tvalid;
|
||||
input clk;
|
||||
input resetn;
|
||||
|
||||
wire [15:0]SLOT_0_AXIS_tdata;
|
||||
wire SLOT_0_AXIS_tlast;
|
||||
wire SLOT_0_AXIS_tready;
|
||||
wire SLOT_0_AXIS_tvalid;
|
||||
wire [15:0]SLOT_1_AXIS_tdata;
|
||||
wire SLOT_1_AXIS_tlast;
|
||||
wire SLOT_1_AXIS_tready;
|
||||
wire SLOT_1_AXIS_tvalid;
|
||||
wire clk;
|
||||
wire resetn;
|
||||
|
||||
bd_3e86 bd_3e86_i
|
||||
(.SLOT_0_AXIS_tdata(SLOT_0_AXIS_tdata),
|
||||
.SLOT_0_AXIS_tlast(SLOT_0_AXIS_tlast),
|
||||
.SLOT_0_AXIS_tready(SLOT_0_AXIS_tready),
|
||||
.SLOT_0_AXIS_tvalid(SLOT_0_AXIS_tvalid),
|
||||
.SLOT_1_AXIS_tdata(SLOT_1_AXIS_tdata),
|
||||
.SLOT_1_AXIS_tlast(SLOT_1_AXIS_tlast),
|
||||
.SLOT_1_AXIS_tready(SLOT_1_AXIS_tready),
|
||||
.SLOT_1_AXIS_tvalid(SLOT_1_AXIS_tvalid),
|
||||
.clk(clk),
|
||||
.resetn(resetn));
|
||||
endmodule
|
||||
-4824
File diff suppressed because it is too large
Load Diff
-6306
File diff suppressed because it is too large
Load Diff
-74950
File diff suppressed because it is too large
Load Diff
-69
@@ -1,69 +0,0 @@
|
||||
|
||||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
|
||||
################################################################################
|
||||
#create_clock -name clock_name -period 10 [get_ports clock_name]
|
||||
################################################################################
|
||||
|
||||
#list of all the clock needed for ILA core
|
||||
|
||||
|
||||
|
||||
create_clock -name ILA_CLK -period 10 [get_ports clk]
|
||||
|
||||
################################################################################
|
||||
-103
@@ -1,103 +0,0 @@
|
||||
##
|
||||
## ARM and HALT transfer false paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/dout_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/temp_reg0_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Register False Paths
|
||||
##
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/itrigger_out_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/use_probe_debug_circuit_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/en_adv_trigger_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/capture_qual_ctrl_2_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/debug_data_in_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*.cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/cfg_data_vec_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_sync1_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_ila_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/s_dclk_flag_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/next_state_xsdb_reg*" && IS_SEQUENTIAL} ]
|
||||
#set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/ila_clk_flag_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL} ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[*].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/probeDelay1_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*" && IS_SEQUENTIAL}]]
|
||||
#set_false_path -from [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK}] -to [get_pins -hierarchical -filter {NAME =~ *allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D}]
|
||||
|
||||
##
|
||||
## ILA Capture Block False Paths
|
||||
##
|
||||
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*cfg_data_vec_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/*icap_addr_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/captured_samples*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_DONE_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/CAP_TRIGGER_O*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg*/I_EN_STAT_EQ1.U_STAT/xsdb_reg*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Capture State to XSDB register False Paths
|
||||
##
|
||||
set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS*/I_YESLUT6.I_YES_OREG.O_reg_reg*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_regs/reg_*/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
#set_false_path -from [get_pins -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*/CLK*"}] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/u_srl_drive*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg*" && IS_SEQUENTIAL }]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*" }]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg*" && IS_SEQUENTIAL} ]
|
||||
|
||||
|
||||
|
||||
|
||||
##
|
||||
## Waivers
|
||||
##
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_xsdb_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/next_state_ila_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-1 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/s_dclk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]]
|
||||
#create_waiver -internal -scope -type CDC -id CDC-15 -description {The cross clock communication is handled through hand shake process} -tags "1025927" -user "ila" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/ila_clk_flag_reg*"} ]] -to [get_pins -filter {REF_PIN_NAME=~R} -of_objects [get_cells -hierarchical -filter { NAME =~ "*/ila_core_inst/u_ila_regs/clk_lost_cnt_reg[*]*"} ]]
|
||||
|
||||
-30
@@ -1,30 +0,0 @@
|
||||
##
|
||||
## Match Unit Configuration to Match Output false path
|
||||
##
|
||||
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D*} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]]
|
||||
|
||||
##
|
||||
## ILA Sample Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
##
|
||||
## ILA Window Counter Match Condition out False Paths
|
||||
##
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*" && IS_SEQUENTIAL } ]
|
||||
set_false_path -from [get_pins -filter {REF_PIN_NAME=~CLK*} -of_objects [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_cells -hierarchical -filter { NAME =~ "*ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*" && IS_SEQUENTIAL } ]
|
||||
|
||||
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_CDONE/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS1/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/U_NS0/I_YESLUT6.I_YES_OREG.O_reg_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/iwcnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/iscnt_reg[*]*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/u_scnt_cmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32*"}]] -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srl*/S*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
#create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/u_srlD/S1*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_trig/N_DDR_TC.N_DDR_TC_INST[*].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[*].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
create_waiver -internal -scope -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~CLK} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E*"}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_ila_cap_ctrl/u_cap_addrgen/icap_wr_en_reg*"}]] -tags "1037291" -user "xsdbm" -description {CDC is handled through handshake process}
|
||||
|
||||
-76
@@ -1,76 +0,0 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module bd_3e86_ila_lib_0 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [15 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [15 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [0 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
|
||||
|
||||
endmodule
|
||||
-4254
File diff suppressed because it is too large
Load Diff
-2882
File diff suppressed because it is too large
Load Diff
-113892
File diff suppressed because it is too large
Load Diff
-4882
File diff suppressed because it is too large
Load Diff
-4118
File diff suppressed because it is too large
Load Diff
-4178
File diff suppressed because it is too large
Load Diff
-9
@@ -1,9 +0,0 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"bd_3e86": {
|
||||
"proto_instances": {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-91
@@ -1,91 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86.bd
|
||||
//Design : bd_3e86
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_3e86,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_3e86,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_syn_system_ila_0_2.hwdef" *)
|
||||
module bd_3e86
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_0_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_0_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TLAST" *) input SLOT_0_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TREADY" *) input SLOT_0_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TVALID" *) input SLOT_0_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_1_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST" *) input SLOT_1_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY" *) input SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID" *) input SLOT_1_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXIS:SLOT_1_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
|
||||
|
||||
wire [15:0]Conn1_TDATA;
|
||||
wire Conn1_TLAST;
|
||||
wire Conn1_TREADY;
|
||||
wire Conn1_TVALID;
|
||||
wire [15:0]Conn_TDATA;
|
||||
wire Conn_TLAST;
|
||||
wire Conn_TREADY;
|
||||
wire Conn_TVALID;
|
||||
wire clk_1;
|
||||
wire [15:0]net_slot_0_axis_tdata;
|
||||
wire net_slot_0_axis_tlast;
|
||||
wire net_slot_0_axis_tready;
|
||||
wire net_slot_0_axis_tvalid;
|
||||
wire [15:0]net_slot_1_axis_tdata;
|
||||
wire net_slot_1_axis_tlast;
|
||||
wire net_slot_1_axis_tready;
|
||||
wire net_slot_1_axis_tvalid;
|
||||
wire resetn_1;
|
||||
|
||||
assign Conn1_TDATA = SLOT_1_AXIS_tdata[15:0];
|
||||
assign Conn1_TLAST = SLOT_1_AXIS_tlast;
|
||||
assign Conn1_TREADY = SLOT_1_AXIS_tready;
|
||||
assign Conn1_TVALID = SLOT_1_AXIS_tvalid;
|
||||
assign Conn_TDATA = SLOT_0_AXIS_tdata[15:0];
|
||||
assign Conn_TLAST = SLOT_0_AXIS_tlast;
|
||||
assign Conn_TREADY = SLOT_0_AXIS_tready;
|
||||
assign Conn_TVALID = SLOT_0_AXIS_tvalid;
|
||||
assign clk_1 = clk;
|
||||
assign resetn_1 = resetn;
|
||||
bd_3e86_g_inst_0 g_inst
|
||||
(.aclk(clk_1),
|
||||
.aresetn(resetn_1),
|
||||
.m_slot_0_axis_tdata(net_slot_0_axis_tdata),
|
||||
.m_slot_0_axis_tlast(net_slot_0_axis_tlast),
|
||||
.m_slot_0_axis_tready(net_slot_0_axis_tready),
|
||||
.m_slot_0_axis_tvalid(net_slot_0_axis_tvalid),
|
||||
.m_slot_1_axis_tdata(net_slot_1_axis_tdata),
|
||||
.m_slot_1_axis_tlast(net_slot_1_axis_tlast),
|
||||
.m_slot_1_axis_tready(net_slot_1_axis_tready),
|
||||
.m_slot_1_axis_tvalid(net_slot_1_axis_tvalid),
|
||||
.slot_0_axis_tdata(Conn_TDATA),
|
||||
.slot_0_axis_tlast(Conn_TLAST),
|
||||
.slot_0_axis_tready(Conn_TREADY),
|
||||
.slot_0_axis_tvalid(Conn_TVALID),
|
||||
.slot_1_axis_tdata(Conn1_TDATA),
|
||||
.slot_1_axis_tlast(Conn1_TLAST),
|
||||
.slot_1_axis_tready(Conn1_TREADY),
|
||||
.slot_1_axis_tvalid(Conn1_TVALID));
|
||||
bd_3e86_ila_lib_0 ila_lib
|
||||
(.clk(clk_1),
|
||||
.probe0(net_slot_0_axis_tdata),
|
||||
.probe1(net_slot_0_axis_tvalid),
|
||||
.probe2(net_slot_0_axis_tready),
|
||||
.probe3(net_slot_0_axis_tlast),
|
||||
.probe4(net_slot_1_axis_tdata),
|
||||
.probe5(net_slot_1_axis_tvalid),
|
||||
.probe6(net_slot_1_axis_tready),
|
||||
.probe7(net_slot_1_axis_tlast));
|
||||
endmodule
|
||||
-91
@@ -1,91 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_3e86.bd
|
||||
//Design : bd_3e86
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "bd_3e86,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_3e86,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=SBD,synth_mode=Global}" *) (* HW_HANDOFF = "design_1_syn_system_ila_0_2.hwdef" *)
|
||||
module bd_3e86
|
||||
(SLOT_0_AXIS_tdata,
|
||||
SLOT_0_AXIS_tlast,
|
||||
SLOT_0_AXIS_tready,
|
||||
SLOT_0_AXIS_tvalid,
|
||||
SLOT_1_AXIS_tdata,
|
||||
SLOT_1_AXIS_tlast,
|
||||
SLOT_1_AXIS_tready,
|
||||
SLOT_1_AXIS_tvalid,
|
||||
clk,
|
||||
resetn);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_0_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 1, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_0_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TLAST" *) input SLOT_0_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TREADY" *) input SLOT_0_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_0_AXIS TVALID" *) input SLOT_0_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLOT_1_AXIS, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0" *) input [15:0]SLOT_1_AXIS_tdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TLAST" *) input SLOT_1_AXIS_tlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TREADY" *) input SLOT_1_AXIS_tready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 SLOT_1_AXIS TVALID" *) input SLOT_1_AXIS_tvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLOT_0_AXIS:SLOT_1_AXIS, ASSOCIATED_RESET resetn, CLK_DOMAIN bd_3e86_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input resetn;
|
||||
|
||||
wire [15:0]Conn1_TDATA;
|
||||
wire Conn1_TLAST;
|
||||
wire Conn1_TREADY;
|
||||
wire Conn1_TVALID;
|
||||
wire [15:0]Conn_TDATA;
|
||||
wire Conn_TLAST;
|
||||
wire Conn_TREADY;
|
||||
wire Conn_TVALID;
|
||||
wire clk_1;
|
||||
wire [15:0]net_slot_0_axis_tdata;
|
||||
wire net_slot_0_axis_tlast;
|
||||
wire net_slot_0_axis_tready;
|
||||
wire net_slot_0_axis_tvalid;
|
||||
wire [15:0]net_slot_1_axis_tdata;
|
||||
wire net_slot_1_axis_tlast;
|
||||
wire net_slot_1_axis_tready;
|
||||
wire net_slot_1_axis_tvalid;
|
||||
wire resetn_1;
|
||||
|
||||
assign Conn1_TDATA = SLOT_1_AXIS_tdata[15:0];
|
||||
assign Conn1_TLAST = SLOT_1_AXIS_tlast;
|
||||
assign Conn1_TREADY = SLOT_1_AXIS_tready;
|
||||
assign Conn1_TVALID = SLOT_1_AXIS_tvalid;
|
||||
assign Conn_TDATA = SLOT_0_AXIS_tdata[15:0];
|
||||
assign Conn_TLAST = SLOT_0_AXIS_tlast;
|
||||
assign Conn_TREADY = SLOT_0_AXIS_tready;
|
||||
assign Conn_TVALID = SLOT_0_AXIS_tvalid;
|
||||
assign clk_1 = clk;
|
||||
assign resetn_1 = resetn;
|
||||
bd_3e86_g_inst_0 g_inst
|
||||
(.aclk(clk_1),
|
||||
.aresetn(resetn_1),
|
||||
.m_slot_0_axis_tdata(net_slot_0_axis_tdata),
|
||||
.m_slot_0_axis_tlast(net_slot_0_axis_tlast),
|
||||
.m_slot_0_axis_tready(net_slot_0_axis_tready),
|
||||
.m_slot_0_axis_tvalid(net_slot_0_axis_tvalid),
|
||||
.m_slot_1_axis_tdata(net_slot_1_axis_tdata),
|
||||
.m_slot_1_axis_tlast(net_slot_1_axis_tlast),
|
||||
.m_slot_1_axis_tready(net_slot_1_axis_tready),
|
||||
.m_slot_1_axis_tvalid(net_slot_1_axis_tvalid),
|
||||
.slot_0_axis_tdata(Conn_TDATA),
|
||||
.slot_0_axis_tlast(Conn_TLAST),
|
||||
.slot_0_axis_tready(Conn_TREADY),
|
||||
.slot_0_axis_tvalid(Conn_TVALID),
|
||||
.slot_1_axis_tdata(Conn1_TDATA),
|
||||
.slot_1_axis_tlast(Conn1_TLAST),
|
||||
.slot_1_axis_tready(Conn1_TREADY),
|
||||
.slot_1_axis_tvalid(Conn1_TVALID));
|
||||
bd_3e86_ila_lib_0 ila_lib
|
||||
(.clk(clk_1),
|
||||
.probe0(net_slot_0_axis_tdata),
|
||||
.probe1(net_slot_0_axis_tvalid),
|
||||
.probe2(net_slot_0_axis_tready),
|
||||
.probe3(net_slot_0_axis_tlast),
|
||||
.probe4(net_slot_1_axis_tdata),
|
||||
.probe5(net_slot_1_axis_tvalid),
|
||||
.probe6(net_slot_1_axis_tready),
|
||||
.probe7(net_slot_1_axis_tlast));
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+45
@@ -0,0 +1,45 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0x0",
|
||||
"design_src": "SBD",
|
||||
"device": "xc7z020clg400-1",
|
||||
"name": "bd_3e86_0",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"scoped": "true",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {},
|
||||
"interface_ports": {
|
||||
"SLOT_0_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
},
|
||||
"SLOT_1_AXIS": {
|
||||
"mode": "Monitor",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:axis:1.0",
|
||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"clk": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "SLOT_0_AXIS:SLOT_1_AXIS"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "resetn"
|
||||
}
|
||||
}
|
||||
},
|
||||
"resetn": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "bd_3e86_0",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "bd_3e86_0",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_3e86_0" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1730194747"/>
|
||||
<Generation Name="SIMULATION" State="STALE" Timestamp="1730194747"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1730194747"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1730194747"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
+267
-76
@@ -137,6 +137,22 @@
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:monitor spirit:interfaceMode="slave"/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDEST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tdest</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
@@ -145,6 +161,22 @@
|
||||
<spirit:name>SLOT_0_AXIS_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
@@ -153,6 +185,14 @@
|
||||
<spirit:name>SLOT_0_AXIS_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_0_AXIS_tuser</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
@@ -296,6 +336,22 @@
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
||||
<spirit:monitor spirit:interfaceMode="slave"/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDEST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tdest</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TDATA</spirit:name>
|
||||
@@ -304,6 +360,22 @@
|
||||
<spirit:name>SLOT_1_AXIS_tdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TKEEP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tkeep</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TLAST</spirit:name>
|
||||
@@ -312,6 +384,14 @@
|
||||
<spirit:name>SLOT_1_AXIS_tlast</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TUSER</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>SLOT_1_AXIS_tuser</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TVALID</spirit:name>
|
||||
@@ -471,24 +551,6 @@
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_elaboratebd</spirit:name>
|
||||
<spirit:displayName>Elaborate BD</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:elaborate.bd</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_elaboratebd_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 20:56:44 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:526c76d0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_elaborateports</spirit:name>
|
||||
<spirit:displayName>Elaborate Ports</spirit:displayName>
|
||||
@@ -499,7 +561,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Mon Oct 28 20:55:52 UTC 2024</spirit:value>
|
||||
<spirit:value>Tue Oct 29 09:39:06 UTC 2024</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
@@ -555,10 +617,6 @@
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d1584098</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
@@ -579,10 +637,6 @@
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:d1584098</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>sim_type</spirit:name>
|
||||
<spirit:value>rtl</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
@@ -620,12 +674,92 @@
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tdest</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tstrb</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -641,7 +775,7 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tlast</spirit:name>
|
||||
<spirit:name>SLOT_0_AXIS_tuser</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -658,6 +792,43 @@
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -673,7 +844,39 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_0_AXIS_tready</spirit:name>
|
||||
<spirit:name>SLOT_1_AXIS_tdest</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tstrb</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -689,11 +892,27 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tdata</spirit:name>
|
||||
<spirit:name>SLOT_1_AXIS_tkeep</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tlast</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -709,7 +928,7 @@
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tlast</spirit:name>
|
||||
<spirit:name>SLOT_1_AXIS_tuser</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
@@ -728,25 +947,30 @@
|
||||
<spirit:name>SLOT_1_AXIS_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>SLOT_1_AXIS_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
@@ -767,9 +991,6 @@
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
@@ -1921,17 +2142,10 @@
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_elaboratebd_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_0/bd_3e86.bd</spirit:name>
|
||||
<spirit:userFileType>block_diagram</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_elaborateports_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_0/bd_3e86.bd</spirit:name>
|
||||
<spirit:name>bd_1/bd_3e86_0.bd</spirit:name>
|
||||
<spirit:userFileType>block_diagram</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
@@ -36233,7 +36447,6 @@
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>System ILA</xilinx:displayName>
|
||||
<xilinx:supportsDeferredElaboration>true</xilinx:supportsDeferredElaboration>
|
||||
<xilinx:coreRevision>14</xilinx:coreRevision>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="xilinx.com:ip:system_ila:1.0_ARCHIVE_LOCATION">/proj/xhdhdstaff/niloyr/debug_tools/IP3_niloyr_cs/DEV/output/internal/vivado/data/ip/xilinx</xilinx:tag>
|
||||
@@ -36241,38 +36454,16 @@
|
||||
<xilinx:tag xilinx:name="driver_mode">mixed</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESETN.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESETN.POLARITY" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TKEEP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TLAST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TREADY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.HAS_TSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.FREQ_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TKEEP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TLAST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TREADY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MON_TYPE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_MONITOR_SLOTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT_0_APC_EN" xilinx:valueSource="user"/>
|
||||
|
||||
-50
@@ -1,50 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define GC_XSDB_MSI_SL_SEL_WIDTH 8 /* Slave Select Width */
|
||||
`define GC_XSDB_MSI_ADDR_WIDTH 17 /* Address Width */
|
||||
`define GC_XSDB_MSI_BRST_WD_LEN_WIDTH 17
|
||||
`define GC_XSDB_MSI_DATA_WIDTH 16 /* Data Width */
|
||||
`define GC_XSDB_MSI_BRST_CNT_WIDTH 16 /* Burst Count Width */
|
||||
`define GC_XSDB_S_IPORT_WIDTH 37 /* Slave Port input interface width */
|
||||
|
||||
`define GC_XSDB_S_OPORT_WIDTH 17 /* Slave Port output interface width */
|
||||
|
||||
`define GC_XSDB_S_ADDR_WIDTH `GC_XSDB_MSI_ADDR_WIDTH /* Slave Addr width */
|
||||
`define GC_XSDB_S_DATA_WIDTH `GC_XSDB_MSI_DATA_WIDTH /* Slave Data width */
|
||||
|
||||
`define GC_IPORT_RST_IDX 0
|
||||
`define GC_IPORT_DCLK_IDX 1
|
||||
`define GC_IPORT_DEN_IDX 2
|
||||
`define GC_IPORT_DWE_IDX 3
|
||||
`define GC_IPORT_DADDR_IDX 4
|
||||
`define GC_IPORT_DI_IDX `GC_IPORT_DADDR_IDX+`GC_XSDB_S_ADDR_WIDTH
|
||||
`define GC_OPORT_RDY_IDX 0
|
||||
`define GC_OPORT_DO_IDX 1
|
||||
|
||||
`define GC_ICN_CTL_WIDTH 36
|
||||
`define GC_ICN_CMD4_WIDTH 3 + `GC_XSDB_MSI_SL_SEL_WIDTH+ `GC_XSDB_MSI_BRST_WD_LEN_WIDTH
|
||||
`define GC_ICN_CMD5_WIDTH 1 + `GC_XSDB_MSI_ADDR_WIDTH
|
||||
`define GC_ICN_CMD6_WIDTH `GC_XSDB_MSI_DATA_WIDTH
|
||||
|
||||
-107
@@ -1,107 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX6 "virtex6"
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
-552
@@ -1,552 +0,0 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
IYB6YMUpLRG67Sjv6mvLa0lJDa9M83l3pszRl7mNKDbm3JQq1xub6O3MDaxf4WUUoRlbj6UmK+ls
|
||||
5TT1rZBI42slY2M8d8G/12u9ZwNU0B9Ysw0A9f7H2/gZw+bCFVT2XOufXRtM8469/cgTzPdX6455
|
||||
eehGCOlFNzztUpCCBuo=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
a/7EQ8W4oMyysM5YxqT496V07EUaiHtsiTeMr+xwggjSXDgZBxdH9zS0ZwSbWGNiHwg8nXSCMzIT
|
||||
bUcHpdhYenBbvS6lFHc+OYja/GxpeotPfuhlGtbxN3fXZjw43NjXQI/ojWzEeo5ATyxr94HJ8sHD
|
||||
JA1CsMdglOQT6QZiD9TVY3RkvJVUxzXGEK/4umSz/Fc5dPh6gxxp7cVofeuJ+snpie5VVQQJoj4j
|
||||
tjyBNmGrIhr0Y0IV+3TgWooJ+r24u/VBLLE6lnzKxh0zYnJ5zUjs4eHuQTqInalvOAdYvbUSVqio
|
||||
Lzp5Bj6tb7kmD+A/qe86yLb4GbJzLTehOjcfdg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
Bm8/8qhHbJitBA3cG0BWpho8+cHGNcXoWDJOit3rZ1HeeUrKdPeoNkL9hkzhf9ZUHxLpbdTUCjkz
|
||||
uhVRU8UTRMdIPDzL/7HSIQXCDLdOz1nxeYLnDxwllTKxlZ4aRFdGbB0RXQ/iZNRQW2EmaDTFRcRV
|
||||
v0IjKU+PjNN3ZYIXCkA=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
bOGsLKO2Wjd3RNfQsUHtM5NcPLVbC6ZCRWCjSRRmyvuNhRjavSsIHbXkxLZHDjZnlnBuHdEZ8oea
|
||||
UHHfvapGkuZI0S7deY4irowm1O51aMUIiyYUNQJCaEgTDbqwyEsnkylKzYrQzRU/JO8aErpyMDc+
|
||||
dxDZeGYfZaF3iUzWGpDyEDaQh7d/AMIR890b/cRJ0JPD6S/d68REfiAIau8ZUsXiSCgHP9ot5Why
|
||||
yUKZOeml+FbZ2/zqywrRRADVaEpoSqu6cZux0zJFUOfKwG3rO6e2WYwBKucJSM1O+MXqHqUBqEfl
|
||||
IHl8aYzdxpc89jXiMIYfoqN06f8LwbIAKe3Z+w==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
xyJ+44oGcnu3f/PRr5Q/pt05L20B492JqgiTtcs5oGrsK7nBtr3Jek5JEMvW6gatRMUMnyBEipiF
|
||||
gspt+3c11bhyA0kxxX/8oyNTxGgVhXNyL8HzbkDekMgwRooksQIxmtBQVoCBuyCmgnBOavlrGQRt
|
||||
FtwkHEj4CcUeXXGnFtAt+WOYFScFD17WfS2yPJ5BpD82DvvacbCh7Hbm8sieB2ImG0NiCZXJ2sTF
|
||||
lxRVW8XI4p2q8xA0iSwcF5ZUDD8UmYwHHwFaz9VOXtg3i/iphI/xnKYZ2IQeHkkRf3JRQEAhLQCN
|
||||
mywjCvcVbMSrJkkJ6lHrazZzzBU8tJ9SXhvc1A==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
DKpQGvLhbUl8BJ/8XLn/tPRtGzCl6Z5B9dlBIZ3hIdMpvX5L6qTHJiPL+EPJzvKR3hwn+y3Kf0/e
|
||||
56tD0N9yqf/8HSBzUPN1Wx83eiE7+pWNxuGq7e15dNN7e3+AcR7gjUu0hLG5jSqOt75iiFr0vqqy
|
||||
UPb39HUFrCDaIRNh0fCFdGbydh7zEuizbnn7GRErU0r//wJ+WqhZsjKAuSH/9rkJXt5VJzrFRh2H
|
||||
2zZzduUfRWhphNTH09M8QAQ5RSWmlr7t9fXON4HIIaNpt14zvilBmCZgEfyV1N7+Mbi8zISGSVwM
|
||||
r20FpLJcMjFy8H4kZ7SMF51dIlCCySUMitZhBw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ahGj9cu5vw+TGhDRETTpUmguNUrGkzj4c4HpfbBQWexaOi1CnxDewq4mIuyo2pPRt9bsxMyxinAi
|
||||
yqfZSys3iKpMLTF2rLlaJR5DR+s7MHg3TXo6DwE4YOUz2kUn+kcmB5Oipr2uxn5fY/2OTA6236rk
|
||||
kg96Xfcnb3hsRdNnyl3s8r1r/GO6lcYCfWw2HtuVB73JqZOdMK5WQnRs2nCzyarDak52q8w92CuR
|
||||
jtBAO6iM8C8YYYtdY3bZrNoY2ErKwC2x21gWULEUfsaHyjjhoA1gN+VnA1jThgYsbf0kWw13Grhs
|
||||
2COb8mAkB/0fC26SxfxSy30x8trX0jLDnfntAQ==
|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
pM202SIs14RGJlgktq4skB0l7ESlGSPOj1+hAC77mcDHHrczLsAhEpxsiJCrX4tT1I8gJAEoUAhT
|
||||
2AzFczZHKP8ix8wKM9R2i6LZSGPqwG9iMYU/dt/a2tE9vfVY+OxeI0NfGXBvslCOEUGuPq0cQ0cw
|
||||
fSFkfZVVzwr6bhw/htrvJgxFLZKoinkKaocnUwx9C7QHy8rnQ4M8wUbcwoxHDObwJaC6LyVWMmZu
|
||||
kMgZFSpo6p7KOE051S7v8SN2jC64Qu804IoG5zXsnLp60dS4+1fgc7fwF+IiN4mOjBz208J/gcB6
|
||||
0Zjf5PrRbObEBaQt8a9CnelDkWVdP3uTr1rSFz+syFbYPJ/3XU2G/yLmk16QYP9kCQo9CAcIjwxh
|
||||
g41o91RxGZj8PwCpcnZrAoW7se6+/H5h2JrNvoOz8Yr09ZkOhWM0r75h8Rx3OyutUqeqr3BQ1b9B
|
||||
lvB/+l6p6intfTshH8BsTtE0j292jiNGV5cvexC4cczkPuzrIeMxa/xJ
|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
eSvh9J2q6NyrGpZqUatGKIA8QDMInI2iwKgziwfCT+i9aojxHhLpFdTm0zLW6vVDbs/IusTTBrYn
|
||||
NVfkcSUH5/jvLRUwLbq9vzH+BhvxZBvdurXPgSJdE/TAka47qAK1KWzgbQ6eoz88SN7MyuoSGGc2
|
||||
6gS0Ba5hhKYx1b8sr66Gjx3DlfaRtcEogEfV8f3DF6j6eL2oGyE6eN3jJQqh8Pb+VBypaE4ia9pR
|
||||
761fYKzcrhd3nvqYI+jRFosC0ZHv3akRZ/GMMOUX9fnkYWn3o4X9t46tehxqU8PXPrS3v/ZJ5wrY
|
||||
YQ/jig9XDE4QndCSZD1niwWxZJrJd1mXs1KKGg==
|
||||
|
||||
`pragma protect key_keyowner = "Synplicity", key_keyname = "SYNP15_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ff7t8AbFHBpUzmzv37xcV3BaELGXwW2FFoCl9wmbcAMmSLJEeoiYqjiI3XDM4XpMM3cFNM8gQmKz
|
||||
BgEuusWTof+slNUrSsJ5oD354i7b4BucHhOJi1f+LOwqns8ZlfE/Rrpmykq3ApSBIOhbi9mNKfnK
|
||||
0MBBVAY6hK/VLC5VYOy/Nhmbs3uqrr3hY4m+IK3Chy3QTHRdwhQwtRH2hUniNN2nHd1JIS4VwB8x
|
||||
uPCb97uEaIy8cz6h1SApBmWrY9IZKiXvZnBlqAzoVGxsqGB41TtpIISbliL2hGXUFSu0bz8RHT2F
|
||||
fkM9u94uhLFDP/QYjq/SfpByClx8fogg7ejfDA==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-PREC-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
oBc5fYhhP4GDV60D8m6mIIi+6Xspsu6fa6mpRPbQL3lyyZOIW7aY9ehXKE4SewCv0/fpmHMByAsF
|
||||
aFhoGiVGdHT2TtQShdlc5CHrugjHogcTwVhX0awKmb62UeeyTfMrM2krGBcv+KTY+E9Yt4zJZAVM
|
||||
Sf+2Tmup8qb8oKz98yBNuBAlfxqK/VJZfPBeAYq5W5l7vgUBXOhnsiIKqnEuaPcfRrrjrrsrueT9
|
||||
RmvfXIlDjIIC1Vo8LUH+sn4SFtvEa6+9wj+hYFhalOtpexbpZgcDdBcHxxVsqh4fdv9fY6R1msRB
|
||||
ZZFKiIK50d7XvGw4Rs5DAg9ESYyF7BOlcRBOsg==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25472)
|
||||
`pragma protect data_block
|
||||
/9vfmgSxR/Rz5jH6WG+Vbr4TobbsOI1owrDDlkeEUmRviechxnb4JeBm0rumqx23QCmYo6p2Q00o
|
||||
BMwgC4UHixTsIVC3K7DTr0QzFajBYbdnkynjCejGnjlIjxdxz5qf12AePggB4LJXEx0Lv/MKJxp9
|
||||
OiAMa6w/YLl34eImd2P3vCX8r2jJnF3nZlOaW53bqZoGq8TzVQyk5lHWgkwIquCYMRUxSmLSrVWD
|
||||
i2/BnIBWZYq2Jo7PGTLaKk9zgjogdKiVWZD48olniusa673x30stQ0i2WLTbpk8wOt1RTSS48DWE
|
||||
cOFtEK7fzyZgIHPXta5+tHQ8HNf6Q6Aydb1F4d8Eidlaetp17hoGLE2Zdli/H8cY4TQmh/pkD13/
|
||||
B8jLAD286BTywt7XCSPGU+GkJH7+zq/qQQuNPKXCFRzahVkJ0vEgZFiCGEE7192SgHZ7hI1eLG+Z
|
||||
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|
||||
/MYM02wyZUs3ivY8zw6Y1B4XISjGf5ff3Smo3xLtvu5dnBHnxb2nywTNv4KFzwh0HVB8z/eTLrs1
|
||||
5ACXQdKRPCQefxVeqm1vEigm9zoYQ+3gkByG9RNOdVi7pAOwAtawfcWtvLdinYsKFU9oUoEFF9YZ
|
||||
WEP6gfy4Dd/YNTLVxp7v0721mnHz4gSXuwzPkJ3XAUMCUXMr6PAS3pT3Mdv15Rb/n7fc3PUoodHv
|
||||
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|
||||
0+s30q0sbKeDJVP7x8yaZxIpfVhmak+xMx6A4LOKZSAKYUvnZWN+Au3MIUVU/FP6ZMCy9Gzoxjh3
|
||||
WLFLPqwijIuFmOAxjKa0U8PBKSg2zw8OI4lbAZdVHizkBDHxnb6Y0B+AzWVyBXJUxc0dvWsw4wPc
|
||||
SPEKU/Ms9fJZof3cvJhpYjSnvuDEVT6iqpXm35Pbum1vTzYJk7eRcuAEnuyBcDTYTZ0zh6a/8MzZ
|
||||
cZpleg1Q5M5lyogqAr16SYDpY4B44PxPRvm29ZzlNe/+IuwrCFJt2JVBrfFlZMSlINQT6nlUf0v7
|
||||
YIhFGdSJ1jPt8Th3dj2vfU1BjIzYLz/MtJj2qNqugc4LD72XOIOe/SNUvfVot0iSwwTpD2+pNJA4
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Fz7NLD/AcJ5KWCjjnp62PwSMSCo1Mf5hPPlvLSqFPNAy/OqJzqNRB7w5ygvU0bKTvkavspJXJ2Ic
|
||||
Cqmq0fwTVm9JR3dJi7E0/JN3WxmMcIt/dS597bIDwhH40XQe74/tuG0lyfxwIyX61wLuLqDQKTZO
|
||||
dXvGorweqWqpLPunjMTMvcos4GPDJv/oze8d8TnWWIShTM3TDbUdLMtS1ZENVTTgiJOMlZUYpQwh
|
||||
QsLtTVCakE0X2Fd+ndlLOaNQ5Hs0AfVEchJi3BPsclMlaeMMloFTpWEOxh4dKtr4b8omj/4Isv0v
|
||||
YuNPh8hTSNNwHuFOxhThNWP9xty6OLGAGE/DpyV4fugyhS6bJa1SAhw2PJLBS1KbuNa43nyed+dB
|
||||
pxzfkgUlD/Z3fzgalS5187HZ2gqyuDzwSCIsT4Fbd/xM5fs63Q8vRA6LK3Uq3KhT5Cc0IHcCIVbb
|
||||
Kwa2RBpN0ZePJz9yjIt1vnjefVoKHfXpYBU/WpCRD1qgPSsiJlDiBENnt2Kq32puuR9zSNIF2qNK
|
||||
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|
||||
8MGne2ScqnRQD7y6UD+XFOBrwm0EewYVf4JmqdskW7XqsZY0hm5r9XVC1qLTlraQs0eOpjc1Pq6C
|
||||
srrj2s1e1B8T1JBPWy3WF2dUhr1srf4W5giere64zBRF7RTTaLyWSQuzma34CSUzbnsj4b/LGAq6
|
||||
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|
||||
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|
||||
BhwBbcGmIc67l9UWmqC3M/ziy81BwWUkLi9GpI9gMT2Po0lbRVskqyzl/JktH/ztr+mJBR5qEI4e
|
||||
iwrAW1z9wxjGFN6zN4IU4SVdC/QiIbsoAbCxz60B6SP/USxzv27yGOKx9qc9w+L0cgfnATCgKqXz
|
||||
hjrIS/e6xjYx+S2oaJp2yBtrEvsxQLtS4arpZQOuxnvsBTtz3GM95iMTH2UQmSI+Fs7KeWPaM8Gn
|
||||
kbOreE33M6ag5jVt+wLYRVdlfQvhvN/m7FHkQzDRSBBi/ErSm/quYqIBtPfklveI7T2GG0e4d2jg
|
||||
ndAQkjOj17Wl8GqFLrni/sCFaMw+PBkR1LT17fHnWaBTAYNZhx4NMzHXarCEibSziJZGVOuXSMjA
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
lMWloSrmK+qIIsXipXom9wuMlI3dXWkZCKGNgye6v6AbkUAcfaqzARGqiakKyEYW7fSvrSDxvYVM
|
||||
dlIryOIRdEwKS7U2TJsrnc6GCGKKnxHh1NHhdKp2Yo6xHhswvsAenjGAEkxrPUX0ppvAkYVX9qDh
|
||||
jwBD0RjaCpRcwxx9oPjo8nN8tVf8WYJxOB0QcXLWpS51AXfEAbfwoLJS63mdLOAMjVGwxW5vqzcb
|
||||
HLCTw0ZPrPjbwFkMJbz67B/XpMPZy2maf2nwdg6cdHgsNb+5Ut3Y9ng0MMoxNzzNzQS103y4OyBA
|
||||
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|
||||
eprrM9DQjWQZbjyqkujHXlp1CauZwE6omxJ1z2oSAa8ZUOcbNEi4BrIH+Dk81cnnU+ZteIKstGCX
|
||||
n3nvhsz2cCLSPc+E/R1fJDJiUeSTcpHwIDxkV2vcZT59En2OkNdIy9J7DCmP91elMjOu4nf6Pi7T
|
||||
XcRX0n5IlkKhR/kPtGyFu5jhLnRnBfIAHIYbAAo9b57/4cmlaMykL0VKMIS7Ee8LaYLjnuczc5EX
|
||||
Xtkem30IXGBbDtBCi7SBQ3f9hKZqP77iv8P6mwM93hjh7s+gZVyAHmFuuoEE2M9Q+rI/CSnCMGuy
|
||||
GTEbsmICQKOxqW2t1F/wufELT+Tz72Tc13g8Hqp0ES46cqzBf4/HvdsHjbXShBuYUirIIkWyBtyn
|
||||
m+jWaJBF84xa2GzA3KrjG8JsqGeu3Ftqa8ui/sD/gG5HPsLcr2o1rJM7TfIgbWBFq+tU3SDDabBx
|
||||
kd8FaOg3evZuBQE99GNLVgaozPOTt7d4NeqlfsWnyCtgWaEO83LqAzxZpq23XwGdI7IgjQGt5i+l
|
||||
x025q6WnJBixe+KH/VkoOOuFNOyAPWZzw4Ecfyvb20rs4d4IbPfONNjnd9Gq70rqJvsD8mtm9MJV
|
||||
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|
||||
HyTNHT44r/NEs04DgTuxluhivbtevtVSEBinQNtTYyXk/AoUHIywHHe3M4hs9Z+VUZsjvoTaqrBb
|
||||
wKw55iU76pnbjuyT/YKBsR6cXrIuYV4/Y3DELxe61XYeLhrx1P9BOGPy+ZLGBkcmsPKYCyNMFteN
|
||||
DznfH/+dGN3z2HhnatAuS/tTtrZncMBX6OHfAH9+8NE66XrjCoHNXykVbNsyEyx77a+jNVaH2NtN
|
||||
Kv9YB8etHxHw/3e71djAYtdelBoicgTw6ChsxOoxsGCCnLAo5QRKTUA5/C12vbOjzAh0urBOQxCN
|
||||
8oe7kK9UnYCLr8ugczWLu2p+TE5DxeBQlAwVL6NKw8UWxYH/A4fI1F1EHdrzC59GIgNz2gRvySd3
|
||||
QGA1UWFpiQDE0xtfs62NXptvYs/aowduC6J9xsMFR0LcPnW5WjEJ+/c4oPasc550I+P3Ofm66eUB
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
6QrgZDu16PWp2buBRAMUj4ktBh//jSl6h4BwKUHR3kiNh1/4Cnd9/wINx7cDK4lUtcg=
|
||||
`pragma protect end_protected
|
||||
-1241
File diff suppressed because it is too large
Load Diff
-104
@@ -1,104 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2011/04/26
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* General functions used by other Labtools IP cores. Functions will
|
||||
* be added as needed.
|
||||
*
|
||||
*Notes:
|
||||
* Include the file inside the Verilog module after the module and port
|
||||
* section. Do not include at the top of the module.
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
`include "ltlib_v1_0_0_ver.vh"
|
||||
|
||||
function integer clogb2;
|
||||
input integer depth;
|
||||
integer d;
|
||||
begin
|
||||
if (depth == 0)
|
||||
clogb2 = 1;
|
||||
else
|
||||
begin
|
||||
d = depth;
|
||||
for (clogb2=0; d > 0; clogb2 = clogb2+1)
|
||||
d = d >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function string_contains;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] familyName;
|
||||
input [`FAMILY_NAME_LENGTH*8-1:0] expectedName;
|
||||
input integer expectedLength;
|
||||
integer i;
|
||||
integer j;
|
||||
reg temp_contain;
|
||||
begin
|
||||
string_contains = 1;
|
||||
temp_contain = 0;
|
||||
for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)
|
||||
begin
|
||||
if (familyName[(8*i)+:8] == expectedName[0+:8])
|
||||
begin
|
||||
temp_contain = 1;
|
||||
for (j=0; j<expectedLength; j=j+1)
|
||||
begin
|
||||
if (familyName[((8*i)+(8*j))+:8] != expectedName[(8*j)+:8])
|
||||
begin
|
||||
temp_contain = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if (temp_contain == 1)
|
||||
begin
|
||||
string_contains = 1;
|
||||
i = `FAMILY_NAME_LENGTH;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_bscane2;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_bscane2 = 1;
|
||||
else
|
||||
supports_bscane2 = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_bufr;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_bufr = 1;
|
||||
else
|
||||
supports_series7_bufr = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer supports_series7_startup;
|
||||
input [`FAMILY_NAME_LENGTH-1:0] familyName;
|
||||
begin
|
||||
if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
|
||||
supports_series7_startup = 1;
|
||||
else
|
||||
supports_series7_startup = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
-106
@@ -1,106 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
-7910
File diff suppressed because it is too large
Load Diff
-1045
File diff suppressed because it is too large
Load Diff
-124
@@ -1,124 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*******************************************************************************
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2011/10/14
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Verilog functions required by ila_lib
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
function integer size_of_data;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
integer i;
|
||||
begin
|
||||
size_of_data = match_width_string[0+:16]+1;
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
if (match_tpid_string[(16*(i))+:16] > match_tpid_string[(16*(i-1))+:16])
|
||||
size_of_data = size_of_data + match_width_string[(match_tpid_string[(i*`GC_TRIG_TYPEID_VEC_W)+:16]*16)+:16]+1;
|
||||
end
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
function integer match_units_count;
|
||||
input integer num_probes;
|
||||
input [`GC_MU_CNT_VEC_ARRAY_W-1:0] match_cnt_string;
|
||||
integer i;
|
||||
begin
|
||||
match_units_count = match_cnt_string[0+:4]+1;
|
||||
for (i=1; i<num_probes; i=i+1)
|
||||
begin
|
||||
match_units_count = match_units_count + match_cnt_string[(4*i)+:4]+1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [255:0] match_tpid;
|
||||
// Cast as bit16. Replace with null_value if not qualified.
|
||||
input [15:0] arg_ddr;
|
||||
input [15:0] arg;
|
||||
input qual;
|
||||
input [15:0] val;
|
||||
integer i;
|
||||
integer j;
|
||||
integer arg_temp;
|
||||
begin
|
||||
arg_temp = qual ? arg_ddr : arg;
|
||||
|
||||
for (i=0; i<arg_temp; i=i+1)
|
||||
begin
|
||||
match_tpid[i*16+:16] = val[15:0];
|
||||
end
|
||||
for (j=arg_temp; j<16; j=j+1)
|
||||
begin
|
||||
match_tpid[j*16+:16] = 16'h0000;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer match_units_count_en;
|
||||
input integer num_mu;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
//match_units_count = match_cnt_string[0+:2]+1;
|
||||
match_units_count_en = 0;
|
||||
for (i=0; i<num_mu; i=i+1)
|
||||
begin
|
||||
if (is_string[i] == 1'b1) begin
|
||||
match_units_count_en = match_units_count_en + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer size_of_data_less;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
if (is_string[0] == 1'b1) begin
|
||||
size_of_data_less = match_width_string[0+:16]+1;
|
||||
end else begin
|
||||
size_of_data_less = 0 ;
|
||||
end
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
if (is_string[i] == 1'b1) begin
|
||||
size_of_data_less = size_of_data_less + match_width_string[i*16+:16]+1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer size_of_data_full;
|
||||
input integer num_match_units;
|
||||
input [`GC_TRIG_WIDTH_VEC_ARRAY_W-1:0] match_width_string;
|
||||
input [`GC_TRIG_TYPEID_VEC_ARRAY_W-1:0] match_tpid_string;
|
||||
input [1023:0] is_string;
|
||||
integer i;
|
||||
begin
|
||||
size_of_data_full = match_width_string[0+:16]+1;
|
||||
for (i=1; i<num_match_units; i=i+1)
|
||||
begin
|
||||
size_of_data_full = size_of_data_full + match_width_string[i*16+:16]+1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
-8410
File diff suppressed because it is too large
Load Diff
-3148
File diff suppressed because it is too large
Load Diff
-122
@@ -1,122 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (c) 2011 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*******************************************************************************
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2001/08/10
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* ILA constant values library
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
//--
|
||||
//-- ILA Pro command types:
|
||||
//--
|
||||
//-- These command values match those found in the documentation. The
|
||||
//-- CONTROL bus bit offset can be derived by adding CONTROL_OFFSET to
|
||||
//-- these values.
|
||||
//--
|
||||
`define READ_STATIC_STAT_CMD 0
|
||||
`define READ_DYNAMIC_STAT_CMD 1
|
||||
`define READ_DATA_CMD 2
|
||||
`define READ_TSTAMP_CMD 3
|
||||
`define WRITE_TRIG_SETUP_CMD 4
|
||||
`define WRITE_CAP_CTRL_SETUP_CMD 5
|
||||
`define WRITE_ENABLE_EXTCAP_CMD 6
|
||||
`define WRITE_DISABLE_EXTCAP_CMD 7
|
||||
`define WRITE_ARM_CMD 8
|
||||
`define WRITE_HALT_CMD 9
|
||||
`define WRITE_RESET_CMD 10
|
||||
`define WRITE_RESET_DCM_CMD 11
|
||||
`define RESERVED_0C_CMD 12
|
||||
`define RESERVED_0D_CMD 13
|
||||
`define RESERVED_0E_CMD 14
|
||||
`define WRITE_TSEQ_TRIGOUT 15
|
||||
`define WRITE_M0_SETUP_CMD 16
|
||||
`define WRITE_M1_SETUP_CMD 17
|
||||
`define WRITE_M2_SETUP_CMD 18
|
||||
`define WRITE_M3_SETUP_CMD 19
|
||||
`define WRITE_M4_SETUP_CMD 20
|
||||
`define WRITE_M5_SETUP_CMD 21
|
||||
`define WRITE_M6_SETUP_CMD 22
|
||||
`define WRITE_M7_SETUP_CMD 23
|
||||
`define WRITE_M8_SETUP_CMD 24
|
||||
`define WRITE_M9_SETUP_CMD 25
|
||||
`define WRITE_M10_SETUP_CMD 26
|
||||
`define WRITE_M11_SETUP_CMD 27
|
||||
`define WRITE_M12_SETUP_CMD 28
|
||||
`define WRITE_M13_SETUP_CMD 29
|
||||
`define WRITE_M14_SETUP_CMD 30
|
||||
`define WRITE_M15_SETUP_CMD 31
|
||||
|
||||
`define CONTROL_CMD_OFFSET 3
|
||||
|
||||
`define CFG_CLK_BIT 0
|
||||
`define CFG_DIN_BIT 1
|
||||
`define UNUSED_BIT 2
|
||||
`define CFG_DOUT_BIT 3
|
||||
`define READ_STATIC_STAT_CMD_BIT `READ_STATIC_STAT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_DYNAMIC_STAT_CMD_BIT `READ_DYNAMIC_STAT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_DATA_CMD_BIT `READ_DATA_CMD + `CONTROL_CMD_OFFSET
|
||||
`define READ_TSTAMP_CMD_BIT `READ_TSTAMP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_TRIG_SETUP_CMD_BIT `WRITE_TRIG_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_CAP_CTRL_SETUP_CMD_BIT `WRITE_CAP_CTRL_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_ENABLE_EXTCAP_CMD_BIT `WRITE_ENABLE_EXTCAP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_DISABLE_EXTCAP_CMD_BIT `WRITE_DISABLE_EXTCAP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_ARM_CMD_BIT `WRITE_ARM_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_HALT_CMD_BIT `WRITE_HALT_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_RESET_CMD_BIT `WRITE_RESET_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_RESET_DCM_CMD_BIT `WRITE_RESET_DCM_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0C_CMD_BIT `RESERVED_0C_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0D_CMD_BIT `RESERVED_0D_CMD + `CONTROL_CMD_OFFSET
|
||||
`define RESERVED_0E_CMD_BIT `RESERVED_0E_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_TSEQ_TRIGOUT_BIT `WRITE_TSEQ_TRIGOUT + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M0_SETUP_CMD_BIT `WRITE_M0_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M1_SETUP_CMD_BIT `WRITE_M1_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M2_SETUP_CMD_BIT `WRITE_M2_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M3_SETUP_CMD_BIT `WRITE_M3_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M4_SETUP_CMD_BIT `WRITE_M4_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M5_SETUP_CMD_BIT `WRITE_M5_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M6_SETUP_CMD_BIT `WRITE_M6_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M7_SETUP_CMD_BIT `WRITE_M7_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M8_SETUP_CMD_BIT `WRITE_M8_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M9_SETUP_CMD_BIT `WRITE_M9_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M10_SETUP_CMD_BIT `WRITE_M10_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M11_SETUP_CMD_BIT `WRITE_M11_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M12_SETUP_CMD_BIT `WRITE_M12_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M13_SETUP_CMD_BIT `WRITE_M13_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M14_SETUP_CMD_BIT `WRITE_M14_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
`define WRITE_M15_SETUP_CMD_BIT `WRITE_M15_SETUP_CMD + `CONTROL_CMD_OFFSET
|
||||
|
||||
//--
|
||||
//-- Delay of data due to trigger delay
|
||||
//--
|
||||
`define ILA_PRO_DATA_DELAY 9
|
||||
//--constant ILA_PRO_DATA_DELAY : integer := 8;
|
||||
|
||||
//-- Width of vector used to encode each Trigger Width value (see ila_core)
|
||||
`define GC_MAX_NUM_MU 1024
|
||||
`define GC_TRIG_WIDTH_VEC_W 16
|
||||
`define GC_TRIG_WIDTH_VEC_ARRAY_W `GC_TRIG_WIDTH_VEC_W*`GC_MAX_NUM_MU
|
||||
`define GC_TRIG_TYPEID_VEC_W 16
|
||||
`define GC_TRIG_TYPEID_VEC_ARRAY_W `GC_TRIG_TYPEID_VEC_W*`GC_MAX_NUM_MU
|
||||
`define GC_MU_CNT_VEC_W 4
|
||||
`define GC_MU_CNT_VEC_ARRAY_W `GC_MU_CNT_VEC_W*`GC_MAX_NUM_MU
|
||||
|
||||
//-- Width of vector used to encode each Trigger Width value (see ila_core)
|
||||
`define GC_TRIG_TYPE_ID_W 15
|
||||
|
||||
|
||||
//-- Static Status Width
|
||||
`define GC_STATIC_STAT_W 672
|
||||
|
||||
|
||||
-193171
File diff suppressed because it is too large
Load Diff
-638
@@ -1,638 +0,0 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
-638
@@ -1,638 +0,0 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (1'b0),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
-638
@@ -1,638 +0,0 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,tdo_int}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
-491
@@ -1,491 +0,0 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS+1)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (drck_bs),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE_temp_i),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0,idrck}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0,CAPTURE}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0,UPDATE_temp}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0,SHIFT}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0,RESET}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0,SEL}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0,TDI}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0,TDO}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0,tms_int}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0,itck}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0,runtest_int}),
|
||||
.m_bscan_bscanid ({bscanid_15[31:0],bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0],C_BSCANID})
|
||||
);
|
||||
end
|
||||
|
||||
-638
@@ -1,638 +0,0 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v3_0_0_bscan_switch
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscanid_en (bscanid_en_bs),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid_en (bscanid_en_int)
|
||||
);
|
||||
|
||||
assign bscanid_en_0 = bscanid_en_int;
|
||||
assign bscanid_en_1 = bscanid_en_int;
|
||||
assign bscanid_en_2 = bscanid_en_int;
|
||||
assign bscanid_en_3 = bscanid_en_int;
|
||||
assign bscanid_en_4 = bscanid_en_int;
|
||||
assign bscanid_en_5 = bscanid_en_int;
|
||||
assign bscanid_en_6 = bscanid_en_int;
|
||||
assign bscanid_en_7 = bscanid_en_int;
|
||||
assign bscanid_en_8 = bscanid_en_int;
|
||||
assign bscanid_en_9 = bscanid_en_int;
|
||||
assign bscanid_en_10 = bscanid_en_int;
|
||||
assign bscanid_en_11 = bscanid_en_int;
|
||||
assign bscanid_en_12 = bscanid_en_int;
|
||||
assign bscanid_en_13 = bscanid_en_int;
|
||||
assign bscanid_en_14 = bscanid_en_int;
|
||||
assign bscanid_en_15 = bscanid_en_int;
|
||||
end
|
||||
|
||||
-176
@@ -1,176 +0,0 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output update_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output capture_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output reset_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output runtest_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tms_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tck_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output tdi_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output sel_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output shift_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output drck_0,
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)input tdo_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output update_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output capture_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output reset_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output runtest_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tms_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tck_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output tdi_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output sel_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output shift_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output drck_1,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)input tdo_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output update_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output capture_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output reset_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output runtest_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tms_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tck_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output tdi_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output sel_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output shift_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output drck_2,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)input tdo_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output update_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output capture_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output reset_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output runtest_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tms_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tck_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output tdi_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output sel_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output shift_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output drck_3,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)input tdo_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output update_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output capture_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output reset_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output runtest_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tms_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tck_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output tdi_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output sel_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output shift_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output drck_4,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)input tdo_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output update_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output capture_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output reset_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output runtest_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tms_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tck_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output tdi_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output sel_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output shift_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output drck_5,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)input tdo_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output update_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output capture_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output reset_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output runtest_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tms_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tck_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output tdi_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output sel_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output shift_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output drck_6,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)input tdo_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output update_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output capture_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output reset_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output runtest_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tms_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tck_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output tdi_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output sel_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output shift_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output drck_7,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)input tdo_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output update_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output capture_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output reset_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output runtest_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tms_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tck_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output tdi_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output sel_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output shift_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output drck_8,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)input tdo_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output update_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output capture_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output reset_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output runtest_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tms_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tck_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output tdi_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output sel_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output shift_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output drck_9,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)input tdo_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output update_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output capture_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output reset_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output runtest_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tms_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tck_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output tdi_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output sel_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output shift_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output drck_10,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)input tdo_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output update_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output capture_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output reset_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output runtest_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tms_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tck_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output tdi_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output sel_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output shift_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output drck_11,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)input tdo_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output update_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output capture_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output reset_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output runtest_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tms_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tck_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output tdi_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output sel_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output shift_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output drck_12,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)input tdo_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output update_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output capture_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output reset_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output runtest_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tms_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tck_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output tdi_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output sel_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output shift_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output drck_13,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)input tdo_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output update_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output capture_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output reset_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output runtest_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tms_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tck_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output tdi_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output sel_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output shift_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output drck_14,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)input tdo_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output update_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output capture_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output reset_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output runtest_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tms_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tck_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output tdi_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output sel_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output shift_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output drck_15,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)input tdo_15,
|
||||
-491
@@ -1,491 +0,0 @@
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 3)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 4)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 5)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 6)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 7)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 8)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 9)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 10)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 11)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 12)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 13)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 14)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 15)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
else if (C_NUM_BSCAN_MASTER_PORTS == 16)
|
||||
begin
|
||||
(* DONT_TOUCH = "TRUE" *)xsdbm_v2_0_bscan_switch_vec
|
||||
#(
|
||||
.PORTS (C_NUM_BSCAN_MASTER_PORTS)
|
||||
) bscan_switch_vec
|
||||
(
|
||||
//.rst_b (1'b1),
|
||||
//.clk (xsdb_clk),
|
||||
.s_bscan_drck (DRCK),
|
||||
.s_bscan_capture (capture_bs),
|
||||
.s_bscan_update (UPDATE),
|
||||
.s_bscan_shift (shift_bs),
|
||||
.s_bscan_reset (reset_bs),
|
||||
.s_bscan_sel (sel_bs),
|
||||
.s_bscan_tdi (tdi_bs),
|
||||
.s_bscan_tdo (tdo_bs),
|
||||
.s_bscan_tms (tms_bs),
|
||||
.s_bscan_tck (itck_i),
|
||||
.s_bscan_runtest (runtest_bs),
|
||||
.s_bscan_bscanid (bscanid),
|
||||
.m_bscan_drck ({drck_15,drck_14,drck_13,drck_12,drck_11,drck_10,drck_9,drck_8,drck_7,drck_6,drck_5,drck_4,drck_3,drck_2,drck_1,drck_0}),
|
||||
.m_bscan_capture ({capture_15,capture_14,capture_13,capture_12,capture_11,capture_10,capture_9,capture_8,capture_7,capture_6,capture_5,capture_4,capture_3,capture_2,capture_1,capture_0}),
|
||||
.m_bscan_update ({update_15,update_14,update_13,update_12,update_11,update_10,update_9,update_8,update_7,update_6,update_5,update_4,update_3,update_2,update_1,update_0}),
|
||||
.m_bscan_shift ({shift_15,shift_14,shift_13,shift_12,shift_11,shift_10,shift_9,shift_8,shift_7,shift_6,shift_5,shift_4,shift_3,shift_2,shift_1,shift_0}),
|
||||
.m_bscan_reset ({reset_15,reset_14,reset_13,reset_12,reset_11,reset_10,reset_9,reset_8,reset_7,reset_6,reset_5,reset_4,reset_3,reset_2,reset_1,reset_0}),
|
||||
.m_bscan_sel ({sel_15,sel_14,sel_13,sel_12,sel_11,sel_10,sel_9,sel_8,sel_7,sel_6,sel_5,sel_4,sel_3,sel_2,sel_1,sel_0}),
|
||||
.m_bscan_tdi ({tdi_15,tdi_14,tdi_13,tdi_12,tdi_11,tdi_10,tdi_9,tdi_8,tdi_7,tdi_6,tdi_5,tdi_4,tdi_3,tdi_2,tdi_1,tdi_0}),
|
||||
.m_bscan_tdo ({tdo_15,tdo_14,tdo_13,tdo_12,tdo_11,tdo_10,tdo_9,tdo_8,tdo_7,tdo_6,tdo_5,tdo_4,tdo_3,tdo_2,tdo_1,tdo_0}),
|
||||
.m_bscan_tms ({tms_15,tms_14,tms_13,tms_12,tms_11,tms_10,tms_9,tms_8,tms_7,tms_6,tms_5,tms_4,tms_3,tms_2,tms_1,tms_0}),
|
||||
.m_bscan_tck ({tck_15,tck_14,tck_13,tck_12,tck_11,tck_10,tck_9,tck_8,tck_7,tck_6,tck_5,tck_4,tck_3,tck_2,tck_1,tck_0}),
|
||||
.m_bscan_runtest ({runtest_15,runtest_14,runtest_13,runtest_12,runtest_11,runtest_10,runtest_9,runtest_8,runtest_7,runtest_6,runtest_5,runtest_4,runtest_3,runtest_2,runtest_1,runtest_0}),
|
||||
.m_bscan_bscanid ({bscanid_15[31:0],bscanid_14[31:0],bscanid_13[31:0],bscanid_12[31:0],bscanid_11[31:0],bscanid_10[31:0],bscanid_9[31:0],bscanid_8[31:0],bscanid_7[31:0],bscanid_6[31:0],bscanid_5[31:0],bscanid_4[31:0],bscanid_3[31:0],bscanid_2[31:0],bscanid_1[31:0],bscanid_0[31:0]})
|
||||
);
|
||||
end
|
||||
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)output bscanid_en_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)output bscanid_en_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)output bscanid_en_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)output bscanid_en_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)output bscanid_en_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)output bscanid_en_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)output bscanid_en_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)output bscanid_en_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)output bscanid_en_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)output bscanid_en_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)output bscanid_en_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)output bscanid_en_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)output bscanid_en_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)output bscanid_en_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)output bscanid_en_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)output bscanid_en_15,
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
(* BSCAN_SLAVE_INDEX = 0 *)input [31:0] bscanid_0,
|
||||
(* BSCAN_SLAVE_INDEX = 1 *)input [31:0] bscanid_1,
|
||||
(* BSCAN_SLAVE_INDEX = 2 *)input [31:0] bscanid_2,
|
||||
(* BSCAN_SLAVE_INDEX = 3 *)input [31:0] bscanid_3,
|
||||
(* BSCAN_SLAVE_INDEX = 4 *)input [31:0] bscanid_4,
|
||||
(* BSCAN_SLAVE_INDEX = 5 *)input [31:0] bscanid_5,
|
||||
(* BSCAN_SLAVE_INDEX = 6 *)input [31:0] bscanid_6,
|
||||
(* BSCAN_SLAVE_INDEX = 7 *)input [31:0] bscanid_7,
|
||||
(* BSCAN_SLAVE_INDEX = 8 *)input [31:0] bscanid_8,
|
||||
(* BSCAN_SLAVE_INDEX = 9 *)input [31:0] bscanid_9,
|
||||
(* BSCAN_SLAVE_INDEX = 10 *)input [31:0] bscanid_10,
|
||||
(* BSCAN_SLAVE_INDEX = 11 *)input [31:0] bscanid_11,
|
||||
(* BSCAN_SLAVE_INDEX = 12 *)input [31:0] bscanid_12,
|
||||
(* BSCAN_SLAVE_INDEX = 13 *)input [31:0] bscanid_13,
|
||||
(* BSCAN_SLAVE_INDEX = 14 *)input [31:0] bscanid_14,
|
||||
(* BSCAN_SLAVE_INDEX = 15 *)input [31:0] bscanid_15,
|
||||
-50
@@ -1,50 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define GC_XSDB_MSI_SL_SEL_WIDTH 8 /* Slave Select Width */
|
||||
`define GC_XSDB_MSI_ADDR_WIDTH 17 /* Address Width */
|
||||
`define GC_XSDB_MSI_BRST_WD_LEN_WIDTH 17
|
||||
`define GC_XSDB_MSI_DATA_WIDTH 16 /* Data Width */
|
||||
`define GC_XSDB_MSI_BRST_CNT_WIDTH 16 /* Burst Count Width */
|
||||
`define GC_XSDB_S_IPORT_WIDTH 37 /* Slave Port input interface width */
|
||||
|
||||
`define GC_XSDB_S_OPORT_WIDTH 17 /* Slave Port output interface width */
|
||||
|
||||
`define GC_XSDB_S_ADDR_WIDTH `GC_XSDB_MSI_ADDR_WIDTH /* Slave Addr width */
|
||||
`define GC_XSDB_S_DATA_WIDTH `GC_XSDB_MSI_DATA_WIDTH /* Slave Data width */
|
||||
|
||||
`define GC_IPORT_RST_IDX 0
|
||||
`define GC_IPORT_DCLK_IDX 1
|
||||
`define GC_IPORT_DEN_IDX 2
|
||||
`define GC_IPORT_DWE_IDX 3
|
||||
`define GC_IPORT_DADDR_IDX 4
|
||||
`define GC_IPORT_DI_IDX `GC_IPORT_DADDR_IDX+`GC_XSDB_S_ADDR_WIDTH
|
||||
`define GC_OPORT_RDY_IDX 0
|
||||
`define GC_OPORT_DO_IDX 1
|
||||
|
||||
`define GC_ICN_CTL_WIDTH 36
|
||||
`define GC_ICN_CMD4_WIDTH 3 + `GC_XSDB_MSI_SL_SEL_WIDTH+ `GC_XSDB_MSI_BRST_WD_LEN_WIDTH
|
||||
`define GC_ICN_CMD5_WIDTH 1 + `GC_XSDB_MSI_ADDR_WIDTH
|
||||
`define GC_ICN_CMD6_WIDTH `GC_XSDB_MSI_DATA_WIDTH
|
||||
|
||||
-39
@@ -1,39 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define Values for Verilog instatiation of icn2xsdb_mstrbr_ver
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
`define TARGET_HIGH_INDEX 15
|
||||
`define TARGET_CORE_ID_HIGH_INDEX 15
|
||||
`define TARGET_CORE_ID_LOW_INDEX 12
|
||||
`define TARGET_COMMAND_HIGH_INDEX 11
|
||||
`define TARGET_COMMAND_LOW_INDEX 8
|
||||
`define TARGET_COMMAND_GROUP_HIGH_INDEX 7
|
||||
`define TARGET_COMMAND_GROUP_LOW_INDEX 6
|
||||
`define TARGET_LOW_INDEX 6
|
||||
|
||||
`define TARGET_CORE_ID_WIDTH `TARGET_CORE_ID_HIGH_INDEX - `TARGET_CORE_ID_LOW_INDEX + 1
|
||||
`define TARGET_COMMAND_WIDTH `TARGET_COMMAND_HIGH_INDEX - `TARGET_COMMAND_LOW_INDEX + 1
|
||||
|
||||
`define ICON_READ_STAT_CMD 0
|
||||
|
||||
|
||||
-192
@@ -1,192 +0,0 @@
|
||||
.update_0 (update_0),
|
||||
.capture_0 (capture_0),
|
||||
.reset_0 (reset_0),
|
||||
.runtest_0 (runtest_0),
|
||||
.tms_0 (tms_0),
|
||||
.tck_0 (tck_0),
|
||||
.tdi_0 (tdi_0),
|
||||
.sel_0 (sel_0),
|
||||
.shift_0 (shift_0),
|
||||
.drck_0 (drck_0),
|
||||
.tdo_0 (tdo_0),
|
||||
.bscanid_en_0 (bscanid_en_0),
|
||||
.update_1 (update_1),
|
||||
.capture_1 (capture_1),
|
||||
.reset_1 (reset_1),
|
||||
.runtest_1 (runtest_1),
|
||||
.tms_1 (tms_1),
|
||||
.tck_1 (tck_1),
|
||||
.tdi_1 (tdi_1),
|
||||
.sel_1 (sel_1),
|
||||
.shift_1 (shift_1),
|
||||
.drck_1 (drck_1),
|
||||
.tdo_1 (tdo_1),
|
||||
.bscanid_en_1 (bscanid_en_1),
|
||||
.update_2 (update_2),
|
||||
.capture_2 (capture_2),
|
||||
.reset_2 (reset_2),
|
||||
.runtest_2 (runtest_2),
|
||||
.tms_2 (tms_2),
|
||||
.tck_2 (tck_2),
|
||||
.tdi_2 (tdi_2),
|
||||
.sel_2 (sel_2),
|
||||
.shift_2 (shift_2),
|
||||
.drck_2 (drck_2),
|
||||
.tdo_2 (tdo_2),
|
||||
.bscanid_en_2 (bscanid_en_2),
|
||||
.update_3 (update_3),
|
||||
.capture_3 (capture_3),
|
||||
.reset_3 (reset_3),
|
||||
.runtest_3 (runtest_3),
|
||||
.tms_3 (tms_3),
|
||||
.tck_3 (tck_3),
|
||||
.tdi_3 (tdi_3),
|
||||
.sel_3 (sel_3),
|
||||
.shift_3 (shift_3),
|
||||
.drck_3 (drck_3),
|
||||
.tdo_3 (tdo_3),
|
||||
.bscanid_en_3 (bscanid_en_3),
|
||||
.update_4 (update_4),
|
||||
.capture_4 (capture_4),
|
||||
.reset_4 (reset_4),
|
||||
.runtest_4 (runtest_4),
|
||||
.tms_4 (tms_4),
|
||||
.tck_4 (tck_4),
|
||||
.tdi_4 (tdi_4),
|
||||
.sel_4 (sel_4),
|
||||
.shift_4 (shift_4),
|
||||
.drck_4 (drck_4),
|
||||
.tdo_4 (tdo_4),
|
||||
.bscanid_en_4 (bscanid_en_4),
|
||||
.update_5 (update_5),
|
||||
.capture_5 (capture_5),
|
||||
.reset_5 (reset_5),
|
||||
.runtest_5 (runtest_5),
|
||||
.tms_5 (tms_5),
|
||||
.tck_5 (tck_5),
|
||||
.tdi_5 (tdi_5),
|
||||
.sel_5 (sel_5),
|
||||
.shift_5 (shift_5),
|
||||
.drck_5 (drck_5),
|
||||
.tdo_5 (tdo_5),
|
||||
.bscanid_en_5 (bscanid_en_5),
|
||||
.update_6 (update_6),
|
||||
.capture_6 (capture_6),
|
||||
.reset_6 (reset_6),
|
||||
.runtest_6 (runtest_6),
|
||||
.tms_6 (tms_6),
|
||||
.tck_6 (tck_6),
|
||||
.tdi_6 (tdi_6),
|
||||
.sel_6 (sel_6),
|
||||
.shift_6 (shift_6),
|
||||
.drck_6 (drck_6),
|
||||
.tdo_6 (tdo_6),
|
||||
.bscanid_en_6 (bscanid_en_6),
|
||||
.update_7 (update_7),
|
||||
.capture_7 (capture_7),
|
||||
.reset_7 (reset_7),
|
||||
.runtest_7 (runtest_7),
|
||||
.tms_7 (tms_7),
|
||||
.tck_7 (tck_7),
|
||||
.tdi_7 (tdi_7),
|
||||
.sel_7 (sel_7),
|
||||
.shift_7 (shift_7),
|
||||
.drck_7 (drck_7),
|
||||
.tdo_7 (tdo_7),
|
||||
.bscanid_en_7 (bscanid_en_7),
|
||||
.update_8 (update_8),
|
||||
.capture_8 (capture_8),
|
||||
.reset_8 (reset_8),
|
||||
.runtest_8 (runtest_8),
|
||||
.tms_8 (tms_8),
|
||||
.tck_8 (tck_8),
|
||||
.tdi_8 (tdi_8),
|
||||
.sel_8 (sel_8),
|
||||
.shift_8 (shift_8),
|
||||
.drck_8 (drck_8),
|
||||
.tdo_8 (tdo_8),
|
||||
.bscanid_en_8 (bscanid_en_8),
|
||||
.update_9 (update_9),
|
||||
.capture_9 (capture_9),
|
||||
.reset_9 (reset_9),
|
||||
.runtest_9 (runtest_9),
|
||||
.tms_9 (tms_9),
|
||||
.tck_9 (tck_9),
|
||||
.tdi_9 (tdi_9),
|
||||
.sel_9 (sel_9),
|
||||
.shift_9 (shift_9),
|
||||
.drck_9 (drck_9),
|
||||
.tdo_9 (tdo_9),
|
||||
.bscanid_en_9 (bscanid_en_9),
|
||||
.update_10 (update_10),
|
||||
.capture_10 (capture_10),
|
||||
.reset_10 (reset_10),
|
||||
.runtest_10 (runtest_10),
|
||||
.tms_10 (tms_10),
|
||||
.tck_10 (tck_10),
|
||||
.tdi_10 (tdi_10),
|
||||
.sel_10 (sel_10),
|
||||
.shift_10 (shift_10),
|
||||
.drck_10 (drck_10),
|
||||
.tdo_10 (tdo_10),
|
||||
.bscanid_en_10 (bscanid_en_10),
|
||||
.update_11 (update_11),
|
||||
.capture_11 (capture_11),
|
||||
.reset_11 (reset_11),
|
||||
.runtest_11 (runtest_11),
|
||||
.tms_11 (tms_11),
|
||||
.tck_11 (tck_11),
|
||||
.tdi_11 (tdi_11),
|
||||
.sel_11 (sel_11),
|
||||
.shift_11 (shift_11),
|
||||
.drck_11 (drck_11),
|
||||
.tdo_11 (tdo_11),
|
||||
.bscanid_en_11 (bscanid_en_11),
|
||||
.update_12 (update_12),
|
||||
.capture_12 (capture_12),
|
||||
.reset_12 (reset_12),
|
||||
.runtest_12 (runtest_12),
|
||||
.tms_12 (tms_12),
|
||||
.tck_12 (tck_12),
|
||||
.tdi_12 (tdi_12),
|
||||
.sel_12 (sel_12),
|
||||
.shift_12 (shift_12),
|
||||
.drck_12 (drck_12),
|
||||
.tdo_12 (tdo_12),
|
||||
.bscanid_en_12 (bscanid_en_12),
|
||||
.update_13 (update_13),
|
||||
.capture_13 (capture_13),
|
||||
.reset_13 (reset_13),
|
||||
.runtest_13 (runtest_13),
|
||||
.tms_13 (tms_13),
|
||||
.tck_13 (tck_13),
|
||||
.tdi_13 (tdi_13),
|
||||
.sel_13 (sel_13),
|
||||
.shift_13 (shift_13),
|
||||
.drck_13 (drck_13),
|
||||
.tdo_13 (tdo_13),
|
||||
.bscanid_en_13 (bscanid_en_13),
|
||||
.update_14 (update_14),
|
||||
.capture_14 (capture_14),
|
||||
.reset_14 (reset_14),
|
||||
.runtest_14 (runtest_14),
|
||||
.tms_14 (tms_14),
|
||||
.tck_14 (tck_14),
|
||||
.tdi_14 (tdi_14),
|
||||
.sel_14 (sel_14),
|
||||
.shift_14 (shift_14),
|
||||
.drck_14 (drck_14),
|
||||
.tdo_14 (tdo_14),
|
||||
.bscanid_en_14 (bscanid_en_14),
|
||||
.update_15 (update_15),
|
||||
.capture_15 (capture_15),
|
||||
.reset_15 (reset_15),
|
||||
.runtest_15 (runtest_15),
|
||||
.tms_15 (tms_15),
|
||||
.tck_15 (tck_15),
|
||||
.tdi_15 (tdi_15),
|
||||
.sel_15 (sel_15),
|
||||
.shift_15 (shift_15),
|
||||
.drck_15 (drck_15),
|
||||
.tdo_15 (tdo_15),
|
||||
.bscanid_en_15 (bscanid_en_15),
|
||||
-192
@@ -1,192 +0,0 @@
|
||||
.update_0 (update_0),
|
||||
.capture_0 (capture_0),
|
||||
.reset_0 (reset_0),
|
||||
.runtest_0 (runtest_0),
|
||||
.tms_0 (tms_0),
|
||||
.tck_0 (tck_0),
|
||||
.tdi_0 (tdi_0),
|
||||
.sel_0 (sel_0),
|
||||
.shift_0 (shift_0),
|
||||
.drck_0 (drck_0),
|
||||
.tdo_0 (tdo_0),
|
||||
.bscanid_0 (bscanid_0),
|
||||
.update_1 (update_1),
|
||||
.capture_1 (capture_1),
|
||||
.reset_1 (reset_1),
|
||||
.runtest_1 (runtest_1),
|
||||
.tms_1 (tms_1),
|
||||
.tck_1 (tck_1),
|
||||
.tdi_1 (tdi_1),
|
||||
.sel_1 (sel_1),
|
||||
.shift_1 (shift_1),
|
||||
.drck_1 (drck_1),
|
||||
.tdo_1 (tdo_1),
|
||||
.bscanid_1 (bscanid_1),
|
||||
.update_2 (update_2),
|
||||
.capture_2 (capture_2),
|
||||
.reset_2 (reset_2),
|
||||
.runtest_2 (runtest_2),
|
||||
.tms_2 (tms_2),
|
||||
.tck_2 (tck_2),
|
||||
.tdi_2 (tdi_2),
|
||||
.sel_2 (sel_2),
|
||||
.shift_2 (shift_2),
|
||||
.drck_2 (drck_2),
|
||||
.tdo_2 (tdo_2),
|
||||
.bscanid_2 (bscanid_2),
|
||||
.update_3 (update_3),
|
||||
.capture_3 (capture_3),
|
||||
.reset_3 (reset_3),
|
||||
.runtest_3 (runtest_3),
|
||||
.tms_3 (tms_3),
|
||||
.tck_3 (tck_3),
|
||||
.tdi_3 (tdi_3),
|
||||
.sel_3 (sel_3),
|
||||
.shift_3 (shift_3),
|
||||
.drck_3 (drck_3),
|
||||
.tdo_3 (tdo_3),
|
||||
.bscanid_3 (bscanid_3),
|
||||
.update_4 (update_4),
|
||||
.capture_4 (capture_4),
|
||||
.reset_4 (reset_4),
|
||||
.runtest_4 (runtest_4),
|
||||
.tms_4 (tms_4),
|
||||
.tck_4 (tck_4),
|
||||
.tdi_4 (tdi_4),
|
||||
.sel_4 (sel_4),
|
||||
.shift_4 (shift_4),
|
||||
.drck_4 (drck_4),
|
||||
.tdo_4 (tdo_4),
|
||||
.bscanid_4 (bscanid_4),
|
||||
.update_5 (update_5),
|
||||
.capture_5 (capture_5),
|
||||
.reset_5 (reset_5),
|
||||
.runtest_5 (runtest_5),
|
||||
.tms_5 (tms_5),
|
||||
.tck_5 (tck_5),
|
||||
.tdi_5 (tdi_5),
|
||||
.sel_5 (sel_5),
|
||||
.shift_5 (shift_5),
|
||||
.drck_5 (drck_5),
|
||||
.tdo_5 (tdo_5),
|
||||
.bscanid_5 (bscanid_5),
|
||||
.update_6 (update_6),
|
||||
.capture_6 (capture_6),
|
||||
.reset_6 (reset_6),
|
||||
.runtest_6 (runtest_6),
|
||||
.tms_6 (tms_6),
|
||||
.tck_6 (tck_6),
|
||||
.tdi_6 (tdi_6),
|
||||
.sel_6 (sel_6),
|
||||
.shift_6 (shift_6),
|
||||
.drck_6 (drck_6),
|
||||
.tdo_6 (tdo_6),
|
||||
.bscanid_6 (bscanid_6),
|
||||
.update_7 (update_7),
|
||||
.capture_7 (capture_7),
|
||||
.reset_7 (reset_7),
|
||||
.runtest_7 (runtest_7),
|
||||
.tms_7 (tms_7),
|
||||
.tck_7 (tck_7),
|
||||
.tdi_7 (tdi_7),
|
||||
.sel_7 (sel_7),
|
||||
.shift_7 (shift_7),
|
||||
.drck_7 (drck_7),
|
||||
.tdo_7 (tdo_7),
|
||||
.bscanid_7 (bscanid_7),
|
||||
.update_8 (update_8),
|
||||
.capture_8 (capture_8),
|
||||
.reset_8 (reset_8),
|
||||
.runtest_8 (runtest_8),
|
||||
.tms_8 (tms_8),
|
||||
.tck_8 (tck_8),
|
||||
.tdi_8 (tdi_8),
|
||||
.sel_8 (sel_8),
|
||||
.shift_8 (shift_8),
|
||||
.drck_8 (drck_8),
|
||||
.tdo_8 (tdo_8),
|
||||
.bscanid_8 (bscanid_8),
|
||||
.update_9 (update_9),
|
||||
.capture_9 (capture_9),
|
||||
.reset_9 (reset_9),
|
||||
.runtest_9 (runtest_9),
|
||||
.tms_9 (tms_9),
|
||||
.tck_9 (tck_9),
|
||||
.tdi_9 (tdi_9),
|
||||
.sel_9 (sel_9),
|
||||
.shift_9 (shift_9),
|
||||
.drck_9 (drck_9),
|
||||
.tdo_9 (tdo_9),
|
||||
.bscanid_9 (bscanid_9),
|
||||
.update_10 (update_10),
|
||||
.capture_10 (capture_10),
|
||||
.reset_10 (reset_10),
|
||||
.runtest_10 (runtest_10),
|
||||
.tms_10 (tms_10),
|
||||
.tck_10 (tck_10),
|
||||
.tdi_10 (tdi_10),
|
||||
.sel_10 (sel_10),
|
||||
.shift_10 (shift_10),
|
||||
.drck_10 (drck_10),
|
||||
.tdo_10 (tdo_10),
|
||||
.bscanid_10 (bscanid_10),
|
||||
.update_11 (update_11),
|
||||
.capture_11 (capture_11),
|
||||
.reset_11 (reset_11),
|
||||
.runtest_11 (runtest_11),
|
||||
.tms_11 (tms_11),
|
||||
.tck_11 (tck_11),
|
||||
.tdi_11 (tdi_11),
|
||||
.sel_11 (sel_11),
|
||||
.shift_11 (shift_11),
|
||||
.drck_11 (drck_11),
|
||||
.tdo_11 (tdo_11),
|
||||
.bscanid_11 (bscanid_11),
|
||||
.update_12 (update_12),
|
||||
.capture_12 (capture_12),
|
||||
.reset_12 (reset_12),
|
||||
.runtest_12 (runtest_12),
|
||||
.tms_12 (tms_12),
|
||||
.tck_12 (tck_12),
|
||||
.tdi_12 (tdi_12),
|
||||
.sel_12 (sel_12),
|
||||
.shift_12 (shift_12),
|
||||
.drck_12 (drck_12),
|
||||
.tdo_12 (tdo_12),
|
||||
.bscanid_12 (bscanid_12),
|
||||
.update_13 (update_13),
|
||||
.capture_13 (capture_13),
|
||||
.reset_13 (reset_13),
|
||||
.runtest_13 (runtest_13),
|
||||
.tms_13 (tms_13),
|
||||
.tck_13 (tck_13),
|
||||
.tdi_13 (tdi_13),
|
||||
.sel_13 (sel_13),
|
||||
.shift_13 (shift_13),
|
||||
.drck_13 (drck_13),
|
||||
.tdo_13 (tdo_13),
|
||||
.bscanid_13 (bscanid_13),
|
||||
.update_14 (update_14),
|
||||
.capture_14 (capture_14),
|
||||
.reset_14 (reset_14),
|
||||
.runtest_14 (runtest_14),
|
||||
.tms_14 (tms_14),
|
||||
.tck_14 (tck_14),
|
||||
.tdi_14 (tdi_14),
|
||||
.sel_14 (sel_14),
|
||||
.shift_14 (shift_14),
|
||||
.drck_14 (drck_14),
|
||||
.tdo_14 (tdo_14),
|
||||
.bscanid_14 (bscanid_14),
|
||||
.update_15 (update_15),
|
||||
.capture_15 (capture_15),
|
||||
.reset_15 (reset_15),
|
||||
.runtest_15 (runtest_15),
|
||||
.tms_15 (tms_15),
|
||||
.tck_15 (tck_15),
|
||||
.tdi_15 (tdi_15),
|
||||
.sel_15 (sel_15),
|
||||
.shift_15 (shift_15),
|
||||
.drck_15 (drck_15),
|
||||
.tdo_15 (tdo_15),
|
||||
.bscanid_15 (bscanid_15),
|
||||
-117
@@ -1,117 +0,0 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2008 Xilinx, Inc.
|
||||
* This design is confidential and proprietary of Xilinx, All Rights Reserved.
|
||||
*-----------------------------------------------------------------------------
|
||||
* ____ ____
|
||||
* / /\/ /
|
||||
* /___/ \ / Vendor: Xilinx
|
||||
* \ \ \/ Date Created: 2008/08/18
|
||||
* \ \
|
||||
* / /
|
||||
* /___/ /\
|
||||
* \ \ / \
|
||||
* \___\/\___\
|
||||
*
|
||||
*Device: All
|
||||
*Purpose:
|
||||
* Define values for Verilog instatiation of labtools ip
|
||||
*
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
*-- C O N S T A N T S
|
||||
*-----------------------------------------------------------------------------*/
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_MFG_ID 0
|
||||
`define XILINX_MFG_ID 1
|
||||
`define XILINX_AND_AGILENT_MFG_ID 2
|
||||
`define GC_XILINX_MFG_ID `XILINX_MFG_ID
|
||||
|
||||
//
|
||||
// Core type (non-negative integers from 0 to 255)
|
||||
//
|
||||
`define RESERVED_CORE_TYPE 0
|
||||
`define ICON_CORE_TYPE 1
|
||||
`define ILA_CORE_TYPE 2
|
||||
`define IBA_GENERIC_CORE_TYPE 3
|
||||
`define IBA_OPB_CORE_TYPE 4
|
||||
`define IBA_PLB_CORE_TYPE 5
|
||||
`define ILA_ATC_CORE_TYPE 6
|
||||
`define IBA_OPB_ATC_CORE_TYPE 7
|
||||
`define IBA_PLB_ATC_CORE_TYPE 8
|
||||
`define VIO_CORE_TYPE 9
|
||||
`define ATC2_CORE_TYPE 10
|
||||
`define ATC3_CORE_TYPE 11
|
||||
`define GC_RESERVED_CORE_TYPE2 12
|
||||
`define IBERT_CORE_TYPE 13
|
||||
`define GC_XSDB_MASTER_V1_0 14
|
||||
`define GC_ICON_NULL_CORE_TYPE 15
|
||||
|
||||
//
|
||||
// Width of the ChipScope Pro Core CONTROL port
|
||||
//
|
||||
`define CONTROL_WIDTH 36
|
||||
|
||||
// Match unit type
|
||||
`define MATCH_UNIT_TYPEA_ALLX 0
|
||||
//`define MATCH_UNIT_TYPE_GANDOR 2
|
||||
//`define MATCH_UNIT_TYPE_GANDORX 3
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Device family constants
|
||||
//
|
||||
`define FAMILY_NAME_LENGTH 15 //leave room for radhard/automotive and low power part names
|
||||
`define FAMILY_VIRTEX6 "virtex6"
|
||||
`define FAMILY_VIRTEX7 "virtex7"
|
||||
`define FAMILY_VIRTEX7_LENGTH 7
|
||||
`define FAMILY_KINTEX7 "kintex7"
|
||||
`define FAMILY_KINTEX7_LENGTH 7
|
||||
`define FAMILY_ARTIX7 "artix7"
|
||||
`define FAMILY_ARTIX7_LENGTH 6
|
||||
`define FAMILY_ZYNQ "zynq"
|
||||
`define FAMILY_ZYNQ_LENGTH 4
|
||||
`define FAMILY_KINTEXU "kintexu"
|
||||
`define FAMILY_KINTEXUPLUS "kintexuplus"
|
||||
`define FAMILY_ARTIXUPLUS "artixuplus"
|
||||
`define FAMILY_AARTIXUPLUS "aartixuplus"
|
||||
`define FAMILY_VIRTEXU "virtexu"
|
||||
`define FAMILY_VIRTEXUPLUS "virtexuplus"
|
||||
`define FAMILY_VIRTEXUPLUSHBM "virtexuplusHBM"
|
||||
`define FAMILY_VIRTEXUPLUS58G "virtexuplus58g"
|
||||
`define FAMILY_ZYNQUPLUS "zynquplus"
|
||||
`define FAMILY_ZYNQUPLUSRFSOC "zynquplusRFSOC"
|
||||
|
||||
//
|
||||
// Architecture match type constants, start at 100 so that code can't incorrectly mix up family and match unit type
|
||||
//
|
||||
`define ARCH_MATCH_TYPE_A 100
|
||||
|
||||
//
|
||||
// Device JTAG Stuff
|
||||
//
|
||||
`define GC_SBT_IR_W 10;
|
||||
`define GC_SBT_IR_ID_INSTR 10'b1111001001
|
||||
`define GC_SBT_IR_USER1_INSTR 10'b11_1100_0010
|
||||
`define GC_CHIP_ID_CHIPSCOPE_SBT 32'b0000_1010_0000_0000_0011_0000_1001_0011
|
||||
// 0a00_3093
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Virtex7
|
||||
//
|
||||
// IR Info
|
||||
`define GC_V7_IR_W 6
|
||||
`define GC_V7_IR_ID_INSTR 6'b00_1001
|
||||
`define GC_V7_IR_USER1_INSTR 6'b00_0010
|
||||
`define GC_V7_IR_USER2_INSTR 6'b00_0011
|
||||
`define GC_V7_IR_USER3_INSTR 6'b10_0010
|
||||
`define GC_V7_IR_USER4_INSTR 6'b10_0011
|
||||
// Chip IDs
|
||||
`define GC_CHIP_ID_XC7V285T 32'b0000_0011_1010_0110_0100_0000_1001_0011
|
||||
// 0424a093
|
||||
|
||||
|
||||
-512
@@ -1,512 +0,0 @@
|
||||
.sl_iport0_o (sl_iport0_o),
|
||||
.sl_iport1_o (sl_iport1_o),
|
||||
.sl_iport2_o (sl_iport2_o),
|
||||
.sl_iport3_o (sl_iport3_o),
|
||||
.sl_iport4_o (sl_iport4_o),
|
||||
.sl_iport5_o (sl_iport5_o),
|
||||
.sl_iport6_o (sl_iport6_o),
|
||||
.sl_iport7_o (sl_iport7_o),
|
||||
.sl_iport8_o (sl_iport8_o),
|
||||
.sl_iport9_o (sl_iport9_o),
|
||||
.sl_iport10_o (sl_iport10_o),
|
||||
.sl_iport11_o (sl_iport11_o),
|
||||
.sl_iport12_o (sl_iport12_o),
|
||||
.sl_iport13_o (sl_iport13_o),
|
||||
.sl_iport14_o (sl_iport14_o),
|
||||
.sl_iport15_o (sl_iport15_o),
|
||||
.sl_iport16_o (sl_iport16_o),
|
||||
.sl_iport17_o (sl_iport17_o),
|
||||
.sl_iport18_o (sl_iport18_o),
|
||||
.sl_iport19_o (sl_iport19_o),
|
||||
.sl_iport20_o (sl_iport20_o),
|
||||
.sl_iport21_o (sl_iport21_o),
|
||||
.sl_iport22_o (sl_iport22_o),
|
||||
.sl_iport23_o (sl_iport23_o),
|
||||
.sl_iport24_o (sl_iport24_o),
|
||||
.sl_iport25_o (sl_iport25_o),
|
||||
.sl_iport26_o (sl_iport26_o),
|
||||
.sl_iport27_o (sl_iport27_o),
|
||||
.sl_iport28_o (sl_iport28_o),
|
||||
.sl_iport29_o (sl_iport29_o),
|
||||
.sl_iport30_o (sl_iport30_o),
|
||||
.sl_iport31_o (sl_iport31_o),
|
||||
.sl_iport32_o (sl_iport32_o),
|
||||
.sl_iport33_o (sl_iport33_o),
|
||||
.sl_iport34_o (sl_iport34_o),
|
||||
.sl_iport35_o (sl_iport35_o),
|
||||
.sl_iport36_o (sl_iport36_o),
|
||||
.sl_iport37_o (sl_iport37_o),
|
||||
.sl_iport38_o (sl_iport38_o),
|
||||
.sl_iport39_o (sl_iport39_o),
|
||||
.sl_iport40_o (sl_iport40_o),
|
||||
.sl_iport41_o (sl_iport41_o),
|
||||
.sl_iport42_o (sl_iport42_o),
|
||||
.sl_iport43_o (sl_iport43_o),
|
||||
.sl_iport44_o (sl_iport44_o),
|
||||
.sl_iport45_o (sl_iport45_o),
|
||||
.sl_iport46_o (sl_iport46_o),
|
||||
.sl_iport47_o (sl_iport47_o),
|
||||
.sl_iport48_o (sl_iport48_o),
|
||||
.sl_iport49_o (sl_iport49_o),
|
||||
.sl_iport50_o (sl_iport50_o),
|
||||
.sl_iport51_o (sl_iport51_o),
|
||||
.sl_iport52_o (sl_iport52_o),
|
||||
.sl_iport53_o (sl_iport53_o),
|
||||
.sl_iport54_o (sl_iport54_o),
|
||||
.sl_iport55_o (sl_iport55_o),
|
||||
.sl_iport56_o (sl_iport56_o),
|
||||
.sl_iport57_o (sl_iport57_o),
|
||||
.sl_iport58_o (sl_iport58_o),
|
||||
.sl_iport59_o (sl_iport59_o),
|
||||
.sl_iport60_o (sl_iport60_o),
|
||||
.sl_iport61_o (sl_iport61_o),
|
||||
.sl_iport62_o (sl_iport62_o),
|
||||
.sl_iport63_o (sl_iport63_o),
|
||||
.sl_iport64_o (sl_iport64_o),
|
||||
.sl_iport65_o (sl_iport65_o),
|
||||
.sl_iport66_o (sl_iport66_o),
|
||||
.sl_iport67_o (sl_iport67_o),
|
||||
.sl_iport68_o (sl_iport68_o),
|
||||
.sl_iport69_o (sl_iport69_o),
|
||||
.sl_iport70_o (sl_iport70_o),
|
||||
.sl_iport71_o (sl_iport71_o),
|
||||
.sl_iport72_o (sl_iport72_o),
|
||||
.sl_iport73_o (sl_iport73_o),
|
||||
.sl_iport74_o (sl_iport74_o),
|
||||
.sl_iport75_o (sl_iport75_o),
|
||||
.sl_iport76_o (sl_iport76_o),
|
||||
.sl_iport77_o (sl_iport77_o),
|
||||
.sl_iport78_o (sl_iport78_o),
|
||||
.sl_iport79_o (sl_iport79_o),
|
||||
.sl_iport80_o (sl_iport80_o),
|
||||
.sl_iport81_o (sl_iport81_o),
|
||||
.sl_iport82_o (sl_iport82_o),
|
||||
.sl_iport83_o (sl_iport83_o),
|
||||
.sl_iport84_o (sl_iport84_o),
|
||||
.sl_iport85_o (sl_iport85_o),
|
||||
.sl_iport86_o (sl_iport86_o),
|
||||
.sl_iport87_o (sl_iport87_o),
|
||||
.sl_iport88_o (sl_iport88_o),
|
||||
.sl_iport89_o (sl_iport89_o),
|
||||
.sl_iport90_o (sl_iport90_o),
|
||||
.sl_iport91_o (sl_iport91_o),
|
||||
.sl_iport92_o (sl_iport92_o),
|
||||
.sl_iport93_o (sl_iport93_o),
|
||||
.sl_iport94_o (sl_iport94_o),
|
||||
.sl_iport95_o (sl_iport95_o),
|
||||
.sl_iport96_o (sl_iport96_o),
|
||||
.sl_iport97_o (sl_iport97_o),
|
||||
.sl_iport98_o (sl_iport98_o),
|
||||
.sl_iport99_o (sl_iport99_o),
|
||||
.sl_iport100_o (sl_iport100_o),
|
||||
.sl_iport101_o (sl_iport101_o),
|
||||
.sl_iport102_o (sl_iport102_o),
|
||||
.sl_iport103_o (sl_iport103_o),
|
||||
.sl_iport104_o (sl_iport104_o),
|
||||
.sl_iport105_o (sl_iport105_o),
|
||||
.sl_iport106_o (sl_iport106_o),
|
||||
.sl_iport107_o (sl_iport107_o),
|
||||
.sl_iport108_o (sl_iport108_o),
|
||||
.sl_iport109_o (sl_iport109_o),
|
||||
.sl_iport110_o (sl_iport110_o),
|
||||
.sl_iport111_o (sl_iport111_o),
|
||||
.sl_iport112_o (sl_iport112_o),
|
||||
.sl_iport113_o (sl_iport113_o),
|
||||
.sl_iport114_o (sl_iport114_o),
|
||||
.sl_iport115_o (sl_iport115_o),
|
||||
.sl_iport116_o (sl_iport116_o),
|
||||
.sl_iport117_o (sl_iport117_o),
|
||||
.sl_iport118_o (sl_iport118_o),
|
||||
.sl_iport119_o (sl_iport119_o),
|
||||
.sl_iport120_o (sl_iport120_o),
|
||||
.sl_iport121_o (sl_iport121_o),
|
||||
.sl_iport122_o (sl_iport122_o),
|
||||
.sl_iport123_o (sl_iport123_o),
|
||||
.sl_iport124_o (sl_iport124_o),
|
||||
.sl_iport125_o (sl_iport125_o),
|
||||
.sl_iport126_o (sl_iport126_o),
|
||||
.sl_iport127_o (sl_iport127_o),
|
||||
.sl_iport128_o (sl_iport128_o),
|
||||
.sl_iport129_o (sl_iport129_o),
|
||||
.sl_iport130_o (sl_iport130_o),
|
||||
.sl_iport131_o (sl_iport131_o),
|
||||
.sl_iport132_o (sl_iport132_o),
|
||||
.sl_iport133_o (sl_iport133_o),
|
||||
.sl_iport134_o (sl_iport134_o),
|
||||
.sl_iport135_o (sl_iport135_o),
|
||||
.sl_iport136_o (sl_iport136_o),
|
||||
.sl_iport137_o (sl_iport137_o),
|
||||
.sl_iport138_o (sl_iport138_o),
|
||||
.sl_iport139_o (sl_iport139_o),
|
||||
.sl_iport140_o (sl_iport140_o),
|
||||
.sl_iport141_o (sl_iport141_o),
|
||||
.sl_iport142_o (sl_iport142_o),
|
||||
.sl_iport143_o (sl_iport143_o),
|
||||
.sl_iport144_o (sl_iport144_o),
|
||||
.sl_iport145_o (sl_iport145_o),
|
||||
.sl_iport146_o (sl_iport146_o),
|
||||
.sl_iport147_o (sl_iport147_o),
|
||||
.sl_iport148_o (sl_iport148_o),
|
||||
.sl_iport149_o (sl_iport149_o),
|
||||
.sl_iport150_o (sl_iport150_o),
|
||||
.sl_iport151_o (sl_iport151_o),
|
||||
.sl_iport152_o (sl_iport152_o),
|
||||
.sl_iport153_o (sl_iport153_o),
|
||||
.sl_iport154_o (sl_iport154_o),
|
||||
.sl_iport155_o (sl_iport155_o),
|
||||
.sl_iport156_o (sl_iport156_o),
|
||||
.sl_iport157_o (sl_iport157_o),
|
||||
.sl_iport158_o (sl_iport158_o),
|
||||
.sl_iport159_o (sl_iport159_o),
|
||||
.sl_iport160_o (sl_iport160_o),
|
||||
.sl_iport161_o (sl_iport161_o),
|
||||
.sl_iport162_o (sl_iport162_o),
|
||||
.sl_iport163_o (sl_iport163_o),
|
||||
.sl_iport164_o (sl_iport164_o),
|
||||
.sl_iport165_o (sl_iport165_o),
|
||||
.sl_iport166_o (sl_iport166_o),
|
||||
.sl_iport167_o (sl_iport167_o),
|
||||
.sl_iport168_o (sl_iport168_o),
|
||||
.sl_iport169_o (sl_iport169_o),
|
||||
.sl_iport170_o (sl_iport170_o),
|
||||
.sl_iport171_o (sl_iport171_o),
|
||||
.sl_iport172_o (sl_iport172_o),
|
||||
.sl_iport173_o (sl_iport173_o),
|
||||
.sl_iport174_o (sl_iport174_o),
|
||||
.sl_iport175_o (sl_iport175_o),
|
||||
.sl_iport176_o (sl_iport176_o),
|
||||
.sl_iport177_o (sl_iport177_o),
|
||||
.sl_iport178_o (sl_iport178_o),
|
||||
.sl_iport179_o (sl_iport179_o),
|
||||
.sl_iport180_o (sl_iport180_o),
|
||||
.sl_iport181_o (sl_iport181_o),
|
||||
.sl_iport182_o (sl_iport182_o),
|
||||
.sl_iport183_o (sl_iport183_o),
|
||||
.sl_iport184_o (sl_iport184_o),
|
||||
.sl_iport185_o (sl_iport185_o),
|
||||
.sl_iport186_o (sl_iport186_o),
|
||||
.sl_iport187_o (sl_iport187_o),
|
||||
.sl_iport188_o (sl_iport188_o),
|
||||
.sl_iport189_o (sl_iport189_o),
|
||||
.sl_iport190_o (sl_iport190_o),
|
||||
.sl_iport191_o (sl_iport191_o),
|
||||
.sl_iport192_o (sl_iport192_o),
|
||||
.sl_iport193_o (sl_iport193_o),
|
||||
.sl_iport194_o (sl_iport194_o),
|
||||
.sl_iport195_o (sl_iport195_o),
|
||||
.sl_iport196_o (sl_iport196_o),
|
||||
.sl_iport197_o (sl_iport197_o),
|
||||
.sl_iport198_o (sl_iport198_o),
|
||||
.sl_iport199_o (sl_iport199_o),
|
||||
.sl_iport200_o (sl_iport200_o),
|
||||
.sl_iport201_o (sl_iport201_o),
|
||||
.sl_iport202_o (sl_iport202_o),
|
||||
.sl_iport203_o (sl_iport203_o),
|
||||
.sl_iport204_o (sl_iport204_o),
|
||||
.sl_iport205_o (sl_iport205_o),
|
||||
.sl_iport206_o (sl_iport206_o),
|
||||
.sl_iport207_o (sl_iport207_o),
|
||||
.sl_iport208_o (sl_iport208_o),
|
||||
.sl_iport209_o (sl_iport209_o),
|
||||
.sl_iport210_o (sl_iport210_o),
|
||||
.sl_iport211_o (sl_iport211_o),
|
||||
.sl_iport212_o (sl_iport212_o),
|
||||
.sl_iport213_o (sl_iport213_o),
|
||||
.sl_iport214_o (sl_iport214_o),
|
||||
.sl_iport215_o (sl_iport215_o),
|
||||
.sl_iport216_o (sl_iport216_o),
|
||||
.sl_iport217_o (sl_iport217_o),
|
||||
.sl_iport218_o (sl_iport218_o),
|
||||
.sl_iport219_o (sl_iport219_o),
|
||||
.sl_iport220_o (sl_iport220_o),
|
||||
.sl_iport221_o (sl_iport221_o),
|
||||
.sl_iport222_o (sl_iport222_o),
|
||||
.sl_iport223_o (sl_iport223_o),
|
||||
.sl_iport224_o (sl_iport224_o),
|
||||
.sl_iport225_o (sl_iport225_o),
|
||||
.sl_iport226_o (sl_iport226_o),
|
||||
.sl_iport227_o (sl_iport227_o),
|
||||
.sl_iport228_o (sl_iport228_o),
|
||||
.sl_iport229_o (sl_iport229_o),
|
||||
.sl_iport230_o (sl_iport230_o),
|
||||
.sl_iport231_o (sl_iport231_o),
|
||||
.sl_iport232_o (sl_iport232_o),
|
||||
.sl_iport233_o (sl_iport233_o),
|
||||
.sl_iport234_o (sl_iport234_o),
|
||||
.sl_iport235_o (sl_iport235_o),
|
||||
.sl_iport236_o (sl_iport236_o),
|
||||
.sl_iport237_o (sl_iport237_o),
|
||||
.sl_iport238_o (sl_iport238_o),
|
||||
.sl_iport239_o (sl_iport239_o),
|
||||
.sl_iport240_o (sl_iport240_o),
|
||||
.sl_iport241_o (sl_iport241_o),
|
||||
.sl_iport242_o (sl_iport242_o),
|
||||
.sl_iport243_o (sl_iport243_o),
|
||||
.sl_iport244_o (sl_iport244_o),
|
||||
.sl_iport245_o (sl_iport245_o),
|
||||
.sl_iport246_o (sl_iport246_o),
|
||||
.sl_iport247_o (sl_iport247_o),
|
||||
.sl_iport248_o (sl_iport248_o),
|
||||
.sl_iport249_o (sl_iport249_o),
|
||||
.sl_iport250_o (sl_iport250_o),
|
||||
.sl_iport251_o (sl_iport251_o),
|
||||
.sl_iport252_o (sl_iport252_o),
|
||||
.sl_iport253_o (sl_iport253_o),
|
||||
.sl_iport254_o (sl_iport254_o),
|
||||
.sl_iport255_o (sl_iport255_o),
|
||||
.sl_oport0_i (sl_oport0_i),
|
||||
.sl_oport1_i (sl_oport1_i),
|
||||
.sl_oport2_i (sl_oport2_i),
|
||||
.sl_oport3_i (sl_oport3_i),
|
||||
.sl_oport4_i (sl_oport4_i),
|
||||
.sl_oport5_i (sl_oport5_i),
|
||||
.sl_oport6_i (sl_oport6_i),
|
||||
.sl_oport7_i (sl_oport7_i),
|
||||
.sl_oport8_i (sl_oport8_i),
|
||||
.sl_oport9_i (sl_oport9_i),
|
||||
.sl_oport10_i (sl_oport10_i),
|
||||
.sl_oport11_i (sl_oport11_i),
|
||||
.sl_oport12_i (sl_oport12_i),
|
||||
.sl_oport13_i (sl_oport13_i),
|
||||
.sl_oport14_i (sl_oport14_i),
|
||||
.sl_oport15_i (sl_oport15_i),
|
||||
.sl_oport16_i (sl_oport16_i),
|
||||
.sl_oport17_i (sl_oport17_i),
|
||||
.sl_oport18_i (sl_oport18_i),
|
||||
.sl_oport19_i (sl_oport19_i),
|
||||
.sl_oport20_i (sl_oport20_i),
|
||||
.sl_oport21_i (sl_oport21_i),
|
||||
.sl_oport22_i (sl_oport22_i),
|
||||
.sl_oport23_i (sl_oport23_i),
|
||||
.sl_oport24_i (sl_oport24_i),
|
||||
.sl_oport25_i (sl_oport25_i),
|
||||
.sl_oport26_i (sl_oport26_i),
|
||||
.sl_oport27_i (sl_oport27_i),
|
||||
.sl_oport28_i (sl_oport28_i),
|
||||
.sl_oport29_i (sl_oport29_i),
|
||||
.sl_oport30_i (sl_oport30_i),
|
||||
.sl_oport31_i (sl_oport31_i),
|
||||
.sl_oport32_i (sl_oport32_i),
|
||||
.sl_oport33_i (sl_oport33_i),
|
||||
.sl_oport34_i (sl_oport34_i),
|
||||
.sl_oport35_i (sl_oport35_i),
|
||||
.sl_oport36_i (sl_oport36_i),
|
||||
.sl_oport37_i (sl_oport37_i),
|
||||
.sl_oport38_i (sl_oport38_i),
|
||||
.sl_oport39_i (sl_oport39_i),
|
||||
.sl_oport40_i (sl_oport40_i),
|
||||
.sl_oport41_i (sl_oport41_i),
|
||||
.sl_oport42_i (sl_oport42_i),
|
||||
.sl_oport43_i (sl_oport43_i),
|
||||
.sl_oport44_i (sl_oport44_i),
|
||||
.sl_oport45_i (sl_oport45_i),
|
||||
.sl_oport46_i (sl_oport46_i),
|
||||
.sl_oport47_i (sl_oport47_i),
|
||||
.sl_oport48_i (sl_oport48_i),
|
||||
.sl_oport49_i (sl_oport49_i),
|
||||
.sl_oport50_i (sl_oport50_i),
|
||||
.sl_oport51_i (sl_oport51_i),
|
||||
.sl_oport52_i (sl_oport52_i),
|
||||
.sl_oport53_i (sl_oport53_i),
|
||||
.sl_oport54_i (sl_oport54_i),
|
||||
.sl_oport55_i (sl_oport55_i),
|
||||
.sl_oport56_i (sl_oport56_i),
|
||||
.sl_oport57_i (sl_oport57_i),
|
||||
.sl_oport58_i (sl_oport58_i),
|
||||
.sl_oport59_i (sl_oport59_i),
|
||||
.sl_oport60_i (sl_oport60_i),
|
||||
.sl_oport61_i (sl_oport61_i),
|
||||
.sl_oport62_i (sl_oport62_i),
|
||||
.sl_oport63_i (sl_oport63_i),
|
||||
.sl_oport64_i (sl_oport64_i),
|
||||
.sl_oport65_i (sl_oport65_i),
|
||||
.sl_oport66_i (sl_oport66_i),
|
||||
.sl_oport67_i (sl_oport67_i),
|
||||
.sl_oport68_i (sl_oport68_i),
|
||||
.sl_oport69_i (sl_oport69_i),
|
||||
.sl_oport70_i (sl_oport70_i),
|
||||
.sl_oport71_i (sl_oport71_i),
|
||||
.sl_oport72_i (sl_oport72_i),
|
||||
.sl_oport73_i (sl_oport73_i),
|
||||
.sl_oport74_i (sl_oport74_i),
|
||||
.sl_oport75_i (sl_oport75_i),
|
||||
.sl_oport76_i (sl_oport76_i),
|
||||
.sl_oport77_i (sl_oport77_i),
|
||||
.sl_oport78_i (sl_oport78_i),
|
||||
.sl_oport79_i (sl_oport79_i),
|
||||
.sl_oport80_i (sl_oport80_i),
|
||||
.sl_oport81_i (sl_oport81_i),
|
||||
.sl_oport82_i (sl_oport82_i),
|
||||
.sl_oport83_i (sl_oport83_i),
|
||||
.sl_oport84_i (sl_oport84_i),
|
||||
.sl_oport85_i (sl_oport85_i),
|
||||
.sl_oport86_i (sl_oport86_i),
|
||||
.sl_oport87_i (sl_oport87_i),
|
||||
.sl_oport88_i (sl_oport88_i),
|
||||
.sl_oport89_i (sl_oport89_i),
|
||||
.sl_oport90_i (sl_oport90_i),
|
||||
.sl_oport91_i (sl_oport91_i),
|
||||
.sl_oport92_i (sl_oport92_i),
|
||||
.sl_oport93_i (sl_oport93_i),
|
||||
.sl_oport94_i (sl_oport94_i),
|
||||
.sl_oport95_i (sl_oport95_i),
|
||||
.sl_oport96_i (sl_oport96_i),
|
||||
.sl_oport97_i (sl_oport97_i),
|
||||
.sl_oport98_i (sl_oport98_i),
|
||||
.sl_oport99_i (sl_oport99_i),
|
||||
.sl_oport100_i (sl_oport100_i),
|
||||
.sl_oport101_i (sl_oport101_i),
|
||||
.sl_oport102_i (sl_oport102_i),
|
||||
.sl_oport103_i (sl_oport103_i),
|
||||
.sl_oport104_i (sl_oport104_i),
|
||||
.sl_oport105_i (sl_oport105_i),
|
||||
.sl_oport106_i (sl_oport106_i),
|
||||
.sl_oport107_i (sl_oport107_i),
|
||||
.sl_oport108_i (sl_oport108_i),
|
||||
.sl_oport109_i (sl_oport109_i),
|
||||
.sl_oport110_i (sl_oport110_i),
|
||||
.sl_oport111_i (sl_oport111_i),
|
||||
.sl_oport112_i (sl_oport112_i),
|
||||
.sl_oport113_i (sl_oport113_i),
|
||||
.sl_oport114_i (sl_oport114_i),
|
||||
.sl_oport115_i (sl_oport115_i),
|
||||
.sl_oport116_i (sl_oport116_i),
|
||||
.sl_oport117_i (sl_oport117_i),
|
||||
.sl_oport118_i (sl_oport118_i),
|
||||
.sl_oport119_i (sl_oport119_i),
|
||||
.sl_oport120_i (sl_oport120_i),
|
||||
.sl_oport121_i (sl_oport121_i),
|
||||
.sl_oport122_i (sl_oport122_i),
|
||||
.sl_oport123_i (sl_oport123_i),
|
||||
.sl_oport124_i (sl_oport124_i),
|
||||
.sl_oport125_i (sl_oport125_i),
|
||||
.sl_oport126_i (sl_oport126_i),
|
||||
.sl_oport127_i (sl_oport127_i),
|
||||
.sl_oport128_i (sl_oport128_i),
|
||||
.sl_oport129_i (sl_oport129_i),
|
||||
.sl_oport130_i (sl_oport130_i),
|
||||
.sl_oport131_i (sl_oport131_i),
|
||||
.sl_oport132_i (sl_oport132_i),
|
||||
.sl_oport133_i (sl_oport133_i),
|
||||
.sl_oport134_i (sl_oport134_i),
|
||||
.sl_oport135_i (sl_oport135_i),
|
||||
.sl_oport136_i (sl_oport136_i),
|
||||
.sl_oport137_i (sl_oport137_i),
|
||||
.sl_oport138_i (sl_oport138_i),
|
||||
.sl_oport139_i (sl_oport139_i),
|
||||
.sl_oport140_i (sl_oport140_i),
|
||||
.sl_oport141_i (sl_oport141_i),
|
||||
.sl_oport142_i (sl_oport142_i),
|
||||
.sl_oport143_i (sl_oport143_i),
|
||||
.sl_oport144_i (sl_oport144_i),
|
||||
.sl_oport145_i (sl_oport145_i),
|
||||
.sl_oport146_i (sl_oport146_i),
|
||||
.sl_oport147_i (sl_oport147_i),
|
||||
.sl_oport148_i (sl_oport148_i),
|
||||
.sl_oport149_i (sl_oport149_i),
|
||||
.sl_oport150_i (sl_oport150_i),
|
||||
.sl_oport151_i (sl_oport151_i),
|
||||
.sl_oport152_i (sl_oport152_i),
|
||||
.sl_oport153_i (sl_oport153_i),
|
||||
.sl_oport154_i (sl_oport154_i),
|
||||
.sl_oport155_i (sl_oport155_i),
|
||||
.sl_oport156_i (sl_oport156_i),
|
||||
.sl_oport157_i (sl_oport157_i),
|
||||
.sl_oport158_i (sl_oport158_i),
|
||||
.sl_oport159_i (sl_oport159_i),
|
||||
.sl_oport160_i (sl_oport160_i),
|
||||
.sl_oport161_i (sl_oport161_i),
|
||||
.sl_oport162_i (sl_oport162_i),
|
||||
.sl_oport163_i (sl_oport163_i),
|
||||
.sl_oport164_i (sl_oport164_i),
|
||||
.sl_oport165_i (sl_oport165_i),
|
||||
.sl_oport166_i (sl_oport166_i),
|
||||
.sl_oport167_i (sl_oport167_i),
|
||||
.sl_oport168_i (sl_oport168_i),
|
||||
.sl_oport169_i (sl_oport169_i),
|
||||
.sl_oport170_i (sl_oport170_i),
|
||||
.sl_oport171_i (sl_oport171_i),
|
||||
.sl_oport172_i (sl_oport172_i),
|
||||
.sl_oport173_i (sl_oport173_i),
|
||||
.sl_oport174_i (sl_oport174_i),
|
||||
.sl_oport175_i (sl_oport175_i),
|
||||
.sl_oport176_i (sl_oport176_i),
|
||||
.sl_oport177_i (sl_oport177_i),
|
||||
.sl_oport178_i (sl_oport178_i),
|
||||
.sl_oport179_i (sl_oport179_i),
|
||||
.sl_oport180_i (sl_oport180_i),
|
||||
.sl_oport181_i (sl_oport181_i),
|
||||
.sl_oport182_i (sl_oport182_i),
|
||||
.sl_oport183_i (sl_oport183_i),
|
||||
.sl_oport184_i (sl_oport184_i),
|
||||
.sl_oport185_i (sl_oport185_i),
|
||||
.sl_oport186_i (sl_oport186_i),
|
||||
.sl_oport187_i (sl_oport187_i),
|
||||
.sl_oport188_i (sl_oport188_i),
|
||||
.sl_oport189_i (sl_oport189_i),
|
||||
.sl_oport190_i (sl_oport190_i),
|
||||
.sl_oport191_i (sl_oport191_i),
|
||||
.sl_oport192_i (sl_oport192_i),
|
||||
.sl_oport193_i (sl_oport193_i),
|
||||
.sl_oport194_i (sl_oport194_i),
|
||||
.sl_oport195_i (sl_oport195_i),
|
||||
.sl_oport196_i (sl_oport196_i),
|
||||
.sl_oport197_i (sl_oport197_i),
|
||||
.sl_oport198_i (sl_oport198_i),
|
||||
.sl_oport199_i (sl_oport199_i),
|
||||
.sl_oport200_i (sl_oport200_i),
|
||||
.sl_oport201_i (sl_oport201_i),
|
||||
.sl_oport202_i (sl_oport202_i),
|
||||
.sl_oport203_i (sl_oport203_i),
|
||||
.sl_oport204_i (sl_oport204_i),
|
||||
.sl_oport205_i (sl_oport205_i),
|
||||
.sl_oport206_i (sl_oport206_i),
|
||||
.sl_oport207_i (sl_oport207_i),
|
||||
.sl_oport208_i (sl_oport208_i),
|
||||
.sl_oport209_i (sl_oport209_i),
|
||||
.sl_oport210_i (sl_oport210_i),
|
||||
.sl_oport211_i (sl_oport211_i),
|
||||
.sl_oport212_i (sl_oport212_i),
|
||||
.sl_oport213_i (sl_oport213_i),
|
||||
.sl_oport214_i (sl_oport214_i),
|
||||
.sl_oport215_i (sl_oport215_i),
|
||||
.sl_oport216_i (sl_oport216_i),
|
||||
.sl_oport217_i (sl_oport217_i),
|
||||
.sl_oport218_i (sl_oport218_i),
|
||||
.sl_oport219_i (sl_oport219_i),
|
||||
.sl_oport220_i (sl_oport220_i),
|
||||
.sl_oport221_i (sl_oport221_i),
|
||||
.sl_oport222_i (sl_oport222_i),
|
||||
.sl_oport223_i (sl_oport223_i),
|
||||
.sl_oport224_i (sl_oport224_i),
|
||||
.sl_oport225_i (sl_oport225_i),
|
||||
.sl_oport226_i (sl_oport226_i),
|
||||
.sl_oport227_i (sl_oport227_i),
|
||||
.sl_oport228_i (sl_oport228_i),
|
||||
.sl_oport229_i (sl_oport229_i),
|
||||
.sl_oport230_i (sl_oport230_i),
|
||||
.sl_oport231_i (sl_oport231_i),
|
||||
.sl_oport232_i (sl_oport232_i),
|
||||
.sl_oport233_i (sl_oport233_i),
|
||||
.sl_oport234_i (sl_oport234_i),
|
||||
.sl_oport235_i (sl_oport235_i),
|
||||
.sl_oport236_i (sl_oport236_i),
|
||||
.sl_oport237_i (sl_oport237_i),
|
||||
.sl_oport238_i (sl_oport238_i),
|
||||
.sl_oport239_i (sl_oport239_i),
|
||||
.sl_oport240_i (sl_oport240_i),
|
||||
.sl_oport241_i (sl_oport241_i),
|
||||
.sl_oport242_i (sl_oport242_i),
|
||||
.sl_oport243_i (sl_oport243_i),
|
||||
.sl_oport244_i (sl_oport244_i),
|
||||
.sl_oport245_i (sl_oport245_i),
|
||||
.sl_oport246_i (sl_oport246_i),
|
||||
.sl_oport247_i (sl_oport247_i),
|
||||
.sl_oport248_i (sl_oport248_i),
|
||||
.sl_oport249_i (sl_oport249_i),
|
||||
.sl_oport250_i (sl_oport250_i),
|
||||
.sl_oport251_i (sl_oport251_i),
|
||||
.sl_oport252_i (sl_oport252_i),
|
||||
.sl_oport253_i (sl_oport253_i),
|
||||
.sl_oport254_i (sl_oport254_i),
|
||||
.sl_oport255_i (sl_oport255_i),
|
||||
-8826
File diff suppressed because it is too large
Load Diff
-193219
File diff suppressed because it is too large
Load Diff
-31647
File diff suppressed because it is too large
Load Diff
-287
@@ -1,287 +0,0 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.1"
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
nsFylERiuG7mpTKUIOx2ctX6bezOiVe7YLeXdrNT5EcXJeoUZJQBgRY9zpMCohWLZVJIz5ayl5ae
|
||||
pQBEiwwztPtPXIYKvRvb7pVYhzlmd3r5mYquJdVlCE9c2Sy0QoD9Ao4pLJTHHcXPZQ4TQp5ISkw8
|
||||
k1jcY8lFjetrBZOo7Tg=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
rkFPXh1ETlc+Q6DfuqnM8aeUF47lt0HQyZBcz5VW8K2Womvx7LKRivpxeqgwfsDaoPk1yThEhfUq
|
||||
Xn1Zkv9dYsuU4kL0Qxh1+nrJyyXzQ+2CNEXLoKdBvKEfm+cN5H4wJOlLTkV+5XULcjTJ8cKlHtNZ
|
||||
68D9ZsSnei2xwEQlG8bPETVaLF3XGeIEdDVuzqe+s6GVs8YbGTTEDUMQqGuLh7v4JqP+FeKrQ1y5
|
||||
Eo4crGE8W4s8YMxk2Fs7102cU81NzmPnu6GJTNLPT/tqj+UZ/ER3FLt2WScdWmdRD/p/7hgoHjaL
|
||||
AB1sYtukt5mXbeMyi/lgTz8BCAY61ptehv0vQg==
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
shtWPi1XoFPsFP3Q6GB8b8IHUMjsXmDTTfwF9IGG9gPGcZY/f4njhpqff0fSyG0oUuTYStZ7bZNK
|
||||
PAr3hTxLWaBPtP3S8Rn77d8nO52FyKvqMkyfwkey5R6XKbMi/sN22y6SXK/CoaPJxkVYfROQDAX2
|
||||
a9/LrZ2uzBBzAo7zHMY=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
knvWAAxWkfz6AAtQB7jMJ1FHLy7fRYm9KI3gm8pRV982DAd2aSwO2DDUsgYz/0nXstBb2i7kfusi
|
||||
v4tGFxCzrgyzoX2zqSWxeukMygN8Xv+Ej/ZHmeArkjivkOtrI9jeECACusooRPE1O99KiWGzYXCA
|
||||
NGkmphM2wenV+6627AgfgIaQbNPtEQ9k7ww4jXYwViUc8/IWjRBBs+ZD1WsM+A5CZ/yDx4dUCya2
|
||||
tYPj9se81x4fuacVcgyf/pb3W7yC8HhveMOos7HHzbJHvkqUhkeponoQrYF94UI4pGjFhjJ/z5I6
|
||||
2Lodrp/uTk41S5ga0S142suf1vixEbsLt8Jd3A==
|
||||
|
||||
`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
fNmi3pGuVT4Ek4sb4B8QYuGRjbNE5fCWNZPQ3HtaxoCmgQVj6V7m+WnlQ4sV1/fyRFzfm+cS6tdD
|
||||
Pfk0A4Fzsu8vDeosoumrOCHQRc7USQJkjMzDdX5qk2arJvVWKGwQjOAe39aSsrfOfVq7qhudaGnF
|
||||
2ss6t1TGc2ZT8dx85tsD1ZFYw8GAFzf6SfLASEuZgRzwC+GkLKQKXSELST+tk41vEQeVesjA0JJ4
|
||||
mecCUxTY8Ym75qCOxJ/VxRq2U66EgvnxbwoRJnmxqkt7yQk54Yg9voVCvA3OOLjuvwK1MlJvEOuk
|
||||
OO2gqrMgzKMHqHx28cFT5P5wPltWhh+vkFAngA==
|
||||
|
||||
`pragma protect key_keyowner = "Metrics Technologies Inc.", key_keyname = "DSim", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
YcCXZF3TxRWwHPrSiEu++e+rXiU309Kp7Lam6HESEjorpJOWid9x6jnNQT6KV1a6rmVkUelAeuv8
|
||||
nLEYk65CIocxtr0/ZzW+U8SX1CME1/S9f/gPD0qEYXQl3LM986P3K+Bth9Y4GDGrwti3i9GORZ0L
|
||||
9fae3T/kgBIf+txtsl/3eNDxTEMxN5hDJIuG/Ei3ihXcsz/xmc0sYPF7B5CshP+6EFqmIe+oC9yQ
|
||||
BGILVMqEdAAHiJXi9k9l9OOZUgZHSk5GbtMDSJsGW/SYM8mVkO9ijzrh+yDGlXJg7xunTf6QC9Ls
|
||||
EvHxMN5n4ZLBneMHuAMYzSAtuPSU/kW0Utuauw==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2022_10", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
b/ikbNkY/8vWVmXkQQuseZIc9Ft5dbZ7HhnvpYanTPQq8abw5e8ttsiUN5p0Gy4+TEKVw9wLZgxh
|
||||
Y3fDEKfUFIfqvE7g/JUHI0l51IF/6Q5PXzfMT4vnq82E8Os90QPVt7c73SSAT53P3ioZrgKXk5d5
|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Atrenta", key_keyname = "ATR-SG-RSA-1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 384)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "CDS_RSA_KEY_VER_1", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11376)
|
||||
`pragma protect data_block
|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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qY5yY+Z9REBIYqBIGaS27ku0bSbXwFPHQhHX0s/xqPiU
|
||||
`pragma protect end_protected
|
||||
+55
-35
@@ -3865,15 +3865,25 @@
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"SLOT_0_AXIS_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tlast": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tready": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"resetn": [ { "direction": "in", "driver_value": "1" } ]
|
||||
"SLOT_0_AXIS_tid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tdest": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tdata": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tstrb": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_0_AXIS_tkeep": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_0_AXIS_tlast": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tuser": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_0_AXIS_tvalid": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"SLOT_0_AXIS_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tdest": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tdata": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tstrb": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tkeep": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"SLOT_1_AXIS_tlast": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tuser": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SLOT_1_AXIS_tvalid": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
|
||||
"SLOT_1_AXIS_tready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"resetn": [ { "direction": "in" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK.clk": {
|
||||
@@ -3881,13 +3891,13 @@
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXIS:SLOT_1_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_src": "default_prop", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXIS:SLOT_1_AXIS", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
@@ -3899,7 +3909,7 @@
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
@@ -3911,23 +3921,28 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "monitor",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TID": [ { "physical_name": "SLOT_0_AXIS_tid" } ],
|
||||
"TDEST": [ { "physical_name": "SLOT_0_AXIS_tdest" } ],
|
||||
"TDATA": [ { "physical_name": "SLOT_0_AXIS_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "SLOT_0_AXIS_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "SLOT_0_AXIS_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "SLOT_0_AXIS_tlast" } ],
|
||||
"TUSER": [ { "physical_name": "SLOT_0_AXIS_tuser" } ],
|
||||
"TVALID": [ { "physical_name": "SLOT_0_AXIS_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "SLOT_0_AXIS_tready" } ]
|
||||
}
|
||||
@@ -3937,23 +3952,28 @@
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "monitor",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "bd_3e86_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TID": [ { "physical_name": "SLOT_1_AXIS_tid" } ],
|
||||
"TDEST": [ { "physical_name": "SLOT_1_AXIS_tdest" } ],
|
||||
"TDATA": [ { "physical_name": "SLOT_1_AXIS_tdata" } ],
|
||||
"TSTRB": [ { "physical_name": "SLOT_1_AXIS_tstrb" } ],
|
||||
"TKEEP": [ { "physical_name": "SLOT_1_AXIS_tkeep" } ],
|
||||
"TLAST": [ { "physical_name": "SLOT_1_AXIS_tlast" } ],
|
||||
"TUSER": [ { "physical_name": "SLOT_1_AXIS_tuser" } ],
|
||||
"TVALID": [ { "physical_name": "SLOT_1_AXIS_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "SLOT_1_AXIS_tready" } ]
|
||||
}
|
||||
|
||||
+7
-7
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.62744",
|
||||
"Default View_TopLeft":"-93,-90",
|
||||
"Default View_TopLeft":"98,-90",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
@@ -22,9 +22,9 @@ preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 950 -y 70 -defaultsOSRD
|
||||
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1180 -y 140 -defaultsOSRD
|
||||
preplace inst system_ila_0 -pg 1 -lvl 4 -x 950 -y 230 -defaultsOSRD
|
||||
preplace netloc clk_1 1 0 1 20J 120n
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 240 140 520 50 820 320 1070
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 4 250 140 520 50 830 320 1060
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 NJ 160 510 260 N
|
||||
preplace netloc rec_dat_0_1 1 0 5 NJ 70 NJ 70 470J 60 830J 140 1060J
|
||||
preplace netloc rec_dat_0_1 1 0 5 NJ 70 NJ 70 460J 60 840J 140 1050J
|
||||
preplace netloc reset_1 1 0 1 NJ 150
|
||||
preplace netloc zybo_audio_0_bclk 1 5 1 1330J 150n
|
||||
preplace netloc zybo_audio_0_mclk 1 5 1 1340J 130n
|
||||
@@ -32,11 +32,11 @@ preplace netloc zybo_audio_0_mute 1 5 1 1340J 110n
|
||||
preplace netloc zybo_audio_0_pb_dat 1 5 1 1320J 170n
|
||||
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1310J 190n
|
||||
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1300J 210n
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 250 330 NJ 330 NJ 330 NJ 330 1290
|
||||
preplace netloc zybo_audio_0_i2c 1 5 1 NJ 90
|
||||
preplace netloc axis_audio_bitcrusher_0_M_AXIS 1 3 1 840 60n
|
||||
preplace netloc axis_audio_bitcrusher_0_M_AXIS 1 3 1 850 60n
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 1050 70n
|
||||
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 530 220 NJ
|
||||
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 1060 70n
|
||||
preplace netloc zybo_audio_0_axis_rec 1 1 5 260 330 NJ 330 NJ 330 NJ 330 1290
|
||||
preplace netloc zybo_audio_0_i2c 1 5 1 NJ 90
|
||||
levelinfo -pg 1 0 130 360 660 950 1180 1360
|
||||
pagesize -pg 1 -db -bbox -sgen -100 0 1460 470
|
||||
"
|
||||
|
||||
@@ -104,23 +104,23 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_system_ila_0_2/design_1_syn_system_ila_0_2.xci">
|
||||
<Proxy FileSetName="design_1_syn_system_ila_0_2"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_bitcrusher_0_0/design_1_syn_axis_audio_bitcrusher_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_bitcrusher_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_mono2ster_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_stereo2mo_0_0/design_1_syn_axis_audio_stereo2mo_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_stereo2mo_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_zybo_audio_0_0/design_1_syn_zybo_audio_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_zybo_audio_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_clk_rst_generator_0_0/design_1_syn_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_zybo_audio_0_0/design_1_syn_zybo_audio_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_zybo_audio_0_0"/>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_system_ila_0_2/design_1_syn_system_ila_0_2.xci">
|
||||
<Proxy FileSetName="design_1_syn_system_ila_0_2"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1_syn.bd" FileRelPathName="ip/design_1_syn_axis_audio_mono2ster_0_0/design_1_syn_axis_audio_mono2ster_0_0.xci">
|
||||
<Proxy FileSetName="design_1_syn_axis_audio_mono2ster_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/design_1_syn/hdl/design_1_syn_wrapper.v">
|
||||
@@ -260,9 +260,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_system_ila_0_2_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_system_ila_0_2" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_system_ila_0_2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_system_ila_0_2_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_system_ila_0_2_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_system_ila_0_2_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -272,9 +270,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_bitcrusher_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_axis_audio_bitcrusher_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_bitcrusher_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_axis_audio_bitcrusher_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -284,9 +280,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_mono2ster_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_axis_audio_mono2ster_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_mono2ster_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -296,9 +290,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_stereo2mo_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_axis_audio_stereo2mo_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_stereo2mo_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_axis_audio_stereo2mo_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_stereo2mo_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_stereo2mo_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -308,9 +300,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_clk_rst_generator_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_clk_rst_generator_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_clk_rst_generator_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_clk_rst_generator_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_clk_rst_generator_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_clk_rst_generator_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -320,9 +310,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_zybo_audio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_syn_zybo_audio_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_zybo_audio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_syn_zybo_audio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_zybo_audio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_zybo_audio_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -350,9 +338,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_system_ila_0_2_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_system_ila_0_2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_system_ila_0_2_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_system_ila_0_2_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_system_ila_0_2_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -369,9 +355,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_bitcrusher_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_bitcrusher_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_axis_audio_bitcrusher_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_bitcrusher_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -388,9 +372,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_mono2ster_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_mono2ster_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_axis_audio_mono2ster_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_mono2ster_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -407,9 +389,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_axis_audio_stereo2mo_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_axis_audio_stereo2mo_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_axis_audio_stereo2mo_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_stereo2mo_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_axis_audio_stereo2mo_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -426,9 +406,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_clk_rst_generator_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_clk_rst_generator_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_clk_rst_generator_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_clk_rst_generator_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_clk_rst_generator_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -445,9 +423,7 @@
|
||||
</Run>
|
||||
<Run Id="design_1_syn_zybo_audio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_syn_zybo_audio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_syn_zybo_audio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_syn_zybo_audio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_syn_zybo_audio_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
Reference in New Issue
Block a user