crc_axi_master
This commit is contained in:
Matthias Biermann
@@ -1,3 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c4755494d6f6465:3
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6d6f64655f636f756e7465727c4755494d6f6465:4
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eof:
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@@ -0,0 +1,13 @@
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{
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"design": {
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"design_info": {
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"boundary_crc": "0x0",
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"gen_directory": "../../../../axi_crc.gen/sources_1/bd/design_1",
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"name": "design_1",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "Hierarchical",
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"tool_version": "2023.1"
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},
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"design_tree": {}
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}
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}
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@@ -119,6 +119,14 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="axi_crc"/>
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@@ -4,52 +4,80 @@ use IEEE.NUMERIC_STD.ALL;
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entity crc_axi_control is
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generic (
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BRAM_AWIDTH : positve := 4
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LUTRAM_AWIDTH : positive := 4;
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PACKET_SIZE_WIDTH : positive := 16;
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PACKET_NUM_WIDTH : positive := 16;
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MAX_BURSTLEN : positive := 16;
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);
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port (
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CLK : in std_logic;
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RESETN : in std_logic;
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CLK : in std_logic;
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RESETN : in std_logic;
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-- AXIL Registers
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start_ip : in std_logic;
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stop_ip : in std_logic;
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status : out std_logic;
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interrupt_enable : in std_logic;
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interrupt_status : out std_logic;
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interrupt_reset : in std_logic;
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raddr : in std_logic_vector(31 downto 0);
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waddr : in std_logic_vector(31 downto 0);
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packet_size : in std_logic_vector(15 downto 0);
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packet_number : in std_logic_vector(15 downto 0);
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start_ip : in std_logic;
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stop_ip : in std_logic;
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status : out std_logic;
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interrupt_enable : in std_logic;
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interrupt_status : out std_logic;
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interrupt_reset : in std_logic;
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raddr : in std_logic_vector(31 downto 0);
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waddr : in std_logic_vector(31 downto 0);
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packet_size : in std_logic_vector(PACKET_SIZE_WIDTH-1 downto 0);
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packet_number : in std_logic_vector(PACKET_NUM_WIDTH-1 downto 0);
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-- Interface to Block-RAM
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ram_sel : out std_logic;
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ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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ram_we : out std_logic;
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ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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ram_re : out std_logic;
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ram_sel : out std_logic;
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ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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ram_we : out std_logic;
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ram_waddr : out std_logic_vector(BRAM_AWIDTH-1 downto 0);
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ram_re : out std_logic;
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-- Interface to AXI Master component
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axi_start : out std_logic;
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axi_write : out std_logic;
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axi_addr : out std_logic_vector(31 downto 0);
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axi_size : out std_logic_vector(3 downto 0);
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axi_idle : in std_logic;
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axi_start : out std_logic;
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axi_write : out std_logic;
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axi_addr : out std_logic_vector(31 downto 0);
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axi_size : out std_logic_vector(3 downto 0);
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axi_idle : in std_logic;
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-- Control signals for CRC component
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crc_en : out std_logic;
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cec_rst : out std_logic;
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byte_sel : out std_logic_vector(1 downto 0);
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crc_en : out std_logic;
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cec_rst : out std_logic;
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byte_sel : out std_logic_vector(1 downto 0);
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);
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end entity;
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architecture rtl of crc_axi_control is
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type state_t is (IDLE);
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type state_t is (IDLE, READ_DATA);
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signal state : state_t := IDLE;
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signal packets_cnt : unsigned(PACKET_NUM_WIDTH-1 downto 0) := (others=>'0');
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signal data_cnt : unsigned(PACKET_SIZE_WIDTH+PACKET_NUM_WIDTH-1 downto 0) := (others=>'0');
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signal read_addr : unsigned(31 downto 0) := (others=>'0');
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signal write_addr : unsigned(31 downto 0) := (others=>'0');
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begin
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process
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begin
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wait until rising_edge(CLK);
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if RESETN = '0' then
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state <= IDLE;
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else
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case state is
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when IDLE =>
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if start_ip = '1' then
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packets_cnt <= unsigned(packet_number);
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data_cnt <= unsigned(packet_size);
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read_addr <= unsigned(raddr);
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write_addr <= unsigned(waddr);
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end if;
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when others =>
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null;
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end case;
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end if;
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end process;
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end architecture;
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+5
-50
@@ -2,55 +2,10 @@
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<Root MajorVersion="0" MinorVersion="40">
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<CompositeFile CompositeFileTopName="crc_axi_master_sim" CanBeSetAsTop="true" CanDisplayChildGraph="true">
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<Description>Composite Fileset</Description>
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<Generation Name="SYNTHESIS" State="STALE" Timestamp="1738284380"/>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738284380"/>
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<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1738284380"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738284380"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<File Name="synth\crc_axi_master_sim.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<Library Name="xil_defaultlib"/>
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<UsedIn Val="SYNTHESIS"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="sim\crc_axi_master_sim.vhd" Type="VHDL">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<Library Name="xil_defaultlib"/>
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<UsedIn Val="SIMULATION"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="crc_axi_master_sim_ooc.xdc" Type="XDC">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="SYNTHESIS"/>
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<UsedIn Val="IMPLEMENTATION"/>
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<UsedIn Val="OUT_OF_CONTEXT"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="hw_handoff\crc_axi_master_sim.hwh" Type="HwHandoff">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="HW_HANDOFF"/>
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||||
<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="crc_axi_master_sim.bda">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="HW_HANDOFF"/>
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||||
<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="synth\crc_axi_master_sim.hwdef">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="HW_HANDOFF"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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<File Name="sim\crc_axi_master_sim.protoinst">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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||||
<Library Name="xil_defaultlib"/>
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||||
<UsedIn Val="SIMULATION"/>
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<ProcessingOrder Val="NORMAL"/>
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</File>
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</FileCollection>
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<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738336143"/>
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<Generation Name="SIMULATION" State="RESET" Timestamp="1738336143"/>
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<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738336143"/>
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<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738336143"/>
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<FileCollection Name="SOURCES" Type="SOURCES"/>
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</CompositeFile>
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</Root>
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-10
@@ -1,10 +0,0 @@
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################################################################################
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# This XDC is used only for OOC mode of synthesis, implementation
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# This constraints file contains default clock frequencies to be used during
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# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
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# This constraints file is not used in normal top-down synthesis (default flow
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# of Vivado)
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################################################################################
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################################################################################
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+2
-2
@@ -1222,7 +1222,7 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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@@ -1233,7 +1233,7 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
|
||||
|
||||
+47
-91
@@ -689,40 +689,6 @@
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||||
</spirit:addressSpace>
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||||
</spirit:addressSpaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:cf9c9909</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_sim_crc_axi_master_0_2</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 00:46:20 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:cf9c9909</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -731,7 +697,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -743,7 +709,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -755,7 +721,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -767,7 +733,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -783,7 +749,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -799,7 +765,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -811,7 +777,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -827,7 +793,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -843,7 +809,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -855,7 +821,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -871,7 +837,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -887,7 +853,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -899,7 +865,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -911,7 +877,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -926,7 +892,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -945,7 +911,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -961,7 +927,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -977,7 +943,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -993,7 +959,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1009,7 +975,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1025,7 +991,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1041,7 +1007,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1053,7 +1019,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1065,7 +1031,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1084,7 +1050,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1103,7 +1069,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1122,7 +1088,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1137,7 +1103,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1152,7 +1118,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1167,7 +1133,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1186,7 +1152,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1202,7 +1168,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1218,7 +1184,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1234,7 +1200,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1250,7 +1216,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1266,7 +1232,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1282,7 +1248,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1294,7 +1260,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1309,7 +1275,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1328,7 +1294,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1344,7 +1310,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1356,7 +1322,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1372,7 +1338,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1384,7 +1350,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1396,7 +1362,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1415,7 +1381,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1434,7 +1400,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1473,16 +1439,6 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_sim_crc_axi_master_0_2.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
|
||||
-293
@@ -1,293 +0,0 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Jan 31 01:46:20 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim.bd
|
||||
--Design : crc_axi_master_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=4,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
|
||||
end crc_axi_master_sim;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim is
|
||||
component crc_axi_master_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
component crc_axi_master_sim_axi3_slave_verif_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_RLAST : out STD_LOGIC;
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WLAST : in STD_LOGIC;
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_axi3_slave_verif_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
start : out STD_LOGIC;
|
||||
write : out STD_LOGIC;
|
||||
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_idle : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
component crc_axi_master_sim_crc_axi_ram_0_0 is
|
||||
port (
|
||||
waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : in STD_LOGIC;
|
||||
raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_0_2 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
start : in STD_LOGIC;
|
||||
write : in STD_LOGIC;
|
||||
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ip_idle : out STD_LOGIC;
|
||||
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : out STD_LOGIC;
|
||||
raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_0_2;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_idle : STD_LOGIC;
|
||||
signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_re : STD_LOGIC;
|
||||
signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_we : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
|
||||
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
begin
|
||||
axi3_slave_verif_0: component crc_axi_master_sim_axi3_slave_verif_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
S_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
S_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
S_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
S_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
S_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
S_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
S_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
S_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
S_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
S_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
S_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
S_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
S_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
S_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
S_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
S_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
S_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
S_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
S_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
S_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
S_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
S_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
S_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
S_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
S_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
S_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_AWID(0) => NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED(0),
|
||||
M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
|
||||
M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED(31 downto 0),
|
||||
M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
ip_idle => crc_axi_master_0_idle,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
|
||||
port map (
|
||||
addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
axi_idle => crc_axi_master_0_idle,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
|
||||
port map (
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we
|
||||
);
|
||||
end STRUCTURE;
|
||||
-293
@@ -1,293 +0,0 @@
|
||||
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
--Date : Fri Jan 31 01:46:20 2025
|
||||
--Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
--Command : generate_target crc_axi_master_sim.bd
|
||||
--Design : crc_axi_master_sim
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity crc_axi_master_sim is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of crc_axi_master_sim : entity is "crc_axi_master_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=crc_axi_master_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=4,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}";
|
||||
attribute HW_HANDOFF : string;
|
||||
attribute HW_HANDOFF of crc_axi_master_sim : entity is "crc_axi_master_sim.hwdef";
|
||||
end crc_axi_master_sim;
|
||||
|
||||
architecture STRUCTURE of crc_axi_master_sim is
|
||||
component crc_axi_master_sim_clk_rst_generator_0_0 is
|
||||
port (
|
||||
clk_in : in STD_LOGIC;
|
||||
rst_in : in STD_LOGIC;
|
||||
clk : out STD_LOGIC;
|
||||
rst_n : out STD_LOGIC;
|
||||
stop_simulation : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_clk_rst_generator_0_0;
|
||||
component crc_axi_master_sim_axi3_slave_verif_0_0 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
S_AXI_ARVALID : in STD_LOGIC;
|
||||
S_AXI_ARREADY : out STD_LOGIC;
|
||||
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_ARID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RVALID : out STD_LOGIC;
|
||||
S_AXI_RREADY : in STD_LOGIC;
|
||||
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_RID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S_AXI_RLAST : out STD_LOGIC;
|
||||
S_AXI_AWVALID : in STD_LOGIC;
|
||||
S_AXI_AWREADY : out STD_LOGIC;
|
||||
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S_AXI_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S_AXI_WVALID : in STD_LOGIC;
|
||||
S_AXI_WREADY : out STD_LOGIC;
|
||||
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S_AXI_WLAST : in STD_LOGIC;
|
||||
S_AXI_BVALID : out STD_LOGIC;
|
||||
S_AXI_BREADY : in STD_LOGIC;
|
||||
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_axi3_slave_verif_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_sim_c_0_0 is
|
||||
port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
start : out STD_LOGIC;
|
||||
write : out STD_LOGIC;
|
||||
addr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_idle : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_sim_c_0_0;
|
||||
component crc_axi_master_sim_crc_axi_ram_0_0 is
|
||||
port (
|
||||
waddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : in STD_LOGIC;
|
||||
raddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : in STD_LOGIC
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_ram_0_0;
|
||||
component crc_axi_master_sim_crc_axi_master_0_2 is
|
||||
port (
|
||||
CLK : in STD_LOGIC;
|
||||
RESETN : in STD_LOGIC;
|
||||
start : in STD_LOGIC;
|
||||
write : in STD_LOGIC;
|
||||
addr_axi : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
size : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
ip_idle : out STD_LOGIC;
|
||||
waddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
we : out STD_LOGIC;
|
||||
raddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
re : out STD_LOGIC;
|
||||
M_AXI_ARREADY : in STD_LOGIC;
|
||||
M_AXI_ARVALID : out STD_LOGIC;
|
||||
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_RREADY : out STD_LOGIC;
|
||||
M_AXI_RVALID : in STD_LOGIC;
|
||||
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_RLAST : in STD_LOGIC;
|
||||
M_AXI_AWREADY : in STD_LOGIC;
|
||||
M_AXI_AWVALID : out STD_LOGIC;
|
||||
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WREADY : in STD_LOGIC;
|
||||
M_AXI_WVALID : out STD_LOGIC;
|
||||
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_WLAST : out STD_LOGIC;
|
||||
M_AXI_WID : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BREADY : out STD_LOGIC;
|
||||
M_AXI_BVALID : in STD_LOGIC;
|
||||
M_AXI_BID : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
end component crc_axi_master_sim_crc_axi_master_0_2;
|
||||
signal clk_rst_generator_0_clk : STD_LOGIC;
|
||||
signal clk_rst_generator_0_rst_n : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_ARVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_AWVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_BVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal crc_axi_master_0_M_AXI_RLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_RVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WLAST : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WREADY : STD_LOGIC;
|
||||
signal crc_axi_master_0_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_M_AXI_WVALID : STD_LOGIC;
|
||||
signal crc_axi_master_0_idle : STD_LOGIC;
|
||||
signal crc_axi_master_0_raddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_re : STD_LOGIC;
|
||||
signal crc_axi_master_0_waddr : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_0_we : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_addr : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_size : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal crc_axi_master_sim_c_0_start : STD_LOGIC;
|
||||
signal crc_axi_master_sim_c_0_write : STD_LOGIC;
|
||||
signal crc_axi_ram_0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
signal NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
begin
|
||||
axi3_slave_verif_0: component crc_axi_master_sim_axi3_slave_verif_0_0
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
S_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
S_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
S_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
S_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
S_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
S_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
S_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
S_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
S_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
S_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
S_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
S_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
S_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
S_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
S_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
S_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
S_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
S_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
S_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
S_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
S_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
S_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
S_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
S_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
S_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
S_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
S_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID
|
||||
);
|
||||
clk_rst_generator_0: component crc_axi_master_sim_clk_rst_generator_0_0
|
||||
port map (
|
||||
clk => clk_rst_generator_0_clk,
|
||||
clk_in => '1',
|
||||
rst_in => '0',
|
||||
rst_n => clk_rst_generator_0_rst_n,
|
||||
stop_simulation => '0'
|
||||
);
|
||||
crc_axi_master_0: component crc_axi_master_sim_crc_axi_master_0_2
|
||||
port map (
|
||||
CLK => clk_rst_generator_0_clk,
|
||||
M_AXI_ARADDR(31 downto 0) => crc_axi_master_0_M_AXI_ARADDR(31 downto 0),
|
||||
M_AXI_ARBURST(1 downto 0) => crc_axi_master_0_M_AXI_ARBURST(1 downto 0),
|
||||
M_AXI_ARCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_ARID(0) => crc_axi_master_0_M_AXI_ARID(0),
|
||||
M_AXI_ARLEN(3 downto 0) => crc_axi_master_0_M_AXI_ARLEN(3 downto 0),
|
||||
M_AXI_ARPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_ARREADY => crc_axi_master_0_M_AXI_ARREADY,
|
||||
M_AXI_ARSIZE(2 downto 0) => crc_axi_master_0_M_AXI_ARSIZE(2 downto 0),
|
||||
M_AXI_ARVALID => crc_axi_master_0_M_AXI_ARVALID,
|
||||
M_AXI_AWADDR(31 downto 0) => crc_axi_master_0_M_AXI_AWADDR(31 downto 0),
|
||||
M_AXI_AWBURST(1 downto 0) => crc_axi_master_0_M_AXI_AWBURST(1 downto 0),
|
||||
M_AXI_AWCACHE(3 downto 0) => NLW_crc_axi_master_0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
|
||||
M_AXI_AWID(0) => NLW_crc_axi_master_0_M_AXI_AWID_UNCONNECTED(0),
|
||||
M_AXI_AWLEN(3 downto 0) => crc_axi_master_0_M_AXI_AWLEN(3 downto 0),
|
||||
M_AXI_AWPROT(2 downto 0) => NLW_crc_axi_master_0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
|
||||
M_AXI_AWREADY => crc_axi_master_0_M_AXI_AWREADY,
|
||||
M_AXI_AWSIZE(2 downto 0) => crc_axi_master_0_M_AXI_AWSIZE(2 downto 0),
|
||||
M_AXI_AWVALID => crc_axi_master_0_M_AXI_AWVALID,
|
||||
M_AXI_BID(31 downto 0) => B"00000000000000000000000000000000",
|
||||
M_AXI_BREADY => crc_axi_master_0_M_AXI_BREADY,
|
||||
M_AXI_BRESP(1 downto 0) => crc_axi_master_0_M_AXI_BRESP(1 downto 0),
|
||||
M_AXI_BVALID => crc_axi_master_0_M_AXI_BVALID,
|
||||
M_AXI_RDATA(31 downto 0) => crc_axi_master_0_M_AXI_RDATA(31 downto 0),
|
||||
M_AXI_RID(0) => crc_axi_master_0_M_AXI_RID(0),
|
||||
M_AXI_RLAST => crc_axi_master_0_M_AXI_RLAST,
|
||||
M_AXI_RREADY => crc_axi_master_0_M_AXI_RREADY,
|
||||
M_AXI_RRESP(1 downto 0) => crc_axi_master_0_M_AXI_RRESP(1 downto 0),
|
||||
M_AXI_RVALID => crc_axi_master_0_M_AXI_RVALID,
|
||||
M_AXI_WDATA(31 downto 0) => crc_axi_master_0_M_AXI_WDATA(31 downto 0),
|
||||
M_AXI_WID(31 downto 0) => NLW_crc_axi_master_0_M_AXI_WID_UNCONNECTED(31 downto 0),
|
||||
M_AXI_WLAST => crc_axi_master_0_M_AXI_WLAST,
|
||||
M_AXI_WREADY => crc_axi_master_0_M_AXI_WREADY,
|
||||
M_AXI_WSTRB(3 downto 0) => crc_axi_master_0_M_AXI_WSTRB(3 downto 0),
|
||||
M_AXI_WVALID => crc_axi_master_0_M_AXI_WVALID,
|
||||
RESETN => clk_rst_generator_0_rst_n,
|
||||
addr_axi(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
ip_idle => crc_axi_master_0_idle,
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_master_sim_c_0: component crc_axi_master_sim_crc_axi_master_sim_c_0_0
|
||||
port map (
|
||||
addr(31 downto 0) => crc_axi_master_sim_c_0_addr(31 downto 0),
|
||||
axi_idle => crc_axi_master_0_idle,
|
||||
clk => clk_rst_generator_0_clk,
|
||||
resetn => clk_rst_generator_0_rst_n,
|
||||
size(3 downto 0) => crc_axi_master_sim_c_0_size(3 downto 0),
|
||||
start => crc_axi_master_sim_c_0_start,
|
||||
write => crc_axi_master_sim_c_0_write
|
||||
);
|
||||
crc_axi_ram_0: component crc_axi_master_sim_crc_axi_ram_0_0
|
||||
port map (
|
||||
raddr(3 downto 0) => crc_axi_master_0_raddr(3 downto 0),
|
||||
rdata(31 downto 0) => crc_axi_ram_0_rdata(31 downto 0),
|
||||
re => crc_axi_master_0_re,
|
||||
waddr(3 downto 0) => crc_axi_master_0_waddr(3 downto 0),
|
||||
wdata(31 downto 0) => crc_axi_master_0_wdata(31 downto 0),
|
||||
we => crc_axi_master_0_we
|
||||
);
|
||||
end STRUCTURE;
|
||||
+4
-4
@@ -2,10 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="crc_axi_master_syn" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738284371"/>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738336160"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738336160"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738336160"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738336160"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
+94
-93
@@ -1746,7 +1746,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1762,7 +1762,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1782,7 +1782,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1809,7 +1809,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1836,7 +1836,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1863,7 +1863,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1890,7 +1890,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1917,7 +1917,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1944,7 +1944,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1971,7 +1971,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1998,7 +1998,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2025,7 +2025,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2048,7 +2048,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2071,7 +2071,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2095,7 +2095,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2122,7 +2122,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2145,7 +2145,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2168,7 +2168,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2191,7 +2191,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2215,7 +2215,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2239,7 +2239,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2259,7 +2259,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2279,7 +2279,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2306,7 +2306,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2333,7 +2333,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2360,7 +2360,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2387,7 +2387,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2414,7 +2414,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2441,7 +2441,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2468,7 +2468,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2495,7 +2495,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2522,7 +2522,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2549,7 +2549,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2572,7 +2572,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2595,7 +2595,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2619,7 +2619,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2643,7 +2643,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2667,7 +2667,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2687,7 +2687,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2707,7 +2707,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2727,7 +2727,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2750,7 +2750,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2773,7 +2773,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -2800,7 +2800,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2824,7 +2824,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2848,7 +2848,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2872,7 +2872,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2896,7 +2896,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2920,7 +2920,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2944,7 +2944,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2968,7 +2968,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -2992,7 +2992,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3012,7 +3012,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3032,7 +3032,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3059,7 +3059,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3083,7 +3083,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3103,7 +3103,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3123,7 +3123,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3143,7 +3143,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3170,7 +3170,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3193,7 +3193,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3216,7 +3216,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3240,7 +3240,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3264,7 +3264,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3288,7 +3288,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3312,7 +3312,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3336,7 +3336,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3360,7 +3360,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3384,7 +3384,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3408,7 +3408,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3432,7 +3432,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3452,7 +3452,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -3472,7 +3472,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3499,7 +3499,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3526,7 +3526,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3549,7 +3549,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3572,7 +3572,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -3595,7 +3595,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -4387,7 +4387,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
@@ -4420,31 +4420,32 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SI_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
|
||||
+11
-11
@@ -40687,22 +40687,22 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_BRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_BURST" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_CACHE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_LOCK" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_PROT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_QOS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_RRESP" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.ID_WIDTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
@@ -40710,7 +40710,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.PROTOCOL" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.READ_WRITE_MODE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACP.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
|
||||
+5
-50
@@ -2,55 +2,10 @@
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="crc_axi_master_syn_HP_Port" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1738284525"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1738284525"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1738284525"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1738284525"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth\crc_axi_master_syn_HP_Port.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_syn_HP_Port.vhd" Type="VHDL">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_syn_HP_Port_ooc.xdc" Type="XDC">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<UsedIn Val="OUT_OF_CONTEXT"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff\crc_axi_master_syn_HP_Port.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="crc_axi_master_syn_HP_Port.bda">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth\crc_axi_master_syn_HP_Port.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim\crc_axi_master_syn_HP_Port.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1738336148"/>
|
||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1738336148"/>
|
||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1738336148"/>
|
||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1738336148"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
||||
-14
@@ -1,14 +0,0 @@
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# This constraints file is not used in normal top-down synthesis (default flow
|
||||
# of Vivado)
|
||||
################################################################################
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK0 -period 10 [get_pins PS/processing_system7_0/FCLK_CLK0]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK1 -period 8 [get_pins PS/processing_system7_0/FCLK_CLK1]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK2 -period 5 [get_pins PS/processing_system7_0/FCLK_CLK2]
|
||||
create_clock -name PS_processing_system7_0_FCLK_CLK3 -period 15 [get_pins PS/processing_system7_0/FCLK_CLK3]
|
||||
|
||||
################################################################################
|
||||
+51
-247
@@ -514,7 +514,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -652,7 +652,7 @@
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
@@ -689,101 +689,6 @@
|
||||
</spirit:addressSpace>
|
||||
</spirit:addressSpaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b8bf5ced</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>crc_axi_master</spirit:modelName>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:679a87f9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 00:49:53 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:679a87f9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:679a87f9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_HP_Port_crc_axi_master_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 00:48:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:b8bf5ced</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>crc_axi_master_syn_HP_Port_crc_axi_master_0_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Fri Jan 31 00:48:45 UTC 2025</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:679a87f9</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
@@ -792,8 +697,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -805,8 +709,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -818,8 +721,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -831,8 +733,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -848,8 +749,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -865,8 +765,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -878,8 +777,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -895,8 +793,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -912,8 +809,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -925,8 +821,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -942,8 +837,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -959,8 +853,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -972,8 +865,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -985,8 +877,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1001,8 +892,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1021,8 +911,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1038,8 +927,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1055,8 +943,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1072,8 +959,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1089,8 +975,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1106,8 +991,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1123,8 +1007,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1136,8 +1019,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1149,8 +1031,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1169,8 +1050,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1189,8 +1069,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1209,8 +1088,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1225,8 +1103,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1241,8 +1118,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1257,8 +1133,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1277,8 +1152,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1294,8 +1168,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1311,8 +1184,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1328,8 +1200,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1345,8 +1216,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1362,8 +1232,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1379,8 +1248,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1392,8 +1260,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1408,8 +1275,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1428,8 +1294,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1445,8 +1310,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1458,8 +1322,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1475,8 +1338,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1488,8 +1350,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1501,8 +1362,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1521,8 +1381,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1541,8 +1400,7 @@
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1581,60 +1439,6 @@
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_0_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>crc_axi_master_syn_HP_Port_crc_axi_master_0_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>xilinx.com:module_ref:crc_axi_master:1.0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
@@ -1671,7 +1475,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
||||
@@ -1679,7 +1483,7 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
|
||||
-1619
File diff suppressed because it is too large
Load Diff
-74
@@ -1,74 +0,0 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
|
||||
// Date : Fri Jan 31 01:49:53 2025
|
||||
// Host : BiermannSurface running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// c:/hs/es-abschlussprojekt/Hardware/crc_axi_master/crc_axi_master.gen/sources_1/bd/crc_axi_master_syn_HP_Port/ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_stub.v
|
||||
// Design : crc_axi_master_syn_HP_Port_crc_axi_master_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z020clg400-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "crc_axi_master,Vivado 2023.1" *)
|
||||
module crc_axi_master_syn_HP_Port_crc_axi_master_0_0(CLK, RESETN, start, write, addr_axi, size, ip_idle,
|
||||
waddr, wdata, we, raddr, rdata, re, M_AXI_ARREADY, M_AXI_ARVALID, M_AXI_ARADDR, M_AXI_ARID,
|
||||
M_AXI_ARLEN, M_AXI_ARSIZE, M_AXI_ARBURST, M_AXI_ARPROT, M_AXI_ARCACHE, M_AXI_RREADY,
|
||||
M_AXI_RVALID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RID, M_AXI_RLAST, M_AXI_AWREADY, M_AXI_AWVALID,
|
||||
M_AXI_AWADDR, M_AXI_AWLEN, M_AXI_AWSIZE, M_AXI_AWID, M_AXI_AWBURST, M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE, M_AXI_WREADY, M_AXI_WVALID, M_AXI_WDATA, M_AXI_WSTRB, M_AXI_WLAST, M_AXI_WID,
|
||||
M_AXI_BREADY, M_AXI_BVALID, M_AXI_BID, M_AXI_BRESP)
|
||||
/* synthesis syn_black_box black_box_pad_pin="RESETN,start,write,addr_axi[31:0],size[3:0],ip_idle,waddr[3:0],wdata[31:0],we,raddr[3:0],rdata[31:0],re,M_AXI_ARREADY,M_AXI_ARVALID,M_AXI_ARADDR[31:0],M_AXI_ARID[0:0],M_AXI_ARLEN[3:0],M_AXI_ARSIZE[2:0],M_AXI_ARBURST[1:0],M_AXI_ARPROT[2:0],M_AXI_ARCACHE[3:0],M_AXI_RREADY,M_AXI_RVALID,M_AXI_RDATA[31:0],M_AXI_RRESP[1:0],M_AXI_RID[0:0],M_AXI_RLAST,M_AXI_AWREADY,M_AXI_AWVALID,M_AXI_AWADDR[31:0],M_AXI_AWLEN[3:0],M_AXI_AWSIZE[2:0],M_AXI_AWID[0:0],M_AXI_AWBURST[1:0],M_AXI_AWPROT[2:0],M_AXI_AWCACHE[3:0],M_AXI_WREADY,M_AXI_WVALID,M_AXI_WDATA[31:0],M_AXI_WSTRB[3:0],M_AXI_WLAST,M_AXI_WID[31:0],M_AXI_BREADY,M_AXI_BVALID,M_AXI_BID[31:0],M_AXI_BRESP[1:0]" */
|
||||
/* synthesis syn_force_seq_prim="CLK" */;
|
||||
input CLK /* synthesis syn_isclock = 1 */;
|
||||
input RESETN;
|
||||
input start;
|
||||
input write;
|
||||
input [31:0]addr_axi;
|
||||
input [3:0]size;
|
||||
output ip_idle;
|
||||
output [3:0]waddr;
|
||||
output [31:0]wdata;
|
||||
output we;
|
||||
output [3:0]raddr;
|
||||
input [31:0]rdata;
|
||||
output re;
|
||||
input M_AXI_ARREADY;
|
||||
output M_AXI_ARVALID;
|
||||
output [31:0]M_AXI_ARADDR;
|
||||
output [0:0]M_AXI_ARID;
|
||||
output [3:0]M_AXI_ARLEN;
|
||||
output [2:0]M_AXI_ARSIZE;
|
||||
output [1:0]M_AXI_ARBURST;
|
||||
output [2:0]M_AXI_ARPROT;
|
||||
output [3:0]M_AXI_ARCACHE;
|
||||
output M_AXI_RREADY;
|
||||
input M_AXI_RVALID;
|
||||
input [31:0]M_AXI_RDATA;
|
||||
input [1:0]M_AXI_RRESP;
|
||||
input [0:0]M_AXI_RID;
|
||||
input M_AXI_RLAST;
|
||||
input M_AXI_AWREADY;
|
||||
output M_AXI_AWVALID;
|
||||
output [31:0]M_AXI_AWADDR;
|
||||
output [3:0]M_AXI_AWLEN;
|
||||
output [2:0]M_AXI_AWSIZE;
|
||||
output [0:0]M_AXI_AWID;
|
||||
output [1:0]M_AXI_AWBURST;
|
||||
output [2:0]M_AXI_AWPROT;
|
||||
output [3:0]M_AXI_AWCACHE;
|
||||
input M_AXI_WREADY;
|
||||
output M_AXI_WVALID;
|
||||
output [31:0]M_AXI_WDATA;
|
||||
output [3:0]M_AXI_WSTRB;
|
||||
output M_AXI_WLAST;
|
||||
output [31:0]M_AXI_WID;
|
||||
output M_AXI_BREADY;
|
||||
input M_AXI_BVALID;
|
||||
input [31:0]M_AXI_BID;
|
||||
input [1:0]M_AXI_BRESP;
|
||||
endmodule
|
||||
-267
@@ -1,267 +0,0 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_master:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
start : IN STD_LOGIC;
|
||||
write : IN STD_LOGIC;
|
||||
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
ip_idle : OUT STD_LOGIC;
|
||||
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : OUT STD_LOGIC;
|
||||
raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
LUTRAM_AWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
start : IN STD_LOGIC;
|
||||
write : IN STD_LOGIC;
|
||||
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
ip_idle : OUT STD_LOGIC;
|
||||
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : OUT STD_LOGIC;
|
||||
raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT crc_axi_master;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NU" &
|
||||
"M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
BEGIN
|
||||
U0 : crc_axi_master
|
||||
GENERIC MAP (
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
LUTRAM_AWIDTH => 4
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
start => start,
|
||||
write => write,
|
||||
addr_axi => addr_axi,
|
||||
size => size,
|
||||
ip_idle => ip_idle,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
raddr => raddr,
|
||||
rdata => rdata,
|
||||
re => re,
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch;
|
||||
-275
@@ -1,275 +0,0 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:module_ref:crc_axi_master:1.0
|
||||
-- IP Revision: 1
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
start : IN STD_LOGIC;
|
||||
write : IN STD_LOGIC;
|
||||
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
ip_idle : OUT STD_LOGIC;
|
||||
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : OUT STD_LOGIC;
|
||||
raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0;
|
||||
|
||||
ARCHITECTURE crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT crc_axi_master IS
|
||||
GENERIC (
|
||||
DWIDTH : INTEGER;
|
||||
IDWIDTH : INTEGER;
|
||||
MAX_BURSTLEN : INTEGER;
|
||||
LUTRAM_AWIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESETN : IN STD_LOGIC;
|
||||
start : IN STD_LOGIC;
|
||||
write : IN STD_LOGIC;
|
||||
addr_axi : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
size : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
ip_idle : OUT STD_LOGIC;
|
||||
waddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
we : OUT STD_LOGIC;
|
||||
raddr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
re : OUT STD_LOGIC;
|
||||
M_AXI_ARREADY : IN STD_LOGIC;
|
||||
M_AXI_ARVALID : OUT STD_LOGIC;
|
||||
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_RREADY : OUT STD_LOGIC;
|
||||
M_AXI_RVALID : IN STD_LOGIC;
|
||||
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_RLAST : IN STD_LOGIC;
|
||||
M_AXI_AWREADY : IN STD_LOGIC;
|
||||
M_AXI_AWVALID : OUT STD_LOGIC;
|
||||
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WREADY : IN STD_LOGIC;
|
||||
M_AXI_WVALID : OUT STD_LOGIC;
|
||||
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
M_AXI_WLAST : OUT STD_LOGIC;
|
||||
M_AXI_WID : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BREADY : OUT STD_LOGIC;
|
||||
M_AXI_BVALID : IN STD_LOGIC;
|
||||
M_AXI_BID : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT crc_axi_master;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master,Vivado 2023.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch : ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "crc_axi_master_syn_HP_Port_crc_axi_master_0_0,crc_axi_master,{x_ipProduct=Vivado 2023.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=crc_axi_master,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DWIDTH=32,IDWIDTH=1,MAX_BURSTLEN=16,LUTRAM_AWIDTH=4}";
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
|
||||
ATTRIBUTE IP_DEFINITION_SOURCE OF crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch: ARCHITECTURE IS "module_ref";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME CLK, ASSOCIATED_BUSIF M_AXI, ASSOCIATED_RESET RESETN, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF M_AXI_ARREADY: SIGNAL IS "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.0, CLK_DOMAIN crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0, NU" &
|
||||
"M_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF RESETN: SIGNAL IS "XIL_INTERFACENAME RESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF RESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 RESETN RST";
|
||||
BEGIN
|
||||
U0 : crc_axi_master
|
||||
GENERIC MAP (
|
||||
DWIDTH => 32,
|
||||
IDWIDTH => 1,
|
||||
MAX_BURSTLEN => 16,
|
||||
LUTRAM_AWIDTH => 4
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESETN => RESETN,
|
||||
start => start,
|
||||
write => write,
|
||||
addr_axi => addr_axi,
|
||||
size => size,
|
||||
ip_idle => ip_idle,
|
||||
waddr => waddr,
|
||||
wdata => wdata,
|
||||
we => we,
|
||||
raddr => raddr,
|
||||
rdata => rdata,
|
||||
re => re,
|
||||
M_AXI_ARREADY => M_AXI_ARREADY,
|
||||
M_AXI_ARVALID => M_AXI_ARVALID,
|
||||
M_AXI_ARADDR => M_AXI_ARADDR,
|
||||
M_AXI_ARID => M_AXI_ARID,
|
||||
M_AXI_ARLEN => M_AXI_ARLEN,
|
||||
M_AXI_ARSIZE => M_AXI_ARSIZE,
|
||||
M_AXI_ARBURST => M_AXI_ARBURST,
|
||||
M_AXI_ARPROT => M_AXI_ARPROT,
|
||||
M_AXI_ARCACHE => M_AXI_ARCACHE,
|
||||
M_AXI_RREADY => M_AXI_RREADY,
|
||||
M_AXI_RVALID => M_AXI_RVALID,
|
||||
M_AXI_RDATA => M_AXI_RDATA,
|
||||
M_AXI_RRESP => M_AXI_RRESP,
|
||||
M_AXI_RID => M_AXI_RID,
|
||||
M_AXI_RLAST => M_AXI_RLAST,
|
||||
M_AXI_AWREADY => M_AXI_AWREADY,
|
||||
M_AXI_AWVALID => M_AXI_AWVALID,
|
||||
M_AXI_AWADDR => M_AXI_AWADDR,
|
||||
M_AXI_AWLEN => M_AXI_AWLEN,
|
||||
M_AXI_AWSIZE => M_AXI_AWSIZE,
|
||||
M_AXI_AWID => M_AXI_AWID,
|
||||
M_AXI_AWBURST => M_AXI_AWBURST,
|
||||
M_AXI_AWPROT => M_AXI_AWPROT,
|
||||
M_AXI_AWCACHE => M_AXI_AWCACHE,
|
||||
M_AXI_WREADY => M_AXI_WREADY,
|
||||
M_AXI_WVALID => M_AXI_WVALID,
|
||||
M_AXI_WDATA => M_AXI_WDATA,
|
||||
M_AXI_WSTRB => M_AXI_WSTRB,
|
||||
M_AXI_WLAST => M_AXI_WLAST,
|
||||
M_AXI_WID => M_AXI_WID,
|
||||
M_AXI_BREADY => M_AXI_BREADY,
|
||||
M_AXI_BVALID => M_AXI_BVALID,
|
||||
M_AXI_BID => M_AXI_BID,
|
||||
M_AXI_BRESP => M_AXI_BRESP
|
||||
);
|
||||
END crc_axi_master_syn_HP_Port_crc_axi_master_0_0_arch;
|
||||
-1601
File diff suppressed because it is too large
Load Diff
-1601
File diff suppressed because it is too large
Load Diff
+3
-3
@@ -355,7 +355,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>8177cd08</spirit:value>
|
||||
<spirit:value>27642c7b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -368,7 +368,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>8177cd08</spirit:value>
|
||||
<spirit:value>27642c7b</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@@ -1231,7 +1231,7 @@
|
||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
||||
</xilinx:designToolContexts>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2025-01-31T00:46:10Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreCreationDateTime>2025-01-31T15:09:11Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
|
||||
|
||||
+1
-2
@@ -7,8 +7,7 @@
|
||||
"name": "crc_axi_master_sim",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "None",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"clk_rst_generator_0": "",
|
||||
|
||||
+2
-2
@@ -81,10 +81,10 @@
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+12
-12
@@ -7,22 +7,22 @@
|
||||
# -string -flagsOSRD
|
||||
preplace inst clk_rst_generator_0 -pg 1 -lvl 1 -x 90 -y 160 -defaultsOSRD
|
||||
preplace inst axi3_slave_verif_0 -pg 1 -lvl 4 -x 1070 -y 10 -defaultsOSRD
|
||||
preplace inst crc_axi_master_sim_c_0 -pg 1 -lvl 2 -x 400 -y 170 -defaultsOSRD
|
||||
preplace inst crc_axi_master_sim_c_0 -pg 1 -lvl 2 -x 400 -y 180 -defaultsOSRD
|
||||
preplace inst crc_axi_ram_0 -pg 1 -lvl 2 -x 400 -y 420 -defaultsOSRD
|
||||
preplace inst crc_axi_master_0 -pg 1 -lvl 3 -x 770 -y 0 -defaultsOSRD
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 200 10 540 -120 960
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 210 30 640 120 960
|
||||
preplace netloc crc_axi_master_0_idle 1 1 3 250 60 590J 130 930
|
||||
preplace netloc crc_axi_master_0_raddr 1 1 3 220 40 610J 140 910
|
||||
preplace netloc crc_axi_master_0_re 1 1 3 240 50 580J 150 900
|
||||
preplace netloc crc_axi_master_0_waddr 1 1 3 260 70 560J 160 940
|
||||
preplace netloc crc_axi_master_0_wdata 1 1 3 230 -130 NJ -130 900
|
||||
preplace netloc crc_axi_master_0_we 1 1 3 270 80 530J 170 920
|
||||
preplace netloc clk_rst_generator_0_clk 1 1 3 200 10 550 -120 960
|
||||
preplace netloc clk_rst_generator_0_rst_n 1 1 3 210 40 610 120 960
|
||||
preplace netloc crc_axi_master_0_idle 1 1 3 240 60 620J 130 930
|
||||
preplace netloc crc_axi_master_0_raddr 1 1 3 250 70 580J 140 910
|
||||
preplace netloc crc_axi_master_0_re 1 1 3 230 50 590J 150 900
|
||||
preplace netloc crc_axi_master_0_waddr 1 1 3 260 80 550J 160 940
|
||||
preplace netloc crc_axi_master_0_wdata 1 1 3 220 -130 NJ -130 900
|
||||
preplace netloc crc_axi_master_0_we 1 1 3 270 90 540J 170 920
|
||||
preplace netloc crc_axi_master_sim_c_0_addr 1 2 1 600 20n
|
||||
preplace netloc crc_axi_master_sim_c_0_size 1 2 1 620 40n
|
||||
preplace netloc crc_axi_master_sim_c_0_size 1 2 1 630 40n
|
||||
preplace netloc crc_axi_master_sim_c_0_start 1 2 1 570 -20n
|
||||
preplace netloc crc_axi_master_sim_c_0_write 1 2 1 550 0n
|
||||
preplace netloc crc_axi_ram_0_rdata 1 2 1 630 60n
|
||||
preplace netloc crc_axi_master_sim_c_0_write 1 2 1 530 0n
|
||||
preplace netloc crc_axi_ram_0_rdata 1 2 1 640 60n
|
||||
preplace netloc crc_axi_master_0_M_AXI 1 3 1 950 -60n
|
||||
levelinfo -pg 1 -20 90 400 770 1070 1170
|
||||
pagesize -pg 1 -db -bbox -sgen -20 -150 1280 530
|
||||
|
||||
+16
-16
@@ -145,26 +145,26 @@
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -222,7 +222,7 @@
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -315,7 +315,7 @@
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
|
||||
+11
-11
@@ -1131,22 +1131,22 @@
|
||||
"DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "3", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "5", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "5", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "5", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "5", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
||||
+1
-10
@@ -7,8 +7,7 @@
|
||||
"name": "crc_axi_master_syn_HP_Port",
|
||||
"rev_ctrl_bd_flag": "RevCtrlBdOff",
|
||||
"synth_flow_mode": "Hierarchical",
|
||||
"tool_version": "2023.1",
|
||||
"validated": "true"
|
||||
"tool_version": "2023.1"
|
||||
},
|
||||
"design_tree": {
|
||||
"crc_axi_master_contr_0": "",
|
||||
@@ -1956,10 +1955,6 @@
|
||||
"MAX_BURST_LENGTH": {
|
||||
"value": "16",
|
||||
"value_src": "auto"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
},
|
||||
"address_space_ref": "M_AXI",
|
||||
@@ -2164,10 +2159,6 @@
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "RESETN",
|
||||
"value_src": "constant"
|
||||
},
|
||||
"CLK_DOMAIN": {
|
||||
"value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0",
|
||||
"value_src": "default_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
+2
-2
@@ -126,7 +126,7 @@
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
@@ -192,7 +192,7 @@
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "crc_axi_master_syn_HP_Port_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.21552",
|
||||
"Default View_TopLeft":"5,0",
|
||||
"Default View_TopLeft":"5,-2",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
|
||||
# -string -flagsOSRD
|
||||
|
||||
@@ -119,9 +119,6 @@
|
||||
<CompFileExtendedInfo CompFileName="crc_axi_master_syn_HP_Port.bd" FileRelPathName="ip/crc_axi_master_syn_HP_Port_processing_system7_0_0/crc_axi_master_syn_HP_Port_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="crc_axi_master_syn_HP_Port_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="crc_axi_master_syn_HP_Port.bd" FileRelPathName="ip/crc_axi_master_syn_HP_Port_crc_axi_master_0_0/crc_axi_master_syn_HP_Port_crc_axi_master_0_0.xci">
|
||||
<Proxy FileSetName="crc_axi_master_syn_HP_Port_crc_axi_master_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="crc_axi_master_syn_HP_Port.bd" FileRelPathName="ip/crc_axi_master_syn_HP_Port_system_ila_0_0/crc_axi_master_syn_HP_Port_system_ila_0_0.xci">
|
||||
<Proxy FileSetName="crc_axi_master_syn_HP_Port_system_ila_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
@@ -138,12 +135,12 @@
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="crc_axi_master_syn_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_system_ila_0_0/crc_axi_master_syn_system_ila_0_0.xci">
|
||||
<Proxy FileSetName="crc_axi_master_syn_system_ila_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="crc_axi_master_syn.bd" FileRelPathName="ip/crc_axi_master_syn_processing_system7_0_0/crc_axi_master_syn_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="crc_axi_master_syn_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/crc_axi_master_syn/hdl/crc_axi_master_syn_wrapper.vhd">
|
||||
<FileInfo>
|
||||
@@ -159,14 +156,14 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axi_vip_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
|
||||
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_vip_0_0/design_1_axi_vip_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axi_vip_0_0"/>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_read_generator_0_0/design_1_axi_read_generator_0_0.xci">
|
||||
<Proxy FileSetName="design_1_axi_read_generator_0_0"/>
|
||||
@@ -324,12 +321,6 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="crc_axi_master_syn_HP_Port_crc_axi_master_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/crc_axi_master_syn_HP_Port_crc_axi_master_0_0" RelGenDir="$PGENDIR/crc_axi_master_syn_HP_Port_crc_axi_master_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="crc_axi_master_syn_HP_Port_crc_axi_master_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="crc_axi_master_syn_HP_Port_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/crc_axi_master_syn_HP_Port_system_ila_0_0" RelGenDir="$PGENDIR/crc_axi_master_syn_HP_Port_system_ila_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="crc_axi_master_syn_HP_Port_system_ila_0_0"/>
|
||||
@@ -425,7 +416,7 @@
|
||||
<ReportConfig DisplayName="synthesis_report" Name="synth_1_copy_1_synth_synthesis_report_0" Spec="" RunStep="synth_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper.vds">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Utilization - Synth Design" Name="synth_1_copy_1_synth_report_utilization_0" Spec="report_utilization" RunStep="synth_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_utilization_synth_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Utilization - Synth Design" Name="synth_1_copy_1_synth_report_utilization_0" Spec="report_utilization" RunStep="synth_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_utilization_synth.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
@@ -445,21 +436,7 @@
|
||||
</Run>
|
||||
<Run Id="crc_axi_master_syn_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="crc_axi_master_syn_HP_Port_crc_axi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_HP_Port_crc_axi_master_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_HP_Port_crc_axi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -469,9 +446,7 @@
|
||||
</Run>
|
||||
<Run Id="crc_axi_master_syn_HP_Port_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="crc_axi_master_syn_HP_Port_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_HP_Port_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/crc_axi_master_syn_HP_Port_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_system_ila_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -596,58 +571,58 @@
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023" CtrlBit="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_init_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_init.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_drc_opted_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_drc_opted.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_opted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_opted.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_io_placed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_io_placed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_utilization_placed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_utilization_placed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_control_sets_placed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_control_sets_placed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="verbose" Type="" Value="true"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_incremental_reuse_pre_placed.rpt_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_incremental_reuse_pre_placed.rpt.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_incremental_reuse_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_incremental_reuse_placed.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_placed.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_postplace_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_postplace_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_physopted_1.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_physopted.rpt" Version="1" Minor="0" IsDisabled="true">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
@@ -656,50 +631,50 @@
|
||||
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper.vdi">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_drc_routed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_drc_routed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_methodology_drc_routed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_methodology_drc_routed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_power_routed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_power_routed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_route_status_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_route_status.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_routed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_routed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_incremental_reuse_routed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_incremental_reuse_routed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_clock_utilization_routed_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_clock_utilization_routed.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_bus_skew_routed_1.rpt" Version="1" Minor="1">
|
||||
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_bus_skew_routed.rpt" Version="1" Minor="1">
|
||||
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_postroute_physopted_1.rpt" Version="1" Minor="0">
|
||||
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_timing_summary_postroute_physopted.rpt" Version="1" Minor="0">
|
||||
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
</ReportConfig>
|
||||
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_bus_skew_postroute_physopted_1.rpt" Version="1" Minor="1">
|
||||
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="crc_axi_master_syn_HP_Port_wrapper_bus_skew_postroute_physopted.rpt" Version="1" Minor="1">
|
||||
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||
@@ -733,28 +708,7 @@
|
||||
</Run>
|
||||
<Run Id="crc_axi_master_syn_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_system_ila_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="crc_axi_master_syn_HP_Port_crc_axi_master_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_HP_Port_crc_axi_master_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_HP_Port_crc_axi_master_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_crc_axi_master_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -771,9 +725,7 @@
|
||||
</Run>
|
||||
<Run Id="crc_axi_master_syn_HP_Port_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="crc_axi_master_syn_HP_Port_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="crc_axi_master_syn_HP_Port_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/crc_axi_master_syn_HP_Port_system_ila_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
Reference in New Issue
Block a user