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M3: Praktikumstermin Abschluss

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This commit is contained in:
Matthias Biermann
2024-11-28 13:30:01 +01:00
parent 1351a81381
commit c1d3ff190f
36 changed files with 417 additions and 856 deletions
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Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim.bxml
+5 -50
View File
@@ -2,55 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="af_sim" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1732630962"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732630962"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1732630962"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732630962"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\af_sim.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\af_sim.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="af_sim_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff\af_sim.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="af_sim.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth\af_sim.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim\af_sim.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1732725121"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1732725121"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1732725121"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1732725121"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/af_sim_ooc.xdc
-10
View File
@@ -1,10 +0,0 @@
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
################################################################################
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xml
+46 -90
View File
@@ -882,40 +882,6 @@
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axis_prog_audio_filter3</spirit:modelName>
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<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:08ca8409</spirit:value>
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<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>af_sim_axis_prog_audio_filt_0_0</spirit:modelName>
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<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
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<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:22:42 UTC 2024</spirit:value>
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<spirit:parameter>
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<spirit:value>9:08ca8409</spirit:value>
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<spirit:name>AXI_ACLK</spirit:name>
@@ -924,7 +890,7 @@
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@@ -936,7 +902,7 @@
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@@ -952,7 +918,7 @@
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@@ -967,7 +933,7 @@
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@@ -982,7 +948,7 @@
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@@ -998,7 +964,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1013,7 +979,7 @@
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1028,7 +994,7 @@
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1044,7 +1010,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1059,7 +1025,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1071,7 +1037,7 @@
<spirit:wireTypeDefs>
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<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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<spirit:driver>
@@ -1090,7 +1056,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1106,7 +1072,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1121,7 +1087,7 @@
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@@ -1136,7 +1102,7 @@
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@@ -1152,7 +1118,7 @@
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@@ -1164,7 +1130,7 @@
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@@ -1176,7 +1142,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1195,7 +1161,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1207,7 +1173,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1223,7 +1189,7 @@
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -1238,7 +1204,7 @@
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@@ -1253,7 +1219,7 @@
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@@ -1265,7 +1231,7 @@
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@@ -1281,7 +1247,7 @@
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@@ -1354,16 +1320,6 @@
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@@ -1427,36 +1383,36 @@
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/sim/af_sim.vhd
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@@ -1,205 +0,0 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 15:22:42 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target af_sim.bd
--Design : af_sim
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity af_sim is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef";
end af_sim;
architecture STRUCTURE of af_sim is
component af_sim_clk_rst_generator_0_0 is
port (
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end component af_sim_clk_rst_generator_0_0;
component af_sim_axis_audio_master_si_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC;
WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 )
);
end component af_sim_axis_audio_master_si_0_0;
component af_sim_axis_audio_mono2ster_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end component af_sim_axis_audio_mono2ster_0_0;
component af_sim_axis_audio_stereo2mo_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end component af_sim_axis_audio_stereo2mo_0_0;
component af_sim_axis_audio_slave_sim_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
FINISHED : out STD_LOGIC;
WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 )
);
end component af_sim_axis_audio_slave_sim_0_0;
component af_sim_axis_prog_audio_filt_0_0 is
port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component af_sim_axis_prog_audio_filt_0_0;
signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 );
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC;
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal clk_rst_generator_0_rst_n : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0
port map (
ACLK => clk_rst_generator_0_clk,
ARESETN => clk_rst_generator_0_rst_n,
M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID,
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
);
axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0
port map (
AXIS_ACLK => clk_rst_generator_0_clk,
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
);
axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0
port map (
ACLK => clk_rst_generator_0_clk,
ARESETN => clk_rst_generator_0_rst_n,
FINISHED => axis_audio_slave_sim_0_FINISHED,
S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
);
axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0
port map (
AXIS_ACLK => clk_rst_generator_0_clk,
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID
);
axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0
port map (
AXI_ACLK => clk_rst_generator_0_clk,
AXI_ARESETN => clk_rst_generator_0_rst_n,
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED,
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
S_AXIL_ARADDR(7 downto 0) => B"00000000",
S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED,
S_AXIL_ARVALID => '0',
S_AXIL_AWADDR(7 downto 0) => B"00000000",
S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED,
S_AXIL_AWVALID => '0',
S_AXIL_BREADY => '0',
S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0),
S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED,
S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0),
S_AXIL_RREADY => '0',
S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0),
S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED,
S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED,
S_AXIL_WSTRB(3 downto 0) => B"1111",
S_AXIL_WVALID => '0',
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
S_AXIS_TLAST => '0',
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
);
clk_rst_generator_0: component af_sim_clk_rst_generator_0_0
port map (
clk => clk_rst_generator_0_clk,
rst_n => clk_rst_generator_0_rst_n,
stop_simulation => axis_audio_slave_sim_0_FINISHED
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/af_sim/synth/af_sim.vhd
-205
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@@ -1,205 +0,0 @@
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 15:22:42 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Command : generate_target af_sim.bd
--Design : af_sim
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity af_sim is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of af_sim : entity is "af_sim,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=af_sim,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of af_sim : entity is "af_sim.hwdef";
end af_sim;
architecture STRUCTURE of af_sim is
component af_sim_clk_rst_generator_0_0 is
port (
clk : out STD_LOGIC;
rst_n : out STD_LOGIC;
stop_simulation : in STD_LOGIC
);
end component af_sim_clk_rst_generator_0_0;
component af_sim_axis_audio_master_si_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC;
WAV_HEADER : out STD_LOGIC_VECTOR ( 351 downto 0 )
);
end component af_sim_axis_audio_master_si_0_0;
component af_sim_axis_audio_mono2ster_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end component af_sim_axis_audio_mono2ster_0_0;
component af_sim_axis_audio_stereo2mo_0_0 is
port (
AXIS_ACLK : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TREADY : in STD_LOGIC
);
end component af_sim_axis_audio_stereo2mo_0_0;
component af_sim_axis_audio_slave_sim_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIS_TREADY : out STD_LOGIC;
FINISHED : out STD_LOGIC;
WAV_HEADER : in STD_LOGIC_VECTOR ( 351 downto 0 )
);
end component af_sim_axis_audio_slave_sim_0_0;
component af_sim_axis_prog_audio_filt_0_0 is
port (
AXI_ACLK : in STD_LOGIC;
AXI_ARESETN : in STD_LOGIC;
S_AXIL_AWADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_AWVALID : in STD_LOGIC;
S_AXIL_AWREADY : out STD_LOGIC;
S_AXIL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_WVALID : in STD_LOGIC;
S_AXIL_WREADY : out STD_LOGIC;
S_AXIL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXIL_BVALID : out STD_LOGIC;
S_AXIL_BREADY : in STD_LOGIC;
S_AXIL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIL_ARADDR : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXIL_ARVALID : in STD_LOGIC;
S_AXIL_ARREADY : out STD_LOGIC;
S_AXIL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXIL_RVALID : out STD_LOGIC;
S_AXIL_RREADY : in STD_LOGIC;
S_AXIL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXIS_TLAST : in STD_LOGIC;
S_AXIS_TREADY : out STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXIS_TLAST : out STD_LOGIC;
M_AXIS_TREADY : in STD_LOGIC
);
end component af_sim_axis_prog_audio_filt_0_0;
signal axis_audio_master_si_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_audio_master_si_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_audio_master_si_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_audio_master_si_0_WAV_HEADER : STD_LOGIC_VECTOR ( 351 downto 0 );
signal axis_audio_mono2ster_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_audio_mono2ster_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_audio_mono2ster_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_audio_slave_sim_0_FINISHED : STD_LOGIC;
signal axis_audio_stereo2mo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axis_audio_stereo2mo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_audio_stereo2mo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_prog_audio_filt_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axis_prog_audio_filt_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_prog_audio_filt_0_M_AXIS_TVALID : STD_LOGIC;
signal clk_rst_generator_0_clk : STD_LOGIC;
signal clk_rst_generator_0_rst_n : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
axis_audio_master_si_0: component af_sim_axis_audio_master_si_0_0
port map (
ACLK => clk_rst_generator_0_clk,
ARESETN => clk_rst_generator_0_rst_n,
M_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID,
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
);
axis_audio_mono2ster_0: component af_sim_axis_audio_mono2ster_0_0
port map (
AXIS_ACLK => clk_rst_generator_0_clk,
M_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
M_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
S_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
S_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID
);
axis_audio_slave_sim_0: component af_sim_axis_audio_slave_sim_0_0
port map (
ACLK => clk_rst_generator_0_clk,
ARESETN => clk_rst_generator_0_rst_n,
FINISHED => axis_audio_slave_sim_0_FINISHED,
S_AXIS_TDATA(31 downto 0) => axis_audio_mono2ster_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TREADY => axis_audio_mono2ster_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_audio_mono2ster_0_M_AXIS_TVALID,
WAV_HEADER(351 downto 0) => axis_audio_master_si_0_WAV_HEADER(351 downto 0)
);
axis_audio_stereo2mo_0: component af_sim_axis_audio_stereo2mo_0_0
port map (
AXIS_ACLK => clk_rst_generator_0_clk,
M_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
M_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID,
S_AXIS_TDATA(31 downto 0) => axis_audio_master_si_0_M_AXIS_TDATA(31 downto 0),
S_AXIS_TREADY => axis_audio_master_si_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_audio_master_si_0_M_AXIS_TVALID
);
axis_prog_audio_filt_0: component af_sim_axis_prog_audio_filt_0_0
port map (
AXI_ACLK => clk_rst_generator_0_clk,
AXI_ARESETN => clk_rst_generator_0_rst_n,
M_AXIS_TDATA(15 downto 0) => axis_prog_audio_filt_0_M_AXIS_TDATA(15 downto 0),
M_AXIS_TLAST => NLW_axis_prog_audio_filt_0_M_AXIS_TLAST_UNCONNECTED,
M_AXIS_TREADY => axis_prog_audio_filt_0_M_AXIS_TREADY,
M_AXIS_TVALID => axis_prog_audio_filt_0_M_AXIS_TVALID,
S_AXIL_ARADDR(7 downto 0) => B"00000000",
S_AXIL_ARREADY => NLW_axis_prog_audio_filt_0_S_AXIL_ARREADY_UNCONNECTED,
S_AXIL_ARVALID => '0',
S_AXIL_AWADDR(7 downto 0) => B"00000000",
S_AXIL_AWREADY => NLW_axis_prog_audio_filt_0_S_AXIL_AWREADY_UNCONNECTED,
S_AXIL_AWVALID => '0',
S_AXIL_BREADY => '0',
S_AXIL_BRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_BRESP_UNCONNECTED(1 downto 0),
S_AXIL_BVALID => NLW_axis_prog_audio_filt_0_S_AXIL_BVALID_UNCONNECTED,
S_AXIL_RDATA(31 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RDATA_UNCONNECTED(31 downto 0),
S_AXIL_RREADY => '0',
S_AXIL_RRESP(1 downto 0) => NLW_axis_prog_audio_filt_0_S_AXIL_RRESP_UNCONNECTED(1 downto 0),
S_AXIL_RVALID => NLW_axis_prog_audio_filt_0_S_AXIL_RVALID_UNCONNECTED,
S_AXIL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXIL_WREADY => NLW_axis_prog_audio_filt_0_S_AXIL_WREADY_UNCONNECTED,
S_AXIL_WSTRB(3 downto 0) => B"1111",
S_AXIL_WVALID => '0',
S_AXIS_TDATA(15 downto 0) => axis_audio_stereo2mo_0_M_AXIS_TDATA(15 downto 0),
S_AXIS_TLAST => '0',
S_AXIS_TREADY => axis_audio_stereo2mo_0_M_AXIS_TREADY,
S_AXIS_TVALID => axis_audio_stereo2mo_0_M_AXIS_TVALID
);
clk_rst_generator_0: component af_sim_clk_rst_generator_0_0
port map (
clk => clk_rst_generator_0_clk,
rst_n => clk_rst_generator_0_rst_n,
stop_simulation => axis_audio_slave_sim_0_FINISHED
);
end STRUCTURE;
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/design_1.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732725224"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732725224"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732725224"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732725224"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd
+2 -2
View File
@@ -2,8 +2,8 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 15:15:29 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Date : Wed Nov 27 17:33:33 2024
--Host : sb0217-172 running 64-bit major release (build 9200)
--Command : generate_target design_1_wrapper.bd
--Design : design_1_wrapper
--Purpose : IP block netlist
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xml
+5 -5
View File
@@ -577,7 +577,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -596,7 +596,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -614,7 +614,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:25:48 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:53:20 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -645,7 +645,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -665,7 +665,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xml
+5 -5
View File
@@ -422,7 +422,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:05 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -441,7 +441,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:05 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -459,7 +459,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:25:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:53:16 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -490,7 +490,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:05 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -510,7 +510,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:05 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xml
+5 -5
View File
@@ -422,7 +422,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -441,7 +441,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -459,7 +459,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:25:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:53:16 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -490,7 +490,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -510,7 +510,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:55 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xml
+40 -36
View File
@@ -891,7 +891,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:15e36279</spirit:value>
<spirit:value>9:d16ada26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -903,7 +903,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
<spirit:value>9:1bcb63e3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -917,11 +917,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:25:50 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:34:48 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
<spirit:value>9:1bcb63e3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -932,7 +932,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
<spirit:value>9:1bcb63e3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -948,11 +948,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:45 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:15e36279</spirit:value>
<spirit:value>9:d16ada26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -968,11 +968,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:45 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d2381e3b</spirit:value>
<spirit:value>9:1bcb63e3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1406,22 +1406,22 @@
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>COEFF_0</spirit:name>
<spirit:displayName>Coeff 0</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_0">42</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_0">16</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>COEFF_1</spirit:name>
<spirit:displayName>Coeff 1</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_1">42</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_1">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>COEFF_2</spirit:name>
<spirit:displayName>Coeff 2</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_2">42</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.COEFF_2">16</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>SHIFT</spirit:name>
<spirit:displayName>Shift</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHIFT">7</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SHIFT">6</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>RUN_AFTER_RESET</spirit:name>
@@ -1501,22 +1501,22 @@
<spirit:parameter>
<spirit:name>COEFF_0</spirit:name>
<spirit:displayName>Coeff 0</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_0">42</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_0">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>COEFF_1</spirit:name>
<spirit:displayName>Coeff 1</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_1">42</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_1">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>COEFF_2</spirit:name>
<spirit:displayName>Coeff 2</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_2">42</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.COEFF_2">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SHIFT</spirit:name>
<spirit:displayName>Shift</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SHIFT">7</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SHIFT">6</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RUN_AFTER_RESET</spirit:name>
@@ -1559,36 +1559,36 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_READ_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.NUM_WRITE_THREADS" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PHASE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIL.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
@@ -1601,6 +1601,10 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.COEFF_0" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.COEFF_1" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.COEFF_2" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SHIFT" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xml
+5 -5
View File
@@ -17,7 +17,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:54 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -36,7 +36,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:54 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -54,7 +54,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:25:44 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:53:17 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -85,7 +85,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:54 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -105,7 +105,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:29 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:51:54 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bd
+1 -1
View File
@@ -336,7 +336,7 @@
"value": "FALSE"
},
"C_DATA_DEPTH": {
"value": "16384"
"value": "8192"
},
"C_EN_STRG_QUAL": {
"value": "0"
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/bd_f60c.bxml
+4 -4
View File
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="40">
<CompositeFile CompositeFileTopName="bd_f60c" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732630534"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732725222"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1732725222"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732725222"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732725222"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\bd_f60c.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xci
+2 -2
View File
@@ -2055,7 +2055,7 @@
"C_PROBE2_WIDTH": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "26", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "bd_f60c_ila_lib_0", "resolve_type": "user", "usage": "all" } ],
@@ -3136,7 +3136,7 @@
"C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_ILA_AXI_MON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "26", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "8192", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MAJOR_VERSION": [ { "value": "2023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MINOR_VERSION": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_BUILD_REVISION": [ { "value": "0", "format": "long", "usage": "all" } ],
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_0/bd_f60c_ila_lib_0.xml
+11 -11
View File
@@ -1046,11 +1046,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:31 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:39 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:1964941d</spirit:value>
<spirit:value>9:0a92643b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1065,11 +1065,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:31 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:39 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:1964941d</spirit:value>
<spirit:value>9:0a92643b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1080,7 +1080,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:1964941d</spirit:value>
<spirit:value>9:0a92643b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1096,11 +1096,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:31 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:39 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:6cb62d17</spirit:value>
<spirit:value>9:cdd9092f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1116,11 +1116,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:31 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:39 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:1964941d</spirit:value>
<spirit:value>9:0a92643b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -28998,7 +28998,7 @@
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_DATA_DEPTH</spirit:name>
<spirit:displayName>Sample Data Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_DEPTH">16384</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DATA_DEPTH">8192</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_MAJOR_VERSION</spirit:name>
@@ -69461,7 +69461,7 @@
<spirit:parameter>
<spirit:name>C_DATA_DEPTH</spirit:name>
<spirit:displayName>Sample Data Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">16384</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">8192</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_1/bd_f60c_g_inst_0.xml
+4 -4
View File
@@ -31172,7 +31172,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:41 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31192,7 +31192,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:41 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31212,7 +31212,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:41 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -31232,7 +31232,7 @@ lot_5_axi:slot_6_axi:slot_7_axi:slot_8_axi:slot_9_axi:slot_10_axi:slot_11_axi:sl
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:41 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_2/bd_f60c_slot_0_aw_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_3/bd_f60c_slot_0_w_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_4/bd_f60c_slot_0_b_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_5/bd_f60c_slot_0_ar_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/bd_0/ip/ip_6/bd_f60c_slot_0_r_0.xml
+4 -4
View File
@@ -29,7 +29,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -49,7 +49,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -69,7 +69,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:43 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -89,7 +89,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:33 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:44 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xml
+69 -20
View File
@@ -904,11 +904,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:36 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5a9d8cb3</spirit:value>
<spirit:value>9:f75ccf4d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -922,11 +922,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:01:38 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:22 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:18b60821</spirit:value>
<spirit:value>9:2d6fafa7</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -940,11 +940,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:01:38 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:06 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:1eaebf2b</spirit:value>
<spirit:value>9:5d5ff010</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -958,11 +958,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:18:46 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:35:56 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5a9d8cb3</spirit:value>
<spirit:value>9:f75ccf4d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -977,11 +977,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:36 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5a9d8cb3</spirit:value>
<spirit:value>9:f75ccf4d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -994,7 +994,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:383766bf</spirit:value>
<spirit:value>9:acafc754</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1014,11 +1014,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:37 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:383766bf</spirit:value>
<spirit:value>9:acafc754</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -1038,11 +1038,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:30 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 16:33:37 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:5a9d8cb3</spirit:value>
<spirit:value>9:f75ccf4d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -30629,7 +30629,7 @@
<spirit:parameter>
<spirit:name>C_DATA_DEPTH</spirit:name>
<spirit:displayName>Sample Data Depth</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">16384</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DATA_DEPTH" spirit:choiceRef="choice_list_d4fc98f8" spirit:order="10800" spirit:configGroups="1 UnGrouped">8192</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -37022,19 +37022,68 @@
<xilinx:tag xilinx:name="driver_mode">mixed</xilinx:tag>
</xilinx:tags>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESETN.POLARITY" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_BUSIF" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.ASSOCIATED_RESET" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.RESETN.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.CLK_DOMAIN" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.FREQ_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_0_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.FREQ_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TKEEP" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TLAST" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TREADY" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.HAS_TSTRB" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_1_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.CLK_DOMAIN" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.FREQ_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.HAS_TKEEP" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.HAS_TLAST" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.HAS_TREADY" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.HAS_TSTRB" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.LAYERED_METADATA" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TDATA_NUM_BYTES" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TDEST_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLOT_2_AXIS.TUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DATA_DEPTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_MONITOR_SLOTS" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SLOT" xilinx:valueSource="user"/>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xml
+5 -5
View File
@@ -503,7 +503,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:06 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -522,7 +522,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:06 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -540,7 +540,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:16:46 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:53:19 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -571,7 +571,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:06 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -591,7 +591,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Nov 26 14:15:34 UTC 2024</spirit:value>
<spirit:value>Wed Nov 27 15:52:06 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/sim/design_1.vhd
+2 -2
View File
@@ -2,8 +2,8 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 15:15:29 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Date : Wed Nov 27 17:33:33 2024
--Host : sb0217-172 running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/design_1/synth/design_1.vhd
+2 -2
View File
@@ -2,8 +2,8 @@
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Tue Nov 26 15:15:29 2024
--Host : BiermannSurface running 64-bit major release (build 9200)
--Date : Wed Nov 27 17:33:33 2024
--Host : sb0217-172 running 64-bit major release (build 9200)
--Command : generate_target design_1.bd
--Design : design_1
--Purpose : IP block netlist
Milestone3/es-milestone3/es-milestone3.gen/sources_1/bd/mref/axis_prog_audio_filter3/component.xml
+3 -3
View File
@@ -301,7 +301,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f3a26ecd</spirit:value>
<spirit:value>7d34b594</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -314,7 +314,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>f3a26ecd</spirit:value>
<spirit:value>7d34b594</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -855,7 +855,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-11-26T14:02:40Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-11-27T16:32:03Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/af_sim.bd
+1 -2
View File
@@ -7,8 +7,7 @@
"name": "af_sim",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2023.1",
"validated": "true"
"tool_version": "2023.1"
},
"design_tree": {
"clk_rst_generator_0": "",
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ip/af_sim_axis_prog_audio_filt_0_0/af_sim_axis_prog_audio_filt_0_0.xci
+19 -19
View File
@@ -137,26 +137,26 @@
"mode": "slave",
"memory_map_ref": "S_AXIL",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/af_sim/ui/bd_279d689d.ui
+6 -6
View File
@@ -8,10 +8,10 @@
"Interfaces View_Layout":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
preplace inst axis_audio_master_si_0 -pg 1 -lvl 2 -x 140 -y 60 -defaultsOSRD
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 780 -y 70 -defaultsOSRD
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 340 -y 60 -defaultsOSRD
preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 980 -y 70 -defaultsOSRD
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 560 -y 70 -defaultsOSRD
preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 5 -x 830 -y 70 -defaultsOSRD
preplace inst axis_audio_stereo2mo_0 -pg 1 -lvl 3 -x 350 -y 60 -defaultsOSRD
preplace inst axis_audio_slave_sim_0 -pg 1 -lvl 6 -x 1040 -y 70 -defaultsOSRD
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 4 -x 590 -y 70 -defaultsOSRD
preplace netloc axis_audio_master_si_0_WAV_HEADER 1 2 4 250J -40n NJ -40n NJ -40n 1080
preplace netloc axis_audio_slave_sim_0_FINISHED 1 0 7 -240 -30n NJ -30n NJ -30n NJ -30n NJ -30n NJ -30n 1360
preplace netloc clk_rst_generator_0_clk 1 1 5 -10 -80n 260 -80n 540 -70n 830 -60n 1060
@@ -20,8 +20,8 @@ preplace netloc axis_audio_master_si_0_M_AXIS 1 2 1 N 60
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 5 1 N 70
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 3 1 N 60
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 4 1 N 70
levelinfo -pg 1 0 20 140 340 560 780 980 1080
pagesize -pg 1 -db -bbox -sgen 0 0 1080 140
levelinfo -pg 1 0 20 140 350 590 830 1040 1140
pagesize -pg 1 -db -bbox -sgen 0 0 1140 140
",
"Interfaces View_ScaleFactor":"1.39512",
"Interfaces View_TopLeft":"32,-191",
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/design_1.bd
+15 -1
View File
@@ -127,7 +127,7 @@
"inst_hier_path": "system_ila_0",
"parameters": {
"C_DATA_DEPTH": {
"value": "16384"
"value": "8192"
},
"C_NUM_MONITOR_SLOTS": {
"value": "3"
@@ -177,6 +177,20 @@
"xci_name": "design_1_axis_prog_audio_filt_0_1",
"xci_path": "ip\\design_1_axis_prog_audio_filt_0_1\\design_1_axis_prog_audio_filt_0_1.xci",
"inst_hier_path": "axis_prog_audio_filt_0",
"parameters": {
"COEFF_0": {
"value": "16"
},
"COEFF_1": {
"value": "32"
},
"COEFF_2": {
"value": "16"
},
"SHIFT": {
"value": "6"
}
},
"reference_info": {
"ref_type": "hdl",
"ref_name": "axis_prog_audio_filter3",
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci
+27 -27
View File
@@ -8,19 +8,19 @@
"gen_directory": "../../../../../../es-milestone3.gen/sources_1/bd/design_1/ip/design_1_axis_prog_audio_filt_0_1",
"parameters": {
"component_parameters": {
"COEFF_0": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
"COEFF_1": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
"COEFF_2": [ { "value": "42", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SHIFT": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
"COEFF_0": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"COEFF_1": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"COEFF_2": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SHIFT": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HAS_LAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Component_Name": [ { "value": "design_1_axis_prog_audio_filt_0_1", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"COEFF_0": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"COEFF_1": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"COEFF_2": [ { "value": "42", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SHIFT": [ { "value": "7", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"COEFF_0": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"COEFF_1": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"COEFF_2": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SHIFT": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"RUN_AFTER_RESET": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"HAS_LAST": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
},
@@ -137,26 +137,26 @@
"mode": "slave",
"memory_map_ref": "S_AXIL",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci
+54 -54
View File
@@ -2571,7 +2571,7 @@
"C_PROBE2_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_DATA_DEPTH": [ { "value": "8192", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_NUM_OF_PROBES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
"Component_Name": [ { "value": "design_1_system_ila_0_0", "resolve_type": "user", "usage": "all" } ],
@@ -3900,13 +3900,13 @@
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_src": "default_prop", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "resolve_type": "generated", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_1_AXIS:SLOT_2_AXIS", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
@@ -3918,7 +3918,7 @@
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "resolve_type": "generated", "is_static_object": false } ],
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
@@ -3930,36 +3930,36 @@
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "monitor",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "generated", "is_static_object": false } ],
"DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "generated", "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
@@ -3989,18 +3989,18 @@
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "monitor",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TLAST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
@@ -4015,18 +4015,18 @@
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
"mode": "monitor",
"parameters": {
"TDATA_NUM_BYTES": [ { "value": "2", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TDATA_NUM_BYTES": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TDEST_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"TUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TREADY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TSTRB": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TKEEP": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"HAS_TLAST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "bd_f60c_clk", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ],
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
},
"port_maps": {
Milestone3/es-milestone3/es-milestone3.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
+7 -7
View File
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.42004",
"Default View_TopLeft":"20,-332",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-825,-402",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0
# -string -flagsOSRD
@@ -23,8 +23,8 @@ preplace inst axis_audio_mono2ster_0 -pg 1 -lvl 4 -x 940 -y 110 -defaultsOSRD
preplace inst zybo_audio_0 -pg 1 -lvl 5 -x 1170 -y 130 -defaultsOSRD
preplace inst axis_prog_audio_filt_0 -pg 1 -lvl 3 -x 640 -y -110 -defaultsOSRD
preplace netloc clk_1 1 0 1 -220 -40n
preplace netloc clk_rst_generator_0_clk 1 1 4 180 -160 500 0 820 180 1050
preplace netloc clk_rst_generator_0_rst_n 1 1 3 190 -20 510 -20 830
preplace netloc clk_rst_generator_0_clk 1 1 4 170 -160 490 0 820 180 1050
preplace netloc clk_rst_generator_0_rst_n 1 1 3 180 -20 500 -20 830
preplace netloc rec_dat_1 1 0 5 NJ 200 NJ 200 NJ 200 NJ 200 1060
preplace netloc resez_1 1 0 1 N 0
preplace netloc zybo_audio_0_bclk 1 5 1 1290 140n
@@ -33,11 +33,11 @@ preplace netloc zybo_audio_0_mute 1 5 1 1290 10n
preplace netloc zybo_audio_0_pb_dat 1 5 1 1300 40n
preplace netloc zybo_audio_0_pb_lrc 1 5 1 1280 180n
preplace netloc zybo_audio_0_rec_lrc 1 5 1 1320 190n
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 480 -210 NJ
preplace netloc axil_master_with_rom_0_M_AXIL 1 2 2 470 -210 NJ
preplace netloc axis_audio_mono2ster_0_M_AXIS 1 4 1 N 110
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 490 -200 770J
preplace netloc axis_audio_stereo2mo_0_M_AXIS 1 2 2 480 -200 780J
preplace netloc axis_prog_audio_filt_0_M_AXIS 1 3 1 810 -170n
preplace netloc zybo_audio_0_axis_rec 1 1 5 200 -10 NJ -10 NJ -10 NJ -10 1280
preplace netloc zybo_audio_0_axis_rec 1 1 5 190 -10 NJ -10 NJ -10 NJ -10 1280
preplace netloc zybo_audio_0_i2c 1 5 1 N 80
levelinfo -pg 1 -240 -20 320 640 940 1170 1340
pagesize -pg 1 -db -bbox -sgen -340 -420 1450 560
Milestone3/es-milestone3/es-milestone3.xpr
+47 -43
View File
@@ -4,7 +4,7 @@
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="63" Path="C:/hs/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
<Project Product="Vivado" Version="7" Minor="63" Path="Z:/Praktika/Elektronische Systeme/es-praktikum/Milestone3/es-milestone3/es-milestone3.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ac364057cd1843739edfb55c505ac94b"/>
@@ -103,27 +103,27 @@
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci">
<Proxy FileSetName="design_1_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_zybo_audio_0_0/design_1_zybo_audio_0_0.xci">
<Proxy FileSetName="design_1_zybo_audio_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_rst_generator_0_0/design_1_clk_rst_generator_0_0.xci">
<Proxy FileSetName="design_1_clk_rst_generator_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axil_master_with_rom_0_0/design_1_axil_master_with_rom_0_0.xci">
<Proxy FileSetName="design_1_axil_master_with_rom_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_mono2ster_0_0/design_1_axis_audio_mono2ster_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_mono2ster_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_system_ila_0_0/design_1_system_ila_0_0.xci">
<Proxy FileSetName="design_1_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_audio_stereo2mo_0_0/design_1_axis_audio_stereo2mo_0_0.xci">
<Proxy FileSetName="design_1_axis_audio_stereo2mo_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axis_prog_audio_filt_0_1/design_1_axis_prog_audio_filt_0_1.xci">
<Proxy FileSetName="design_1_axis_prog_audio_filt_0_1"/>
</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.vhd">
<FileInfo>
@@ -186,6 +186,14 @@
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
@@ -214,12 +222,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_axis_prog_audio_filt_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axis_prog_audio_filt_0_1" RelGenDir="$PGENDIR/design_1_axis_prog_audio_filt_0_1">
<Config>
<Option Name="TopModule" Val="design_1_axis_prog_audio_filt_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_system_ila_0_0" RelGenDir="$PGENDIR/design_1_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="design_1_system_ila_0_0"/>
@@ -232,6 +234,12 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="design_1_axis_prog_audio_filt_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_axis_prog_audio_filt_0_1" RelGenDir="$PGENDIR/design_1_axis_prog_audio_filt_0_1">
<Config>
<Option Name="TopModule" Val="design_1_axis_prog_audio_filt_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -252,7 +260,7 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="20">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/design_1_wrapper.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
@@ -302,7 +310,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_axis_prog_audio_filt_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_prog_audio_filt_0_1" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1">
<Run Id="design_1_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
@@ -312,19 +320,17 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_system_ila_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_zybo_audio_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_zybo_audio_0_0" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_zybo_audio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_axis_prog_audio_filt_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_axis_prog_audio_filt_0_1" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
@@ -336,7 +342,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 12 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
@@ -422,7 +428,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_axis_prog_audio_filt_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1">
<Run Id="design_1_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
@@ -439,11 +445,9 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_system_ila_0_0_impl_1">
<Run Id="design_1_zybo_audio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_zybo_audio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -458,7 +462,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="design_1_zybo_audio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_zybo_audio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_zybo_audio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_zybo_audio_0_0_impl_1">
<Run Id="design_1_axis_prog_audio_filt_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="design_1_axis_prog_audio_filt_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_axis_prog_audio_filt_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_axis_prog_audio_filt_0_1_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
Milestone3/sources/axis_audio_filter3.vhd
+1 -1
View File
@@ -97,7 +97,6 @@ begin
case state is
when IDLE =>
S_AXIS_TREADY <= '1';
if S_AXIS_TVALID = '1' then
s2 := s1;
s1 := s0;
@@ -112,6 +111,7 @@ begin
res := res + (p2(23)&p2(23)&p2);
state <= CALC;
S_AXIS_TREADY <= '0';
end if;
when CALC =>
M_AXIS_TVALID <= '1';